drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/io.h>
  36 #include <linux/clk.h>
  37 #include <linux/serial_core.h>
  38 #include <linux/irq.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/of.h>
  41 #include <linux/gpio.h>
  42
  43 #include <plat/dmtimer.h>
  44 #include <plat/omap-serial.h>
  45
  46 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  47
  48 #define OMAP_UART_REV_42 0x0402
  49 #define OMAP_UART_REV_46 0x0406
  50 #define OMAP_UART_REV_52 0x0502
  51 #define OMAP_UART_REV_63 0x0603
  52
  53 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  54
  55 /* SCR register bitmasks */
  56 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  57
  58 /* FCR register bitmasks */
  59 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT                6
  60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  61
  62 /* MVR register bitmasks */
  63 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  64
  65 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  66 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  67 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  68
  69 #define OMAP_UART_MVR_MAJ_MASK          0x700
  70 #define OMAP_UART_MVR_MAJ_SHIFT         8
  71 #define OMAP_UART_MVR_MIN_MASK          0x3f
  72
  73 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
  74
  75 /* Forward declaration of functions */
  76 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
  77
  78 static struct workqueue_struct *serial_omap_uart_wq;
  79
  80 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
  81 {
  82         offset <<= up->port.regshift;
  83         return readw(up->port.membase + offset);
  84 }
  85
  86 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
  87 {
  88         offset <<= up->port.regshift;
  89         writew(value, up->port.membase + offset);
  90 }
  91
  92 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
  93 {
  94         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
  95         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
  96                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
  97         serial_out(up, UART_FCR, 0);
  98 }
  99
 100 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 101 {
 102         struct omap_uart_port_info *pdata = up->dev->platform_data;
 103
 104         if (!pdata->get_context_loss_count)
 105                 return 0;
 106
 107         return pdata->get_context_loss_count(up->dev);
 108 }
 109
 110 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 111 {
 112         struct omap_uart_port_info *pdata = up->dev->platform_data;
 113
 114         if (pdata->set_forceidle)
 115                 pdata->set_forceidle(up->dev);
 116 }
 117
 118 static void serial_omap_set_noidle(struct uart_omap_port *up)
 119 {
 120         struct omap_uart_port_info *pdata = up->dev->platform_data;
 121
 122         if (pdata->set_noidle)
 123                 pdata->set_noidle(up->dev);
 124 }
 125
 126 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 127 {
 128         struct omap_uart_port_info *pdata = up->dev->platform_data;
 129
 130         if (pdata->enable_wakeup)
 131                 pdata->enable_wakeup(up->dev, enable);
 132 }
 133
 134 /*
 135  * serial_omap_get_divisor - calculate divisor value
 136  * @port: uart port info
 137  * @baud: baudrate for which divisor needs to be calculated.
 138  *
 139  * We have written our own function to get the divisor so as to support
 140  * 13x mode. 3Mbps Baudrate as an different divisor.
 141  * Reference OMAP TRM Chapter 17:
 142  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 143  * referring to oversampling - divisor value
 144  * baudrate 460,800 to 3,686,400 all have divisor 13
 145  * except 3,000,000 which has divisor value 16
 146  */
 147 static unsigned int
 148 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 149 {
 150         unsigned int divisor;
 151
 152         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 153                 divisor = 13;
 154         else
 155                 divisor = 16;
 156         return port->uartclk/(baud * divisor);
 157 }
 158
 159 static void serial_omap_enable_ms(struct uart_port *port)
 160 {
 161         struct uart_omap_port *up = to_uart_omap_port(port);
 162
 163         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 164
 165         pm_runtime_get_sync(up->dev);
 166         up->ier |= UART_IER_MSI;
 167         serial_out(up, UART_IER, up->ier);
 168         pm_runtime_mark_last_busy(up->dev);
 169         pm_runtime_put_autosuspend(up->dev);
 170 }
 171
 172 static void serial_omap_stop_tx(struct uart_port *port)
 173 {
 174         struct uart_omap_port *up = to_uart_omap_port(port);
 175
 176         pm_runtime_get_sync(up->dev);
 177         if (up->ier & UART_IER_THRI) {
 178                 up->ier &= ~UART_IER_THRI;
 179                 serial_out(up, UART_IER, up->ier);
 180         }
 181
 182         serial_omap_set_forceidle(up);
 183
 184         pm_runtime_mark_last_busy(up->dev);
 185         pm_runtime_put_autosuspend(up->dev);
 186 }
 187
 188 static void serial_omap_stop_rx(struct uart_port *port)
 189 {
 190         struct uart_omap_port *up = to_uart_omap_port(port);
 191
 192         pm_runtime_get_sync(up->dev);
 193         up->ier &= ~UART_IER_RLSI;
 194         up->port.read_status_mask &= ~UART_LSR_DR;
 195         serial_out(up, UART_IER, up->ier);
 196         pm_runtime_mark_last_busy(up->dev);
 197         pm_runtime_put_autosuspend(up->dev);
 198 }
 199
 200 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 201 {
 202         struct circ_buf *xmit = &up->port.state->xmit;
 203         int count;
 204
 205         if (!(lsr & UART_LSR_THRE))
 206                 return;
 207
 208         if (up->port.x_char) {
 209                 serial_out(up, UART_TX, up->port.x_char);
 210                 up->port.icount.tx++;
 211                 up->port.x_char = 0;
 212                 return;
 213         }
 214         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 215                 serial_omap_stop_tx(&up->port);
 216                 return;
 217         }
 218         count = up->port.fifosize / 4;
 219         do {
 220                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 221                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 222                 up->port.icount.tx++;
 223                 if (uart_circ_empty(xmit))
 224                         break;
 225         } while (--count > 0);
 226
 227         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 228                 uart_write_wakeup(&up->port);
 229
 230         if (uart_circ_empty(xmit))
 231                 serial_omap_stop_tx(&up->port);
 232 }
 233
 234 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 235 {
 236         if (!(up->ier & UART_IER_THRI)) {
 237                 up->ier |= UART_IER_THRI;
 238                 serial_out(up, UART_IER, up->ier);
 239         }
 240 }
 241
 242 static void serial_omap_start_tx(struct uart_port *port)
 243 {
 244         struct uart_omap_port *up = to_uart_omap_port(port);
 245
 246         pm_runtime_get_sync(up->dev);
 247         serial_omap_enable_ier_thri(up);
 248         serial_omap_set_noidle(up);
 249         pm_runtime_mark_last_busy(up->dev);
 250         pm_runtime_put_autosuspend(up->dev);
 251 }
 252
 253 static unsigned int check_modem_status(struct uart_omap_port *up)
 254 {
 255         unsigned int status;
 256
 257         status = serial_in(up, UART_MSR);
 258         status |= up->msr_saved_flags;
 259         up->msr_saved_flags = 0;
 260         if ((status & UART_MSR_ANY_DELTA) == 0)
 261                 return status;
 262
 263         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 264             up->port.state != NULL) {
 265                 if (status & UART_MSR_TERI)
 266                         up->port.icount.rng++;
 267                 if (status & UART_MSR_DDSR)
 268                         up->port.icount.dsr++;
 269                 if (status & UART_MSR_DDCD)
 270                         uart_handle_dcd_change
 271                                 (&up->port, status & UART_MSR_DCD);
 272                 if (status & UART_MSR_DCTS)
 273                         uart_handle_cts_change
 274                                 (&up->port, status & UART_MSR_CTS);
 275                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 276         }
 277
 278         return status;
 279 }
 280
 281 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 282 {
 283         unsigned int flag;
 284
 285         up->port.icount.rx++;
 286         flag = TTY_NORMAL;
 287
 288         if (lsr & UART_LSR_BI) {
 289                 flag = TTY_BREAK;
 290                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 291                 up->port.icount.brk++;
 292                 /*
 293                  * We do the SysRQ and SAK checking
 294                  * here because otherwise the break
 295                  * may get masked by ignore_status_mask
 296                  * or read_status_mask.
 297                  */
 298                 if (uart_handle_break(&up->port))
 299                         return;
 300
 301         }
 302
 303         if (lsr & UART_LSR_PE) {
 304                 flag = TTY_PARITY;
 305                 up->port.icount.parity++;
 306         }
 307
 308         if (lsr & UART_LSR_FE) {
 309                 flag = TTY_FRAME;
 310                 up->port.icount.frame++;
 311         }
 312
 313         if (lsr & UART_LSR_OE)
 314                 up->port.icount.overrun++;
 315
 316 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 317         if (up->port.line == up->port.cons->index) {
 318                 /* Recover the break flag from console xmit */
 319                 lsr |= up->lsr_break_flag;
 320         }
 321 #endif
 322         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 323 }
 324
 325 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 326 {
 327         unsigned char ch = 0;
 328         unsigned int flag;
 329
 330         if (!(lsr & UART_LSR_DR))
 331                 return;
 332
 333         ch = serial_in(up, UART_RX);
 334         flag = TTY_NORMAL;
 335         up->port.icount.rx++;
 336
 337         if (uart_handle_sysrq_char(&up->port, ch))
 338                 return;
 339
 340         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 341 }
 342
 343 /**
 344  * serial_omap_irq() - This handles the interrupt from one port
 345  * @irq: uart port irq number
 346  * @dev_id: uart port info
 347  */
 348 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 349 {
 350         struct uart_omap_port *up = dev_id;
 351         struct tty_struct *tty = up->port.state->port.tty;
 352         unsigned int iir, lsr;
 353         unsigned int type;
 354         irqreturn_t ret = IRQ_NONE;
 355         int max_count = 256;
 356
 357         spin_lock(&up->port.lock);
 358         pm_runtime_get_sync(up->dev);
 359
 360         do {
 361                 iir = serial_in(up, UART_IIR);
 362                 if (iir & UART_IIR_NO_INT)
 363                         break;
 364
 365                 ret = IRQ_HANDLED;
 366                 lsr = serial_in(up, UART_LSR);
 367
 368                 /* extract IRQ type from IIR register */
 369                 type = iir & 0x3e;
 370
 371                 switch (type) {
 372                 case UART_IIR_MSI:
 373                         check_modem_status(up);
 374                         break;
 375                 case UART_IIR_THRI:
 376                         transmit_chars(up, lsr);
 377                         break;
 378                 case UART_IIR_RX_TIMEOUT:
 379                         /* FALLTHROUGH */
 380                 case UART_IIR_RDI:
 381                         serial_omap_rdi(up, lsr);
 382                         break;
 383                 case UART_IIR_RLSI:
 384                         serial_omap_rlsi(up, lsr);
 385                         break;
 386                 case UART_IIR_CTS_RTS_DSR:
 387                         /* simply try again */
 388                         break;
 389                 case UART_IIR_XOFF:
 390                         /* FALLTHROUGH */
 391                 default:
 392                         break;
 393                 }
 394         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 395
 396         spin_unlock(&up->port.lock);
 397
 398         tty_flip_buffer_push(tty);
 399
 400         pm_runtime_mark_last_busy(up->dev);
 401         pm_runtime_put_autosuspend(up->dev);
 402         up->port_activity = jiffies;
 403
 404         return ret;
 405 }
 406
 407 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 408 {
 409         struct uart_omap_port *up = to_uart_omap_port(port);
 410         unsigned long flags = 0;
 411         unsigned int ret = 0;
 412
 413         pm_runtime_get_sync(up->dev);
 414         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 415         spin_lock_irqsave(&up->port.lock, flags);
 416         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 417         spin_unlock_irqrestore(&up->port.lock, flags);
 418         pm_runtime_mark_last_busy(up->dev);
 419         pm_runtime_put_autosuspend(up->dev);
 420         return ret;
 421 }
 422
 423 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 424 {
 425         struct uart_omap_port *up = to_uart_omap_port(port);
 426         unsigned int status;
 427         unsigned int ret = 0;
 428
 429         pm_runtime_get_sync(up->dev);
 430         status = check_modem_status(up);
 431         pm_runtime_mark_last_busy(up->dev);
 432         pm_runtime_put_autosuspend(up->dev);
 433
 434         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 435
 436         if (status & UART_MSR_DCD)
 437                 ret |= TIOCM_CAR;
 438         if (status & UART_MSR_RI)
 439                 ret |= TIOCM_RNG;
 440         if (status & UART_MSR_DSR)
 441                 ret |= TIOCM_DSR;
 442         if (status & UART_MSR_CTS)
 443                 ret |= TIOCM_CTS;
 444         return ret;
 445 }
 446
 447 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 448 {
 449         struct uart_omap_port *up = to_uart_omap_port(port);
 450         unsigned char mcr = 0;
 451
 452         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 453         if (mctrl & TIOCM_RTS)
 454                 mcr |= UART_MCR_RTS;
 455         if (mctrl & TIOCM_DTR)
 456                 mcr |= UART_MCR_DTR;
 457         if (mctrl & TIOCM_OUT1)
 458                 mcr |= UART_MCR_OUT1;
 459         if (mctrl & TIOCM_OUT2)
 460                 mcr |= UART_MCR_OUT2;
 461         if (mctrl & TIOCM_LOOP)
 462                 mcr |= UART_MCR_LOOP;
 463
 464         pm_runtime_get_sync(up->dev);
 465         up->mcr = serial_in(up, UART_MCR);
 466         up->mcr |= mcr;
 467         serial_out(up, UART_MCR, up->mcr);
 468         pm_runtime_mark_last_busy(up->dev);
 469         pm_runtime_put_autosuspend(up->dev);
 470
 471         if (gpio_is_valid(up->DTR_gpio) &&
 472             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 473                 up->DTR_active = !up->DTR_active;
 474                 if (gpio_cansleep(up->DTR_gpio))
 475                         schedule_work(&up->qos_work);
 476                 else
 477                         gpio_set_value(up->DTR_gpio,
 478                                        up->DTR_active != up->DTR_inverted);
 479         }
 480 }
 481
 482 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 483 {
 484         struct uart_omap_port *up = to_uart_omap_port(port);
 485         unsigned long flags = 0;
 486
 487         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 488         pm_runtime_get_sync(up->dev);
 489         spin_lock_irqsave(&up->port.lock, flags);
 490         if (break_state == -1)
 491                 up->lcr |= UART_LCR_SBC;
 492         else
 493                 up->lcr &= ~UART_LCR_SBC;
 494         serial_out(up, UART_LCR, up->lcr);
 495         spin_unlock_irqrestore(&up->port.lock, flags);
 496         pm_runtime_mark_last_busy(up->dev);
 497         pm_runtime_put_autosuspend(up->dev);
 498 }
 499
 500 static int serial_omap_startup(struct uart_port *port)
 501 {
 502         struct uart_omap_port *up = to_uart_omap_port(port);
 503         unsigned long flags = 0;
 504         int retval;
 505
 506         /*
 507          * Allocate the IRQ
 508          */
 509         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 510                                 up->name, up);
 511         if (retval)
 512                 return retval;
 513
 514         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 515
 516         pm_runtime_get_sync(up->dev);
 517         /*
 518          * Clear the FIFO buffers and disable them.
 519          * (they will be reenabled in set_termios())
 520          */
 521         serial_omap_clear_fifos(up);
 522         /* For Hardware flow control */
 523         serial_out(up, UART_MCR, UART_MCR_RTS);
 524
 525         /*
 526          * Clear the interrupt registers.
 527          */
 528         (void) serial_in(up, UART_LSR);
 529         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 530                 (void) serial_in(up, UART_RX);
 531         (void) serial_in(up, UART_IIR);
 532         (void) serial_in(up, UART_MSR);
 533
 534         /*
 535          * Now, initialize the UART
 536          */
 537         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 538         spin_lock_irqsave(&up->port.lock, flags);
 539         /*
 540          * Most PC uarts need OUT2 raised to enable interrupts.
 541          */
 542         up->port.mctrl |= TIOCM_OUT2;
 543         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 544         spin_unlock_irqrestore(&up->port.lock, flags);
 545
 546         up->msr_saved_flags = 0;
 547         /*
 548          * Finally, enable interrupts. Note: Modem status interrupts
 549          * are set via set_termios(), which will be occurring imminently
 550          * anyway, so we don't enable them here.
 551          */
 552         up->ier = UART_IER_RLSI | UART_IER_RDI;
 553         serial_out(up, UART_IER, up->ier);
 554
 555         /* Enable module level wake up */
 556         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 557
 558         pm_runtime_mark_last_busy(up->dev);
 559         pm_runtime_put_autosuspend(up->dev);
 560         up->port_activity = jiffies;
 561         return 0;
 562 }
 563
 564 static void serial_omap_shutdown(struct uart_port *port)
 565 {
 566         struct uart_omap_port *up = to_uart_omap_port(port);
 567         unsigned long flags = 0;
 568
 569         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 570
 571         pm_runtime_get_sync(up->dev);
 572         /*
 573          * Disable interrupts from this port
 574          */
 575         up->ier = 0;
 576         serial_out(up, UART_IER, 0);
 577
 578         spin_lock_irqsave(&up->port.lock, flags);
 579         up->port.mctrl &= ~TIOCM_OUT2;
 580         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 581         spin_unlock_irqrestore(&up->port.lock, flags);
 582
 583         /*
 584          * Disable break condition and FIFOs
 585          */
 586         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 587         serial_omap_clear_fifos(up);
 588
 589         /*
 590          * Read data port to reset things, and then free the irq
 591          */
 592         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 593                 (void) serial_in(up, UART_RX);
 594
 595         pm_runtime_mark_last_busy(up->dev);
 596         pm_runtime_put_autosuspend(up->dev);
 597         free_irq(up->port.irq, up);
 598 }
 599
 600 static inline void
 601 serial_omap_configure_xonxoff
 602                 (struct uart_omap_port *up, struct ktermios *termios)
 603 {
 604         up->lcr = serial_in(up, UART_LCR);
 605         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 606         up->efr = serial_in(up, UART_EFR);
 607         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
 608
 609         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 610         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 611
 612         /* clear SW control mode bits */
 613         up->efr &= OMAP_UART_SW_CLR;
 614
 615         /*
 616          * IXON Flag:
 617          * Enable XON/XOFF flow control on output.
 618          * Transmit XON1, XOFF1
 619          */
 620         if (termios->c_iflag & IXON)
 621                 up->efr |= OMAP_UART_SW_TX;
 622
 623         /*
 624          * IXOFF Flag:
 625          * Enable XON/XOFF flow control on input.
 626          * Receiver compares XON1, XOFF1.
 627          */
 628         if (termios->c_iflag & IXOFF)
 629                 up->efr |= OMAP_UART_SW_RX;
 630
 631         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 632         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 633
 634         up->mcr = serial_in(up, UART_MCR);
 635
 636         /*
 637          * IXANY Flag:
 638          * Enable any character to restart output.
 639          * Operation resumes after receiving any
 640          * character after recognition of the XOFF character
 641          */
 642         if (termios->c_iflag & IXANY)
 643                 up->mcr |= UART_MCR_XONANY;
 644
 645         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 646         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 647         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 648         /* Enable special char function UARTi.EFR_REG[5] and
 649          * load the new software flow control mode IXON or IXOFF
 650          * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
 651          */
 652         serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
 653         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 654
 655         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
 656         serial_out(up, UART_LCR, up->lcr);
 657 }
 658
 659 static void serial_omap_uart_qos_work(struct work_struct *work)
 660 {
 661         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 662                                                 qos_work);
 663
 664         pm_qos_update_request(&up->pm_qos_request, up->latency);
 665         if (gpio_is_valid(up->DTR_gpio))
 666                 gpio_set_value_cansleep(up->DTR_gpio,
 667                                         up->DTR_active != up->DTR_inverted);
 668 }
 669
 670 static void
 671 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 672                         struct ktermios *old)
 673 {
 674         struct uart_omap_port *up = to_uart_omap_port(port);
 675         unsigned char cval = 0;
 676         unsigned char efr = 0;
 677         unsigned long flags = 0;
 678         unsigned int baud, quot;
 679
 680         switch (termios->c_cflag & CSIZE) {
 681         case CS5:
 682                 cval = UART_LCR_WLEN5;
 683                 break;
 684         case CS6:
 685                 cval = UART_LCR_WLEN6;
 686                 break;
 687         case CS7:
 688                 cval = UART_LCR_WLEN7;
 689                 break;
 690         default:
 691         case CS8:
 692                 cval = UART_LCR_WLEN8;
 693                 break;
 694         }
 695
 696         if (termios->c_cflag & CSTOPB)
 697                 cval |= UART_LCR_STOP;
 698         if (termios->c_cflag & PARENB)
 699                 cval |= UART_LCR_PARITY;
 700         if (!(termios->c_cflag & PARODD))
 701                 cval |= UART_LCR_EPAR;
 702
 703         /*
 704          * Ask the core to calculate the divisor for us.
 705          */
 706
 707         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 708         quot = serial_omap_get_divisor(port, baud);
 709
 710         /* calculate wakeup latency constraint */
 711         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 712         up->latency = up->calc_latency;
 713         schedule_work(&up->qos_work);
 714
 715         up->dll = quot & 0xff;
 716         up->dlh = quot >> 8;
 717         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 718
 719         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 720                         UART_FCR_ENABLE_FIFO;
 721
 722         /*
 723          * Ok, we're now changing the port state. Do it with
 724          * interrupts disabled.
 725          */
 726         pm_runtime_get_sync(up->dev);
 727         spin_lock_irqsave(&up->port.lock, flags);
 728
 729         /*
 730          * Update the per-port timeout.
 731          */
 732         uart_update_timeout(port, termios->c_cflag, baud);
 733
 734         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 735         if (termios->c_iflag & INPCK)
 736                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 737         if (termios->c_iflag & (BRKINT | PARMRK))
 738                 up->port.read_status_mask |= UART_LSR_BI;
 739
 740         /*
 741          * Characters to ignore
 742          */
 743         up->port.ignore_status_mask = 0;
 744         if (termios->c_iflag & IGNPAR)
 745                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 746         if (termios->c_iflag & IGNBRK) {
 747                 up->port.ignore_status_mask |= UART_LSR_BI;
 748                 /*
 749                  * If we're ignoring parity and break indicators,
 750                  * ignore overruns too (for real raw support).
 751                  */
 752                 if (termios->c_iflag & IGNPAR)
 753                         up->port.ignore_status_mask |= UART_LSR_OE;
 754         }
 755
 756         /*
 757          * ignore all characters if CREAD is not set
 758          */
 759         if ((termios->c_cflag & CREAD) == 0)
 760                 up->port.ignore_status_mask |= UART_LSR_DR;
 761
 762         /*
 763          * Modem status interrupts
 764          */
 765         up->ier &= ~UART_IER_MSI;
 766         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 767                 up->ier |= UART_IER_MSI;
 768         serial_out(up, UART_IER, up->ier);
 769         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 770         up->lcr = cval;
 771         up->scr = OMAP_UART_SCR_TX_EMPTY;
 772
 773         /* FIFOs and DMA Settings */
 774
 775         /* FCR can be changed only when the
 776          * baud clock is not running
 777          * DLL_REG and DLH_REG set to 0.
 778          */
 779         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 780         serial_out(up, UART_DLL, 0);
 781         serial_out(up, UART_DLM, 0);
 782         serial_out(up, UART_LCR, 0);
 783
 784         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 785
 786         up->efr = serial_in(up, UART_EFR);
 787         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 788
 789         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 790         up->mcr = serial_in(up, UART_MCR);
 791         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 792         /* FIFO ENABLE, DMA MODE */
 793
 794         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 795
 796         /* Set receive FIFO threshold to 1 byte */
 797         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 798         up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
 799
 800         serial_out(up, UART_FCR, up->fcr);
 801         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 802
 803         serial_out(up, UART_OMAP_SCR, up->scr);
 804
 805         serial_out(up, UART_EFR, up->efr);
 806         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 807         serial_out(up, UART_MCR, up->mcr);
 808
 809         /* Protocol, Baud Rate, and Interrupt Settings */
 810
 811         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 812                 serial_omap_mdr1_errataset(up, up->mdr1);
 813         else
 814                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 815
 816         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 817
 818         up->efr = serial_in(up, UART_EFR);
 819         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 820
 821         serial_out(up, UART_LCR, 0);
 822         serial_out(up, UART_IER, 0);
 823         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 824
 825         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 826         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 827
 828         serial_out(up, UART_LCR, 0);
 829         serial_out(up, UART_IER, up->ier);
 830         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 831
 832         serial_out(up, UART_EFR, up->efr);
 833         serial_out(up, UART_LCR, cval);
 834
 835         if (baud > 230400 && baud != 3000000)
 836                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 837         else
 838                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 839
 840         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 841                 serial_omap_mdr1_errataset(up, up->mdr1);
 842         else
 843                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 844
 845         /* Hardware Flow Control Configuration */
 846
 847         if (termios->c_cflag & CRTSCTS) {
 848                 efr |= (UART_EFR_CTS | UART_EFR_RTS);
 849                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 850
 851                 up->mcr = serial_in(up, UART_MCR);
 852                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 853
 854                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 855                 up->efr = serial_in(up, UART_EFR);
 856                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 857
 858                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 859                 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
 860                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 861                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
 862                 serial_out(up, UART_LCR, cval);
 863         }
 864
 865         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 866         /* Software Flow Control Configuration */
 867         serial_omap_configure_xonxoff(up, termios);
 868
 869         spin_unlock_irqrestore(&up->port.lock, flags);
 870         pm_runtime_mark_last_busy(up->dev);
 871         pm_runtime_put_autosuspend(up->dev);
 872         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 873 }
 874
 875 static void
 876 serial_omap_pm(struct uart_port *port, unsigned int state,
 877                unsigned int oldstate)
 878 {
 879         struct uart_omap_port *up = to_uart_omap_port(port);
 880         unsigned char efr;
 881
 882         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 883
 884         pm_runtime_get_sync(up->dev);
 885         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 886         efr = serial_in(up, UART_EFR);
 887         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 888         serial_out(up, UART_LCR, 0);
 889
 890         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 891         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 892         serial_out(up, UART_EFR, efr);
 893         serial_out(up, UART_LCR, 0);
 894
 895         if (!device_may_wakeup(up->dev)) {
 896                 if (!state)
 897                         pm_runtime_forbid(up->dev);
 898                 else
 899                         pm_runtime_allow(up->dev);
 900         }
 901
 902         pm_runtime_mark_last_busy(up->dev);
 903         pm_runtime_put_autosuspend(up->dev);
 904 }
 905
 906 static void serial_omap_release_port(struct uart_port *port)
 907 {
 908         dev_dbg(port->dev, "serial_omap_release_port+\n");
 909 }
 910
 911 static int serial_omap_request_port(struct uart_port *port)
 912 {
 913         dev_dbg(port->dev, "serial_omap_request_port+\n");
 914         return 0;
 915 }
 916
 917 static void serial_omap_config_port(struct uart_port *port, int flags)
 918 {
 919         struct uart_omap_port *up = to_uart_omap_port(port);
 920
 921         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 922                                                         up->port.line);
 923         up->port.type = PORT_OMAP;
 924 }
 925
 926 static int
 927 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 928 {
 929         /* we don't want the core code to modify any port params */
 930         dev_dbg(port->dev, "serial_omap_verify_port+\n");
 931         return -EINVAL;
 932 }
 933
 934 static const char *
 935 serial_omap_type(struct uart_port *port)
 936 {
 937         struct uart_omap_port *up = to_uart_omap_port(port);
 938
 939         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
 940         return up->name;
 941 }
 942
 943 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 944
 945 static inline void wait_for_xmitr(struct uart_omap_port *up)
 946 {
 947         unsigned int status, tmout = 10000;
 948
 949         /* Wait up to 10ms for the character(s) to be sent. */
 950         do {
 951                 status = serial_in(up, UART_LSR);
 952
 953                 if (status & UART_LSR_BI)
 954                         up->lsr_break_flag = UART_LSR_BI;
 955
 956                 if (--tmout == 0)
 957                         break;
 958                 udelay(1);
 959         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
 960
 961         /* Wait up to 1s for flow control if necessary */
 962         if (up->port.flags & UPF_CONS_FLOW) {
 963                 tmout = 1000000;
 964                 for (tmout = 1000000; tmout; tmout--) {
 965                         unsigned int msr = serial_in(up, UART_MSR);
 966
 967                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
 968                         if (msr & UART_MSR_CTS)
 969                                 break;
 970
 971                         udelay(1);
 972                 }
 973         }
 974 }
 975
 976 #ifdef CONFIG_CONSOLE_POLL
 977
 978 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 979 {
 980         struct uart_omap_port *up = to_uart_omap_port(port);
 981
 982         pm_runtime_get_sync(up->dev);
 983         wait_for_xmitr(up);
 984         serial_out(up, UART_TX, ch);
 985         pm_runtime_mark_last_busy(up->dev);
 986         pm_runtime_put_autosuspend(up->dev);
 987 }
 988
 989 static int serial_omap_poll_get_char(struct uart_port *port)
 990 {
 991         struct uart_omap_port *up = to_uart_omap_port(port);
 992         unsigned int status;
 993
 994         pm_runtime_get_sync(up->dev);
 995         status = serial_in(up, UART_LSR);
 996         if (!(status & UART_LSR_DR))
 997                 return NO_POLL_CHAR;
 998
 999         status = serial_in(up, UART_RX);
1000         pm_runtime_mark_last_busy(up->dev);
1001         pm_runtime_put_autosuspend(up->dev);
1002         return status;
1003 }
1004
1005 #endif /* CONFIG_CONSOLE_POLL */
1006
1007 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1008
1009 static struct uart_omap_port *serial_omap_console_ports[4];
1010
1011 static struct uart_driver serial_omap_reg;
1012
1013 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1014 {
1015         struct uart_omap_port *up = to_uart_omap_port(port);
1016
1017         wait_for_xmitr(up);
1018         serial_out(up, UART_TX, ch);
1019 }
1020
1021 static void
1022 serial_omap_console_write(struct console *co, const char *s,
1023                 unsigned int count)
1024 {
1025         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1026         unsigned long flags;
1027         unsigned int ier;
1028         int locked = 1;
1029
1030         pm_runtime_get_sync(up->dev);
1031
1032         local_irq_save(flags);
1033         if (up->port.sysrq)
1034                 locked = 0;
1035         else if (oops_in_progress)
1036                 locked = spin_trylock(&up->port.lock);
1037         else
1038                 spin_lock(&up->port.lock);
1039
1040         /*
1041          * First save the IER then disable the interrupts
1042          */
1043         ier = serial_in(up, UART_IER);
1044         serial_out(up, UART_IER, 0);
1045
1046         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1047
1048         /*
1049          * Finally, wait for transmitter to become empty
1050          * and restore the IER
1051          */
1052         wait_for_xmitr(up);
1053         serial_out(up, UART_IER, ier);
1054         /*
1055          * The receive handling will happen properly because the
1056          * receive ready bit will still be set; it is not cleared
1057          * on read.  However, modem control will not, we must
1058          * call it if we have saved something in the saved flags
1059          * while processing with interrupts off.
1060          */
1061         if (up->msr_saved_flags)
1062                 check_modem_status(up);
1063
1064         pm_runtime_mark_last_busy(up->dev);
1065         pm_runtime_put_autosuspend(up->dev);
1066         if (locked)
1067                 spin_unlock(&up->port.lock);
1068         local_irq_restore(flags);
1069 }
1070
1071 static int __init
1072 serial_omap_console_setup(struct console *co, char *options)
1073 {
1074         struct uart_omap_port *up;
1075         int baud = 115200;
1076         int bits = 8;
1077         int parity = 'n';
1078         int flow = 'n';
1079
1080         if (serial_omap_console_ports[co->index] == NULL)
1081                 return -ENODEV;
1082         up = serial_omap_console_ports[co->index];
1083
1084         if (options)
1085                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1086
1087         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1088 }
1089
1090 static struct console serial_omap_console = {
1091         .name           = OMAP_SERIAL_NAME,
1092         .write          = serial_omap_console_write,
1093         .device         = uart_console_device,
1094         .setup          = serial_omap_console_setup,
1095         .flags          = CON_PRINTBUFFER,
1096         .index          = -1,
1097         .data           = &serial_omap_reg,
1098 };
1099
1100 static void serial_omap_add_console_port(struct uart_omap_port *up)
1101 {
1102         serial_omap_console_ports[up->port.line] = up;
1103 }
1104
1105 #define OMAP_CONSOLE    (&serial_omap_console)
1106
1107 #else
1108
1109 #define OMAP_CONSOLE    NULL
1110
1111 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1112 {}
1113
1114 #endif
1115
1116 static struct uart_ops serial_omap_pops = {
1117         .tx_empty       = serial_omap_tx_empty,
1118         .set_mctrl      = serial_omap_set_mctrl,
1119         .get_mctrl      = serial_omap_get_mctrl,
1120         .stop_tx        = serial_omap_stop_tx,
1121         .start_tx       = serial_omap_start_tx,
1122         .stop_rx        = serial_omap_stop_rx,
1123         .enable_ms      = serial_omap_enable_ms,
1124         .break_ctl      = serial_omap_break_ctl,
1125         .startup        = serial_omap_startup,
1126         .shutdown       = serial_omap_shutdown,
1127         .set_termios    = serial_omap_set_termios,
1128         .pm             = serial_omap_pm,
1129         .type           = serial_omap_type,
1130         .release_port   = serial_omap_release_port,
1131         .request_port   = serial_omap_request_port,
1132         .config_port    = serial_omap_config_port,
1133         .verify_port    = serial_omap_verify_port,
1134 #ifdef CONFIG_CONSOLE_POLL
1135         .poll_put_char  = serial_omap_poll_put_char,
1136         .poll_get_char  = serial_omap_poll_get_char,
1137 #endif
1138 };
1139
1140 static struct uart_driver serial_omap_reg = {
1141         .owner          = THIS_MODULE,
1142         .driver_name    = "OMAP-SERIAL",
1143         .dev_name       = OMAP_SERIAL_NAME,
1144         .nr             = OMAP_MAX_HSUART_PORTS,
1145         .cons           = OMAP_CONSOLE,
1146 };
1147
1148 #ifdef CONFIG_PM_SLEEP
1149 static int serial_omap_suspend(struct device *dev)
1150 {
1151         struct uart_omap_port *up = dev_get_drvdata(dev);
1152
1153         if (up) {
1154                 uart_suspend_port(&serial_omap_reg, &up->port);
1155                 flush_work_sync(&up->qos_work);
1156         }
1157
1158         return 0;
1159 }
1160
1161 static int serial_omap_resume(struct device *dev)
1162 {
1163         struct uart_omap_port *up = dev_get_drvdata(dev);
1164
1165         if (up)
1166                 uart_resume_port(&serial_omap_reg, &up->port);
1167         return 0;
1168 }
1169 #endif
1170
1171 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1172 {
1173         u32 mvr, scheme;
1174         u16 revision, major, minor;
1175
1176         mvr = serial_in(up, UART_OMAP_MVER);
1177
1178         /* Check revision register scheme */
1179         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1180
1181         switch (scheme) {
1182         case 0: /* Legacy Scheme: OMAP2/3 */
1183                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1184                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1185                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1186                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1187                 break;
1188         case 1:
1189                 /* New Scheme: OMAP4+ */
1190                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1191                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1192                                         OMAP_UART_MVR_MAJ_SHIFT;
1193                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1194                 break;
1195         default:
1196                 dev_warn(up->dev,
1197                         "Unknown %s revision, defaulting to highest\n",
1198                         up->name);
1199                 /* highest possible revision */
1200                 major = 0xff;
1201                 minor = 0xff;
1202         }
1203
1204         /* normalize revision for the driver */
1205         revision = UART_BUILD_REVISION(major, minor);
1206
1207         switch (revision) {
1208         case OMAP_UART_REV_46:
1209                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1210                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1211                 break;
1212         case OMAP_UART_REV_52:
1213                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1214                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1215                 break;
1216         case OMAP_UART_REV_63:
1217                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1218                 break;
1219         default:
1220                 break;
1221         }
1222 }
1223
1224 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1225 {
1226         struct omap_uart_port_info *omap_up_info;
1227
1228         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1229         if (!omap_up_info)
1230                 return NULL; /* out of memory */
1231
1232         of_property_read_u32(dev->of_node, "clock-frequency",
1233                                          &omap_up_info->uartclk);
1234         return omap_up_info;
1235 }
1236
1237 static int serial_omap_probe(struct platform_device *pdev)
1238 {
1239         struct uart_omap_port   *up;
1240         struct resource         *mem, *irq;
1241         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1242         int ret;
1243
1244         if (pdev->dev.of_node)
1245                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1246
1247         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1248         if (!mem) {
1249                 dev_err(&pdev->dev, "no mem resource?\n");
1250                 return -ENODEV;
1251         }
1252
1253         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1254         if (!irq) {
1255                 dev_err(&pdev->dev, "no irq resource?\n");
1256                 return -ENODEV;
1257         }
1258
1259         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1260                                 pdev->dev.driver->name)) {
1261                 dev_err(&pdev->dev, "memory region already claimed\n");
1262                 return -EBUSY;
1263         }
1264
1265         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1266             omap_up_info->DTR_present) {
1267                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1268                 if (ret < 0)
1269                         return ret;
1270                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1271                                             omap_up_info->DTR_inverted);
1272                 if (ret < 0)
1273                         return ret;
1274         }
1275
1276         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1277         if (!up)
1278                 return -ENOMEM;
1279
1280         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1281             omap_up_info->DTR_present) {
1282                 up->DTR_gpio = omap_up_info->DTR_gpio;
1283                 up->DTR_inverted = omap_up_info->DTR_inverted;
1284         } else
1285                 up->DTR_gpio = -EINVAL;
1286         up->DTR_active = 0;
1287
1288         up->dev = &pdev->dev;
1289         up->port.dev = &pdev->dev;
1290         up->port.type = PORT_OMAP;
1291         up->port.iotype = UPIO_MEM;
1292         up->port.irq = irq->start;
1293
1294         up->port.regshift = 2;
1295         up->port.fifosize = 64;
1296         up->port.ops = &serial_omap_pops;
1297
1298         if (pdev->dev.of_node)
1299                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1300         else
1301                 up->port.line = pdev->id;
1302
1303         if (up->port.line < 0) {
1304                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1305                                                                 up->port.line);
1306                 ret = -ENODEV;
1307                 goto err_port_line;
1308         }
1309
1310         sprintf(up->name, "OMAP UART%d", up->port.line);
1311         up->port.mapbase = mem->start;
1312         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1313                                                 resource_size(mem));
1314         if (!up->port.membase) {
1315                 dev_err(&pdev->dev, "can't ioremap UART\n");
1316                 ret = -ENOMEM;
1317                 goto err_ioremap;
1318         }
1319
1320         up->port.flags = omap_up_info->flags;
1321         up->port.uartclk = omap_up_info->uartclk;
1322         if (!up->port.uartclk) {
1323                 up->port.uartclk = DEFAULT_CLK_SPEED;
1324                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1325                                                 "%d\n", DEFAULT_CLK_SPEED);
1326         }
1327
1328         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1329         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1330         pm_qos_add_request(&up->pm_qos_request,
1331                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1332         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1333         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1334
1335         platform_set_drvdata(pdev, up);
1336         pm_runtime_use_autosuspend(&pdev->dev);
1337         pm_runtime_set_autosuspend_delay(&pdev->dev,
1338                         omap_up_info->autosuspend_timeout);
1339
1340         pm_runtime_irq_safe(&pdev->dev);
1341         pm_runtime_enable(&pdev->dev);
1342         pm_runtime_get_sync(&pdev->dev);
1343
1344         omap_serial_fill_features_erratas(up);
1345
1346         ui[up->port.line] = up;
1347         serial_omap_add_console_port(up);
1348
1349         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1350         if (ret != 0)
1351                 goto err_add_port;
1352
1353         pm_runtime_mark_last_busy(up->dev);
1354         pm_runtime_put_autosuspend(up->dev);
1355         return 0;
1356
1357 err_add_port:
1358         pm_runtime_put(&pdev->dev);
1359         pm_runtime_disable(&pdev->dev);
1360 err_ioremap:
1361 err_port_line:
1362         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1363                                 pdev->id, __func__, ret);
1364         return ret;
1365 }
1366
1367 static int serial_omap_remove(struct platform_device *dev)
1368 {
1369         struct uart_omap_port *up = platform_get_drvdata(dev);
1370
1371         pm_runtime_put_sync(up->dev);
1372         pm_runtime_disable(up->dev);
1373         uart_remove_one_port(&serial_omap_reg, &up->port);
1374         pm_qos_remove_request(&up->pm_qos_request);
1375
1376         return 0;
1377 }
1378
1379 /*
1380  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1381  * The access to uart register after MDR1 Access
1382  * causes UART to corrupt data.
1383  *
1384  * Need a delay =
1385  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1386  * give 10 times as much
1387  */
1388 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1389 {
1390         u8 timeout = 255;
1391
1392         serial_out(up, UART_OMAP_MDR1, mdr1);
1393         udelay(2);
1394         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1395                         UART_FCR_CLEAR_RCVR);
1396         /*
1397          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1398          * TX_FIFO_E bit is 1.
1399          */
1400         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1401                                 (UART_LSR_THRE | UART_LSR_DR))) {
1402                 timeout--;
1403                 if (!timeout) {
1404                         /* Should *never* happen. we warn and carry on */
1405                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1406                                                 serial_in(up, UART_LSR));
1407                         break;
1408                 }
1409                 udelay(1);
1410         }
1411 }
1412
1413 #ifdef CONFIG_PM_RUNTIME
1414 static void serial_omap_restore_context(struct uart_omap_port *up)
1415 {
1416         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1417                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1418         else
1419                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1420
1421         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1422         serial_out(up, UART_EFR, UART_EFR_ECB);
1423         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1424         serial_out(up, UART_IER, 0x0);
1425         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1426         serial_out(up, UART_DLL, up->dll);
1427         serial_out(up, UART_DLM, up->dlh);
1428         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1429         serial_out(up, UART_IER, up->ier);
1430         serial_out(up, UART_FCR, up->fcr);
1431         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1432         serial_out(up, UART_MCR, up->mcr);
1433         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1434         serial_out(up, UART_OMAP_SCR, up->scr);
1435         serial_out(up, UART_EFR, up->efr);
1436         serial_out(up, UART_LCR, up->lcr);
1437         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1438                 serial_omap_mdr1_errataset(up, up->mdr1);
1439         else
1440                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1441 }
1442
1443 static int serial_omap_runtime_suspend(struct device *dev)
1444 {
1445         struct uart_omap_port *up = dev_get_drvdata(dev);
1446         struct omap_uart_port_info *pdata = dev->platform_data;
1447
1448         if (!up)
1449                 return -EINVAL;
1450
1451         if (!pdata)
1452                 return 0;
1453
1454         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1455
1456         if (device_may_wakeup(dev)) {
1457                 if (!up->wakeups_enabled) {
1458                         serial_omap_enable_wakeup(up, true);
1459                         up->wakeups_enabled = true;
1460                 }
1461         } else {
1462                 if (up->wakeups_enabled) {
1463                         serial_omap_enable_wakeup(up, false);
1464                         up->wakeups_enabled = false;
1465                 }
1466         }
1467
1468         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1469         schedule_work(&up->qos_work);
1470
1471         return 0;
1472 }
1473
1474 static int serial_omap_runtime_resume(struct device *dev)
1475 {
1476         struct uart_omap_port *up = dev_get_drvdata(dev);
1477         struct omap_uart_port_info *pdata = dev->platform_data;
1478
1479         if (up && pdata) {
1480                         u32 loss_cnt = serial_omap_get_context_loss_count(up);
1481
1482                         if (up->context_loss_cnt != loss_cnt)
1483                                 serial_omap_restore_context(up);
1484
1485                 up->latency = up->calc_latency;
1486                 schedule_work(&up->qos_work);
1487         }
1488
1489         return 0;
1490 }
1491 #endif
1492
1493 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1494         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1495         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1496                                 serial_omap_runtime_resume, NULL)
1497 };
1498
1499 #if defined(CONFIG_OF)
1500 static const struct of_device_id omap_serial_of_match[] = {
1501         { .compatible = "ti,omap2-uart" },
1502         { .compatible = "ti,omap3-uart" },
1503         { .compatible = "ti,omap4-uart" },
1504         {},
1505 };
1506 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1507 #endif
1508
1509 static struct platform_driver serial_omap_driver = {
1510         .probe          = serial_omap_probe,
1511         .remove         = serial_omap_remove,
1512         .driver         = {
1513                 .name   = DRIVER_NAME,
1514                 .pm     = &serial_omap_dev_pm_ops,
1515                 .of_match_table = of_match_ptr(omap_serial_of_match),
1516         },
1517 };
1518
1519 static int __init serial_omap_init(void)
1520 {
1521         int ret;
1522
1523         ret = uart_register_driver(&serial_omap_reg);
1524         if (ret != 0)
1525                 return ret;
1526         ret = platform_driver_register(&serial_omap_driver);
1527         if (ret != 0)
1528                 uart_unregister_driver(&serial_omap_reg);
1529         return ret;
1530 }
1531
1532 static void __exit serial_omap_exit(void)
1533 {
1534         platform_driver_unregister(&serial_omap_driver);
1535         uart_unregister_driver(&serial_omap_reg);
1536 }
1537
1538 module_init(serial_omap_init);
1539 module_exit(serial_omap_exit);
1540
1541 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1542 MODULE_LICENSE("GPL");
1543 MODULE_AUTHOR("Texas Instruments Inc");