2 * Freescale STMP37XX/STMP378X Application UART driver
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/console.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25 #include <linux/tty.h>
26 #include <linux/tty_driver.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/device.h>
32 #include <linux/clk.h>
33 #include <linux/delay.h>
36 #include <asm/cacheflush.h>
38 #define MXS_AUART_PORTS 5
40 #define AUART_CTRL0 0x00000000
41 #define AUART_CTRL0_SET 0x00000004
42 #define AUART_CTRL0_CLR 0x00000008
43 #define AUART_CTRL0_TOG 0x0000000c
44 #define AUART_CTRL1 0x00000010
45 #define AUART_CTRL1_SET 0x00000014
46 #define AUART_CTRL1_CLR 0x00000018
47 #define AUART_CTRL1_TOG 0x0000001c
48 #define AUART_CTRL2 0x00000020
49 #define AUART_CTRL2_SET 0x00000024
50 #define AUART_CTRL2_CLR 0x00000028
51 #define AUART_CTRL2_TOG 0x0000002c
52 #define AUART_LINECTRL 0x00000030
53 #define AUART_LINECTRL_SET 0x00000034
54 #define AUART_LINECTRL_CLR 0x00000038
55 #define AUART_LINECTRL_TOG 0x0000003c
56 #define AUART_LINECTRL2 0x00000040
57 #define AUART_LINECTRL2_SET 0x00000044
58 #define AUART_LINECTRL2_CLR 0x00000048
59 #define AUART_LINECTRL2_TOG 0x0000004c
60 #define AUART_INTR 0x00000050
61 #define AUART_INTR_SET 0x00000054
62 #define AUART_INTR_CLR 0x00000058
63 #define AUART_INTR_TOG 0x0000005c
64 #define AUART_DATA 0x00000060
65 #define AUART_STAT 0x00000070
66 #define AUART_DEBUG 0x00000080
67 #define AUART_VERSION 0x00000090
68 #define AUART_AUTOBAUD 0x000000a0
70 #define AUART_CTRL0_SFTRST (1 << 31)
71 #define AUART_CTRL0_CLKGATE (1 << 30)
73 #define AUART_CTRL2_CTSEN (1 << 15)
74 #define AUART_CTRL2_RTS (1 << 11)
75 #define AUART_CTRL2_RXE (1 << 9)
76 #define AUART_CTRL2_TXE (1 << 8)
77 #define AUART_CTRL2_UARTEN (1 << 0)
79 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
80 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
81 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
82 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
83 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
84 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
85 #define AUART_LINECTRL_WLEN_MASK 0x00000060
86 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
87 #define AUART_LINECTRL_FEN (1 << 4)
88 #define AUART_LINECTRL_STP2 (1 << 3)
89 #define AUART_LINECTRL_EPS (1 << 2)
90 #define AUART_LINECTRL_PEN (1 << 1)
91 #define AUART_LINECTRL_BRK (1 << 0)
93 #define AUART_INTR_RTIEN (1 << 22)
94 #define AUART_INTR_TXIEN (1 << 21)
95 #define AUART_INTR_RXIEN (1 << 20)
96 #define AUART_INTR_CTSMIEN (1 << 17)
97 #define AUART_INTR_RTIS (1 << 6)
98 #define AUART_INTR_TXIS (1 << 5)
99 #define AUART_INTR_RXIS (1 << 4)
100 #define AUART_INTR_CTSMIS (1 << 1)
102 #define AUART_STAT_BUSY (1 << 29)
103 #define AUART_STAT_CTS (1 << 28)
104 #define AUART_STAT_TXFE (1 << 27)
105 #define AUART_STAT_TXFF (1 << 25)
106 #define AUART_STAT_RXFE (1 << 24)
107 #define AUART_STAT_OERR (1 << 19)
108 #define AUART_STAT_BERR (1 << 18)
109 #define AUART_STAT_PERR (1 << 17)
110 #define AUART_STAT_FERR (1 << 16)
112 static struct uart_driver auart_driver;
114 struct mxs_auart_port {
115 struct uart_port port;
126 static void mxs_auart_stop_tx(struct uart_port *u);
128 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
130 static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
132 struct circ_buf *xmit = &s->port.state->xmit;
134 while (!(readl(s->port.membase + AUART_STAT) &
136 if (s->port.x_char) {
138 writel(s->port.x_char,
139 s->port.membase + AUART_DATA);
143 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
145 writel(xmit->buf[xmit->tail],
146 s->port.membase + AUART_DATA);
147 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
148 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
149 uart_write_wakeup(&s->port);
153 if (uart_circ_empty(&(s->port.state->xmit)))
154 writel(AUART_INTR_TXIEN,
155 s->port.membase + AUART_INTR_CLR);
157 writel(AUART_INTR_TXIEN,
158 s->port.membase + AUART_INTR_SET);
160 if (uart_tx_stopped(&s->port))
161 mxs_auart_stop_tx(&s->port);
164 static void mxs_auart_rx_char(struct mxs_auart_port *s)
170 c = readl(s->port.membase + AUART_DATA);
171 stat = readl(s->port.membase + AUART_STAT);
176 if (stat & AUART_STAT_BERR) {
177 s->port.icount.brk++;
178 if (uart_handle_break(&s->port))
180 } else if (stat & AUART_STAT_PERR) {
181 s->port.icount.parity++;
182 } else if (stat & AUART_STAT_FERR) {
183 s->port.icount.frame++;
187 * Mask off conditions which should be ingored.
189 stat &= s->port.read_status_mask;
191 if (stat & AUART_STAT_BERR) {
193 } else if (stat & AUART_STAT_PERR)
195 else if (stat & AUART_STAT_FERR)
198 if (stat & AUART_STAT_OERR)
199 s->port.icount.overrun++;
201 if (uart_handle_sysrq_char(&s->port, c))
204 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
206 writel(stat, s->port.membase + AUART_STAT);
209 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
211 struct tty_struct *tty = s->port.state->port.tty;
215 stat = readl(s->port.membase + AUART_STAT);
216 if (stat & AUART_STAT_RXFE)
218 mxs_auart_rx_char(s);
221 writel(stat, s->port.membase + AUART_STAT);
222 tty_flip_buffer_push(tty);
225 static int mxs_auart_request_port(struct uart_port *u)
230 static int mxs_auart_verify_port(struct uart_port *u,
231 struct serial_struct *ser)
233 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
238 static void mxs_auart_config_port(struct uart_port *u, int flags)
242 static const char *mxs_auart_type(struct uart_port *u)
244 struct mxs_auart_port *s = to_auart_port(u);
246 return dev_name(s->dev);
249 static void mxs_auart_release_port(struct uart_port *u)
253 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
255 struct mxs_auart_port *s = to_auart_port(u);
257 u32 ctrl = readl(u->membase + AUART_CTRL2);
259 ctrl &= ~AUART_CTRL2_RTS;
260 if (mctrl & TIOCM_RTS)
261 ctrl |= AUART_CTRL2_RTS;
263 writel(ctrl, u->membase + AUART_CTRL2);
266 static u32 mxs_auart_get_mctrl(struct uart_port *u)
268 struct mxs_auart_port *s = to_auart_port(u);
269 u32 stat = readl(u->membase + AUART_STAT);
270 int ctrl2 = readl(u->membase + AUART_CTRL2);
274 if (stat & AUART_STAT_CTS)
277 if (ctrl2 & AUART_CTRL2_RTS)
283 static void mxs_auart_settermios(struct uart_port *u,
284 struct ktermios *termios,
285 struct ktermios *old)
287 u32 bm, ctrl, ctrl2, div;
288 unsigned int cflag, baud;
290 cflag = termios->c_cflag;
292 ctrl = AUART_LINECTRL_FEN;
293 ctrl2 = readl(u->membase + AUART_CTRL2);
296 switch (cflag & CSIZE) {
313 ctrl |= AUART_LINECTRL_WLEN(bm);
316 if (cflag & PARENB) {
317 ctrl |= AUART_LINECTRL_PEN;
318 if ((cflag & PARODD) == 0)
319 ctrl |= AUART_LINECTRL_EPS;
322 u->read_status_mask = 0;
324 if (termios->c_iflag & INPCK)
325 u->read_status_mask |= AUART_STAT_PERR;
326 if (termios->c_iflag & (BRKINT | PARMRK))
327 u->read_status_mask |= AUART_STAT_BERR;
330 * Characters to ignore
332 u->ignore_status_mask = 0;
333 if (termios->c_iflag & IGNPAR)
334 u->ignore_status_mask |= AUART_STAT_PERR;
335 if (termios->c_iflag & IGNBRK) {
336 u->ignore_status_mask |= AUART_STAT_BERR;
338 * If we're ignoring parity and break indicators,
339 * ignore overruns too (for real raw support).
341 if (termios->c_iflag & IGNPAR)
342 u->ignore_status_mask |= AUART_STAT_OERR;
346 * ignore all characters if CREAD is not set
349 ctrl2 |= AUART_CTRL2_RXE;
351 ctrl2 &= ~AUART_CTRL2_RXE;
353 /* figure out the stop bits requested */
355 ctrl |= AUART_LINECTRL_STP2;
357 /* figure out the hardware flow control settings */
359 ctrl2 |= AUART_CTRL2_CTSEN;
361 ctrl2 &= ~AUART_CTRL2_CTSEN;
364 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
365 div = u->uartclk * 32 / baud;
366 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
367 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
369 writel(ctrl, u->membase + AUART_LINECTRL);
370 writel(ctrl2, u->membase + AUART_CTRL2);
372 uart_update_timeout(u, termios->c_cflag, baud);
375 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
378 struct mxs_auart_port *s = context;
379 u32 stat = readl(s->port.membase + AUART_STAT);
381 istat = readl(s->port.membase + AUART_INTR);
384 writel(istat & (AUART_INTR_RTIS
387 | AUART_INTR_CTSMIS),
388 s->port.membase + AUART_INTR_CLR);
390 if (istat & AUART_INTR_CTSMIS) {
391 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
392 writel(AUART_INTR_CTSMIS,
393 s->port.membase + AUART_INTR_CLR);
394 istat &= ~AUART_INTR_CTSMIS;
397 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
398 mxs_auart_rx_chars(s);
399 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
402 if (istat & AUART_INTR_TXIS) {
403 mxs_auart_tx_chars(s);
404 istat &= ~AUART_INTR_TXIS;
410 static void mxs_auart_reset(struct uart_port *u)
415 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
417 for (i = 0; i < 10000; i++) {
418 reg = readl(u->membase + AUART_CTRL0);
419 if (!(reg & AUART_CTRL0_SFTRST))
423 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
426 static int mxs_auart_startup(struct uart_port *u)
428 struct mxs_auart_port *s = to_auart_port(u);
432 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
434 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
436 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
437 u->membase + AUART_INTR);
440 * Enable fifo so all four bytes of a DMA word are written to
441 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
443 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
448 static void mxs_auart_shutdown(struct uart_port *u)
450 struct mxs_auart_port *s = to_auart_port(u);
452 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
454 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
456 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
457 u->membase + AUART_INTR_CLR);
462 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
464 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
470 static void mxs_auart_start_tx(struct uart_port *u)
472 struct mxs_auart_port *s = to_auart_port(u);
474 /* enable transmitter */
475 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
477 mxs_auart_tx_chars(s);
480 static void mxs_auart_stop_tx(struct uart_port *u)
482 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
485 static void mxs_auart_stop_rx(struct uart_port *u)
487 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
490 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
493 writel(AUART_LINECTRL_BRK,
494 u->membase + AUART_LINECTRL_SET);
496 writel(AUART_LINECTRL_BRK,
497 u->membase + AUART_LINECTRL_CLR);
500 static void mxs_auart_enable_ms(struct uart_port *port)
505 static struct uart_ops mxs_auart_ops = {
506 .tx_empty = mxs_auart_tx_empty,
507 .start_tx = mxs_auart_start_tx,
508 .stop_tx = mxs_auart_stop_tx,
509 .stop_rx = mxs_auart_stop_rx,
510 .enable_ms = mxs_auart_enable_ms,
511 .break_ctl = mxs_auart_break_ctl,
512 .set_mctrl = mxs_auart_set_mctrl,
513 .get_mctrl = mxs_auart_get_mctrl,
514 .startup = mxs_auart_startup,
515 .shutdown = mxs_auart_shutdown,
516 .set_termios = mxs_auart_settermios,
517 .type = mxs_auart_type,
518 .release_port = mxs_auart_release_port,
519 .request_port = mxs_auart_request_port,
520 .config_port = mxs_auart_config_port,
521 .verify_port = mxs_auart_verify_port,
524 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
526 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
527 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
529 unsigned int to = 1000;
531 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
537 writel(ch, port->membase + AUART_DATA);
541 auart_console_write(struct console *co, const char *str, unsigned int count)
543 struct mxs_auart_port *s;
544 struct uart_port *port;
545 unsigned int old_ctrl0, old_ctrl2;
546 unsigned int to = 20000;
548 if (co->index > MXS_AUART_PORTS || co->index < 0)
551 s = auart_port[co->index];
556 /* First save the CR then disable the interrupts */
557 old_ctrl2 = readl(port->membase + AUART_CTRL2);
558 old_ctrl0 = readl(port->membase + AUART_CTRL0);
560 writel(AUART_CTRL0_CLKGATE,
561 port->membase + AUART_CTRL0_CLR);
562 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
563 port->membase + AUART_CTRL2_SET);
565 uart_console_write(port, str, count, mxs_auart_console_putchar);
567 /* Finally, wait for transmitter to become empty ... */
568 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
575 * ... and restore the TCR if we waited long enough for the transmitter
576 * to be idle. This might keep the transmitter enabled although it is
577 * unused, but that is better than to disable it while it is still
580 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
581 writel(old_ctrl0, port->membase + AUART_CTRL0);
582 writel(old_ctrl2, port->membase + AUART_CTRL2);
589 auart_console_get_options(struct uart_port *port, int *baud,
590 int *parity, int *bits)
592 unsigned int lcr_h, quot;
594 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
597 lcr_h = readl(port->membase + AUART_LINECTRL);
600 if (lcr_h & AUART_LINECTRL_PEN) {
601 if (lcr_h & AUART_LINECTRL_EPS)
607 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
612 quot = ((readl(port->membase + AUART_LINECTRL)
613 & AUART_LINECTRL_BAUD_DIVINT_MASK))
614 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
615 quot |= ((readl(port->membase + AUART_LINECTRL)
616 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
617 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
621 *baud = (port->uartclk << 2) / quot;
625 auart_console_setup(struct console *co, char *options)
627 struct mxs_auart_port *s;
635 * Check whether an invalid uart number has been specified, and
636 * if so, search for the first available port that does have
639 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
641 s = auart_port[co->index];
648 uart_parse_options(options, &baud, &parity, &bits, &flow);
650 auart_console_get_options(&s->port, &baud, &parity, &bits);
652 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
659 static struct console auart_console = {
661 .write = auart_console_write,
662 .device = uart_console_device,
663 .setup = auart_console_setup,
664 .flags = CON_PRINTBUFFER,
666 .data = &auart_driver,
670 static struct uart_driver auart_driver = {
671 .owner = THIS_MODULE,
672 .driver_name = "ttyAPP",
673 .dev_name = "ttyAPP",
676 .nr = MXS_AUART_PORTS,
677 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
678 .cons = &auart_console,
682 static int __devinit mxs_auart_probe(struct platform_device *pdev)
684 struct mxs_auart_port *s;
689 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
695 s->clk = clk_get(&pdev->dev, NULL);
696 if (IS_ERR(s->clk)) {
697 ret = PTR_ERR(s->clk);
701 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
707 s->port.mapbase = r->start;
708 s->port.membase = ioremap(r->start, resource_size(r));
709 s->port.ops = &mxs_auart_ops;
710 s->port.iotype = UPIO_MEM;
711 s->port.line = pdev->id < 0 ? 0 : pdev->id;
712 s->port.fifosize = 16;
713 s->port.uartclk = clk_get_rate(s->clk);
714 s->port.type = PORT_IMX;
715 s->port.dev = s->dev = get_device(&pdev->dev);
720 s->irq = platform_get_irq(pdev, 0);
721 s->port.irq = s->irq;
722 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
726 platform_set_drvdata(pdev, s);
728 auart_port[pdev->id] = s;
730 mxs_auart_reset(&s->port);
732 ret = uart_add_one_port(&auart_driver, &s->port);
736 version = readl(s->port.membase + AUART_VERSION);
737 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
738 (version >> 24) & 0xff,
739 (version >> 16) & 0xff, version & 0xffff);
744 auart_port[pdev->id] = NULL;
754 static int __devexit mxs_auart_remove(struct platform_device *pdev)
756 struct mxs_auart_port *s = platform_get_drvdata(pdev);
758 uart_remove_one_port(&auart_driver, &s->port);
760 auart_port[pdev->id] = NULL;
769 static struct platform_driver mxs_auart_driver = {
770 .probe = mxs_auart_probe,
771 .remove = __devexit_p(mxs_auart_remove),
774 .owner = THIS_MODULE,
778 static int __init mxs_auart_init(void)
782 r = uart_register_driver(&auart_driver);
786 r = platform_driver_register(&mxs_auart_driver);
792 uart_unregister_driver(&auart_driver);
797 static void __exit mxs_auart_exit(void)
799 platform_driver_unregister(&mxs_auart_driver);
800 uart_unregister_driver(&auart_driver);
803 module_init(mxs_auart_init);
804 module_exit(mxs_auart_exit);
805 MODULE_LICENSE("GPL");
806 MODULE_DESCRIPTION("Freescale MXS application uart driver");