drivers/tty/serial/mfd.c

   1 /*
   2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
   3  *
   4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
   5  *
   6  * (C) Copyright 2010 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; version 2
  11  * of the License.
  12  */
  13
  14 /* Notes:
  15  * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
  16  *    2/3 chan to port 1, 4/5 chan to port 3. Even number chans
  17  *    are used for RX, odd chans for TX
  18  *
  19  * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
  20  *    asserted, only when the HW is reset the DDCD and DDSR will
  21  *    be triggered
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/console.h>
  27 #include <linux/sysrq.h>
  28 #include <linux/slab.h>
  29 #include <linux/serial_reg.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/serial_core.h>
  36 #include <linux/serial_mfd.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/pci.h>
  39 #include <linux/io.h>
  40 #include <linux/debugfs.h>
  41
  42 #define HSU_DMA_BUF_SIZE        2048
  43
  44 #define chan_readl(chan, offset)        readl(chan->reg + offset)
  45 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
  46
  47 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
  48 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
  49
  50 static int hsu_dma_enable;
  51 module_param(hsu_dma_enable, int, 0);
  52 MODULE_PARM_DESC(hsu_dma_enable,
  53                  "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
  54
  55 struct hsu_dma_buffer {
  56         u8              *buf;
  57         dma_addr_t      dma_addr;
  58         u32             dma_size;
  59         u32             ofs;
  60 };
  61
  62 struct hsu_dma_chan {
  63         u32     id;
  64         enum dma_data_direction dirt;
  65         struct uart_hsu_port    *uport;
  66         void __iomem            *reg;
  67 };
  68
  69 struct uart_hsu_port {
  70         struct uart_port        port;
  71         unsigned char           ier;
  72         unsigned char           lcr;
  73         unsigned char           mcr;
  74         unsigned int            lsr_break_flag;
  75         char                    name[12];
  76         int                     index;
  77         struct device           *dev;
  78
  79         struct hsu_dma_chan     *txc;
  80         struct hsu_dma_chan     *rxc;
  81         struct hsu_dma_buffer   txbuf;
  82         struct hsu_dma_buffer   rxbuf;
  83         int                     use_dma;        /* flag for DMA/PIO */
  84         int                     running;
  85         int                     dma_tx_on;
  86 };
  87
  88 /* Top level data structure of HSU */
  89 struct hsu_port {
  90         void __iomem    *reg;
  91         unsigned long   paddr;
  92         unsigned long   iolen;
  93         u32             irq;
  94
  95         struct uart_hsu_port    port[3];
  96         struct hsu_dma_chan     chans[10];
  97
  98         struct dentry *debugfs;
  99 };
 100
 101 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
 102 {
 103         unsigned int val;
 104
 105         if (offset > UART_MSR) {
 106                 offset <<= 2;
 107                 val = readl(up->port.membase + offset);
 108         } else
 109                 val = (unsigned int)readb(up->port.membase + offset);
 110
 111         return val;
 112 }
 113
 114 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
 115 {
 116         if (offset > UART_MSR) {
 117                 offset <<= 2;
 118                 writel(value, up->port.membase + offset);
 119         } else {
 120                 unsigned char val = value & 0xff;
 121                 writeb(val, up->port.membase + offset);
 122         }
 123 }
 124
 125 #ifdef CONFIG_DEBUG_FS
 126
 127 #define HSU_REGS_BUFSIZE        1024
 128
 129 static int hsu_show_regs_open(struct inode *inode, struct file *file)
 130 {
 131         file->private_data = inode->i_private;
 132         return 0;
 133 }
 134
 135 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 136                                 size_t count, loff_t *ppos)
 137 {
 138         struct uart_hsu_port *up = file->private_data;
 139         char *buf;
 140         u32 len = 0;
 141         ssize_t ret;
 142
 143         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 144         if (!buf)
 145                 return 0;
 146
 147         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 148                         "MFD HSU port[%d] regs:\n", up->index);
 149
 150         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 151                         "=================================\n");
 152         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 153                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
 154         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 155                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
 156         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 157                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
 158         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 159                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
 160         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 161                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
 162         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 163                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
 164         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 165                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
 166         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 167                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
 168         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 169                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
 170         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 171                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
 172
 173         if (len > HSU_REGS_BUFSIZE)
 174                 len = HSU_REGS_BUFSIZE;
 175
 176         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 177         kfree(buf);
 178         return ret;
 179 }
 180
 181 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
 182                                 size_t count, loff_t *ppos)
 183 {
 184         struct hsu_dma_chan *chan = file->private_data;
 185         char *buf;
 186         u32 len = 0;
 187         ssize_t ret;
 188
 189         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 190         if (!buf)
 191                 return 0;
 192
 193         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 194                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
 195
 196         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 197                         "=================================\n");
 198         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 199                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
 200         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 201                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
 202         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 203                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
 204         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 205                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
 206         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 207                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
 208         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 209                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
 210         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 211                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
 212         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 213                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
 214         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 215                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
 216         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 217                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
 218         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 219                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
 220         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 221                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
 222
 223         if (len > HSU_REGS_BUFSIZE)
 224                 len = HSU_REGS_BUFSIZE;
 225
 226         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 227         kfree(buf);
 228         return ret;
 229 }
 230
 231 static const struct file_operations port_regs_ops = {
 232         .owner          = THIS_MODULE,
 233         .open           = hsu_show_regs_open,
 234         .read           = port_show_regs,
 235         .llseek         = default_llseek,
 236 };
 237
 238 static const struct file_operations dma_regs_ops = {
 239         .owner          = THIS_MODULE,
 240         .open           = hsu_show_regs_open,
 241         .read           = dma_show_regs,
 242         .llseek         = default_llseek,
 243 };
 244
 245 static int hsu_debugfs_init(struct hsu_port *hsu)
 246 {
 247         int i;
 248         char name[32];
 249
 250         hsu->debugfs = debugfs_create_dir("hsu", NULL);
 251         if (!hsu->debugfs)
 252                 return -ENOMEM;
 253
 254         for (i = 0; i < 3; i++) {
 255                 snprintf(name, sizeof(name), "port_%d_regs", i);
 256                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 257                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
 258         }
 259
 260         for (i = 0; i < 6; i++) {
 261                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
 262                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 263                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
 264         }
 265
 266         return 0;
 267 }
 268
 269 static void hsu_debugfs_remove(struct hsu_port *hsu)
 270 {
 271         if (hsu->debugfs)
 272                 debugfs_remove_recursive(hsu->debugfs);
 273 }
 274
 275 #else
 276 static inline int hsu_debugfs_init(struct hsu_port *hsu)
 277 {
 278         return 0;
 279 }
 280
 281 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
 282 {
 283 }
 284 #endif /* CONFIG_DEBUG_FS */
 285
 286 static void serial_hsu_enable_ms(struct uart_port *port)
 287 {
 288         struct uart_hsu_port *up =
 289                 container_of(port, struct uart_hsu_port, port);
 290
 291         up->ier |= UART_IER_MSI;
 292         serial_out(up, UART_IER, up->ier);
 293 }
 294
 295 void hsu_dma_tx(struct uart_hsu_port *up)
 296 {
 297         struct circ_buf *xmit = &up->port.state->xmit;
 298         struct hsu_dma_buffer *dbuf = &up->txbuf;
 299         int count;
 300
 301         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
 302         if (up->dma_tx_on)
 303                 return;
 304
 305         /* Update the circ buf info */
 306         xmit->tail += dbuf->ofs;
 307         xmit->tail &= UART_XMIT_SIZE - 1;
 308
 309         up->port.icount.tx += dbuf->ofs;
 310         dbuf->ofs = 0;
 311
 312         /* Disable the channel */
 313         chan_writel(up->txc, HSU_CH_CR, 0x0);
 314
 315         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
 316                 dma_sync_single_for_device(up->port.dev,
 317                                            dbuf->dma_addr,
 318                                            dbuf->dma_size,
 319                                            DMA_TO_DEVICE);
 320
 321                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 322                 dbuf->ofs = count;
 323
 324                 /* Reprogram the channel */
 325                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
 326                 chan_writel(up->txc, HSU_CH_D0TSR, count);
 327
 328                 /* Reenable the channel */
 329                 chan_writel(up->txc, HSU_CH_DCR, 0x1
 330                                                  | (0x1 << 8)
 331                                                  | (0x1 << 16)
 332                                                  | (0x1 << 24));
 333                 up->dma_tx_on = 1;
 334                 chan_writel(up->txc, HSU_CH_CR, 0x1);
 335         }
 336
 337         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 338                 uart_write_wakeup(&up->port);
 339 }
 340
 341 /* The buffer is already cache coherent */
 342 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
 343 {
 344         dbuf->ofs = 0;
 345
 346         chan_writel(rxc, HSU_CH_BSR, 32);
 347         chan_writel(rxc, HSU_CH_MOTSR, 4);
 348
 349         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
 350         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
 351         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
 352                                          | (0x1 << 16)
 353                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 354                                          );
 355         chan_writel(rxc, HSU_CH_CR, 0x3);
 356 }
 357
 358 /* Protected by spin_lock_irqsave(port->lock) */
 359 static void serial_hsu_start_tx(struct uart_port *port)
 360 {
 361         struct uart_hsu_port *up =
 362                 container_of(port, struct uart_hsu_port, port);
 363
 364         if (up->use_dma) {
 365                 hsu_dma_tx(up);
 366         } else if (!(up->ier & UART_IER_THRI)) {
 367                 up->ier |= UART_IER_THRI;
 368                 serial_out(up, UART_IER, up->ier);
 369         }
 370 }
 371
 372 static void serial_hsu_stop_tx(struct uart_port *port)
 373 {
 374         struct uart_hsu_port *up =
 375                 container_of(port, struct uart_hsu_port, port);
 376         struct hsu_dma_chan *txc = up->txc;
 377
 378         if (up->use_dma)
 379                 chan_writel(txc, HSU_CH_CR, 0x0);
 380         else if (up->ier & UART_IER_THRI) {
 381                 up->ier &= ~UART_IER_THRI;
 382                 serial_out(up, UART_IER, up->ier);
 383         }
 384 }
 385
 386 /* This is always called in spinlock protected mode, so
 387  * modify timeout timer is safe here */
 388 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
 389 {
 390         struct hsu_dma_buffer *dbuf = &up->rxbuf;
 391         struct hsu_dma_chan *chan = up->rxc;
 392         struct uart_port *port = &up->port;
 393         struct tty_struct *tty = port->state->port.tty;
 394         int count;
 395
 396         if (!tty)
 397                 return;
 398
 399         /*
 400          * First need to know how many is already transferred,
 401          * then check if its a timeout DMA irq, and return
 402          * the trail bytes out, push them up and reenable the
 403          * channel
 404          */
 405
 406         /* Timeout IRQ, need wait some time, see Errata 2 */
 407         if (int_sts & 0xf00)
 408                 udelay(2);
 409
 410         /* Stop the channel */
 411         chan_writel(chan, HSU_CH_CR, 0x0);
 412
 413         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
 414         if (!count) {
 415                 /* Restart the channel before we leave */
 416                 chan_writel(chan, HSU_CH_CR, 0x3);
 417                 return;
 418         }
 419
 420         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
 421                         dbuf->dma_size, DMA_FROM_DEVICE);
 422
 423         /*
 424          * Head will only wrap around when we recycle
 425          * the DMA buffer, and when that happens, we
 426          * explicitly set tail to 0. So head will
 427          * always be greater than tail.
 428          */
 429         tty_insert_flip_string(tty, dbuf->buf, count);
 430         port->icount.rx += count;
 431
 432         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
 433                         dbuf->dma_size, DMA_FROM_DEVICE);
 434
 435         /* Reprogram the channel */
 436         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
 437         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
 438         chan_writel(chan, HSU_CH_DCR, 0x1
 439                                          | (0x1 << 8)
 440                                          | (0x1 << 16)
 441                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 442                                          );
 443         tty_flip_buffer_push(tty);
 444
 445         chan_writel(chan, HSU_CH_CR, 0x3);
 446
 447 }
 448
 449 static void serial_hsu_stop_rx(struct uart_port *port)
 450 {
 451         struct uart_hsu_port *up =
 452                 container_of(port, struct uart_hsu_port, port);
 453         struct hsu_dma_chan *chan = up->rxc;
 454
 455         if (up->use_dma)
 456                 chan_writel(chan, HSU_CH_CR, 0x2);
 457         else {
 458                 up->ier &= ~UART_IER_RLSI;
 459                 up->port.read_status_mask &= ~UART_LSR_DR;
 460                 serial_out(up, UART_IER, up->ier);
 461         }
 462 }
 463
 464 static inline void receive_chars(struct uart_hsu_port *up, int *status)
 465 {
 466         struct tty_struct *tty = up->port.state->port.tty;
 467         unsigned int ch, flag;
 468         unsigned int max_count = 256;
 469
 470         if (!tty)
 471                 return;
 472
 473         do {
 474                 ch = serial_in(up, UART_RX);
 475                 flag = TTY_NORMAL;
 476                 up->port.icount.rx++;
 477
 478                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
 479                                        UART_LSR_FE | UART_LSR_OE))) {
 480
 481                         dev_warn(up->dev, "We really rush into ERR/BI case"
 482                                 "status = 0x%02x", *status);
 483                         /* For statistics only */
 484                         if (*status & UART_LSR_BI) {
 485                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
 486                                 up->port.icount.brk++;
 487                                 /*
 488                                  * We do the SysRQ and SAK checking
 489                                  * here because otherwise the break
 490                                  * may get masked by ignore_status_mask
 491                                  * or read_status_mask.
 492                                  */
 493                                 if (uart_handle_break(&up->port))
 494                                         goto ignore_char;
 495                         } else if (*status & UART_LSR_PE)
 496                                 up->port.icount.parity++;
 497                         else if (*status & UART_LSR_FE)
 498                                 up->port.icount.frame++;
 499                         if (*status & UART_LSR_OE)
 500                                 up->port.icount.overrun++;
 501
 502                         /* Mask off conditions which should be ignored. */
 503                         *status &= up->port.read_status_mask;
 504
 505 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
 506                         if (up->port.cons &&
 507                                 up->port.cons->index == up->port.line) {
 508                                 /* Recover the break flag from console xmit */
 509                                 *status |= up->lsr_break_flag;
 510                                 up->lsr_break_flag = 0;
 511                         }
 512 #endif
 513                         if (*status & UART_LSR_BI) {
 514                                 flag = TTY_BREAK;
 515                         } else if (*status & UART_LSR_PE)
 516                                 flag = TTY_PARITY;
 517                         else if (*status & UART_LSR_FE)
 518                                 flag = TTY_FRAME;
 519                 }
 520
 521                 if (uart_handle_sysrq_char(&up->port, ch))
 522                         goto ignore_char;
 523
 524                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
 525         ignore_char:
 526                 *status = serial_in(up, UART_LSR);
 527         } while ((*status & UART_LSR_DR) && max_count--);
 528         tty_flip_buffer_push(tty);
 529 }
 530
 531 static void transmit_chars(struct uart_hsu_port *up)
 532 {
 533         struct circ_buf *xmit = &up->port.state->xmit;
 534         int count;
 535
 536         if (up->port.x_char) {
 537                 serial_out(up, UART_TX, up->port.x_char);
 538                 up->port.icount.tx++;
 539                 up->port.x_char = 0;
 540                 return;
 541         }
 542         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 543                 serial_hsu_stop_tx(&up->port);
 544                 return;
 545         }
 546
 547         /* The IRQ is for TX FIFO half-empty */
 548         count = up->port.fifosize / 2;
 549
 550         do {
 551                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 552                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 553
 554                 up->port.icount.tx++;
 555                 if (uart_circ_empty(xmit))
 556                         break;
 557         } while (--count > 0);
 558
 559         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 560                 uart_write_wakeup(&up->port);
 561
 562         if (uart_circ_empty(xmit))
 563                 serial_hsu_stop_tx(&up->port);
 564 }
 565
 566 static inline void check_modem_status(struct uart_hsu_port *up)
 567 {
 568         int status;
 569
 570         status = serial_in(up, UART_MSR);
 571
 572         if ((status & UART_MSR_ANY_DELTA) == 0)
 573                 return;
 574
 575         if (status & UART_MSR_TERI)
 576                 up->port.icount.rng++;
 577         if (status & UART_MSR_DDSR)
 578                 up->port.icount.dsr++;
 579         /* We may only get DDCD when HW init and reset */
 580         if (status & UART_MSR_DDCD)
 581                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
 582         /* Will start/stop_tx accordingly */
 583         if (status & UART_MSR_DCTS)
 584                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
 585
 586         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 587 }
 588
 589 /*
 590  * This handles the interrupt from one port.
 591  */
 592 static irqreturn_t port_irq(int irq, void *dev_id)
 593 {
 594         struct uart_hsu_port *up = dev_id;
 595         unsigned int iir, lsr;
 596         unsigned long flags;
 597
 598         if (unlikely(!up->running))
 599                 return IRQ_NONE;
 600
 601         spin_lock_irqsave(&up->port.lock, flags);
 602         if (up->use_dma) {
 603                 lsr = serial_in(up, UART_LSR);
 604                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
 605                                        UART_LSR_FE | UART_LSR_OE)))
 606                         dev_warn(up->dev,
 607                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
 608                                 lsr);
 609                 check_modem_status(up);
 610                 spin_unlock_irqrestore(&up->port.lock, flags);
 611                 return IRQ_HANDLED;
 612         }
 613
 614         iir = serial_in(up, UART_IIR);
 615         if (iir & UART_IIR_NO_INT) {
 616                 spin_unlock_irqrestore(&up->port.lock, flags);
 617                 return IRQ_NONE;
 618         }
 619
 620         lsr = serial_in(up, UART_LSR);
 621         if (lsr & UART_LSR_DR)
 622                 receive_chars(up, &lsr);
 623         check_modem_status(up);
 624
 625         /* lsr will be renewed during the receive_chars */
 626         if (lsr & UART_LSR_THRE)
 627                 transmit_chars(up);
 628
 629         spin_unlock_irqrestore(&up->port.lock, flags);
 630         return IRQ_HANDLED;
 631 }
 632
 633 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
 634 {
 635         struct uart_hsu_port *up = chan->uport;
 636         unsigned long flags;
 637         u32 int_sts;
 638
 639         spin_lock_irqsave(&up->port.lock, flags);
 640
 641         if (!up->use_dma || !up->running)
 642                 goto exit;
 643
 644         /*
 645          * No matter what situation, need read clear the IRQ status
 646          * There is a bug, see Errata 5, HSD 2900918
 647          */
 648         int_sts = chan_readl(chan, HSU_CH_SR);
 649
 650         /* Rx channel */
 651         if (chan->dirt == DMA_FROM_DEVICE)
 652                 hsu_dma_rx(up, int_sts);
 653
 654         /* Tx channel */
 655         if (chan->dirt == DMA_TO_DEVICE) {
 656                 chan_writel(chan, HSU_CH_CR, 0x0);
 657                 up->dma_tx_on = 0;
 658                 hsu_dma_tx(up);
 659         }
 660
 661 exit:
 662         spin_unlock_irqrestore(&up->port.lock, flags);
 663         return;
 664 }
 665
 666 static irqreturn_t dma_irq(int irq, void *dev_id)
 667 {
 668         struct hsu_port *hsu = dev_id;
 669         u32 int_sts, i;
 670
 671         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
 672
 673         /* Currently we only have 6 channels may be used */
 674         for (i = 0; i < 6; i++) {
 675                 if (int_sts & 0x1)
 676                         dma_chan_irq(&hsu->chans[i]);
 677                 int_sts >>= 1;
 678         }
 679
 680         return IRQ_HANDLED;
 681 }
 682
 683 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
 684 {
 685         struct uart_hsu_port *up =
 686                 container_of(port, struct uart_hsu_port, port);
 687         unsigned long flags;
 688         unsigned int ret;
 689
 690         spin_lock_irqsave(&up->port.lock, flags);
 691         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 692         spin_unlock_irqrestore(&up->port.lock, flags);
 693
 694         return ret;
 695 }
 696
 697 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
 698 {
 699         struct uart_hsu_port *up =
 700                 container_of(port, struct uart_hsu_port, port);
 701         unsigned char status;
 702         unsigned int ret;
 703
 704         status = serial_in(up, UART_MSR);
 705
 706         ret = 0;
 707         if (status & UART_MSR_DCD)
 708                 ret |= TIOCM_CAR;
 709         if (status & UART_MSR_RI)
 710                 ret |= TIOCM_RNG;
 711         if (status & UART_MSR_DSR)
 712                 ret |= TIOCM_DSR;
 713         if (status & UART_MSR_CTS)
 714                 ret |= TIOCM_CTS;
 715         return ret;
 716 }
 717
 718 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
 719 {
 720         struct uart_hsu_port *up =
 721                 container_of(port, struct uart_hsu_port, port);
 722         unsigned char mcr = 0;
 723
 724         if (mctrl & TIOCM_RTS)
 725                 mcr |= UART_MCR_RTS;
 726         if (mctrl & TIOCM_DTR)
 727                 mcr |= UART_MCR_DTR;
 728         if (mctrl & TIOCM_OUT1)
 729                 mcr |= UART_MCR_OUT1;
 730         if (mctrl & TIOCM_OUT2)
 731                 mcr |= UART_MCR_OUT2;
 732         if (mctrl & TIOCM_LOOP)
 733                 mcr |= UART_MCR_LOOP;
 734
 735         mcr |= up->mcr;
 736
 737         serial_out(up, UART_MCR, mcr);
 738 }
 739
 740 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
 741 {
 742         struct uart_hsu_port *up =
 743                 container_of(port, struct uart_hsu_port, port);
 744         unsigned long flags;
 745
 746         spin_lock_irqsave(&up->port.lock, flags);
 747         if (break_state == -1)
 748                 up->lcr |= UART_LCR_SBC;
 749         else
 750                 up->lcr &= ~UART_LCR_SBC;
 751         serial_out(up, UART_LCR, up->lcr);
 752         spin_unlock_irqrestore(&up->port.lock, flags);
 753 }
 754
 755 /*
 756  * What special to do:
 757  * 1. chose the 64B fifo mode
 758  * 2. start dma or pio depends on configuration
 759  * 3. we only allocate dma memory when needed
 760  */
 761 static int serial_hsu_startup(struct uart_port *port)
 762 {
 763         struct uart_hsu_port *up =
 764                 container_of(port, struct uart_hsu_port, port);
 765         unsigned long flags;
 766
 767         /*
 768          * Clear the FIFO buffers and disable them.
 769          * (they will be reenabled in set_termios())
 770          */
 771         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 772         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 773                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 774         serial_out(up, UART_FCR, 0);
 775
 776         /* Clear the interrupt registers. */
 777         (void) serial_in(up, UART_LSR);
 778         (void) serial_in(up, UART_RX);
 779         (void) serial_in(up, UART_IIR);
 780         (void) serial_in(up, UART_MSR);
 781
 782         /* Now, initialize the UART, default is 8n1 */
 783         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 784
 785         spin_lock_irqsave(&up->port.lock, flags);
 786
 787         up->port.mctrl |= TIOCM_OUT2;
 788         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 789
 790         /*
 791          * Finally, enable interrupts.  Note: Modem status interrupts
 792          * are set via set_termios(), which will be occurring imminently
 793          * anyway, so we don't enable them here.
 794          */
 795         if (!up->use_dma)
 796                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
 797         else
 798                 up->ier = 0;
 799         serial_out(up, UART_IER, up->ier);
 800
 801         spin_unlock_irqrestore(&up->port.lock, flags);
 802
 803         /* DMA init */
 804         if (up->use_dma) {
 805                 struct hsu_dma_buffer *dbuf;
 806                 struct circ_buf *xmit = &port->state->xmit;
 807
 808                 up->dma_tx_on = 0;
 809
 810                 /* First allocate the RX buffer */
 811                 dbuf = &up->rxbuf;
 812                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
 813                 if (!dbuf->buf) {
 814                         up->use_dma = 0;
 815                         goto exit;
 816                 }
 817                 dbuf->dma_addr = dma_map_single(port->dev,
 818                                                 dbuf->buf,
 819                                                 HSU_DMA_BUF_SIZE,
 820                                                 DMA_FROM_DEVICE);
 821                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
 822
 823                 /* Start the RX channel right now */
 824                 hsu_dma_start_rx_chan(up->rxc, dbuf);
 825
 826                 /* Next init the TX DMA */
 827                 dbuf = &up->txbuf;
 828                 dbuf->buf = xmit->buf;
 829                 dbuf->dma_addr = dma_map_single(port->dev,
 830                                                dbuf->buf,
 831                                                UART_XMIT_SIZE,
 832                                                DMA_TO_DEVICE);
 833                 dbuf->dma_size = UART_XMIT_SIZE;
 834
 835                 /* This should not be changed all around */
 836                 chan_writel(up->txc, HSU_CH_BSR, 32);
 837                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
 838                 dbuf->ofs = 0;
 839         }
 840
 841 exit:
 842          /* And clear the interrupt registers again for luck. */
 843         (void) serial_in(up, UART_LSR);
 844         (void) serial_in(up, UART_RX);
 845         (void) serial_in(up, UART_IIR);
 846         (void) serial_in(up, UART_MSR);
 847
 848         up->running = 1;
 849         return 0;
 850 }
 851
 852 static void serial_hsu_shutdown(struct uart_port *port)
 853 {
 854         struct uart_hsu_port *up =
 855                 container_of(port, struct uart_hsu_port, port);
 856         unsigned long flags;
 857
 858         /* Disable interrupts from this port */
 859         up->ier = 0;
 860         serial_out(up, UART_IER, 0);
 861         up->running = 0;
 862
 863         spin_lock_irqsave(&up->port.lock, flags);
 864         up->port.mctrl &= ~TIOCM_OUT2;
 865         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 866         spin_unlock_irqrestore(&up->port.lock, flags);
 867
 868         /* Disable break condition and FIFOs */
 869         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 870         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 871                                   UART_FCR_CLEAR_RCVR |
 872                                   UART_FCR_CLEAR_XMIT);
 873         serial_out(up, UART_FCR, 0);
 874 }
 875
 876 static void
 877 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
 878                        struct ktermios *old)
 879 {
 880         struct uart_hsu_port *up =
 881                         container_of(port, struct uart_hsu_port, port);
 882         struct tty_struct *tty = port->state->port.tty;
 883         unsigned char cval, fcr = 0;
 884         unsigned long flags;
 885         unsigned int baud, quot;
 886         u32 ps, mul;
 887
 888         switch (termios->c_cflag & CSIZE) {
 889         case CS5:
 890                 cval = UART_LCR_WLEN5;
 891                 break;
 892         case CS6:
 893                 cval = UART_LCR_WLEN6;
 894                 break;
 895         case CS7:
 896                 cval = UART_LCR_WLEN7;
 897                 break;
 898         default:
 899         case CS8:
 900                 cval = UART_LCR_WLEN8;
 901                 break;
 902         }
 903
 904         /* CMSPAR isn't supported by this driver */
 905         if (tty)
 906                 tty->termios->c_cflag &= ~CMSPAR;
 907
 908         if (termios->c_cflag & CSTOPB)
 909                 cval |= UART_LCR_STOP;
 910         if (termios->c_cflag & PARENB)
 911                 cval |= UART_LCR_PARITY;
 912         if (!(termios->c_cflag & PARODD))
 913                 cval |= UART_LCR_EPAR;
 914
 915         /*
 916          * The base clk is 50Mhz, and the baud rate come from:
 917          *      baud = 50M * MUL / (DIV * PS * DLAB)
 918          *
 919          * For those basic low baud rate we can get the direct
 920          * scalar from 2746800, like 115200 = 2746800/24. For those
 921          * higher baud rate, we handle them case by case, mainly by
 922          * adjusting the MUL/PS registers, and DIV register is kept
 923          * as default value 0x3d09 to make things simple
 924          */
 925         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 926
 927         quot = 1;
 928         ps = 0x10;
 929         mul = 0x3600;
 930         switch (baud) {
 931         case 3500000:
 932                 mul = 0x3345;
 933                 ps = 0xC;
 934                 break;
 935         case 1843200:
 936                 mul = 0x2400;
 937                 break;
 938         case 3000000:
 939         case 2500000:
 940         case 2000000:
 941         case 1500000:
 942         case 1000000:
 943         case 500000:
 944                 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
 945                 mul = baud / 500000 * 0x9C4;
 946                 break;
 947         default:
 948                 /* Use uart_get_divisor to get quot for other baud rates */
 949                 quot = 0;
 950         }
 951
 952         if (!quot)
 953                 quot = uart_get_divisor(port, baud);
 954
 955         if ((up->port.uartclk / quot) < (2400 * 16))
 956                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
 957         else if ((up->port.uartclk / quot) < (230400 * 16))
 958                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
 959         else
 960                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
 961
 962         fcr |= UART_FCR_HSU_64B_FIFO;
 963
 964         /*
 965          * Ok, we're now changing the port state.  Do it with
 966          * interrupts disabled.
 967          */
 968         spin_lock_irqsave(&up->port.lock, flags);
 969
 970         /* Update the per-port timeout */
 971         uart_update_timeout(port, termios->c_cflag, baud);
 972
 973         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 974         if (termios->c_iflag & INPCK)
 975                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 976         if (termios->c_iflag & (BRKINT | PARMRK))
 977                 up->port.read_status_mask |= UART_LSR_BI;
 978
 979         /* Characters to ignore */
 980         up->port.ignore_status_mask = 0;
 981         if (termios->c_iflag & IGNPAR)
 982                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 983         if (termios->c_iflag & IGNBRK) {
 984                 up->port.ignore_status_mask |= UART_LSR_BI;
 985                 /*
 986                  * If we're ignoring parity and break indicators,
 987                  * ignore overruns too (for real raw support).
 988                  */
 989                 if (termios->c_iflag & IGNPAR)
 990                         up->port.ignore_status_mask |= UART_LSR_OE;
 991         }
 992
 993         /* Ignore all characters if CREAD is not set */
 994         if ((termios->c_cflag & CREAD) == 0)
 995                 up->port.ignore_status_mask |= UART_LSR_DR;
 996
 997         /*
 998          * CTS flow control flag and modem status interrupts, disable
 999          * MSI by default
1000          */
1001         up->ier &= ~UART_IER_MSI;
1002         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1003                 up->ier |= UART_IER_MSI;
1004
1005         serial_out(up, UART_IER, up->ier);
1006
1007         if (termios->c_cflag & CRTSCTS)
1008                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1009         else
1010                 up->mcr &= ~UART_MCR_AFE;
1011
1012         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1013         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1014         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1015         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1016         serial_out(up, UART_MUL, mul);                  /* set MUL */
1017         serial_out(up, UART_PS, ps);                    /* set PS */
1018         up->lcr = cval;                                 /* Save LCR */
1019         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1020         serial_out(up, UART_FCR, fcr);
1021         spin_unlock_irqrestore(&up->port.lock, flags);
1022 }
1023
1024 static void
1025 serial_hsu_pm(struct uart_port *port, unsigned int state,
1026               unsigned int oldstate)
1027 {
1028 }
1029
1030 static void serial_hsu_release_port(struct uart_port *port)
1031 {
1032 }
1033
1034 static int serial_hsu_request_port(struct uart_port *port)
1035 {
1036         return 0;
1037 }
1038
1039 static void serial_hsu_config_port(struct uart_port *port, int flags)
1040 {
1041         struct uart_hsu_port *up =
1042                 container_of(port, struct uart_hsu_port, port);
1043         up->port.type = PORT_MFD;
1044 }
1045
1046 static int
1047 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1048 {
1049         /* We don't want the core code to modify any port params */
1050         return -EINVAL;
1051 }
1052
1053 static const char *
1054 serial_hsu_type(struct uart_port *port)
1055 {
1056         struct uart_hsu_port *up =
1057                 container_of(port, struct uart_hsu_port, port);
1058         return up->name;
1059 }
1060
1061 /* Mainly for uart console use */
1062 static struct uart_hsu_port *serial_hsu_ports[3];
1063 static struct uart_driver serial_hsu_reg;
1064
1065 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1066
1067 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1068
1069 /* Wait for transmitter & holding register to empty */
1070 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1071 {
1072         unsigned int status, tmout = 1000;
1073
1074         /* Wait up to 1ms for the character to be sent. */
1075         do {
1076                 status = serial_in(up, UART_LSR);
1077
1078                 if (status & UART_LSR_BI)
1079                         up->lsr_break_flag = UART_LSR_BI;
1080
1081                 if (--tmout == 0)
1082                         break;
1083                 udelay(1);
1084         } while (!(status & BOTH_EMPTY));
1085
1086         /* Wait up to 1s for flow control if necessary */
1087         if (up->port.flags & UPF_CONS_FLOW) {
1088                 tmout = 1000000;
1089                 while (--tmout &&
1090                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1091                         udelay(1);
1092         }
1093 }
1094
1095 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1096 {
1097         struct uart_hsu_port *up =
1098                 container_of(port, struct uart_hsu_port, port);
1099
1100         wait_for_xmitr(up);
1101         serial_out(up, UART_TX, ch);
1102 }
1103
1104 /*
1105  * Print a string to the serial port trying not to disturb
1106  * any possible real use of the port...
1107  *
1108  *      The console_lock must be held when we get here.
1109  */
1110 static void
1111 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1112 {
1113         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1114         unsigned long flags;
1115         unsigned int ier;
1116         int locked = 1;
1117
1118         local_irq_save(flags);
1119         if (up->port.sysrq)
1120                 locked = 0;
1121         else if (oops_in_progress) {
1122                 locked = spin_trylock(&up->port.lock);
1123         } else
1124                 spin_lock(&up->port.lock);
1125
1126         /* First save the IER then disable the interrupts */
1127         ier = serial_in(up, UART_IER);
1128         serial_out(up, UART_IER, 0);
1129
1130         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1131
1132         /*
1133          * Finally, wait for transmitter to become empty
1134          * and restore the IER
1135          */
1136         wait_for_xmitr(up);
1137         serial_out(up, UART_IER, ier);
1138
1139         if (locked)
1140                 spin_unlock(&up->port.lock);
1141         local_irq_restore(flags);
1142 }
1143
1144 static struct console serial_hsu_console;
1145
1146 static int __init
1147 serial_hsu_console_setup(struct console *co, char *options)
1148 {
1149         struct uart_hsu_port *up;
1150         int baud = 115200;
1151         int bits = 8;
1152         int parity = 'n';
1153         int flow = 'n';
1154         int ret;
1155
1156         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1157                 co->index = 0;
1158         up = serial_hsu_ports[co->index];
1159         if (!up)
1160                 return -ENODEV;
1161
1162         if (options)
1163                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1164
1165         ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1166
1167         return ret;
1168 }
1169
1170 static struct console serial_hsu_console = {
1171         .name           = "ttyMFD",
1172         .write          = serial_hsu_console_write,
1173         .device         = uart_console_device,
1174         .setup          = serial_hsu_console_setup,
1175         .flags          = CON_PRINTBUFFER,
1176         .index          = 2,
1177         .data           = &serial_hsu_reg,
1178 };
1179 #endif
1180
1181 struct uart_ops serial_hsu_pops = {
1182         .tx_empty       = serial_hsu_tx_empty,
1183         .set_mctrl      = serial_hsu_set_mctrl,
1184         .get_mctrl      = serial_hsu_get_mctrl,
1185         .stop_tx        = serial_hsu_stop_tx,
1186         .start_tx       = serial_hsu_start_tx,
1187         .stop_rx        = serial_hsu_stop_rx,
1188         .enable_ms      = serial_hsu_enable_ms,
1189         .break_ctl      = serial_hsu_break_ctl,
1190         .startup        = serial_hsu_startup,
1191         .shutdown       = serial_hsu_shutdown,
1192         .set_termios    = serial_hsu_set_termios,
1193         .pm             = serial_hsu_pm,
1194         .type           = serial_hsu_type,
1195         .release_port   = serial_hsu_release_port,
1196         .request_port   = serial_hsu_request_port,
1197         .config_port    = serial_hsu_config_port,
1198         .verify_port    = serial_hsu_verify_port,
1199 };
1200
1201 static struct uart_driver serial_hsu_reg = {
1202         .owner          = THIS_MODULE,
1203         .driver_name    = "MFD serial",
1204         .dev_name       = "ttyMFD",
1205         .major          = TTY_MAJOR,
1206         .minor          = 128,
1207         .nr             = 3,
1208 };
1209
1210 #ifdef CONFIG_PM
1211 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1212 {
1213         void *priv = pci_get_drvdata(pdev);
1214         struct uart_hsu_port *up;
1215
1216         /* Make sure this is not the internal dma controller */
1217         if (priv && (pdev->device != 0x081E)) {
1218                 up = priv;
1219                 uart_suspend_port(&serial_hsu_reg, &up->port);
1220         }
1221
1222         pci_save_state(pdev);
1223         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1224         return 0;
1225 }
1226
1227 static int serial_hsu_resume(struct pci_dev *pdev)
1228 {
1229         void *priv = pci_get_drvdata(pdev);
1230         struct uart_hsu_port *up;
1231         int ret;
1232
1233         pci_set_power_state(pdev, PCI_D0);
1234         pci_restore_state(pdev);
1235
1236         ret = pci_enable_device(pdev);
1237         if (ret)
1238                 dev_warn(&pdev->dev,
1239                         "HSU: can't re-enable device, try to continue\n");
1240
1241         if (priv && (pdev->device != 0x081E)) {
1242                 up = priv;
1243                 uart_resume_port(&serial_hsu_reg, &up->port);
1244         }
1245         return 0;
1246 }
1247 #else
1248 #define serial_hsu_suspend      NULL
1249 #define serial_hsu_resume       NULL
1250 #endif
1251
1252 /* temp global pointer before we settle down on using one or four PCI dev */
1253 static struct hsu_port *phsu;
1254
1255 static int serial_hsu_probe(struct pci_dev *pdev,
1256                                 const struct pci_device_id *ent)
1257 {
1258         struct uart_hsu_port *uport;
1259         int index, ret;
1260
1261         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1262                 pdev->vendor, pdev->device);
1263
1264         switch (pdev->device) {
1265         case 0x081B:
1266                 index = 0;
1267                 break;
1268         case 0x081C:
1269                 index = 1;
1270                 break;
1271         case 0x081D:
1272                 index = 2;
1273                 break;
1274         case 0x081E:
1275                 /* internal DMA controller */
1276                 index = 3;
1277                 break;
1278         default:
1279                 dev_err(&pdev->dev, "HSU: out of index!");
1280                 return -ENODEV;
1281         }
1282
1283         ret = pci_enable_device(pdev);
1284         if (ret)
1285                 return ret;
1286
1287         if (index == 3) {
1288                 /* DMA controller */
1289                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1290                 if (ret) {
1291                         dev_err(&pdev->dev, "can not get IRQ\n");
1292                         goto err_disable;
1293                 }
1294                 pci_set_drvdata(pdev, phsu);
1295         } else {
1296                 /* UART port 0~2 */
1297                 uport = &phsu->port[index];
1298                 uport->port.irq = pdev->irq;
1299                 uport->port.dev = &pdev->dev;
1300                 uport->dev = &pdev->dev;
1301
1302                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1303                 if (ret) {
1304                         dev_err(&pdev->dev, "can not get IRQ\n");
1305                         goto err_disable;
1306                 }
1307                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1308
1309 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1310                 if (index == 2) {
1311                         register_console(&serial_hsu_console);
1312                         uport->port.cons = &serial_hsu_console;
1313                 }
1314 #endif
1315                 pci_set_drvdata(pdev, uport);
1316         }
1317
1318         return 0;
1319
1320 err_disable:
1321         pci_disable_device(pdev);
1322         return ret;
1323 }
1324
1325 static void hsu_global_init(void)
1326 {
1327         struct hsu_port *hsu;
1328         struct uart_hsu_port *uport;
1329         struct hsu_dma_chan *dchan;
1330         int i, ret;
1331
1332         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1333         if (!hsu)
1334                 return;
1335
1336         /* Get basic io resource and map it */
1337         hsu->paddr = 0xffa28000;
1338         hsu->iolen = 0x1000;
1339
1340         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1341                 pr_warning("HSU: error in request mem region\n");
1342
1343         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1344         if (!hsu->reg) {
1345                 pr_err("HSU: error in ioremap\n");
1346                 ret = -ENOMEM;
1347                 goto err_free_region;
1348         }
1349
1350         /* Initialise the 3 UART ports */
1351         uport = hsu->port;
1352         for (i = 0; i < 3; i++) {
1353                 uport->port.type = PORT_MFD;
1354                 uport->port.iotype = UPIO_MEM;
1355                 uport->port.mapbase = (resource_size_t)hsu->paddr
1356                                         + HSU_PORT_REG_OFFSET
1357                                         + i * HSU_PORT_REG_LENGTH;
1358                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1359                                         + i * HSU_PORT_REG_LENGTH;
1360
1361                 sprintf(uport->name, "hsu_port%d", i);
1362                 uport->port.fifosize = 64;
1363                 uport->port.ops = &serial_hsu_pops;
1364                 uport->port.line = i;
1365                 uport->port.flags = UPF_IOREMAP;
1366                 /* set the scalable maxim support rate to 2746800 bps */
1367                 uport->port.uartclk = 115200 * 24 * 16;
1368
1369                 uport->running = 0;
1370                 uport->txc = &hsu->chans[i * 2];
1371                 uport->rxc = &hsu->chans[i * 2 + 1];
1372
1373                 serial_hsu_ports[i] = uport;
1374                 uport->index = i;
1375
1376                 if (hsu_dma_enable & (1<<i))
1377                         uport->use_dma = 1;
1378                 else
1379                         uport->use_dma = 0;
1380
1381                 uport++;
1382         }
1383
1384         /* Initialise 6 dma channels */
1385         dchan = hsu->chans;
1386         for (i = 0; i < 6; i++) {
1387                 dchan->id = i;
1388                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1389                 dchan->uport = &hsu->port[i/2];
1390                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1391                                 i * HSU_DMA_CHANS_REG_LENGTH;
1392
1393                 dchan++;
1394         }
1395
1396         phsu = hsu;
1397         hsu_debugfs_init(hsu);
1398         return;
1399
1400 err_free_region:
1401         release_mem_region(hsu->paddr, hsu->iolen);
1402         kfree(hsu);
1403         return;
1404 }
1405
1406 static void serial_hsu_remove(struct pci_dev *pdev)
1407 {
1408         void *priv = pci_get_drvdata(pdev);
1409         struct uart_hsu_port *up;
1410
1411         if (!priv)
1412                 return;
1413
1414         /* For port 0/1/2, priv is the address of uart_hsu_port */
1415         if (pdev->device != 0x081E) {
1416                 up = priv;
1417                 uart_remove_one_port(&serial_hsu_reg, &up->port);
1418         }
1419
1420         pci_set_drvdata(pdev, NULL);
1421         free_irq(pdev->irq, priv);
1422         pci_disable_device(pdev);
1423 }
1424
1425 /* First 3 are UART ports, and the 4th is the DMA */
1426 static const struct pci_device_id pci_ids[] __devinitdata = {
1427         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1428         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1429         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1430         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1431         {},
1432 };
1433
1434 static struct pci_driver hsu_pci_driver = {
1435         .name =         "HSU serial",
1436         .id_table =     pci_ids,
1437         .probe =        serial_hsu_probe,
1438         .remove =       __devexit_p(serial_hsu_remove),
1439         .suspend =      serial_hsu_suspend,
1440         .resume =       serial_hsu_resume,
1441 };
1442
1443 static int __init hsu_pci_init(void)
1444 {
1445         int ret;
1446
1447         hsu_global_init();
1448
1449         ret = uart_register_driver(&serial_hsu_reg);
1450         if (ret)
1451                 return ret;
1452
1453         return pci_register_driver(&hsu_pci_driver);
1454 }
1455
1456 static void __exit hsu_pci_exit(void)
1457 {
1458         pci_unregister_driver(&hsu_pci_driver);
1459         uart_unregister_driver(&serial_hsu_reg);
1460
1461         hsu_debugfs_remove(phsu);
1462
1463         kfree(phsu);
1464 }
1465
1466 module_init(hsu_pci_init);
1467 module_exit(hsu_pci_exit);
1468
1469 MODULE_LICENSE("GPL v2");
1470 MODULE_ALIAS("platform:medfield-hsu");