drivers/tty/serial/fsl_lpuart.c

   1 /*
   2  *  Freescale lpuart serial port driver
   3  *
   4  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/clk.h>
  17 #include <linux/console.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_dma.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/slab.h>
  29 #include <linux/tty_flip.h>
  30
  31 /* All registers are 8-bit width */
  32 #define UARTBDH                 0x00
  33 #define UARTBDL                 0x01
  34 #define UARTCR1                 0x02
  35 #define UARTCR2                 0x03
  36 #define UARTSR1                 0x04
  37 #define UARTCR3                 0x06
  38 #define UARTDR                  0x07
  39 #define UARTCR4                 0x0a
  40 #define UARTCR5                 0x0b
  41 #define UARTMODEM               0x0d
  42 #define UARTPFIFO               0x10
  43 #define UARTCFIFO               0x11
  44 #define UARTSFIFO               0x12
  45 #define UARTTWFIFO              0x13
  46 #define UARTTCFIFO              0x14
  47 #define UARTRWFIFO              0x15
  48
  49 #define UARTBDH_LBKDIE          0x80
  50 #define UARTBDH_RXEDGIE         0x40
  51 #define UARTBDH_SBR_MASK        0x1f
  52
  53 #define UARTCR1_LOOPS           0x80
  54 #define UARTCR1_RSRC            0x20
  55 #define UARTCR1_M               0x10
  56 #define UARTCR1_WAKE            0x08
  57 #define UARTCR1_ILT             0x04
  58 #define UARTCR1_PE              0x02
  59 #define UARTCR1_PT              0x01
  60
  61 #define UARTCR2_TIE             0x80
  62 #define UARTCR2_TCIE            0x40
  63 #define UARTCR2_RIE             0x20
  64 #define UARTCR2_ILIE            0x10
  65 #define UARTCR2_TE              0x08
  66 #define UARTCR2_RE              0x04
  67 #define UARTCR2_RWU             0x02
  68 #define UARTCR2_SBK             0x01
  69
  70 #define UARTSR1_TDRE            0x80
  71 #define UARTSR1_TC              0x40
  72 #define UARTSR1_RDRF            0x20
  73 #define UARTSR1_IDLE            0x10
  74 #define UARTSR1_OR              0x08
  75 #define UARTSR1_NF              0x04
  76 #define UARTSR1_FE              0x02
  77 #define UARTSR1_PE              0x01
  78
  79 #define UARTCR3_R8              0x80
  80 #define UARTCR3_T8              0x40
  81 #define UARTCR3_TXDIR           0x20
  82 #define UARTCR3_TXINV           0x10
  83 #define UARTCR3_ORIE            0x08
  84 #define UARTCR3_NEIE            0x04
  85 #define UARTCR3_FEIE            0x02
  86 #define UARTCR3_PEIE            0x01
  87
  88 #define UARTCR4_MAEN1           0x80
  89 #define UARTCR4_MAEN2           0x40
  90 #define UARTCR4_M10             0x20
  91 #define UARTCR4_BRFA_MASK       0x1f
  92 #define UARTCR4_BRFA_OFF        0
  93
  94 #define UARTCR5_TDMAS           0x80
  95 #define UARTCR5_RDMAS           0x20
  96
  97 #define UARTMODEM_RXRTSE        0x08
  98 #define UARTMODEM_TXRTSPOL      0x04
  99 #define UARTMODEM_TXRTSE        0x02
 100 #define UARTMODEM_TXCTSE        0x01
 101
 102 #define UARTPFIFO_TXFE          0x80
 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 104 #define UARTPFIFO_TXSIZE_OFF    4
 105 #define UARTPFIFO_RXFE          0x08
 106 #define UARTPFIFO_RXSIZE_OFF    0
 107
 108 #define UARTCFIFO_TXFLUSH       0x80
 109 #define UARTCFIFO_RXFLUSH       0x40
 110 #define UARTCFIFO_RXOFE         0x04
 111 #define UARTCFIFO_TXOFE         0x02
 112 #define UARTCFIFO_RXUFE         0x01
 113
 114 #define UARTSFIFO_TXEMPT        0x80
 115 #define UARTSFIFO_RXEMPT        0x40
 116 #define UARTSFIFO_RXOF          0x04
 117 #define UARTSFIFO_TXOF          0x02
 118 #define UARTSFIFO_RXUF          0x01
 119
 120 /* 32-bit register defination */
 121 #define UARTBAUD                0x00
 122 #define UARTSTAT                0x04
 123 #define UARTCTRL                0x08
 124 #define UARTDATA                0x0C
 125 #define UARTMATCH               0x10
 126 #define UARTMODIR               0x14
 127 #define UARTFIFO                0x18
 128 #define UARTWATER               0x1c
 129
 130 #define UARTBAUD_MAEN1          0x80000000
 131 #define UARTBAUD_MAEN2          0x40000000
 132 #define UARTBAUD_M10            0x20000000
 133 #define UARTBAUD_TDMAE          0x00800000
 134 #define UARTBAUD_RDMAE          0x00200000
 135 #define UARTBAUD_MATCFG         0x00400000
 136 #define UARTBAUD_BOTHEDGE       0x00020000
 137 #define UARTBAUD_RESYNCDIS      0x00010000
 138 #define UARTBAUD_LBKDIE         0x00008000
 139 #define UARTBAUD_RXEDGIE        0x00004000
 140 #define UARTBAUD_SBNS           0x00002000
 141 #define UARTBAUD_SBR            0x00000000
 142 #define UARTBAUD_SBR_MASK       0x1fff
 143
 144 #define UARTSTAT_LBKDIF         0x80000000
 145 #define UARTSTAT_RXEDGIF        0x40000000
 146 #define UARTSTAT_MSBF           0x20000000
 147 #define UARTSTAT_RXINV          0x10000000
 148 #define UARTSTAT_RWUID          0x08000000
 149 #define UARTSTAT_BRK13          0x04000000
 150 #define UARTSTAT_LBKDE          0x02000000
 151 #define UARTSTAT_RAF            0x01000000
 152 #define UARTSTAT_TDRE           0x00800000
 153 #define UARTSTAT_TC             0x00400000
 154 #define UARTSTAT_RDRF           0x00200000
 155 #define UARTSTAT_IDLE           0x00100000
 156 #define UARTSTAT_OR             0x00080000
 157 #define UARTSTAT_NF             0x00040000
 158 #define UARTSTAT_FE             0x00020000
 159 #define UARTSTAT_PE             0x00010000
 160 #define UARTSTAT_MA1F           0x00008000
 161 #define UARTSTAT_M21F           0x00004000
 162
 163 #define UARTCTRL_R8T9           0x80000000
 164 #define UARTCTRL_R9T8           0x40000000
 165 #define UARTCTRL_TXDIR          0x20000000
 166 #define UARTCTRL_TXINV          0x10000000
 167 #define UARTCTRL_ORIE           0x08000000
 168 #define UARTCTRL_NEIE           0x04000000
 169 #define UARTCTRL_FEIE           0x02000000
 170 #define UARTCTRL_PEIE           0x01000000
 171 #define UARTCTRL_TIE            0x00800000
 172 #define UARTCTRL_TCIE           0x00400000
 173 #define UARTCTRL_RIE            0x00200000
 174 #define UARTCTRL_ILIE           0x00100000
 175 #define UARTCTRL_TE             0x00080000
 176 #define UARTCTRL_RE             0x00040000
 177 #define UARTCTRL_RWU            0x00020000
 178 #define UARTCTRL_SBK            0x00010000
 179 #define UARTCTRL_MA1IE          0x00008000
 180 #define UARTCTRL_MA2IE          0x00004000
 181 #define UARTCTRL_IDLECFG        0x00000100
 182 #define UARTCTRL_LOOPS          0x00000080
 183 #define UARTCTRL_DOZEEN         0x00000040
 184 #define UARTCTRL_RSRC           0x00000020
 185 #define UARTCTRL_M              0x00000010
 186 #define UARTCTRL_WAKE           0x00000008
 187 #define UARTCTRL_ILT            0x00000004
 188 #define UARTCTRL_PE             0x00000002
 189 #define UARTCTRL_PT             0x00000001
 190
 191 #define UARTDATA_NOISY          0x00008000
 192 #define UARTDATA_PARITYE        0x00004000
 193 #define UARTDATA_FRETSC         0x00002000
 194 #define UARTDATA_RXEMPT         0x00001000
 195 #define UARTDATA_IDLINE         0x00000800
 196 #define UARTDATA_MASK           0x3ff
 197
 198 #define UARTMODIR_IREN          0x00020000
 199 #define UARTMODIR_TXCTSSRC      0x00000020
 200 #define UARTMODIR_TXCTSC        0x00000010
 201 #define UARTMODIR_RXRTSE        0x00000008
 202 #define UARTMODIR_TXRTSPOL      0x00000004
 203 #define UARTMODIR_TXRTSE        0x00000002
 204 #define UARTMODIR_TXCTSE        0x00000001
 205
 206 #define UARTFIFO_TXEMPT         0x00800000
 207 #define UARTFIFO_RXEMPT         0x00400000
 208 #define UARTFIFO_TXOF           0x00020000
 209 #define UARTFIFO_RXUF           0x00010000
 210 #define UARTFIFO_TXFLUSH        0x00008000
 211 #define UARTFIFO_RXFLUSH        0x00004000
 212 #define UARTFIFO_TXOFE          0x00000200
 213 #define UARTFIFO_RXUFE          0x00000100
 214 #define UARTFIFO_TXFE           0x00000080
 215 #define UARTFIFO_FIFOSIZE_MASK  0x7
 216 #define UARTFIFO_TXSIZE_OFF     4
 217 #define UARTFIFO_RXFE           0x00000008
 218 #define UARTFIFO_RXSIZE_OFF     0
 219
 220 #define UARTWATER_COUNT_MASK    0xff
 221 #define UARTWATER_TXCNT_OFF     8
 222 #define UARTWATER_RXCNT_OFF     24
 223 #define UARTWATER_WATER_MASK    0xff
 224 #define UARTWATER_TXWATER_OFF   0
 225 #define UARTWATER_RXWATER_OFF   16
 226
 227 #define FSL_UART_RX_DMA_BUFFER_SIZE     64
 228
 229 #define DRIVER_NAME     "fsl-lpuart"
 230 #define DEV_NAME        "ttyLP"
 231 #define UART_NR         6
 232
 233 struct lpuart_port {
 234         struct uart_port        port;
 235         struct clk              *clk;
 236         unsigned int            txfifo_size;
 237         unsigned int            rxfifo_size;
 238         bool                    lpuart32;
 239
 240         bool                    lpuart_dma_use;
 241         struct dma_chan         *dma_tx_chan;
 242         struct dma_chan         *dma_rx_chan;
 243         struct dma_async_tx_descriptor  *dma_tx_desc;
 244         struct dma_async_tx_descriptor  *dma_rx_desc;
 245         dma_addr_t              dma_tx_buf_bus;
 246         dma_addr_t              dma_rx_buf_bus;
 247         dma_cookie_t            dma_tx_cookie;
 248         dma_cookie_t            dma_rx_cookie;
 249         unsigned char           *dma_tx_buf_virt;
 250         unsigned char           *dma_rx_buf_virt;
 251         unsigned int            dma_tx_bytes;
 252         unsigned int            dma_rx_bytes;
 253         int                     dma_tx_in_progress;
 254         int                     dma_rx_in_progress;
 255         unsigned int            dma_rx_timeout;
 256         struct timer_list       lpuart_timer;
 257 };
 258
 259 static struct of_device_id lpuart_dt_ids[] = {
 260         {
 261                 .compatible = "fsl,vf610-lpuart",
 262         },
 263         {
 264                 .compatible = "fsl,ls1021a-lpuart",
 265         },
 266         { /* sentinel */ }
 267 };
 268 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 269
 270 /* Forward declare this for the dma callbacks*/
 271 static void lpuart_dma_tx_complete(void *arg);
 272 static void lpuart_dma_rx_complete(void *arg);
 273
 274 static u32 lpuart32_read(void __iomem *addr)
 275 {
 276         return ioread32be(addr);
 277 }
 278
 279 static void lpuart32_write(u32 val, void __iomem *addr)
 280 {
 281         iowrite32be(val, addr);
 282 }
 283
 284 static void lpuart_stop_tx(struct uart_port *port)
 285 {
 286         unsigned char temp;
 287
 288         temp = readb(port->membase + UARTCR2);
 289         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 290         writeb(temp, port->membase + UARTCR2);
 291 }
 292
 293 static void lpuart32_stop_tx(struct uart_port *port)
 294 {
 295         unsigned long temp;
 296
 297         temp = lpuart32_read(port->membase + UARTCTRL);
 298         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 299         lpuart32_write(temp, port->membase + UARTCTRL);
 300 }
 301
 302 static void lpuart_stop_rx(struct uart_port *port)
 303 {
 304         unsigned char temp;
 305
 306         temp = readb(port->membase + UARTCR2);
 307         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 308 }
 309
 310 static void lpuart32_stop_rx(struct uart_port *port)
 311 {
 312         unsigned long temp;
 313
 314         temp = lpuart32_read(port->membase + UARTCTRL);
 315         lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
 316 }
 317
 318 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
 319                 struct tty_port *tty, int count)
 320 {
 321         int copied;
 322
 323         sport->port.icount.rx += count;
 324
 325         if (!tty) {
 326                 dev_err(sport->port.dev, "No tty port\n");
 327                 return;
 328         }
 329
 330         dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
 331                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
 332         copied = tty_insert_flip_string(tty,
 333                         ((unsigned char *)(sport->dma_rx_buf_virt)), count);
 334
 335         if (copied != count) {
 336                 WARN_ON(1);
 337                 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
 338         }
 339
 340         dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
 341                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
 342 }
 343
 344 static void lpuart_pio_tx(struct lpuart_port *sport)
 345 {
 346         struct circ_buf *xmit = &sport->port.state->xmit;
 347         unsigned long flags;
 348
 349         spin_lock_irqsave(&sport->port.lock, flags);
 350
 351         while (!uart_circ_empty(xmit) &&
 352                 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
 353                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 354                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 355                 sport->port.icount.tx++;
 356         }
 357
 358         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 359                 uart_write_wakeup(&sport->port);
 360
 361         if (uart_circ_empty(xmit))
 362                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
 363                         sport->port.membase + UARTCR5);
 364
 365         spin_unlock_irqrestore(&sport->port.lock, flags);
 366 }
 367
 368 static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
 369 {
 370         struct circ_buf *xmit = &sport->port.state->xmit;
 371         dma_addr_t tx_bus_addr;
 372
 373         dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
 374                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 375         sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
 376         tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
 377         sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
 378                                         tx_bus_addr, sport->dma_tx_bytes,
 379                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 380
 381         if (!sport->dma_tx_desc) {
 382                 dev_err(sport->port.dev, "Not able to get desc for tx\n");
 383                 return -EIO;
 384         }
 385
 386         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 387         sport->dma_tx_desc->callback_param = sport;
 388         sport->dma_tx_in_progress = 1;
 389         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 390         dma_async_issue_pending(sport->dma_tx_chan);
 391
 392         return 0;
 393 }
 394
 395 static void lpuart_prepare_tx(struct lpuart_port *sport)
 396 {
 397         struct circ_buf *xmit = &sport->port.state->xmit;
 398         unsigned long count =  CIRC_CNT_TO_END(xmit->head,
 399                                         xmit->tail, UART_XMIT_SIZE);
 400
 401         if (!count)
 402                 return;
 403
 404         if (count < sport->txfifo_size)
 405                 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
 406                                 sport->port.membase + UARTCR5);
 407         else {
 408                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
 409                                 sport->port.membase + UARTCR5);
 410                 lpuart_dma_tx(sport, count);
 411         }
 412 }
 413
 414 static void lpuart_dma_tx_complete(void *arg)
 415 {
 416         struct lpuart_port *sport = arg;
 417         struct circ_buf *xmit = &sport->port.state->xmit;
 418         unsigned long flags;
 419
 420         async_tx_ack(sport->dma_tx_desc);
 421
 422         spin_lock_irqsave(&sport->port.lock, flags);
 423
 424         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 425         sport->dma_tx_in_progress = 0;
 426
 427         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 428                 uart_write_wakeup(&sport->port);
 429
 430         lpuart_prepare_tx(sport);
 431
 432         spin_unlock_irqrestore(&sport->port.lock, flags);
 433 }
 434
 435 static int lpuart_dma_rx(struct lpuart_port *sport)
 436 {
 437         dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
 438                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
 439         sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
 440                         sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
 441                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 442
 443         if (!sport->dma_rx_desc) {
 444                 dev_err(sport->port.dev, "Not able to get desc for rx\n");
 445                 return -EIO;
 446         }
 447
 448         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
 449         sport->dma_rx_desc->callback_param = sport;
 450         sport->dma_rx_in_progress = 1;
 451         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
 452         dma_async_issue_pending(sport->dma_rx_chan);
 453
 454         return 0;
 455 }
 456
 457 static void lpuart_dma_rx_complete(void *arg)
 458 {
 459         struct lpuart_port *sport = arg;
 460         struct tty_port *port = &sport->port.state->port;
 461         unsigned long flags;
 462
 463         async_tx_ack(sport->dma_rx_desc);
 464
 465         spin_lock_irqsave(&sport->port.lock, flags);
 466
 467         sport->dma_rx_in_progress = 0;
 468         lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
 469         tty_flip_buffer_push(port);
 470         lpuart_dma_rx(sport);
 471
 472         spin_unlock_irqrestore(&sport->port.lock, flags);
 473 }
 474
 475 static void lpuart_timer_func(unsigned long data)
 476 {
 477         struct lpuart_port *sport = (struct lpuart_port *)data;
 478         struct tty_port *port = &sport->port.state->port;
 479         struct dma_tx_state state;
 480         unsigned long flags;
 481         unsigned char temp;
 482         int count;
 483
 484         del_timer(&sport->lpuart_timer);
 485         dmaengine_pause(sport->dma_rx_chan);
 486         dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
 487         dmaengine_terminate_all(sport->dma_rx_chan);
 488         count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
 489         async_tx_ack(sport->dma_rx_desc);
 490
 491         spin_lock_irqsave(&sport->port.lock, flags);
 492
 493         sport->dma_rx_in_progress = 0;
 494         lpuart_copy_rx_to_tty(sport, port, count);
 495         tty_flip_buffer_push(port);
 496         temp = readb(sport->port.membase + UARTCR5);
 497         writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
 498
 499         spin_unlock_irqrestore(&sport->port.lock, flags);
 500 }
 501
 502 static inline void lpuart_prepare_rx(struct lpuart_port *sport)
 503 {
 504         unsigned long flags;
 505         unsigned char temp;
 506
 507         spin_lock_irqsave(&sport->port.lock, flags);
 508
 509         init_timer(&sport->lpuart_timer);
 510         sport->lpuart_timer.function = lpuart_timer_func;
 511         sport->lpuart_timer.data = (unsigned long)sport;
 512         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
 513         add_timer(&sport->lpuart_timer);
 514
 515         lpuart_dma_rx(sport);
 516         temp = readb(sport->port.membase + UARTCR5);
 517         writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
 518
 519         spin_unlock_irqrestore(&sport->port.lock, flags);
 520 }
 521
 522 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 523 {
 524         struct circ_buf *xmit = &sport->port.state->xmit;
 525
 526         while (!uart_circ_empty(xmit) &&
 527                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 528                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 529                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 530                 sport->port.icount.tx++;
 531         }
 532
 533         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 534                 uart_write_wakeup(&sport->port);
 535
 536         if (uart_circ_empty(xmit))
 537                 lpuart_stop_tx(&sport->port);
 538 }
 539
 540 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 541 {
 542         struct circ_buf *xmit = &sport->port.state->xmit;
 543         unsigned long txcnt;
 544
 545         txcnt = lpuart32_read(sport->port.membase + UARTWATER);
 546         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 547         txcnt &= UARTWATER_COUNT_MASK;
 548         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 549                 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
 550                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 551                 sport->port.icount.tx++;
 552                 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
 553                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 554                 txcnt &= UARTWATER_COUNT_MASK;
 555         }
 556
 557         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 558                 uart_write_wakeup(&sport->port);
 559
 560         if (uart_circ_empty(xmit))
 561                 lpuart32_stop_tx(&sport->port);
 562 }
 563
 564 static void lpuart_start_tx(struct uart_port *port)
 565 {
 566         struct lpuart_port *sport = container_of(port,
 567                         struct lpuart_port, port);
 568         struct circ_buf *xmit = &sport->port.state->xmit;
 569         unsigned char temp;
 570
 571         temp = readb(port->membase + UARTCR2);
 572         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 573
 574         if (sport->lpuart_dma_use) {
 575                 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
 576                         lpuart_prepare_tx(sport);
 577         } else {
 578                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 579                         lpuart_transmit_buffer(sport);
 580         }
 581 }
 582
 583 static void lpuart32_start_tx(struct uart_port *port)
 584 {
 585         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 586         unsigned long temp;
 587
 588         temp = lpuart32_read(port->membase + UARTCTRL);
 589         lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
 590
 591         if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
 592                 lpuart32_transmit_buffer(sport);
 593 }
 594
 595 static irqreturn_t lpuart_txint(int irq, void *dev_id)
 596 {
 597         struct lpuart_port *sport = dev_id;
 598         struct circ_buf *xmit = &sport->port.state->xmit;
 599         unsigned long flags;
 600
 601         spin_lock_irqsave(&sport->port.lock, flags);
 602         if (sport->port.x_char) {
 603                 if (sport->lpuart32)
 604                         lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
 605                 else
 606                         writeb(sport->port.x_char, sport->port.membase + UARTDR);
 607                 goto out;
 608         }
 609
 610         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 611                 if (sport->lpuart32)
 612                         lpuart32_stop_tx(&sport->port);
 613                 else
 614                         lpuart_stop_tx(&sport->port);
 615                 goto out;
 616         }
 617
 618         if (sport->lpuart32)
 619                 lpuart32_transmit_buffer(sport);
 620         else
 621                 lpuart_transmit_buffer(sport);
 622
 623         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 624                 uart_write_wakeup(&sport->port);
 625
 626 out:
 627         spin_unlock_irqrestore(&sport->port.lock, flags);
 628         return IRQ_HANDLED;
 629 }
 630
 631 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
 632 {
 633         struct lpuart_port *sport = dev_id;
 634         unsigned int flg, ignored = 0;
 635         struct tty_port *port = &sport->port.state->port;
 636         unsigned long flags;
 637         unsigned char rx, sr;
 638
 639         spin_lock_irqsave(&sport->port.lock, flags);
 640
 641         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 642                 flg = TTY_NORMAL;
 643                 sport->port.icount.rx++;
 644                 /*
 645                  * to clear the FE, OR, NF, FE, PE flags,
 646                  * read SR1 then read DR
 647                  */
 648                 sr = readb(sport->port.membase + UARTSR1);
 649                 rx = readb(sport->port.membase + UARTDR);
 650
 651                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 652                         continue;
 653
 654                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 655                         if (sr & UARTSR1_PE)
 656                                 sport->port.icount.parity++;
 657                         else if (sr & UARTSR1_FE)
 658                                 sport->port.icount.frame++;
 659
 660                         if (sr & UARTSR1_OR)
 661                                 sport->port.icount.overrun++;
 662
 663                         if (sr & sport->port.ignore_status_mask) {
 664                                 if (++ignored > 100)
 665                                         goto out;
 666                                 continue;
 667                         }
 668
 669                         sr &= sport->port.read_status_mask;
 670
 671                         if (sr & UARTSR1_PE)
 672                                 flg = TTY_PARITY;
 673                         else if (sr & UARTSR1_FE)
 674                                 flg = TTY_FRAME;
 675
 676                         if (sr & UARTSR1_OR)
 677                                 flg = TTY_OVERRUN;
 678
 679 #ifdef SUPPORT_SYSRQ
 680                         sport->port.sysrq = 0;
 681 #endif
 682                 }
 683
 684                 tty_insert_flip_char(port, rx, flg);
 685         }
 686
 687 out:
 688         spin_unlock_irqrestore(&sport->port.lock, flags);
 689
 690         tty_flip_buffer_push(port);
 691         return IRQ_HANDLED;
 692 }
 693
 694 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
 695 {
 696         struct lpuart_port *sport = dev_id;
 697         unsigned int flg, ignored = 0;
 698         struct tty_port *port = &sport->port.state->port;
 699         unsigned long flags;
 700         unsigned long rx, sr;
 701
 702         spin_lock_irqsave(&sport->port.lock, flags);
 703
 704         while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
 705                 flg = TTY_NORMAL;
 706                 sport->port.icount.rx++;
 707                 /*
 708                  * to clear the FE, OR, NF, FE, PE flags,
 709                  * read STAT then read DATA reg
 710                  */
 711                 sr = lpuart32_read(sport->port.membase + UARTSTAT);
 712                 rx = lpuart32_read(sport->port.membase + UARTDATA);
 713                 rx &= 0x3ff;
 714
 715                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 716                         continue;
 717
 718                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 719                         if (sr & UARTSTAT_PE)
 720                                 sport->port.icount.parity++;
 721                         else if (sr & UARTSTAT_FE)
 722                                 sport->port.icount.frame++;
 723
 724                         if (sr & UARTSTAT_OR)
 725                                 sport->port.icount.overrun++;
 726
 727                         if (sr & sport->port.ignore_status_mask) {
 728                                 if (++ignored > 100)
 729                                         goto out;
 730                                 continue;
 731                         }
 732
 733                         sr &= sport->port.read_status_mask;
 734
 735                         if (sr & UARTSTAT_PE)
 736                                 flg = TTY_PARITY;
 737                         else if (sr & UARTSTAT_FE)
 738                                 flg = TTY_FRAME;
 739
 740                         if (sr & UARTSTAT_OR)
 741                                 flg = TTY_OVERRUN;
 742
 743 #ifdef SUPPORT_SYSRQ
 744                         sport->port.sysrq = 0;
 745 #endif
 746                 }
 747
 748                 tty_insert_flip_char(port, rx, flg);
 749         }
 750
 751 out:
 752         spin_unlock_irqrestore(&sport->port.lock, flags);
 753
 754         tty_flip_buffer_push(port);
 755         return IRQ_HANDLED;
 756 }
 757
 758 static irqreturn_t lpuart_int(int irq, void *dev_id)
 759 {
 760         struct lpuart_port *sport = dev_id;
 761         unsigned char sts;
 762
 763         sts = readb(sport->port.membase + UARTSR1);
 764
 765         if (sts & UARTSR1_RDRF) {
 766                 if (sport->lpuart_dma_use)
 767                         lpuart_prepare_rx(sport);
 768                 else
 769                         lpuart_rxint(irq, dev_id);
 770         }
 771         if (sts & UARTSR1_TDRE &&
 772                 !(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS)) {
 773                 if (sport->lpuart_dma_use)
 774                         lpuart_pio_tx(sport);
 775                 else
 776                         lpuart_txint(irq, dev_id);
 777         }
 778
 779         return IRQ_HANDLED;
 780 }
 781
 782 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 783 {
 784         struct lpuart_port *sport = dev_id;
 785         unsigned long sts, rxcount;
 786
 787         sts = lpuart32_read(sport->port.membase + UARTSTAT);
 788         rxcount = lpuart32_read(sport->port.membase + UARTWATER);
 789         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 790
 791         if (sts & UARTSTAT_RDRF || rxcount > 0)
 792                 lpuart32_rxint(irq, dev_id);
 793
 794         if ((sts & UARTSTAT_TDRE) &&
 795                 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
 796                 lpuart_txint(irq, dev_id);
 797
 798         lpuart32_write(sts, sport->port.membase + UARTSTAT);
 799         return IRQ_HANDLED;
 800 }
 801
 802 /* return TIOCSER_TEMT when transmitter is not busy */
 803 static unsigned int lpuart_tx_empty(struct uart_port *port)
 804 {
 805         return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
 806                 TIOCSER_TEMT : 0;
 807 }
 808
 809 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 810 {
 811         return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
 812                 TIOCSER_TEMT : 0;
 813 }
 814
 815 static unsigned int lpuart_get_mctrl(struct uart_port *port)
 816 {
 817         unsigned int temp = 0;
 818         unsigned char reg;
 819
 820         reg = readb(port->membase + UARTMODEM);
 821         if (reg & UARTMODEM_TXCTSE)
 822                 temp |= TIOCM_CTS;
 823
 824         if (reg & UARTMODEM_RXRTSE)
 825                 temp |= TIOCM_RTS;
 826
 827         return temp;
 828 }
 829
 830 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
 831 {
 832         unsigned int temp = 0;
 833         unsigned long reg;
 834
 835         reg = lpuart32_read(port->membase + UARTMODIR);
 836         if (reg & UARTMODIR_TXCTSE)
 837                 temp |= TIOCM_CTS;
 838
 839         if (reg & UARTMODIR_RXRTSE)
 840                 temp |= TIOCM_RTS;
 841
 842         return temp;
 843 }
 844
 845 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 846 {
 847         unsigned char temp;
 848
 849         temp = readb(port->membase + UARTMODEM) &
 850                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
 851
 852         if (mctrl & TIOCM_RTS)
 853                 temp |= UARTMODEM_RXRTSE;
 854
 855         if (mctrl & TIOCM_CTS)
 856                 temp |= UARTMODEM_TXCTSE;
 857
 858         writeb(temp, port->membase + UARTMODEM);
 859 }
 860
 861 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 862 {
 863         unsigned long temp;
 864
 865         temp = lpuart32_read(port->membase + UARTMODIR) &
 866                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
 867
 868         if (mctrl & TIOCM_RTS)
 869                 temp |= UARTMODIR_RXRTSE;
 870
 871         if (mctrl & TIOCM_CTS)
 872                 temp |= UARTMODIR_TXCTSE;
 873
 874         lpuart32_write(temp, port->membase + UARTMODIR);
 875 }
 876
 877 static void lpuart_break_ctl(struct uart_port *port, int break_state)
 878 {
 879         unsigned char temp;
 880
 881         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
 882
 883         if (break_state != 0)
 884                 temp |= UARTCR2_SBK;
 885
 886         writeb(temp, port->membase + UARTCR2);
 887 }
 888
 889 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
 890 {
 891         unsigned long temp;
 892
 893         temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
 894
 895         if (break_state != 0)
 896                 temp |= UARTCTRL_SBK;
 897
 898         lpuart32_write(temp, port->membase + UARTCTRL);
 899 }
 900
 901 static void lpuart_setup_watermark(struct lpuart_port *sport)
 902 {
 903         unsigned char val, cr2;
 904         unsigned char cr2_saved;
 905
 906         cr2 = readb(sport->port.membase + UARTCR2);
 907         cr2_saved = cr2;
 908         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
 909                         UARTCR2_RIE | UARTCR2_RE);
 910         writeb(cr2, sport->port.membase + UARTCR2);
 911
 912         val = readb(sport->port.membase + UARTPFIFO);
 913         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
 914                         sport->port.membase + UARTPFIFO);
 915
 916         /* flush Tx and Rx FIFO */
 917         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 918                         sport->port.membase + UARTCFIFO);
 919
 920         writeb(0, sport->port.membase + UARTTWFIFO);
 921         writeb(1, sport->port.membase + UARTRWFIFO);
 922
 923         /* Restore cr2 */
 924         writeb(cr2_saved, sport->port.membase + UARTCR2);
 925 }
 926
 927 static void lpuart32_setup_watermark(struct lpuart_port *sport)
 928 {
 929         unsigned long val, ctrl;
 930         unsigned long ctrl_saved;
 931
 932         ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
 933         ctrl_saved = ctrl;
 934         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
 935                         UARTCTRL_RIE | UARTCTRL_RE);
 936         lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
 937
 938         /* enable FIFO mode */
 939         val = lpuart32_read(sport->port.membase + UARTFIFO);
 940         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
 941         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 942         lpuart32_write(val, sport->port.membase + UARTFIFO);
 943
 944         /* set the watermark */
 945         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
 946         lpuart32_write(val, sport->port.membase + UARTWATER);
 947
 948         /* Restore cr2 */
 949         lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
 950 }
 951
 952 static int lpuart_dma_tx_request(struct uart_port *port)
 953 {
 954         struct lpuart_port *sport = container_of(port,
 955                                         struct lpuart_port, port);
 956         struct dma_chan *tx_chan;
 957         struct dma_slave_config dma_tx_sconfig;
 958         dma_addr_t dma_bus;
 959         unsigned char *dma_buf;
 960         int ret;
 961
 962         tx_chan  = dma_request_slave_channel(sport->port.dev, "tx");
 963
 964         if (!tx_chan) {
 965                 dev_err(sport->port.dev, "Dma tx channel request failed!\n");
 966                 return -ENODEV;
 967         }
 968
 969         dma_bus = dma_map_single(tx_chan->device->dev,
 970                                 sport->port.state->xmit.buf,
 971                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 972
 973         if (dma_mapping_error(tx_chan->device->dev, dma_bus)) {
 974                 dev_err(sport->port.dev, "dma_map_single tx failed\n");
 975                 dma_release_channel(tx_chan);
 976                 return -ENOMEM;
 977         }
 978
 979         dma_buf = sport->port.state->xmit.buf;
 980         dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
 981         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 982         dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
 983         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 984         ret = dmaengine_slave_config(tx_chan, &dma_tx_sconfig);
 985
 986         if (ret < 0) {
 987                 dev_err(sport->port.dev,
 988                                 "Dma slave config failed, err = %d\n", ret);
 989                 dma_release_channel(tx_chan);
 990                 return ret;
 991         }
 992
 993         sport->dma_tx_chan = tx_chan;
 994         sport->dma_tx_buf_virt = dma_buf;
 995         sport->dma_tx_buf_bus = dma_bus;
 996         sport->dma_tx_in_progress = 0;
 997
 998         return 0;
 999 }
1000
1001 static int lpuart_dma_rx_request(struct uart_port *port)
1002 {
1003         struct lpuart_port *sport = container_of(port,
1004                                         struct lpuart_port, port);
1005         struct dma_chan *rx_chan;
1006         struct dma_slave_config dma_rx_sconfig;
1007         dma_addr_t dma_bus;
1008         unsigned char *dma_buf;
1009         int ret;
1010
1011         rx_chan  = dma_request_slave_channel(sport->port.dev, "rx");
1012
1013         if (!rx_chan) {
1014                 dev_err(sport->port.dev, "Dma rx channel request failed!\n");
1015                 return -ENODEV;
1016         }
1017
1018         dma_buf = devm_kzalloc(sport->port.dev,
1019                                 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
1020
1021         if (!dma_buf) {
1022                 dev_err(sport->port.dev, "Dma rx alloc failed\n");
1023                 dma_release_channel(rx_chan);
1024                 return -ENOMEM;
1025         }
1026
1027         dma_bus = dma_map_single(rx_chan->device->dev, dma_buf,
1028                                 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1029
1030         if (dma_mapping_error(rx_chan->device->dev, dma_bus)) {
1031                 dev_err(sport->port.dev, "dma_map_single rx failed\n");
1032                 dma_release_channel(rx_chan);
1033                 return -ENOMEM;
1034         }
1035
1036         dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1037         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1038         dma_rx_sconfig.src_maxburst = 1;
1039         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1040         ret = dmaengine_slave_config(rx_chan, &dma_rx_sconfig);
1041
1042         if (ret < 0) {
1043                 dev_err(sport->port.dev,
1044                                 "Dma slave config failed, err = %d\n", ret);
1045                 dma_release_channel(rx_chan);
1046                 return ret;
1047         }
1048
1049         sport->dma_rx_chan = rx_chan;
1050         sport->dma_rx_buf_virt = dma_buf;
1051         sport->dma_rx_buf_bus = dma_bus;
1052         sport->dma_rx_in_progress = 0;
1053
1054         return 0;
1055 }
1056
1057 static void lpuart_dma_tx_free(struct uart_port *port)
1058 {
1059         struct lpuart_port *sport = container_of(port,
1060                                         struct lpuart_port, port);
1061         struct dma_chan *dma_chan;
1062
1063         dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
1064                         UART_XMIT_SIZE, DMA_TO_DEVICE);
1065         dma_chan = sport->dma_tx_chan;
1066         sport->dma_tx_chan = NULL;
1067         sport->dma_tx_buf_bus = 0;
1068         sport->dma_tx_buf_virt = NULL;
1069         dma_release_channel(dma_chan);
1070 }
1071
1072 static void lpuart_dma_rx_free(struct uart_port *port)
1073 {
1074         struct lpuart_port *sport = container_of(port,
1075                                         struct lpuart_port, port);
1076         struct dma_chan *dma_chan;
1077
1078         dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
1079                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1080
1081         dma_chan = sport->dma_rx_chan;
1082         sport->dma_rx_chan = NULL;
1083         sport->dma_rx_buf_bus = 0;
1084         sport->dma_rx_buf_virt = NULL;
1085         dma_release_channel(dma_chan);
1086 }
1087
1088 static int lpuart_startup(struct uart_port *port)
1089 {
1090         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1091         int ret;
1092         unsigned long flags;
1093         unsigned char temp;
1094
1095         /* determine FIFO size and enable FIFO mode */
1096         temp = readb(sport->port.membase + UARTPFIFO);
1097
1098         sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1099                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1100
1101         sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1102                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1103
1104         /* Whether use dma support by dma request results */
1105         if (lpuart_dma_tx_request(port) || lpuart_dma_rx_request(port)) {
1106                 sport->lpuart_dma_use = false;
1107         } else {
1108                 sport->lpuart_dma_use = true;
1109                 temp = readb(port->membase + UARTCR5);
1110                 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1111         }
1112
1113         ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1114                                 DRIVER_NAME, sport);
1115         if (ret)
1116                 return ret;
1117
1118         spin_lock_irqsave(&sport->port.lock, flags);
1119
1120         lpuart_setup_watermark(sport);
1121
1122         temp = readb(sport->port.membase + UARTCR2);
1123         temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1124         writeb(temp, sport->port.membase + UARTCR2);
1125
1126         spin_unlock_irqrestore(&sport->port.lock, flags);
1127         return 0;
1128 }
1129
1130 static int lpuart32_startup(struct uart_port *port)
1131 {
1132         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1133         int ret;
1134         unsigned long flags;
1135         unsigned long temp;
1136
1137         /* determine FIFO size */
1138         temp = lpuart32_read(sport->port.membase + UARTFIFO);
1139
1140         sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1141                 UARTFIFO_FIFOSIZE_MASK) - 1);
1142
1143         sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1144                 UARTFIFO_FIFOSIZE_MASK) - 1);
1145
1146         ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1147                                 DRIVER_NAME, sport);
1148         if (ret)
1149                 return ret;
1150
1151         spin_lock_irqsave(&sport->port.lock, flags);
1152
1153         lpuart32_setup_watermark(sport);
1154
1155         temp = lpuart32_read(sport->port.membase + UARTCTRL);
1156         temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1157         temp |= UARTCTRL_ILIE;
1158         lpuart32_write(temp, sport->port.membase + UARTCTRL);
1159
1160         spin_unlock_irqrestore(&sport->port.lock, flags);
1161         return 0;
1162 }
1163
1164 static void lpuart_shutdown(struct uart_port *port)
1165 {
1166         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1167         unsigned char temp;
1168         unsigned long flags;
1169
1170         spin_lock_irqsave(&port->lock, flags);
1171
1172         /* disable Rx/Tx and interrupts */
1173         temp = readb(port->membase + UARTCR2);
1174         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1175                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1176         writeb(temp, port->membase + UARTCR2);
1177
1178         spin_unlock_irqrestore(&port->lock, flags);
1179
1180         devm_free_irq(port->dev, port->irq, sport);
1181
1182         if (sport->lpuart_dma_use) {
1183                 lpuart_dma_tx_free(port);
1184                 lpuart_dma_rx_free(port);
1185         }
1186 }
1187
1188 static void lpuart32_shutdown(struct uart_port *port)
1189 {
1190         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1191         unsigned long temp;
1192         unsigned long flags;
1193
1194         spin_lock_irqsave(&port->lock, flags);
1195
1196         /* disable Rx/Tx and interrupts */
1197         temp = lpuart32_read(port->membase + UARTCTRL);
1198         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1199                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1200         lpuart32_write(temp, port->membase + UARTCTRL);
1201
1202         spin_unlock_irqrestore(&port->lock, flags);
1203
1204         devm_free_irq(port->dev, port->irq, sport);
1205 }
1206
1207 static void
1208 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1209                    struct ktermios *old)
1210 {
1211         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1212         unsigned long flags;
1213         unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
1214         unsigned int  baud;
1215         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1216         unsigned int sbr, brfa;
1217
1218         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1219         old_cr2 = readb(sport->port.membase + UARTCR2);
1220         cr4 = readb(sport->port.membase + UARTCR4);
1221         bdh = readb(sport->port.membase + UARTBDH);
1222         modem = readb(sport->port.membase + UARTMODEM);
1223         /*
1224          * only support CS8 and CS7, and for CS7 must enable PE.
1225          * supported mode:
1226          *  - (7,e/o,1)
1227          *  - (8,n,1)
1228          *  - (8,m/s,1)
1229          *  - (8,e/o,1)
1230          */
1231         while ((termios->c_cflag & CSIZE) != CS8 &&
1232                 (termios->c_cflag & CSIZE) != CS7) {
1233                 termios->c_cflag &= ~CSIZE;
1234                 termios->c_cflag |= old_csize;
1235                 old_csize = CS8;
1236         }
1237
1238         if ((termios->c_cflag & CSIZE) == CS8 ||
1239                 (termios->c_cflag & CSIZE) == CS7)
1240                 cr1 = old_cr1 & ~UARTCR1_M;
1241
1242         if (termios->c_cflag & CMSPAR) {
1243                 if ((termios->c_cflag & CSIZE) != CS8) {
1244                         termios->c_cflag &= ~CSIZE;
1245                         termios->c_cflag |= CS8;
1246                 }
1247                 cr1 |= UARTCR1_M;
1248         }
1249
1250         if (termios->c_cflag & CRTSCTS) {
1251                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1252         } else {
1253                 termios->c_cflag &= ~CRTSCTS;
1254                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1255         }
1256
1257         if (termios->c_cflag & CSTOPB)
1258                 termios->c_cflag &= ~CSTOPB;
1259
1260         /* parity must be enabled when CS7 to match 8-bits format */
1261         if ((termios->c_cflag & CSIZE) == CS7)
1262                 termios->c_cflag |= PARENB;
1263
1264         if ((termios->c_cflag & PARENB)) {
1265                 if (termios->c_cflag & CMSPAR) {
1266                         cr1 &= ~UARTCR1_PE;
1267                         cr1 |= UARTCR1_M;
1268                 } else {
1269                         cr1 |= UARTCR1_PE;
1270                         if ((termios->c_cflag & CSIZE) == CS8)
1271                                 cr1 |= UARTCR1_M;
1272                         if (termios->c_cflag & PARODD)
1273                                 cr1 |= UARTCR1_PT;
1274                         else
1275                                 cr1 &= ~UARTCR1_PT;
1276                 }
1277         }
1278
1279         /* ask the core to calculate the divisor */
1280         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1281
1282         spin_lock_irqsave(&sport->port.lock, flags);
1283
1284         sport->port.read_status_mask = 0;
1285         if (termios->c_iflag & INPCK)
1286                 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1287         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1288                 sport->port.read_status_mask |= UARTSR1_FE;
1289
1290         /* characters to ignore */
1291         sport->port.ignore_status_mask = 0;
1292         if (termios->c_iflag & IGNPAR)
1293                 sport->port.ignore_status_mask |= UARTSR1_PE;
1294         if (termios->c_iflag & IGNBRK) {
1295                 sport->port.ignore_status_mask |= UARTSR1_FE;
1296                 /*
1297                  * if we're ignoring parity and break indicators,
1298                  * ignore overruns too (for real raw support).
1299                  */
1300                 if (termios->c_iflag & IGNPAR)
1301                         sport->port.ignore_status_mask |= UARTSR1_OR;
1302         }
1303
1304         /* update the per-port timeout */
1305         uart_update_timeout(port, termios->c_cflag, baud);
1306
1307         if (sport->lpuart_dma_use) {
1308                 /* Calculate delay for 1.5 DMA buffers */
1309                 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
1310                                         FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
1311                                         sport->rxfifo_size / 2;
1312                 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1313                         sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
1314                 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
1315                         sport->dma_rx_timeout = msecs_to_jiffies(20);
1316         }
1317
1318         /* wait transmit engin complete */
1319         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1320                 barrier();
1321
1322         /* disable transmit and receive */
1323         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1324                         sport->port.membase + UARTCR2);
1325
1326         sbr = sport->port.uartclk / (16 * baud);
1327         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1328         bdh &= ~UARTBDH_SBR_MASK;
1329         bdh |= (sbr >> 8) & 0x1F;
1330         cr4 &= ~UARTCR4_BRFA_MASK;
1331         brfa &= UARTCR4_BRFA_MASK;
1332         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1333         writeb(bdh, sport->port.membase + UARTBDH);
1334         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1335         writeb(cr1, sport->port.membase + UARTCR1);
1336         writeb(modem, sport->port.membase + UARTMODEM);
1337
1338         /* restore control register */
1339         writeb(old_cr2, sport->port.membase + UARTCR2);
1340
1341         spin_unlock_irqrestore(&sport->port.lock, flags);
1342 }
1343
1344 static void
1345 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1346                    struct ktermios *old)
1347 {
1348         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1349         unsigned long flags;
1350         unsigned long ctrl, old_ctrl, bd, modem;
1351         unsigned int  baud;
1352         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1353         unsigned int sbr;
1354
1355         ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1356         bd = lpuart32_read(sport->port.membase + UARTBAUD);
1357         modem = lpuart32_read(sport->port.membase + UARTMODIR);
1358         /*
1359          * only support CS8 and CS7, and for CS7 must enable PE.
1360          * supported mode:
1361          *  - (7,e/o,1)
1362          *  - (8,n,1)
1363          *  - (8,m/s,1)
1364          *  - (8,e/o,1)
1365          */
1366         while ((termios->c_cflag & CSIZE) != CS8 &&
1367                 (termios->c_cflag & CSIZE) != CS7) {
1368                 termios->c_cflag &= ~CSIZE;
1369                 termios->c_cflag |= old_csize;
1370                 old_csize = CS8;
1371         }
1372
1373         if ((termios->c_cflag & CSIZE) == CS8 ||
1374                 (termios->c_cflag & CSIZE) == CS7)
1375                 ctrl = old_ctrl & ~UARTCTRL_M;
1376
1377         if (termios->c_cflag & CMSPAR) {
1378                 if ((termios->c_cflag & CSIZE) != CS8) {
1379                         termios->c_cflag &= ~CSIZE;
1380                         termios->c_cflag |= CS8;
1381                 }
1382                 ctrl |= UARTCTRL_M;
1383         }
1384
1385         if (termios->c_cflag & CRTSCTS) {
1386                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1387         } else {
1388                 termios->c_cflag &= ~CRTSCTS;
1389                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1390         }
1391
1392         if (termios->c_cflag & CSTOPB)
1393                 termios->c_cflag &= ~CSTOPB;
1394
1395         /* parity must be enabled when CS7 to match 8-bits format */
1396         if ((termios->c_cflag & CSIZE) == CS7)
1397                 termios->c_cflag |= PARENB;
1398
1399         if ((termios->c_cflag & PARENB)) {
1400                 if (termios->c_cflag & CMSPAR) {
1401                         ctrl &= ~UARTCTRL_PE;
1402                         ctrl |= UARTCTRL_M;
1403                 } else {
1404                         ctrl |= UARTCR1_PE;
1405                         if ((termios->c_cflag & CSIZE) == CS8)
1406                                 ctrl |= UARTCTRL_M;
1407                         if (termios->c_cflag & PARODD)
1408                                 ctrl |= UARTCTRL_PT;
1409                         else
1410                                 ctrl &= ~UARTCTRL_PT;
1411                 }
1412         }
1413
1414         /* ask the core to calculate the divisor */
1415         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1416
1417         spin_lock_irqsave(&sport->port.lock, flags);
1418
1419         sport->port.read_status_mask = 0;
1420         if (termios->c_iflag & INPCK)
1421                 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1422         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1423                 sport->port.read_status_mask |= UARTSTAT_FE;
1424
1425         /* characters to ignore */
1426         sport->port.ignore_status_mask = 0;
1427         if (termios->c_iflag & IGNPAR)
1428                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1429         if (termios->c_iflag & IGNBRK) {
1430                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1431                 /*
1432                  * if we're ignoring parity and break indicators,
1433                  * ignore overruns too (for real raw support).
1434                  */
1435                 if (termios->c_iflag & IGNPAR)
1436                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1437         }
1438
1439         /* update the per-port timeout */
1440         uart_update_timeout(port, termios->c_cflag, baud);
1441
1442         /* wait transmit engin complete */
1443         while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1444                 barrier();
1445
1446         /* disable transmit and receive */
1447         lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1448                         sport->port.membase + UARTCTRL);
1449
1450         sbr = sport->port.uartclk / (16 * baud);
1451         bd &= ~UARTBAUD_SBR_MASK;
1452         bd |= sbr & UARTBAUD_SBR_MASK;
1453         bd |= UARTBAUD_BOTHEDGE;
1454         bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1455         lpuart32_write(bd, sport->port.membase + UARTBAUD);
1456         lpuart32_write(modem, sport->port.membase + UARTMODIR);
1457         lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1458         /* restore control register */
1459
1460         spin_unlock_irqrestore(&sport->port.lock, flags);
1461 }
1462
1463 static const char *lpuart_type(struct uart_port *port)
1464 {
1465         return "FSL_LPUART";
1466 }
1467
1468 static void lpuart_release_port(struct uart_port *port)
1469 {
1470         /* nothing to do */
1471 }
1472
1473 static int lpuart_request_port(struct uart_port *port)
1474 {
1475         return  0;
1476 }
1477
1478 /* configure/autoconfigure the port */
1479 static void lpuart_config_port(struct uart_port *port, int flags)
1480 {
1481         if (flags & UART_CONFIG_TYPE)
1482                 port->type = PORT_LPUART;
1483 }
1484
1485 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1486 {
1487         int ret = 0;
1488
1489         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1490                 ret = -EINVAL;
1491         if (port->irq != ser->irq)
1492                 ret = -EINVAL;
1493         if (ser->io_type != UPIO_MEM)
1494                 ret = -EINVAL;
1495         if (port->uartclk / 16 != ser->baud_base)
1496                 ret = -EINVAL;
1497         if (port->iobase != ser->port)
1498                 ret = -EINVAL;
1499         if (ser->hub6 != 0)
1500                 ret = -EINVAL;
1501         return ret;
1502 }
1503
1504 static struct uart_ops lpuart_pops = {
1505         .tx_empty       = lpuart_tx_empty,
1506         .set_mctrl      = lpuart_set_mctrl,
1507         .get_mctrl      = lpuart_get_mctrl,
1508         .stop_tx        = lpuart_stop_tx,
1509         .start_tx       = lpuart_start_tx,
1510         .stop_rx        = lpuart_stop_rx,
1511         .break_ctl      = lpuart_break_ctl,
1512         .startup        = lpuart_startup,
1513         .shutdown       = lpuart_shutdown,
1514         .set_termios    = lpuart_set_termios,
1515         .type           = lpuart_type,
1516         .request_port   = lpuart_request_port,
1517         .release_port   = lpuart_release_port,
1518         .config_port    = lpuart_config_port,
1519         .verify_port    = lpuart_verify_port,
1520 };
1521
1522 static struct uart_ops lpuart32_pops = {
1523         .tx_empty       = lpuart32_tx_empty,
1524         .set_mctrl      = lpuart32_set_mctrl,
1525         .get_mctrl      = lpuart32_get_mctrl,
1526         .stop_tx        = lpuart32_stop_tx,
1527         .start_tx       = lpuart32_start_tx,
1528         .stop_rx        = lpuart32_stop_rx,
1529         .break_ctl      = lpuart32_break_ctl,
1530         .startup        = lpuart32_startup,
1531         .shutdown       = lpuart32_shutdown,
1532         .set_termios    = lpuart32_set_termios,
1533         .type           = lpuart_type,
1534         .request_port   = lpuart_request_port,
1535         .release_port   = lpuart_release_port,
1536         .config_port    = lpuart_config_port,
1537         .verify_port    = lpuart_verify_port,
1538 };
1539
1540 static struct lpuart_port *lpuart_ports[UART_NR];
1541
1542 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1543 static void lpuart_console_putchar(struct uart_port *port, int ch)
1544 {
1545         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1546                 barrier();
1547
1548         writeb(ch, port->membase + UARTDR);
1549 }
1550
1551 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1552 {
1553         while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1554                 barrier();
1555
1556         lpuart32_write(ch, port->membase + UARTDATA);
1557 }
1558
1559 static void
1560 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1561 {
1562         struct lpuart_port *sport = lpuart_ports[co->index];
1563         unsigned char  old_cr2, cr2;
1564
1565         /* first save CR2 and then disable interrupts */
1566         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1567         cr2 |= (UARTCR2_TE |  UARTCR2_RE);
1568         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1569         writeb(cr2, sport->port.membase + UARTCR2);
1570
1571         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1572
1573         /* wait for transmitter finish complete and restore CR2 */
1574         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1575                 barrier();
1576
1577         writeb(old_cr2, sport->port.membase + UARTCR2);
1578 }
1579
1580 static void
1581 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1582 {
1583         struct lpuart_port *sport = lpuart_ports[co->index];
1584         unsigned long  old_cr, cr;
1585
1586         /* first save CR2 and then disable interrupts */
1587         cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1588         cr |= (UARTCTRL_TE |  UARTCTRL_RE);
1589         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1590         lpuart32_write(cr, sport->port.membase + UARTCTRL);
1591
1592         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1593
1594         /* wait for transmitter finish complete and restore CR2 */
1595         while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1596                 barrier();
1597
1598         lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1599 }
1600
1601 /*
1602  * if the port was already initialised (eg, by a boot loader),
1603  * try to determine the current setup.
1604  */
1605 static void __init
1606 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1607                            int *parity, int *bits)
1608 {
1609         unsigned char cr, bdh, bdl, brfa;
1610         unsigned int sbr, uartclk, baud_raw;
1611
1612         cr = readb(sport->port.membase + UARTCR2);
1613         cr &= UARTCR2_TE | UARTCR2_RE;
1614         if (!cr)
1615                 return;
1616
1617         /* ok, the port was enabled */
1618
1619         cr = readb(sport->port.membase + UARTCR1);
1620
1621         *parity = 'n';
1622         if (cr & UARTCR1_PE) {
1623                 if (cr & UARTCR1_PT)
1624                         *parity = 'o';
1625                 else
1626                         *parity = 'e';
1627         }
1628
1629         if (cr & UARTCR1_M)
1630                 *bits = 9;
1631         else
1632                 *bits = 8;
1633
1634         bdh = readb(sport->port.membase + UARTBDH);
1635         bdh &= UARTBDH_SBR_MASK;
1636         bdl = readb(sport->port.membase + UARTBDL);
1637         sbr = bdh;
1638         sbr <<= 8;
1639         sbr |= bdl;
1640         brfa = readb(sport->port.membase + UARTCR4);
1641         brfa &= UARTCR4_BRFA_MASK;
1642
1643         uartclk = clk_get_rate(sport->clk);
1644         /*
1645          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1646          */
1647         baud_raw = uartclk / (16 * (sbr + brfa / 32));
1648
1649         if (*baud != baud_raw)
1650                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1651                                 "from %d to %d\n", baud_raw, *baud);
1652 }
1653
1654 static void __init
1655 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1656                            int *parity, int *bits)
1657 {
1658         unsigned long cr, bd;
1659         unsigned int sbr, uartclk, baud_raw;
1660
1661         cr = lpuart32_read(sport->port.membase + UARTCTRL);
1662         cr &= UARTCTRL_TE | UARTCTRL_RE;
1663         if (!cr)
1664                 return;
1665
1666         /* ok, the port was enabled */
1667
1668         cr = lpuart32_read(sport->port.membase + UARTCTRL);
1669
1670         *parity = 'n';
1671         if (cr & UARTCTRL_PE) {
1672                 if (cr & UARTCTRL_PT)
1673                         *parity = 'o';
1674                 else
1675                         *parity = 'e';
1676         }
1677
1678         if (cr & UARTCTRL_M)
1679                 *bits = 9;
1680         else
1681                 *bits = 8;
1682
1683         bd = lpuart32_read(sport->port.membase + UARTBAUD);
1684         bd &= UARTBAUD_SBR_MASK;
1685         sbr = bd;
1686         uartclk = clk_get_rate(sport->clk);
1687         /*
1688          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1689          */
1690         baud_raw = uartclk / (16 * sbr);
1691
1692         if (*baud != baud_raw)
1693                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1694                                 "from %d to %d\n", baud_raw, *baud);
1695 }
1696
1697 static int __init lpuart_console_setup(struct console *co, char *options)
1698 {
1699         struct lpuart_port *sport;
1700         int baud = 115200;
1701         int bits = 8;
1702         int parity = 'n';
1703         int flow = 'n';
1704
1705         /*
1706          * check whether an invalid uart number has been specified, and
1707          * if so, search for the first available port that does have
1708          * console support.
1709          */
1710         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1711                 co->index = 0;
1712
1713         sport = lpuart_ports[co->index];
1714         if (sport == NULL)
1715                 return -ENODEV;
1716
1717         if (options)
1718                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1719         else
1720                 if (sport->lpuart32)
1721                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
1722                 else
1723                         lpuart_console_get_options(sport, &baud, &parity, &bits);
1724
1725         if (sport->lpuart32)
1726                 lpuart32_setup_watermark(sport);
1727         else
1728                 lpuart_setup_watermark(sport);
1729
1730         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1731 }
1732
1733 static struct uart_driver lpuart_reg;
1734 static struct console lpuart_console = {
1735         .name           = DEV_NAME,
1736         .write          = lpuart_console_write,
1737         .device         = uart_console_device,
1738         .setup          = lpuart_console_setup,
1739         .flags          = CON_PRINTBUFFER,
1740         .index          = -1,
1741         .data           = &lpuart_reg,
1742 };
1743
1744 static struct console lpuart32_console = {
1745         .name           = DEV_NAME,
1746         .write          = lpuart32_console_write,
1747         .device         = uart_console_device,
1748         .setup          = lpuart_console_setup,
1749         .flags          = CON_PRINTBUFFER,
1750         .index          = -1,
1751         .data           = &lpuart_reg,
1752 };
1753
1754 #define LPUART_CONSOLE  (&lpuart_console)
1755 #define LPUART32_CONSOLE        (&lpuart32_console)
1756 #else
1757 #define LPUART_CONSOLE  NULL
1758 #define LPUART32_CONSOLE        NULL
1759 #endif
1760
1761 static struct uart_driver lpuart_reg = {
1762         .owner          = THIS_MODULE,
1763         .driver_name    = DRIVER_NAME,
1764         .dev_name       = DEV_NAME,
1765         .nr             = ARRAY_SIZE(lpuart_ports),
1766         .cons           = LPUART_CONSOLE,
1767 };
1768
1769 static int lpuart_probe(struct platform_device *pdev)
1770 {
1771         struct device_node *np = pdev->dev.of_node;
1772         struct lpuart_port *sport;
1773         struct resource *res;
1774         int ret;
1775
1776         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1777         if (!sport)
1778                 return -ENOMEM;
1779
1780         pdev->dev.coherent_dma_mask = 0;
1781
1782         ret = of_alias_get_id(np, "serial");
1783         if (ret < 0) {
1784                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1785                 return ret;
1786         }
1787         sport->port.line = ret;
1788         sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
1789
1790         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1791         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1792         if (IS_ERR(sport->port.membase))
1793                 return PTR_ERR(sport->port.membase);
1794
1795         sport->port.mapbase = res->start;
1796         sport->port.dev = &pdev->dev;
1797         sport->port.type = PORT_LPUART;
1798         sport->port.iotype = UPIO_MEM;
1799         sport->port.irq = platform_get_irq(pdev, 0);
1800         if (sport->lpuart32)
1801                 sport->port.ops = &lpuart32_pops;
1802         else
1803                 sport->port.ops = &lpuart_pops;
1804         sport->port.flags = UPF_BOOT_AUTOCONF;
1805
1806         sport->clk = devm_clk_get(&pdev->dev, "ipg");
1807         if (IS_ERR(sport->clk)) {
1808                 ret = PTR_ERR(sport->clk);
1809                 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1810                 return ret;
1811         }
1812
1813         ret = clk_prepare_enable(sport->clk);
1814         if (ret) {
1815                 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1816                 return ret;
1817         }
1818
1819         sport->port.uartclk = clk_get_rate(sport->clk);
1820
1821         lpuart_ports[sport->port.line] = sport;
1822
1823         platform_set_drvdata(pdev, &sport->port);
1824
1825         if (sport->lpuart32)
1826                 lpuart_reg.cons = LPUART32_CONSOLE;
1827         else
1828                 lpuart_reg.cons = LPUART_CONSOLE;
1829
1830         ret = uart_add_one_port(&lpuart_reg, &sport->port);
1831         if (ret) {
1832                 clk_disable_unprepare(sport->clk);
1833                 return ret;
1834         }
1835
1836         return 0;
1837 }
1838
1839 static int lpuart_remove(struct platform_device *pdev)
1840 {
1841         struct lpuart_port *sport = platform_get_drvdata(pdev);
1842
1843         uart_remove_one_port(&lpuart_reg, &sport->port);
1844
1845         clk_disable_unprepare(sport->clk);
1846
1847         return 0;
1848 }
1849
1850 #ifdef CONFIG_PM_SLEEP
1851 static int lpuart_suspend(struct device *dev)
1852 {
1853         struct lpuart_port *sport = dev_get_drvdata(dev);
1854
1855         uart_suspend_port(&lpuart_reg, &sport->port);
1856
1857         return 0;
1858 }
1859
1860 static int lpuart_resume(struct device *dev)
1861 {
1862         struct lpuart_port *sport = dev_get_drvdata(dev);
1863         unsigned long temp;
1864
1865         if (sport->lpuart32) {
1866                 lpuart32_setup_watermark(sport);
1867                 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1868                 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1869                          UARTCTRL_TE | UARTCTRL_ILIE);
1870                 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1871         } else {
1872                 lpuart_setup_watermark(sport);
1873                 temp = readb(sport->port.membase + UARTCR2);
1874                 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1875                 writeb(temp, sport->port.membase + UARTCR2);
1876         }
1877
1878         uart_resume_port(&lpuart_reg, &sport->port);
1879
1880         return 0;
1881 }
1882 #endif
1883
1884 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1885
1886 static struct platform_driver lpuart_driver = {
1887         .probe          = lpuart_probe,
1888         .remove         = lpuart_remove,
1889         .driver         = {
1890                 .name   = "fsl-lpuart",
1891                 .of_match_table = lpuart_dt_ids,
1892                 .pm     = &lpuart_pm_ops,
1893         },
1894 };
1895
1896 static int __init lpuart_serial_init(void)
1897 {
1898         int ret = uart_register_driver(&lpuart_reg);
1899
1900         if (ret)
1901                 return ret;
1902
1903         ret = platform_driver_register(&lpuart_driver);
1904         if (ret)
1905                 uart_unregister_driver(&lpuart_reg);
1906
1907         return ret;
1908 }
1909
1910 static void __exit lpuart_serial_exit(void)
1911 {
1912         platform_driver_unregister(&lpuart_driver);
1913         uart_unregister_driver(&lpuart_reg);
1914 }
1915
1916 module_init(lpuart_serial_init);
1917 module_exit(lpuart_serial_exit);
1918
1919 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1920 MODULE_LICENSE("GPL v2");