2 * Driver for AMBA serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
32 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/device.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/amba/bus.h>
47 #include <linux/amba/serial.h>
48 #include <linux/clk.h>
49 #include <linux/slab.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53 #include <linux/delay.h>
56 #include <asm/sizes.h>
60 #define SERIAL_AMBA_MAJOR 204
61 #define SERIAL_AMBA_MINOR 64
62 #define SERIAL_AMBA_NR UART_NR
64 #define AMBA_ISR_PASS_LIMIT 256
66 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
67 #define UART_DUMMY_DR_RX (1 << 16)
70 #define UART_WA_SAVE_NR 14
72 static void pl011_lockup_wa(unsigned long data);
73 static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
90 static u32 uart_wa_regdata[UART_WA_SAVE_NR];
91 static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
93 /* There is by now at least one vendor with differing details, so handle it */
96 unsigned int fifosize;
100 bool interrupt_may_hang; /* vendor-specific */
104 static struct vendor_data vendor_arm = {
105 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
107 .lcrh_tx = UART011_LCRH,
108 .lcrh_rx = UART011_LCRH,
109 .oversampling = false,
110 .dma_threshold = false,
113 static struct vendor_data vendor_st = {
114 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
116 .lcrh_tx = ST_UART011_LCRH_TX,
117 .lcrh_rx = ST_UART011_LCRH_RX,
118 .oversampling = true,
119 .interrupt_may_hang = true,
120 .dma_threshold = true,
123 static struct uart_amba_port *amba_ports[UART_NR];
125 /* Deals with DMA transactions */
128 struct scatterlist sg;
132 struct pl011_dmarx_data {
133 struct dma_chan *chan;
134 struct completion complete;
136 struct pl011_sgbuf sgbuf_a;
137 struct pl011_sgbuf sgbuf_b;
142 struct pl011_dmatx_data {
143 struct dma_chan *chan;
144 struct scatterlist sg;
150 * We wrap our port structure around the generic uart_port.
152 struct uart_amba_port {
153 struct uart_port port;
155 const struct vendor_data *vendor;
156 unsigned int dmacr; /* dma control reg */
157 unsigned int im; /* interrupt mask */
158 unsigned int old_status;
159 unsigned int fifosize; /* vendor-specific */
160 unsigned int lcrh_tx; /* vendor-specific */
161 unsigned int lcrh_rx; /* vendor-specific */
162 unsigned int old_cr; /* state during shutdown */
165 bool interrupt_may_hang; /* vendor-specific */
166 #ifdef CONFIG_DMA_ENGINE
170 struct pl011_dmarx_data dmarx;
171 struct pl011_dmatx_data dmatx;
176 * Reads up to 256 characters from the FIFO or until it's empty and
177 * inserts them into the TTY layer. Returns the number of characters
178 * read from the FIFO.
180 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
183 unsigned int flag, max_count = 256;
186 while (max_count--) {
187 status = readw(uap->port.membase + UART01x_FR);
188 if (status & UART01x_FR_RXFE)
191 /* Take chars from the FIFO and update status */
192 ch = readw(uap->port.membase + UART01x_DR) |
195 uap->port.icount.rx++;
198 if (unlikely(ch & UART_DR_ERROR)) {
199 if (ch & UART011_DR_BE) {
200 ch &= ~(UART011_DR_FE | UART011_DR_PE);
201 uap->port.icount.brk++;
202 if (uart_handle_break(&uap->port))
204 } else if (ch & UART011_DR_PE)
205 uap->port.icount.parity++;
206 else if (ch & UART011_DR_FE)
207 uap->port.icount.frame++;
208 if (ch & UART011_DR_OE)
209 uap->port.icount.overrun++;
211 ch &= uap->port.read_status_mask;
213 if (ch & UART011_DR_BE)
215 else if (ch & UART011_DR_PE)
217 else if (ch & UART011_DR_FE)
221 if (uart_handle_sysrq_char(&uap->port, ch & 255))
224 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
232 * All the DMA operation mode stuff goes inside this ifdef.
233 * This assumes that you have a generic DMA device interface,
234 * no custom DMA interfaces are supported.
236 #ifdef CONFIG_DMA_ENGINE
238 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
240 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
241 enum dma_data_direction dir)
243 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
247 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
249 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
256 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
257 enum dma_data_direction dir)
260 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
265 static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
267 /* DMA is the sole user of the platform data right now */
268 struct amba_pl011_data *plat = uap->port.dev->platform_data;
269 struct dma_slave_config tx_conf = {
270 .dst_addr = uap->port.mapbase + UART01x_DR,
271 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
272 .direction = DMA_MEM_TO_DEV,
273 .dst_maxburst = uap->fifosize >> 1,
275 struct dma_chan *chan;
278 /* We need platform data */
279 if (!plat || !plat->dma_filter) {
280 dev_info(uap->port.dev, "no DMA platform data\n");
284 /* Try to acquire a generic DMA engine slave TX channel */
286 dma_cap_set(DMA_SLAVE, mask);
288 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
290 dev_err(uap->port.dev, "no TX DMA channel!\n");
294 dmaengine_slave_config(chan, &tx_conf);
295 uap->dmatx.chan = chan;
297 dev_info(uap->port.dev, "DMA channel TX %s\n",
298 dma_chan_name(uap->dmatx.chan));
300 /* Optionally make use of an RX channel as well */
301 if (plat->dma_rx_param) {
302 struct dma_slave_config rx_conf = {
303 .src_addr = uap->port.mapbase + UART01x_DR,
304 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
305 .direction = DMA_DEV_TO_MEM,
306 .src_maxburst = uap->fifosize >> 1,
309 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
311 dev_err(uap->port.dev, "no RX DMA channel!\n");
315 dmaengine_slave_config(chan, &rx_conf);
316 uap->dmarx.chan = chan;
318 dev_info(uap->port.dev, "DMA channel RX %s\n",
319 dma_chan_name(uap->dmarx.chan));
325 * Stack up the UARTs and let the above initcall be done at device
326 * initcall time, because the serial driver is called as an arch
327 * initcall, and at this time the DMA subsystem is not yet registered.
328 * At this point the driver will switch over to using DMA where desired.
331 struct list_head node;
332 struct uart_amba_port *uap;
335 static LIST_HEAD(pl011_dma_uarts);
337 static int __init pl011_dma_initcall(void)
339 struct list_head *node, *tmp;
341 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
342 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
343 pl011_dma_probe_initcall(dmau->uap);
350 device_initcall(pl011_dma_initcall);
352 static void pl011_dma_probe(struct uart_amba_port *uap)
354 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
357 list_add_tail(&dmau->node, &pl011_dma_uarts);
361 static void pl011_dma_probe(struct uart_amba_port *uap)
363 pl011_dma_probe_initcall(uap);
367 static void pl011_dma_remove(struct uart_amba_port *uap)
369 /* TODO: remove the initcall if it has not yet executed */
371 dma_release_channel(uap->dmatx.chan);
373 dma_release_channel(uap->dmarx.chan);
376 /* Forward declare this for the refill routine */
377 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
380 * The current DMA TX buffer has been sent.
381 * Try to queue up another DMA buffer.
383 static void pl011_dma_tx_callback(void *data)
385 struct uart_amba_port *uap = data;
386 struct pl011_dmatx_data *dmatx = &uap->dmatx;
390 spin_lock_irqsave(&uap->port.lock, flags);
391 if (uap->dmatx.queued)
392 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
396 uap->dmacr = dmacr & ~UART011_TXDMAE;
397 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
400 * If TX DMA was disabled, it means that we've stopped the DMA for
401 * some reason (eg, XOFF received, or we want to send an X-char.)
403 * Note: we need to be careful here of a potential race between DMA
404 * and the rest of the driver - if the driver disables TX DMA while
405 * a TX buffer completing, we must update the tx queued status to
406 * get further refills (hence we check dmacr).
408 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
409 uart_circ_empty(&uap->port.state->xmit)) {
410 uap->dmatx.queued = false;
411 spin_unlock_irqrestore(&uap->port.lock, flags);
415 if (pl011_dma_tx_refill(uap) <= 0) {
417 * We didn't queue a DMA buffer for some reason, but we
418 * have data pending to be sent. Re-enable the TX IRQ.
420 uap->im |= UART011_TXIM;
421 writew(uap->im, uap->port.membase + UART011_IMSC);
423 spin_unlock_irqrestore(&uap->port.lock, flags);
427 * Try to refill the TX DMA buffer.
428 * Locking: called with port lock held and IRQs disabled.
430 * 1 if we queued up a TX DMA buffer.
431 * 0 if we didn't want to handle this by DMA
434 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
436 struct pl011_dmatx_data *dmatx = &uap->dmatx;
437 struct dma_chan *chan = dmatx->chan;
438 struct dma_device *dma_dev = chan->device;
439 struct dma_async_tx_descriptor *desc;
440 struct circ_buf *xmit = &uap->port.state->xmit;
444 * Try to avoid the overhead involved in using DMA if the
445 * transaction fits in the first half of the FIFO, by using
446 * the standard interrupt handling. This ensures that we
447 * issue a uart_write_wakeup() at the appropriate time.
449 count = uart_circ_chars_pending(xmit);
450 if (count < (uap->fifosize >> 1)) {
451 uap->dmatx.queued = false;
456 * Bodge: don't send the last character by DMA, as this
457 * will prevent XON from notifying us to restart DMA.
461 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
462 if (count > PL011_DMA_BUFFER_SIZE)
463 count = PL011_DMA_BUFFER_SIZE;
465 if (xmit->tail < xmit->head)
466 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
468 size_t first = UART_XMIT_SIZE - xmit->tail;
469 size_t second = xmit->head;
471 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
473 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
476 dmatx->sg.length = count;
478 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
479 uap->dmatx.queued = false;
480 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
484 desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
485 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
487 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
488 uap->dmatx.queued = false;
490 * If DMA cannot be used right now, we complete this
491 * transaction via IRQ and let the TTY layer retry.
493 dev_dbg(uap->port.dev, "TX DMA busy\n");
497 /* Some data to go along to the callback */
498 desc->callback = pl011_dma_tx_callback;
499 desc->callback_param = uap;
501 /* All errors should happen at prepare time */
502 dmaengine_submit(desc);
504 /* Fire the DMA transaction */
505 dma_dev->device_issue_pending(chan);
507 uap->dmacr |= UART011_TXDMAE;
508 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
509 uap->dmatx.queued = true;
512 * Now we know that DMA will fire, so advance the ring buffer
513 * with the stuff we just dispatched.
515 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
516 uap->port.icount.tx += count;
518 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
519 uart_write_wakeup(&uap->port);
525 * We received a transmit interrupt without a pending X-char but with
526 * pending characters.
527 * Locking: called with port lock held and IRQs disabled.
529 * false if we want to use PIO to transmit
530 * true if we queued a DMA buffer
532 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
534 if (!uap->using_tx_dma)
538 * If we already have a TX buffer queued, but received a
539 * TX interrupt, it will be because we've just sent an X-char.
540 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
542 if (uap->dmatx.queued) {
543 uap->dmacr |= UART011_TXDMAE;
544 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
545 uap->im &= ~UART011_TXIM;
546 writew(uap->im, uap->port.membase + UART011_IMSC);
551 * We don't have a TX buffer queued, so try to queue one.
552 * If we successfully queued a buffer, mask the TX IRQ.
554 if (pl011_dma_tx_refill(uap) > 0) {
555 uap->im &= ~UART011_TXIM;
556 writew(uap->im, uap->port.membase + UART011_IMSC);
563 * Stop the DMA transmit (eg, due to received XOFF).
564 * Locking: called with port lock held and IRQs disabled.
566 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
568 if (uap->dmatx.queued) {
569 uap->dmacr &= ~UART011_TXDMAE;
570 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
575 * Try to start a DMA transmit, or in the case of an XON/OFF
576 * character queued for send, try to get that character out ASAP.
577 * Locking: called with port lock held and IRQs disabled.
579 * false if we want the TX IRQ to be enabled
580 * true if we have a buffer queued
582 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
586 if (!uap->using_tx_dma)
589 if (!uap->port.x_char) {
590 /* no X-char, try to push chars out in DMA mode */
593 if (!uap->dmatx.queued) {
594 if (pl011_dma_tx_refill(uap) > 0) {
595 uap->im &= ~UART011_TXIM;
598 uap->im |= UART011_TXIM;
601 writew(uap->im, uap->port.membase + UART011_IMSC);
602 } else if (!(uap->dmacr & UART011_TXDMAE)) {
603 uap->dmacr |= UART011_TXDMAE;
605 uap->port.membase + UART011_DMACR);
611 * We have an X-char to send. Disable DMA to prevent it loading
612 * the TX fifo, and then see if we can stuff it into the FIFO.
615 uap->dmacr &= ~UART011_TXDMAE;
616 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
618 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
620 * No space in the FIFO, so enable the transmit interrupt
621 * so we know when there is space. Note that once we've
622 * loaded the character, we should just re-enable DMA.
627 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
628 uap->port.icount.tx++;
629 uap->port.x_char = 0;
631 /* Success - restore the DMA state */
633 writew(dmacr, uap->port.membase + UART011_DMACR);
639 * Flush the transmit buffer.
640 * Locking: called with port lock held and IRQs disabled.
642 static void pl011_dma_flush_buffer(struct uart_port *port)
644 struct uart_amba_port *uap = (struct uart_amba_port *)port;
646 if (!uap->using_tx_dma)
649 /* Avoid deadlock with the DMA engine callback */
650 spin_unlock(&uap->port.lock);
651 dmaengine_terminate_all(uap->dmatx.chan);
652 spin_lock(&uap->port.lock);
653 if (uap->dmatx.queued) {
654 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
656 uap->dmatx.queued = false;
657 uap->dmacr &= ~UART011_TXDMAE;
658 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
662 static void pl011_dma_rx_callback(void *data);
664 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
666 struct dma_chan *rxchan = uap->dmarx.chan;
667 struct dma_device *dma_dev;
668 struct pl011_dmarx_data *dmarx = &uap->dmarx;
669 struct dma_async_tx_descriptor *desc;
670 struct pl011_sgbuf *sgbuf;
675 /* Start the RX DMA job */
676 sgbuf = uap->dmarx.use_buf_b ?
677 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
678 dma_dev = rxchan->device;
679 desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1,
681 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
683 * If the DMA engine is busy and cannot prepare a
684 * channel, no big deal, the driver will fall back
685 * to interrupt mode as a result of this error code.
688 uap->dmarx.running = false;
689 dmaengine_terminate_all(rxchan);
693 /* Some data to go along to the callback */
694 desc->callback = pl011_dma_rx_callback;
695 desc->callback_param = uap;
696 dmarx->cookie = dmaengine_submit(desc);
697 dma_async_issue_pending(rxchan);
699 uap->dmacr |= UART011_RXDMAE;
700 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
701 uap->dmarx.running = true;
703 uap->im &= ~UART011_RXIM;
704 writew(uap->im, uap->port.membase + UART011_IMSC);
710 * This is called when either the DMA job is complete, or
711 * the FIFO timeout interrupt occurred. This must be called
712 * with the port spinlock uap->port.lock held.
714 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
715 u32 pending, bool use_buf_b,
718 struct tty_struct *tty = uap->port.state->port.tty;
719 struct pl011_sgbuf *sgbuf = use_buf_b ?
720 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
721 struct device *dev = uap->dmarx.chan->device->dev;
723 u32 fifotaken = 0; /* only used for vdbg() */
725 /* Pick everything from the DMA first */
728 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
731 * First take all chars in the DMA pipe, then look in the FIFO.
732 * Note that tty_insert_flip_buf() tries to take as many chars
735 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
736 sgbuf->buf, pending);
738 /* Return buffer to device */
739 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
741 uap->port.icount.rx += dma_count;
742 if (dma_count < pending)
743 dev_warn(uap->port.dev,
744 "couldn't insert all characters (TTY is full?)\n");
748 * Only continue with trying to read the FIFO if all DMA chars have
751 if (dma_count == pending && readfifo) {
752 /* Clear any error flags */
753 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
754 uap->port.membase + UART011_ICR);
757 * If we read all the DMA'd characters, and we had an
758 * incomplete buffer, that could be due to an rx error, or
759 * maybe we just timed out. Read any pending chars and check
762 * Error conditions will only occur in the FIFO, these will
763 * trigger an immediate interrupt and stop the DMA job, so we
764 * will always find the error in the FIFO, never in the DMA
767 fifotaken = pl011_fifo_to_tty(uap);
770 spin_unlock(&uap->port.lock);
771 dev_vdbg(uap->port.dev,
772 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
773 dma_count, fifotaken);
774 tty_flip_buffer_push(tty);
775 spin_lock(&uap->port.lock);
778 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
780 struct pl011_dmarx_data *dmarx = &uap->dmarx;
781 struct dma_chan *rxchan = dmarx->chan;
782 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
783 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
785 struct dma_tx_state state;
786 enum dma_status dmastat;
789 * Pause the transfer so we can trust the current counter,
790 * do this before we pause the PL011 block, else we may
793 if (dmaengine_pause(rxchan))
794 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
795 dmastat = rxchan->device->device_tx_status(rxchan,
796 dmarx->cookie, &state);
797 if (dmastat != DMA_PAUSED)
798 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
800 /* Disable RX DMA - incoming data will wait in the FIFO */
801 uap->dmacr &= ~UART011_RXDMAE;
802 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
803 uap->dmarx.running = false;
805 pending = sgbuf->sg.length - state.residue;
806 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
807 /* Then we terminate the transfer - we now know our residue */
808 dmaengine_terminate_all(rxchan);
811 * This will take the chars we have so far and insert
812 * into the framework.
814 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
816 /* Switch buffer & re-trigger DMA job */
817 dmarx->use_buf_b = !dmarx->use_buf_b;
818 if (pl011_dma_rx_trigger_dma(uap)) {
819 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
820 "fall back to interrupt mode\n");
821 uap->im |= UART011_RXIM;
822 writew(uap->im, uap->port.membase + UART011_IMSC);
826 static void pl011_dma_rx_callback(void *data)
828 struct uart_amba_port *uap = data;
829 struct pl011_dmarx_data *dmarx = &uap->dmarx;
830 struct dma_chan *rxchan = dmarx->chan;
831 bool lastbuf = dmarx->use_buf_b;
832 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
833 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
835 struct dma_tx_state state;
839 * This completion interrupt occurs typically when the
840 * RX buffer is totally stuffed but no timeout has yet
841 * occurred. When that happens, we just want the RX
842 * routine to flush out the secondary DMA buffer while
843 * we immediately trigger the next DMA job.
845 spin_lock_irq(&uap->port.lock);
847 * Rx data can be taken by the UART interrupts during
848 * the DMA irq handler. So we check the residue here.
850 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
851 pending = sgbuf->sg.length - state.residue;
852 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
853 /* Then we terminate the transfer - we now know our residue */
854 dmaengine_terminate_all(rxchan);
856 uap->dmarx.running = false;
857 dmarx->use_buf_b = !lastbuf;
858 ret = pl011_dma_rx_trigger_dma(uap);
860 pl011_dma_rx_chars(uap, pending, lastbuf, false);
861 spin_unlock_irq(&uap->port.lock);
863 * Do this check after we picked the DMA chars so we don't
864 * get some IRQ immediately from RX.
867 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
868 "fall back to interrupt mode\n");
869 uap->im |= UART011_RXIM;
870 writew(uap->im, uap->port.membase + UART011_IMSC);
875 * Stop accepting received characters, when we're shutting down or
876 * suspending this port.
877 * Locking: called with port lock held and IRQs disabled.
879 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
881 /* FIXME. Just disable the DMA enable */
882 uap->dmacr &= ~UART011_RXDMAE;
883 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
886 static void pl011_dma_startup(struct uart_amba_port *uap)
890 if (!uap->dmatx.chan)
893 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
894 if (!uap->dmatx.buf) {
895 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
896 uap->port.fifosize = uap->fifosize;
900 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
902 /* The DMA buffer is now the FIFO the TTY subsystem can use */
903 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
904 uap->using_tx_dma = true;
906 if (!uap->dmarx.chan)
909 /* Allocate and map DMA RX buffers */
910 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
913 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
918 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
921 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
923 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
928 uap->using_rx_dma = true;
931 /* Turn on DMA error (RX/TX will be enabled on demand) */
932 uap->dmacr |= UART011_DMAONERR;
933 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
936 * ST Micro variants has some specific dma burst threshold
937 * compensation. Set this to 16 bytes, so burst will only
938 * be issued above/below 16 bytes.
940 if (uap->vendor->dma_threshold)
941 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
942 uap->port.membase + ST_UART011_DMAWM);
944 if (uap->using_rx_dma) {
945 if (pl011_dma_rx_trigger_dma(uap))
946 dev_dbg(uap->port.dev, "could not trigger initial "
947 "RX DMA job, fall back to interrupt mode\n");
951 static void pl011_dma_shutdown(struct uart_amba_port *uap)
953 if (!(uap->using_tx_dma || uap->using_rx_dma))
956 /* Disable RX and TX DMA */
957 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
960 spin_lock_irq(&uap->port.lock);
961 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
962 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
963 spin_unlock_irq(&uap->port.lock);
965 if (uap->using_tx_dma) {
966 /* In theory, this should already be done by pl011_dma_flush_buffer */
967 dmaengine_terminate_all(uap->dmatx.chan);
968 if (uap->dmatx.queued) {
969 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
971 uap->dmatx.queued = false;
974 kfree(uap->dmatx.buf);
975 uap->using_tx_dma = false;
978 if (uap->using_rx_dma) {
979 dmaengine_terminate_all(uap->dmarx.chan);
980 /* Clean up the RX DMA */
981 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
982 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
983 uap->using_rx_dma = false;
987 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
989 return uap->using_rx_dma;
992 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
994 return uap->using_rx_dma && uap->dmarx.running;
999 /* Blank functions if the DMA engine is not available */
1000 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1004 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1008 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1012 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1016 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1021 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1025 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1030 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1034 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1038 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1043 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1048 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1053 #define pl011_dma_flush_buffer NULL
1059 * This workaround aims to break the deadlock situation
1060 * when after long transfer over uart in hardware flow
1061 * control, uart interrupt registers cannot be cleared.
1062 * Hence uart transfer gets blocked.
1064 * It is seen that during such deadlock condition ICR
1065 * don't get cleared even on multiple write. This leads
1066 * pass_counter to decrease and finally reach zero. This
1067 * can be taken as trigger point to run this UART_BT_WA.
1070 static void pl011_lockup_wa(unsigned long data)
1072 struct uart_amba_port *uap = amba_ports[0];
1073 void __iomem *base = uap->port.membase;
1074 struct circ_buf *xmit = &uap->port.state->xmit;
1075 struct tty_struct *tty = uap->port.state->port.tty;
1076 int buf_empty_retries = 200;
1079 /* Stop HCI layer from submitting data for tx */
1080 tty->hw_stopped = 1;
1081 while (!uart_circ_empty(xmit)) {
1082 if (buf_empty_retries-- == 0)
1087 /* Backup registers */
1088 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1089 uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
1091 /* Disable UART so that FIFO data is flushed out */
1092 writew(0x00, uap->port.membase + UART011_CR);
1094 /* Soft reset UART module */
1095 if (uap->port.dev->platform_data) {
1096 struct amba_pl011_data *plat;
1098 plat = uap->port.dev->platform_data;
1103 /* Restore registers */
1104 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1105 writew(uart_wa_regdata[loop] ,
1106 uap->port.membase + uart_wa_reg[loop]);
1108 /* Initialise the old status of the modem signals */
1109 uap->old_status = readw(uap->port.membase + UART01x_FR) &
1110 UART01x_FR_MODEM_ANY;
1112 if (readl(base + UART011_MIS) & 0x2)
1113 printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
1116 tty->hw_stopped = 0;
1119 static void pl011_stop_tx(struct uart_port *port)
1121 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1123 uap->im &= ~UART011_TXIM;
1124 writew(uap->im, uap->port.membase + UART011_IMSC);
1125 pl011_dma_tx_stop(uap);
1128 static void pl011_start_tx(struct uart_port *port)
1130 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1132 if (!pl011_dma_tx_start(uap)) {
1133 uap->im |= UART011_TXIM;
1134 writew(uap->im, uap->port.membase + UART011_IMSC);
1138 static void pl011_stop_rx(struct uart_port *port)
1140 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1142 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1143 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1144 writew(uap->im, uap->port.membase + UART011_IMSC);
1146 pl011_dma_rx_stop(uap);
1149 static void pl011_enable_ms(struct uart_port *port)
1151 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1153 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1154 writew(uap->im, uap->port.membase + UART011_IMSC);
1157 static void pl011_rx_chars(struct uart_amba_port *uap)
1159 struct tty_struct *tty = uap->port.state->port.tty;
1161 pl011_fifo_to_tty(uap);
1163 spin_unlock(&uap->port.lock);
1164 tty_flip_buffer_push(tty);
1166 * If we were temporarily out of DMA mode for a while,
1167 * attempt to switch back to DMA mode again.
1169 if (pl011_dma_rx_available(uap)) {
1170 if (pl011_dma_rx_trigger_dma(uap)) {
1171 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1172 "fall back to interrupt mode again\n");
1173 uap->im |= UART011_RXIM;
1175 uap->im &= ~UART011_RXIM;
1176 writew(uap->im, uap->port.membase + UART011_IMSC);
1178 spin_lock(&uap->port.lock);
1181 static void pl011_tx_chars(struct uart_amba_port *uap)
1183 struct circ_buf *xmit = &uap->port.state->xmit;
1186 if (uap->port.x_char) {
1187 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1188 uap->port.icount.tx++;
1189 uap->port.x_char = 0;
1192 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1193 pl011_stop_tx(&uap->port);
1197 /* If we are using DMA mode, try to send some characters. */
1198 if (pl011_dma_tx_irq(uap))
1201 count = uap->fifosize >> 1;
1203 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1204 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1205 uap->port.icount.tx++;
1206 if (uart_circ_empty(xmit))
1208 } while (--count > 0);
1210 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1211 uart_write_wakeup(&uap->port);
1213 if (uart_circ_empty(xmit))
1214 pl011_stop_tx(&uap->port);
1217 static void pl011_modem_status(struct uart_amba_port *uap)
1219 unsigned int status, delta;
1221 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1223 delta = status ^ uap->old_status;
1224 uap->old_status = status;
1229 if (delta & UART01x_FR_DCD)
1230 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1232 if (delta & UART01x_FR_DSR)
1233 uap->port.icount.dsr++;
1235 if (delta & UART01x_FR_CTS)
1236 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1238 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1241 static irqreturn_t pl011_int(int irq, void *dev_id)
1243 struct uart_amba_port *uap = dev_id;
1244 unsigned long flags;
1245 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1248 spin_lock_irqsave(&uap->port.lock, flags);
1250 status = readw(uap->port.membase + UART011_MIS);
1253 writew(status & ~(UART011_TXIS|UART011_RTIS|
1255 uap->port.membase + UART011_ICR);
1257 if (status & (UART011_RTIS|UART011_RXIS)) {
1258 if (pl011_dma_rx_running(uap))
1259 pl011_dma_rx_irq(uap);
1261 pl011_rx_chars(uap);
1263 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1264 UART011_CTSMIS|UART011_RIMIS))
1265 pl011_modem_status(uap);
1266 if (status & UART011_TXIS)
1267 pl011_tx_chars(uap);
1269 if (pass_counter-- == 0) {
1270 if (uap->interrupt_may_hang)
1271 tasklet_schedule(&pl011_lockup_tlet);
1275 status = readw(uap->port.membase + UART011_MIS);
1276 } while (status != 0);
1280 spin_unlock_irqrestore(&uap->port.lock, flags);
1282 return IRQ_RETVAL(handled);
1285 static unsigned int pl01x_tx_empty(struct uart_port *port)
1287 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1288 unsigned int status = readw(uap->port.membase + UART01x_FR);
1289 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1292 static unsigned int pl01x_get_mctrl(struct uart_port *port)
1294 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1295 unsigned int result = 0;
1296 unsigned int status = readw(uap->port.membase + UART01x_FR);
1298 #define TIOCMBIT(uartbit, tiocmbit) \
1299 if (status & uartbit) \
1302 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1303 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1304 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1305 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1310 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1312 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1315 cr = readw(uap->port.membase + UART011_CR);
1317 #define TIOCMBIT(tiocmbit, uartbit) \
1318 if (mctrl & tiocmbit) \
1323 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1324 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1325 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1326 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1327 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1330 /* We need to disable auto-RTS if we want to turn RTS off */
1331 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1335 writew(cr, uap->port.membase + UART011_CR);
1338 static void pl011_break_ctl(struct uart_port *port, int break_state)
1340 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1341 unsigned long flags;
1344 spin_lock_irqsave(&uap->port.lock, flags);
1345 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1346 if (break_state == -1)
1347 lcr_h |= UART01x_LCRH_BRK;
1349 lcr_h &= ~UART01x_LCRH_BRK;
1350 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1351 spin_unlock_irqrestore(&uap->port.lock, flags);
1354 #ifdef CONFIG_CONSOLE_POLL
1355 static int pl010_get_poll_char(struct uart_port *port)
1357 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1358 unsigned int status;
1360 status = readw(uap->port.membase + UART01x_FR);
1361 if (status & UART01x_FR_RXFE)
1362 return NO_POLL_CHAR;
1364 return readw(uap->port.membase + UART01x_DR);
1367 static void pl010_put_poll_char(struct uart_port *port,
1370 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1372 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1375 writew(ch, uap->port.membase + UART01x_DR);
1378 #endif /* CONFIG_CONSOLE_POLL */
1380 static int pl011_startup(struct uart_port *port)
1382 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1386 retval = clk_prepare(uap->clk);
1391 * Try to enable the clock producer.
1393 retval = clk_enable(uap->clk);
1397 uap->port.uartclk = clk_get_rate(uap->clk);
1399 /* Clear pending error and receive interrupts */
1400 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1401 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1406 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1410 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1413 * Provoke TX FIFO interrupt into asserting.
1415 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1416 writew(cr, uap->port.membase + UART011_CR);
1417 writew(0, uap->port.membase + UART011_FBRD);
1418 writew(1, uap->port.membase + UART011_IBRD);
1419 writew(0, uap->port.membase + uap->lcrh_rx);
1420 if (uap->lcrh_tx != uap->lcrh_rx) {
1423 * Wait 10 PCLKs before writing LCRH_TX register,
1424 * to get this delay write read only register 10 times
1426 for (i = 0; i < 10; ++i)
1427 writew(0xff, uap->port.membase + UART011_MIS);
1428 writew(0, uap->port.membase + uap->lcrh_tx);
1430 writew(0, uap->port.membase + UART01x_DR);
1431 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1434 /* restore RTS and DTR */
1435 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1436 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1437 writew(cr, uap->port.membase + UART011_CR);
1440 * initialise the old status of the modem signals
1442 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1445 pl011_dma_startup(uap);
1448 * Finally, enable interrupts, only timeouts when using DMA
1449 * if initial RX DMA job failed, start in interrupt mode
1452 spin_lock_irq(&uap->port.lock);
1453 /* Clear out any spuriously appearing RX interrupts */
1454 writew(UART011_RTIS | UART011_RXIS,
1455 uap->port.membase + UART011_ICR);
1456 uap->im = UART011_RTIM;
1457 if (!pl011_dma_rx_running(uap))
1458 uap->im |= UART011_RXIM;
1459 writew(uap->im, uap->port.membase + UART011_IMSC);
1460 spin_unlock_irq(&uap->port.lock);
1462 if (uap->port.dev->platform_data) {
1463 struct amba_pl011_data *plat;
1465 plat = uap->port.dev->platform_data;
1473 clk_disable(uap->clk);
1475 clk_unprepare(uap->clk);
1480 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1485 val = readw(uap->port.membase + lcrh);
1486 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1487 writew(val, uap->port.membase + lcrh);
1490 static void pl011_shutdown(struct uart_port *port)
1492 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1496 * disable all interrupts
1498 spin_lock_irq(&uap->port.lock);
1500 writew(uap->im, uap->port.membase + UART011_IMSC);
1501 writew(0xffff, uap->port.membase + UART011_ICR);
1502 spin_unlock_irq(&uap->port.lock);
1504 pl011_dma_shutdown(uap);
1507 * Free the interrupt
1509 free_irq(uap->port.irq, uap);
1513 * disable the port. It should not disable RTS and DTR.
1514 * Also RTS and DTR state should be preserved to restore
1515 * it during startup().
1517 uap->autorts = false;
1518 cr = readw(uap->port.membase + UART011_CR);
1520 cr &= UART011_CR_RTS | UART011_CR_DTR;
1521 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1522 writew(cr, uap->port.membase + UART011_CR);
1525 * disable break condition and fifos
1527 pl011_shutdown_channel(uap, uap->lcrh_rx);
1528 if (uap->lcrh_rx != uap->lcrh_tx)
1529 pl011_shutdown_channel(uap, uap->lcrh_tx);
1532 * Shut down the clock producer
1534 clk_disable(uap->clk);
1535 clk_unprepare(uap->clk);
1537 if (uap->port.dev->platform_data) {
1538 struct amba_pl011_data *plat;
1540 plat = uap->port.dev->platform_data;
1548 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1549 struct ktermios *old)
1551 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1552 unsigned int lcr_h, old_cr;
1553 unsigned long flags;
1554 unsigned int baud, quot, clkdiv;
1556 if (uap->vendor->oversampling)
1562 * Ask the core to calculate the divisor for us.
1564 baud = uart_get_baud_rate(port, termios, old, 0,
1565 port->uartclk / clkdiv);
1567 if (baud > port->uartclk/16)
1568 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1570 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1572 switch (termios->c_cflag & CSIZE) {
1574 lcr_h = UART01x_LCRH_WLEN_5;
1577 lcr_h = UART01x_LCRH_WLEN_6;
1580 lcr_h = UART01x_LCRH_WLEN_7;
1583 lcr_h = UART01x_LCRH_WLEN_8;
1586 if (termios->c_cflag & CSTOPB)
1587 lcr_h |= UART01x_LCRH_STP2;
1588 if (termios->c_cflag & PARENB) {
1589 lcr_h |= UART01x_LCRH_PEN;
1590 if (!(termios->c_cflag & PARODD))
1591 lcr_h |= UART01x_LCRH_EPS;
1593 if (uap->fifosize > 1)
1594 lcr_h |= UART01x_LCRH_FEN;
1596 spin_lock_irqsave(&port->lock, flags);
1599 * Update the per-port timeout.
1601 uart_update_timeout(port, termios->c_cflag, baud);
1603 port->read_status_mask = UART011_DR_OE | 255;
1604 if (termios->c_iflag & INPCK)
1605 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1606 if (termios->c_iflag & (BRKINT | PARMRK))
1607 port->read_status_mask |= UART011_DR_BE;
1610 * Characters to ignore
1612 port->ignore_status_mask = 0;
1613 if (termios->c_iflag & IGNPAR)
1614 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1615 if (termios->c_iflag & IGNBRK) {
1616 port->ignore_status_mask |= UART011_DR_BE;
1618 * If we're ignoring parity and break indicators,
1619 * ignore overruns too (for real raw support).
1621 if (termios->c_iflag & IGNPAR)
1622 port->ignore_status_mask |= UART011_DR_OE;
1626 * Ignore all characters if CREAD is not set.
1628 if ((termios->c_cflag & CREAD) == 0)
1629 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1631 if (UART_ENABLE_MS(port, termios->c_cflag))
1632 pl011_enable_ms(port);
1634 /* first, disable everything */
1635 old_cr = readw(port->membase + UART011_CR);
1636 writew(0, port->membase + UART011_CR);
1638 if (termios->c_cflag & CRTSCTS) {
1639 if (old_cr & UART011_CR_RTS)
1640 old_cr |= UART011_CR_RTSEN;
1642 old_cr |= UART011_CR_CTSEN;
1643 uap->autorts = true;
1645 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1646 uap->autorts = false;
1649 if (uap->vendor->oversampling) {
1650 if (baud > port->uartclk / 16)
1651 old_cr |= ST_UART011_CR_OVSFACT;
1653 old_cr &= ~ST_UART011_CR_OVSFACT;
1657 writew(quot & 0x3f, port->membase + UART011_FBRD);
1658 writew(quot >> 6, port->membase + UART011_IBRD);
1661 * ----------v----------v----------v----------v-----
1662 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
1663 * ----------^----------^----------^----------^-----
1665 writew(lcr_h, port->membase + uap->lcrh_rx);
1666 if (uap->lcrh_rx != uap->lcrh_tx) {
1669 * Wait 10 PCLKs before writing LCRH_TX register,
1670 * to get this delay write read only register 10 times
1672 for (i = 0; i < 10; ++i)
1673 writew(0xff, uap->port.membase + UART011_MIS);
1674 writew(lcr_h, port->membase + uap->lcrh_tx);
1676 writew(old_cr, port->membase + UART011_CR);
1678 spin_unlock_irqrestore(&port->lock, flags);
1681 static const char *pl011_type(struct uart_port *port)
1683 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1684 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1688 * Release the memory region(s) being used by 'port'
1690 static void pl010_release_port(struct uart_port *port)
1692 release_mem_region(port->mapbase, SZ_4K);
1696 * Request the memory region(s) being used by 'port'
1698 static int pl010_request_port(struct uart_port *port)
1700 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1701 != NULL ? 0 : -EBUSY;
1705 * Configure/autoconfigure the port.
1707 static void pl010_config_port(struct uart_port *port, int flags)
1709 if (flags & UART_CONFIG_TYPE) {
1710 port->type = PORT_AMBA;
1711 pl010_request_port(port);
1716 * verify the new serial_struct (for TIOCSSERIAL).
1718 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1721 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1723 if (ser->irq < 0 || ser->irq >= nr_irqs)
1725 if (ser->baud_base < 9600)
1730 static struct uart_ops amba_pl011_pops = {
1731 .tx_empty = pl01x_tx_empty,
1732 .set_mctrl = pl011_set_mctrl,
1733 .get_mctrl = pl01x_get_mctrl,
1734 .stop_tx = pl011_stop_tx,
1735 .start_tx = pl011_start_tx,
1736 .stop_rx = pl011_stop_rx,
1737 .enable_ms = pl011_enable_ms,
1738 .break_ctl = pl011_break_ctl,
1739 .startup = pl011_startup,
1740 .shutdown = pl011_shutdown,
1741 .flush_buffer = pl011_dma_flush_buffer,
1742 .set_termios = pl011_set_termios,
1744 .release_port = pl010_release_port,
1745 .request_port = pl010_request_port,
1746 .config_port = pl010_config_port,
1747 .verify_port = pl010_verify_port,
1748 #ifdef CONFIG_CONSOLE_POLL
1749 .poll_get_char = pl010_get_poll_char,
1750 .poll_put_char = pl010_put_poll_char,
1754 static struct uart_amba_port *amba_ports[UART_NR];
1756 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1758 static void pl011_console_putchar(struct uart_port *port, int ch)
1760 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1762 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1764 writew(ch, uap->port.membase + UART01x_DR);
1768 pl011_console_write(struct console *co, const char *s, unsigned int count)
1770 struct uart_amba_port *uap = amba_ports[co->index];
1771 unsigned int status, old_cr, new_cr;
1772 unsigned long flags;
1775 clk_enable(uap->clk);
1777 local_irq_save(flags);
1778 if (uap->port.sysrq)
1780 else if (oops_in_progress)
1781 locked = spin_trylock(&uap->port.lock);
1783 spin_lock(&uap->port.lock);
1786 * First save the CR then disable the interrupts
1788 old_cr = readw(uap->port.membase + UART011_CR);
1789 new_cr = old_cr & ~UART011_CR_CTSEN;
1790 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1791 writew(new_cr, uap->port.membase + UART011_CR);
1793 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1796 * Finally, wait for transmitter to become empty
1797 * and restore the TCR
1800 status = readw(uap->port.membase + UART01x_FR);
1801 } while (status & UART01x_FR_BUSY);
1802 writew(old_cr, uap->port.membase + UART011_CR);
1805 spin_unlock(&uap->port.lock);
1806 local_irq_restore(flags);
1808 clk_disable(uap->clk);
1812 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1813 int *parity, int *bits)
1815 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1816 unsigned int lcr_h, ibrd, fbrd;
1818 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1821 if (lcr_h & UART01x_LCRH_PEN) {
1822 if (lcr_h & UART01x_LCRH_EPS)
1828 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1833 ibrd = readw(uap->port.membase + UART011_IBRD);
1834 fbrd = readw(uap->port.membase + UART011_FBRD);
1836 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1838 if (uap->vendor->oversampling) {
1839 if (readw(uap->port.membase + UART011_CR)
1840 & ST_UART011_CR_OVSFACT)
1846 static int __init pl011_console_setup(struct console *co, char *options)
1848 struct uart_amba_port *uap;
1856 * Check whether an invalid uart number has been specified, and
1857 * if so, search for the first available port that does have
1860 if (co->index >= UART_NR)
1862 uap = amba_ports[co->index];
1866 ret = clk_prepare(uap->clk);
1870 if (uap->port.dev->platform_data) {
1871 struct amba_pl011_data *plat;
1873 plat = uap->port.dev->platform_data;
1878 uap->port.uartclk = clk_get_rate(uap->clk);
1881 uart_parse_options(options, &baud, &parity, &bits, &flow);
1883 pl011_console_get_options(uap, &baud, &parity, &bits);
1885 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1888 static struct uart_driver amba_reg;
1889 static struct console amba_console = {
1891 .write = pl011_console_write,
1892 .device = uart_console_device,
1893 .setup = pl011_console_setup,
1894 .flags = CON_PRINTBUFFER,
1899 #define AMBA_CONSOLE (&amba_console)
1901 #define AMBA_CONSOLE NULL
1904 static struct uart_driver amba_reg = {
1905 .owner = THIS_MODULE,
1906 .driver_name = "ttyAMA",
1907 .dev_name = "ttyAMA",
1908 .major = SERIAL_AMBA_MAJOR,
1909 .minor = SERIAL_AMBA_MINOR,
1911 .cons = AMBA_CONSOLE,
1914 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1916 struct uart_amba_port *uap;
1917 struct vendor_data *vendor = id->data;
1921 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1922 if (amba_ports[i] == NULL)
1925 if (i == ARRAY_SIZE(amba_ports)) {
1930 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1936 base = ioremap(dev->res.start, resource_size(&dev->res));
1942 uap->clk = clk_get(&dev->dev, NULL);
1943 if (IS_ERR(uap->clk)) {
1944 ret = PTR_ERR(uap->clk);
1948 /* Ensure interrupts from this UART are masked and cleared */
1949 writew(0, uap->port.membase + UART011_IMSC);
1950 writew(0xffff, uap->port.membase + UART011_ICR);
1952 uap->vendor = vendor;
1953 uap->lcrh_rx = vendor->lcrh_rx;
1954 uap->lcrh_tx = vendor->lcrh_tx;
1956 uap->fifosize = vendor->fifosize;
1957 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1958 uap->port.dev = &dev->dev;
1959 uap->port.mapbase = dev->res.start;
1960 uap->port.membase = base;
1961 uap->port.iotype = UPIO_MEM;
1962 uap->port.irq = dev->irq[0];
1963 uap->port.fifosize = uap->fifosize;
1964 uap->port.ops = &amba_pl011_pops;
1965 uap->port.flags = UPF_BOOT_AUTOCONF;
1967 pl011_dma_probe(uap);
1969 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1971 amba_ports[i] = uap;
1973 amba_set_drvdata(dev, uap);
1974 ret = uart_add_one_port(&amba_reg, &uap->port);
1976 amba_set_drvdata(dev, NULL);
1977 amba_ports[i] = NULL;
1978 pl011_dma_remove(uap);
1989 static int pl011_remove(struct amba_device *dev)
1991 struct uart_amba_port *uap = amba_get_drvdata(dev);
1994 amba_set_drvdata(dev, NULL);
1996 uart_remove_one_port(&amba_reg, &uap->port);
1998 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1999 if (amba_ports[i] == uap)
2000 amba_ports[i] = NULL;
2002 pl011_dma_remove(uap);
2003 iounmap(uap->port.membase);
2010 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
2012 struct uart_amba_port *uap = amba_get_drvdata(dev);
2017 return uart_suspend_port(&amba_reg, &uap->port);
2020 static int pl011_resume(struct amba_device *dev)
2022 struct uart_amba_port *uap = amba_get_drvdata(dev);
2027 return uart_resume_port(&amba_reg, &uap->port);
2031 static struct amba_id pl011_ids[] = {
2035 .data = &vendor_arm,
2045 MODULE_DEVICE_TABLE(amba, pl011_ids);
2047 static struct amba_driver pl011_driver = {
2049 .name = "uart-pl011",
2051 .id_table = pl011_ids,
2052 .probe = pl011_probe,
2053 .remove = pl011_remove,
2055 .suspend = pl011_suspend,
2056 .resume = pl011_resume,
2060 static int __init pl011_init(void)
2063 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2065 ret = uart_register_driver(&amba_reg);
2067 ret = amba_driver_register(&pl011_driver);
2069 uart_unregister_driver(&amba_reg);
2074 static void __exit pl011_exit(void)
2076 amba_driver_unregister(&pl011_driver);
2077 uart_unregister_driver(&amba_reg);
2081 * While this can be a module, if builtin it's most likely the console
2082 * So let's leave module_exit but move module_init to an earlier place
2084 arch_initcall(pl011_init);
2085 module_exit(pl011_exit);
2087 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2088 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2089 MODULE_LICENSE("GPL");