drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24
  25 #include <asm/byteorder.h>
  26 #include <asm/io.h>
  27
  28 #include <linux/dmaengine.h>
  29 #include <linux/platform_data/dma-dw.h>
  30
  31 #include "8250.h"
  32
  33 /*
  34  * init function returns:
  35  *  > 0 - number of ports
  36  *  = 0 - use board->num_ports
  37  *  < 0 - error
  38  */
  39 struct pci_serial_quirk {
  40         u32     vendor;
  41         u32     device;
  42         u32     subvendor;
  43         u32     subdevice;
  44         int     (*probe)(struct pci_dev *dev);
  45         int     (*init)(struct pci_dev *dev);
  46         int     (*setup)(struct serial_private *,
  47                          const struct pciserial_board *,
  48                          struct uart_8250_port *, int);
  49         void    (*exit)(struct pci_dev *dev);
  50 };
  51
  52 #define PCI_NUM_BAR_RESOURCES   6
  53
  54 struct serial_private {
  55         struct pci_dev          *dev;
  56         unsigned int            nr;
  57         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  58         struct pci_serial_quirk *quirk;
  59         int                     line[0];
  60 };
  61
  62 static int pci_default_setup(struct serial_private*,
  63           const struct pciserial_board*, struct uart_8250_port *, int);
  64
  65 static void moan_device(const char *str, struct pci_dev *dev)
  66 {
  67         dev_err(&dev->dev,
  68                "%s: %s\n"
  69                "Please send the output of lspci -vv, this\n"
  70                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  71                "manufacturer and name of serial board or\n"
  72                "modem board to rmk+serial@arm.linux.org.uk.\n",
  73                pci_name(dev), str, dev->vendor, dev->device,
  74                dev->subsystem_vendor, dev->subsystem_device);
  75 }
  76
  77 static int
  78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  79            int bar, int offset, int regshift)
  80 {
  81         struct pci_dev *dev = priv->dev;
  82         unsigned long base, len;
  83
  84         if (bar >= PCI_NUM_BAR_RESOURCES)
  85                 return -EINVAL;
  86
  87         base = pci_resource_start(dev, bar);
  88
  89         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  90                 len =  pci_resource_len(dev, bar);
  91
  92                 if (!priv->remapped_bar[bar])
  93                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  94                 if (!priv->remapped_bar[bar])
  95                         return -ENOMEM;
  96
  97                 port->port.iotype = UPIO_MEM;
  98                 port->port.iobase = 0;
  99                 port->port.mapbase = base + offset;
 100                 port->port.membase = priv->remapped_bar[bar] + offset;
 101                 port->port.regshift = regshift;
 102         } else {
 103                 port->port.iotype = UPIO_PORT;
 104                 port->port.iobase = base + offset;
 105                 port->port.mapbase = 0;
 106                 port->port.membase = NULL;
 107                 port->port.regshift = 0;
 108         }
 109         return 0;
 110 }
 111
 112 /*
 113  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 114  */
 115 static int addidata_apci7800_setup(struct serial_private *priv,
 116                                 const struct pciserial_board *board,
 117                                 struct uart_8250_port *port, int idx)
 118 {
 119         unsigned int bar = 0, offset = board->first_offset;
 120         bar = FL_GET_BASE(board->flags);
 121
 122         if (idx < 2) {
 123                 offset += idx * board->uart_offset;
 124         } else if ((idx >= 2) && (idx < 4)) {
 125                 bar += 1;
 126                 offset += ((idx - 2) * board->uart_offset);
 127         } else if ((idx >= 4) && (idx < 6)) {
 128                 bar += 2;
 129                 offset += ((idx - 4) * board->uart_offset);
 130         } else if (idx >= 6) {
 131                 bar += 3;
 132                 offset += ((idx - 6) * board->uart_offset);
 133         }
 134
 135         return setup_port(priv, port, bar, offset, board->reg_shift);
 136 }
 137
 138 /*
 139  * AFAVLAB uses a different mixture of BARs and offsets
 140  * Not that ugly ;) -- HW
 141  */
 142 static int
 143 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 144               struct uart_8250_port *port, int idx)
 145 {
 146         unsigned int bar, offset = board->first_offset;
 147
 148         bar = FL_GET_BASE(board->flags);
 149         if (idx < 4)
 150                 bar += idx;
 151         else {
 152                 bar = 4;
 153                 offset += (idx - 4) * board->uart_offset;
 154         }
 155
 156         return setup_port(priv, port, bar, offset, board->reg_shift);
 157 }
 158
 159 /*
 160  * HP's Remote Management Console.  The Diva chip came in several
 161  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 162  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 163  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 164  * one Diva chip, but it has been expanded to 5 UARTs.
 165  */
 166 static int pci_hp_diva_init(struct pci_dev *dev)
 167 {
 168         int rc = 0;
 169
 170         switch (dev->subsystem_device) {
 171         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 172         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 173         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 174         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 175                 rc = 3;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 178                 rc = 2;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 181                 rc = 4;
 182                 break;
 183         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 184         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 185                 rc = 1;
 186                 break;
 187         }
 188
 189         return rc;
 190 }
 191
 192 /*
 193  * HP's Diva chip puts the 4th/5th serial port further out, and
 194  * some serial ports are supposed to be hidden on certain models.
 195  */
 196 static int
 197 pci_hp_diva_setup(struct serial_private *priv,
 198                 const struct pciserial_board *board,
 199                 struct uart_8250_port *port, int idx)
 200 {
 201         unsigned int offset = board->first_offset;
 202         unsigned int bar = FL_GET_BASE(board->flags);
 203
 204         switch (priv->dev->subsystem_device) {
 205         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 206                 if (idx == 3)
 207                         idx++;
 208                 break;
 209         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 210                 if (idx > 0)
 211                         idx++;
 212                 if (idx > 2)
 213                         idx++;
 214                 break;
 215         }
 216         if (idx > 2)
 217                 offset = 0x18;
 218
 219         offset += idx * board->uart_offset;
 220
 221         return setup_port(priv, port, bar, offset, board->reg_shift);
 222 }
 223
 224 /*
 225  * Added for EKF Intel i960 serial boards
 226  */
 227 static int pci_inteli960ni_init(struct pci_dev *dev)
 228 {
 229         unsigned long oldval;
 230
 231         if (!(dev->subsystem_device & 0x1000))
 232                 return -ENODEV;
 233
 234         /* is firmware started? */
 235         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 236         if (oldval == 0x00001000L) { /* RESET value */
 237                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 238                 return -ENODEV;
 239         }
 240         return 0;
 241 }
 242
 243 /*
 244  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 245  * that the card interrupt be explicitly enabled or disabled.  This
 246  * seems to be mainly needed on card using the PLX which also use I/O
 247  * mapped memory.
 248  */
 249 static int pci_plx9050_init(struct pci_dev *dev)
 250 {
 251         u8 irq_config;
 252         void __iomem *p;
 253
 254         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 255                 moan_device("no memory in bar 0", dev);
 256                 return 0;
 257         }
 258
 259         irq_config = 0x41;
 260         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 261             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 262                 irq_config = 0x43;
 263
 264         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 265             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 266                 /*
 267                  * As the megawolf cards have the int pins active
 268                  * high, and have 2 UART chips, both ints must be
 269                  * enabled on the 9050. Also, the UARTS are set in
 270                  * 16450 mode by default, so we have to enable the
 271                  * 16C950 'enhanced' mode so that we can use the
 272                  * deep FIFOs
 273                  */
 274                 irq_config = 0x5b;
 275         /*
 276          * enable/disable interrupts
 277          */
 278         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 279         if (p == NULL)
 280                 return -ENOMEM;
 281         writel(irq_config, p + 0x4c);
 282
 283         /*
 284          * Read the register back to ensure that it took effect.
 285          */
 286         readl(p + 0x4c);
 287         iounmap(p);
 288
 289         return 0;
 290 }
 291
 292 static void pci_plx9050_exit(struct pci_dev *dev)
 293 {
 294         u8 __iomem *p;
 295
 296         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 297                 return;
 298
 299         /*
 300          * disable interrupts
 301          */
 302         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 303         if (p != NULL) {
 304                 writel(0, p + 0x4c);
 305
 306                 /*
 307                  * Read the register back to ensure that it took effect.
 308                  */
 309                 readl(p + 0x4c);
 310                 iounmap(p);
 311         }
 312 }
 313
 314 #define NI8420_INT_ENABLE_REG   0x38
 315 #define NI8420_INT_ENABLE_BIT   0x2000
 316
 317 static void pci_ni8420_exit(struct pci_dev *dev)
 318 {
 319         void __iomem *p;
 320         unsigned long base, len;
 321         unsigned int bar = 0;
 322
 323         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 324                 moan_device("no memory in bar", dev);
 325                 return;
 326         }
 327
 328         base = pci_resource_start(dev, bar);
 329         len =  pci_resource_len(dev, bar);
 330         p = ioremap_nocache(base, len);
 331         if (p == NULL)
 332                 return;
 333
 334         /* Disable the CPU Interrupt */
 335         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 336                p + NI8420_INT_ENABLE_REG);
 337         iounmap(p);
 338 }
 339
 340
 341 /* MITE registers */
 342 #define MITE_IOWBSR1    0xc4
 343 #define MITE_IOWCR1     0xf4
 344 #define MITE_LCIMR1     0x08
 345 #define MITE_LCIMR2     0x10
 346
 347 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 348
 349 static void pci_ni8430_exit(struct pci_dev *dev)
 350 {
 351         void __iomem *p;
 352         unsigned long base, len;
 353         unsigned int bar = 0;
 354
 355         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 356                 moan_device("no memory in bar", dev);
 357                 return;
 358         }
 359
 360         base = pci_resource_start(dev, bar);
 361         len =  pci_resource_len(dev, bar);
 362         p = ioremap_nocache(base, len);
 363         if (p == NULL)
 364                 return;
 365
 366         /* Disable the CPU Interrupt */
 367         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 368         iounmap(p);
 369 }
 370
 371 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 372 static int
 373 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 374                 struct uart_8250_port *port, int idx)
 375 {
 376         unsigned int bar, offset = board->first_offset;
 377
 378         bar = 0;
 379
 380         if (idx < 4) {
 381                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 382                 offset += idx * board->uart_offset;
 383         } else if (idx < 8) {
 384                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 385                 offset += idx * board->uart_offset + 0xC00;
 386         } else /* we have only 8 ports on PMC-OCTALPRO */
 387                 return 1;
 388
 389         return setup_port(priv, port, bar, offset, board->reg_shift);
 390 }
 391
 392 /*
 393 * This does initialization for PMC OCTALPRO cards:
 394 * maps the device memory, resets the UARTs (needed, bc
 395 * if the module is removed and inserted again, the card
 396 * is in the sleep mode) and enables global interrupt.
 397 */
 398
 399 /* global control register offset for SBS PMC-OctalPro */
 400 #define OCT_REG_CR_OFF          0x500
 401
 402 static int sbs_init(struct pci_dev *dev)
 403 {
 404         u8 __iomem *p;
 405
 406         p = pci_ioremap_bar(dev, 0);
 407
 408         if (p == NULL)
 409                 return -ENOMEM;
 410         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 411         writeb(0x10, p + OCT_REG_CR_OFF);
 412         udelay(50);
 413         writeb(0x0, p + OCT_REG_CR_OFF);
 414
 415         /* Set bit-2 (INTENABLE) of Control Register */
 416         writeb(0x4, p + OCT_REG_CR_OFF);
 417         iounmap(p);
 418
 419         return 0;
 420 }
 421
 422 /*
 423  * Disables the global interrupt of PMC-OctalPro
 424  */
 425
 426 static void sbs_exit(struct pci_dev *dev)
 427 {
 428         u8 __iomem *p;
 429
 430         p = pci_ioremap_bar(dev, 0);
 431         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 432         if (p != NULL)
 433                 writeb(0, p + OCT_REG_CR_OFF);
 434         iounmap(p);
 435 }
 436
 437 /*
 438  * SIIG serial cards have an PCI interface chip which also controls
 439  * the UART clocking frequency. Each UART can be clocked independently
 440  * (except cards equipped with 4 UARTs) and initial clocking settings
 441  * are stored in the EEPROM chip. It can cause problems because this
 442  * version of serial driver doesn't support differently clocked UART's
 443  * on single PCI card. To prevent this, initialization functions set
 444  * high frequency clocking for all UART's on given card. It is safe (I
 445  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 446  * with other OSes (like M$ DOS).
 447  *
 448  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 449  *
 450  * There is two family of SIIG serial cards with different PCI
 451  * interface chip and different configuration methods:
 452  *     - 10x cards have control registers in IO and/or memory space;
 453  *     - 20x cards have control registers in standard PCI configuration space.
 454  *
 455  * Note: all 10x cards have PCI device ids 0x10..
 456  *       all 20x cards have PCI device ids 0x20..
 457  *
 458  * There are also Quartet Serial cards which use Oxford Semiconductor
 459  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 460  *
 461  * Note: some SIIG cards are probed by the parport_serial object.
 462  */
 463
 464 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 465 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 466
 467 static int pci_siig10x_init(struct pci_dev *dev)
 468 {
 469         u16 data;
 470         void __iomem *p;
 471
 472         switch (dev->device & 0xfff8) {
 473         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 474                 data = 0xffdf;
 475                 break;
 476         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 477                 data = 0xf7ff;
 478                 break;
 479         default:                        /* 1S1P, 4S */
 480                 data = 0xfffb;
 481                 break;
 482         }
 483
 484         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 485         if (p == NULL)
 486                 return -ENOMEM;
 487
 488         writew(readw(p + 0x28) & data, p + 0x28);
 489         readw(p + 0x28);
 490         iounmap(p);
 491         return 0;
 492 }
 493
 494 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 495 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 496
 497 static int pci_siig20x_init(struct pci_dev *dev)
 498 {
 499         u8 data;
 500
 501         /* Change clock frequency for the first UART. */
 502         pci_read_config_byte(dev, 0x6f, &data);
 503         pci_write_config_byte(dev, 0x6f, data & 0xef);
 504
 505         /* If this card has 2 UART, we have to do the same with second UART. */
 506         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 507             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 508                 pci_read_config_byte(dev, 0x73, &data);
 509                 pci_write_config_byte(dev, 0x73, data & 0xef);
 510         }
 511         return 0;
 512 }
 513
 514 static int pci_siig_init(struct pci_dev *dev)
 515 {
 516         unsigned int type = dev->device & 0xff00;
 517
 518         if (type == 0x1000)
 519                 return pci_siig10x_init(dev);
 520         else if (type == 0x2000)
 521                 return pci_siig20x_init(dev);
 522
 523         moan_device("Unknown SIIG card", dev);
 524         return -ENODEV;
 525 }
 526
 527 static int pci_siig_setup(struct serial_private *priv,
 528                           const struct pciserial_board *board,
 529                           struct uart_8250_port *port, int idx)
 530 {
 531         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 532
 533         if (idx > 3) {
 534                 bar = 4;
 535                 offset = (idx - 4) * 8;
 536         }
 537
 538         return setup_port(priv, port, bar, offset, 0);
 539 }
 540
 541 /*
 542  * Timedia has an explosion of boards, and to avoid the PCI table from
 543  * growing *huge*, we use this function to collapse some 70 entries
 544  * in the PCI table into one, for sanity's and compactness's sake.
 545  */
 546 static const unsigned short timedia_single_port[] = {
 547         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 548 };
 549
 550 static const unsigned short timedia_dual_port[] = {
 551         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 552         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 553         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 554         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 555         0xD079, 0
 556 };
 557
 558 static const unsigned short timedia_quad_port[] = {
 559         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 560         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 561         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 562         0xB157, 0
 563 };
 564
 565 static const unsigned short timedia_eight_port[] = {
 566         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 567         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 568 };
 569
 570 static const struct timedia_struct {
 571         int num;
 572         const unsigned short *ids;
 573 } timedia_data[] = {
 574         { 1, timedia_single_port },
 575         { 2, timedia_dual_port },
 576         { 4, timedia_quad_port },
 577         { 8, timedia_eight_port }
 578 };
 579
 580 /*
 581  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 582  * listing them individually, this driver merely grabs them all with
 583  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 584  * and should be left free to be claimed by parport_serial instead.
 585  */
 586 static int pci_timedia_probe(struct pci_dev *dev)
 587 {
 588         /*
 589          * Check the third digit of the subdevice ID
 590          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 591          */
 592         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 593                 dev_info(&dev->dev,
 594                         "ignoring Timedia subdevice %04x for parport_serial\n",
 595                         dev->subsystem_device);
 596                 return -ENODEV;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static int pci_timedia_init(struct pci_dev *dev)
 603 {
 604         const unsigned short *ids;
 605         int i, j;
 606
 607         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 608                 ids = timedia_data[i].ids;
 609                 for (j = 0; ids[j]; j++)
 610                         if (dev->subsystem_device == ids[j])
 611                                 return timedia_data[i].num;
 612         }
 613         return 0;
 614 }
 615
 616 /*
 617  * Timedia/SUNIX uses a mixture of BARs and offsets
 618  * Ugh, this is ugly as all hell --- TYT
 619  */
 620 static int
 621 pci_timedia_setup(struct serial_private *priv,
 622                   const struct pciserial_board *board,
 623                   struct uart_8250_port *port, int idx)
 624 {
 625         unsigned int bar = 0, offset = board->first_offset;
 626
 627         switch (idx) {
 628         case 0:
 629                 bar = 0;
 630                 break;
 631         case 1:
 632                 offset = board->uart_offset;
 633                 bar = 0;
 634                 break;
 635         case 2:
 636                 bar = 1;
 637                 break;
 638         case 3:
 639                 offset = board->uart_offset;
 640                 /* FALLTHROUGH */
 641         case 4: /* BAR 2 */
 642         case 5: /* BAR 3 */
 643         case 6: /* BAR 4 */
 644         case 7: /* BAR 5 */
 645                 bar = idx - 2;
 646         }
 647
 648         return setup_port(priv, port, bar, offset, board->reg_shift);
 649 }
 650
 651 /*
 652  * Some Titan cards are also a little weird
 653  */
 654 static int
 655 titan_400l_800l_setup(struct serial_private *priv,
 656                       const struct pciserial_board *board,
 657                       struct uart_8250_port *port, int idx)
 658 {
 659         unsigned int bar, offset = board->first_offset;
 660
 661         switch (idx) {
 662         case 0:
 663                 bar = 1;
 664                 break;
 665         case 1:
 666                 bar = 2;
 667                 break;
 668         default:
 669                 bar = 4;
 670                 offset = (idx - 2) * board->uart_offset;
 671         }
 672
 673         return setup_port(priv, port, bar, offset, board->reg_shift);
 674 }
 675
 676 static int pci_xircom_init(struct pci_dev *dev)
 677 {
 678         msleep(100);
 679         return 0;
 680 }
 681
 682 static int pci_ni8420_init(struct pci_dev *dev)
 683 {
 684         void __iomem *p;
 685         unsigned long base, len;
 686         unsigned int bar = 0;
 687
 688         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 689                 moan_device("no memory in bar", dev);
 690                 return 0;
 691         }
 692
 693         base = pci_resource_start(dev, bar);
 694         len =  pci_resource_len(dev, bar);
 695         p = ioremap_nocache(base, len);
 696         if (p == NULL)
 697                 return -ENOMEM;
 698
 699         /* Enable CPU Interrupt */
 700         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 701                p + NI8420_INT_ENABLE_REG);
 702
 703         iounmap(p);
 704         return 0;
 705 }
 706
 707 #define MITE_IOWBSR1_WSIZE      0xa
 708 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 709 #define MITE_IOWBSR1_WENAB      (1 << 7)
 710 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 711 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 712 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 713
 714 static int pci_ni8430_init(struct pci_dev *dev)
 715 {
 716         void __iomem *p;
 717         unsigned long base, len;
 718         u32 device_window;
 719         unsigned int bar = 0;
 720
 721         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 722                 moan_device("no memory in bar", dev);
 723                 return 0;
 724         }
 725
 726         base = pci_resource_start(dev, bar);
 727         len =  pci_resource_len(dev, bar);
 728         p = ioremap_nocache(base, len);
 729         if (p == NULL)
 730                 return -ENOMEM;
 731
 732         /* Set device window address and size in BAR0 */
 733         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 734                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 735         writel(device_window, p + MITE_IOWBSR1);
 736
 737         /* Set window access to go to RAMSEL IO address space */
 738         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 739                p + MITE_IOWCR1);
 740
 741         /* Enable IO Bus Interrupt 0 */
 742         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 743
 744         /* Enable CPU Interrupt */
 745         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 746
 747         iounmap(p);
 748         return 0;
 749 }
 750
 751 /* UART Port Control Register */
 752 #define NI8430_PORTCON  0x0f
 753 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 754
 755 static int
 756 pci_ni8430_setup(struct serial_private *priv,
 757                  const struct pciserial_board *board,
 758                  struct uart_8250_port *port, int idx)
 759 {
 760         void __iomem *p;
 761         unsigned long base, len;
 762         unsigned int bar, offset = board->first_offset;
 763
 764         if (idx >= board->num_ports)
 765                 return 1;
 766
 767         bar = FL_GET_BASE(board->flags);
 768         offset += idx * board->uart_offset;
 769
 770         base = pci_resource_start(priv->dev, bar);
 771         len =  pci_resource_len(priv->dev, bar);
 772         p = ioremap_nocache(base, len);
 773
 774         /* enable the transceiver */
 775         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 776                p + offset + NI8430_PORTCON);
 777
 778         iounmap(p);
 779
 780         return setup_port(priv, port, bar, offset, board->reg_shift);
 781 }
 782
 783 static int pci_netmos_9900_setup(struct serial_private *priv,
 784                                 const struct pciserial_board *board,
 785                                 struct uart_8250_port *port, int idx)
 786 {
 787         unsigned int bar;
 788
 789         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 790             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 791                 /* netmos apparently orders BARs by datasheet layout, so serial
 792                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 793                  */
 794                 bar = 3 * idx;
 795
 796                 return setup_port(priv, port, bar, 0, board->reg_shift);
 797         } else {
 798                 return pci_default_setup(priv, board, port, idx);
 799         }
 800 }
 801
 802 /* the 99xx series comes with a range of device IDs and a variety
 803  * of capabilities:
 804  *
 805  * 9900 has varying capabilities and can cascade to sub-controllers
 806  *   (cascading should be purely internal)
 807  * 9904 is hardwired with 4 serial ports
 808  * 9912 and 9922 are hardwired with 2 serial ports
 809  */
 810 static int pci_netmos_9900_numports(struct pci_dev *dev)
 811 {
 812         unsigned int c = dev->class;
 813         unsigned int pi;
 814         unsigned short sub_serports;
 815
 816         pi = (c & 0xff);
 817
 818         if (pi == 2) {
 819                 return 1;
 820         } else if ((pi == 0) &&
 821                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 822                 /* two possibilities: 0x30ps encodes number of parallel and
 823                  * serial ports, or 0x1000 indicates *something*. This is not
 824                  * immediately obvious, since the 2s1p+4s configuration seems
 825                  * to offer all functionality on functions 0..2, while still
 826                  * advertising the same function 3 as the 4s+2s1p config.
 827                  */
 828                 sub_serports = dev->subsystem_device & 0xf;
 829                 if (sub_serports > 0) {
 830                         return sub_serports;
 831                 } else {
 832                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 833                         return 0;
 834                 }
 835         }
 836
 837         moan_device("unknown NetMos/Mostech program interface", dev);
 838         return 0;
 839 }
 840
 841 static int pci_netmos_init(struct pci_dev *dev)
 842 {
 843         /* subdevice 0x00PS means <P> parallel, <S> serial */
 844         unsigned int num_serial = dev->subsystem_device & 0xf;
 845
 846         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 847                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 848                 return 0;
 849
 850         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 851                         dev->subsystem_device == 0x0299)
 852                 return 0;
 853
 854         switch (dev->device) { /* FALLTHROUGH on all */
 855                 case PCI_DEVICE_ID_NETMOS_9904:
 856                 case PCI_DEVICE_ID_NETMOS_9912:
 857                 case PCI_DEVICE_ID_NETMOS_9922:
 858                 case PCI_DEVICE_ID_NETMOS_9900:
 859                         num_serial = pci_netmos_9900_numports(dev);
 860                         break;
 861
 862                 default:
 863                         if (num_serial == 0 ) {
 864                                 moan_device("unknown NetMos/Mostech device", dev);
 865                         }
 866         }
 867
 868         if (num_serial == 0)
 869                 return -ENODEV;
 870
 871         return num_serial;
 872 }
 873
 874 /*
 875  * These chips are available with optionally one parallel port and up to
 876  * two serial ports. Unfortunately they all have the same product id.
 877  *
 878  * Basic configuration is done over a region of 32 I/O ports. The base
 879  * ioport is called INTA or INTC, depending on docs/other drivers.
 880  *
 881  * The region of the 32 I/O ports is configured in POSIO0R...
 882  */
 883
 884 /* registers */
 885 #define ITE_887x_MISCR          0x9c
 886 #define ITE_887x_INTCBAR        0x78
 887 #define ITE_887x_UARTBAR        0x7c
 888 #define ITE_887x_PS0BAR         0x10
 889 #define ITE_887x_POSIO0         0x60
 890
 891 /* I/O space size */
 892 #define ITE_887x_IOSIZE         32
 893 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 894 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 895 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 896 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 897 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 898 #define ITE_887x_POSIO_SPEED            (3 << 29)
 899 /* enable IO_Space bit */
 900 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 901
 902 static int pci_ite887x_init(struct pci_dev *dev)
 903 {
 904         /* inta_addr are the configuration addresses of the ITE */
 905         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 906                                                         0x200, 0x280, 0 };
 907         int ret, i, type;
 908         struct resource *iobase = NULL;
 909         u32 miscr, uartbar, ioport;
 910
 911         /* search for the base-ioport */
 912         i = 0;
 913         while (inta_addr[i] && iobase == NULL) {
 914                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 915                                                                 "ite887x");
 916                 if (iobase != NULL) {
 917                         /* write POSIO0R - speed | size | ioport */
 918                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 919                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 920                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 921                         /* write INTCBAR - ioport */
 922                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 923                                                                 inta_addr[i]);
 924                         ret = inb(inta_addr[i]);
 925                         if (ret != 0xff) {
 926                                 /* ioport connected */
 927                                 break;
 928                         }
 929                         release_region(iobase->start, ITE_887x_IOSIZE);
 930                         iobase = NULL;
 931                 }
 932                 i++;
 933         }
 934
 935         if (!inta_addr[i]) {
 936                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 937                 return -ENODEV;
 938         }
 939
 940         /* start of undocumented type checking (see parport_pc.c) */
 941         type = inb(iobase->start + 0x18) & 0x0f;
 942
 943         switch (type) {
 944         case 0x2:       /* ITE8871 (1P) */
 945         case 0xa:       /* ITE8875 (1P) */
 946                 ret = 0;
 947                 break;
 948         case 0xe:       /* ITE8872 (2S1P) */
 949                 ret = 2;
 950                 break;
 951         case 0x6:       /* ITE8873 (1S) */
 952                 ret = 1;
 953                 break;
 954         case 0x8:       /* ITE8874 (2S) */
 955                 ret = 2;
 956                 break;
 957         default:
 958                 moan_device("Unknown ITE887x", dev);
 959                 ret = -ENODEV;
 960         }
 961
 962         /* configure all serial ports */
 963         for (i = 0; i < ret; i++) {
 964                 /* read the I/O port from the device */
 965                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 966                                                                 &ioport);
 967                 ioport &= 0x0000FF00;   /* the actual base address */
 968                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 969                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 970                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 971
 972                 /* write the ioport to the UARTBAR */
 973                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 974                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 975                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 976                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 977
 978                 /* get current config */
 979                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 980                 /* disable interrupts (UARTx_Routing[3:0]) */
 981                 miscr &= ~(0xf << (12 - 4 * i));
 982                 /* activate the UART (UARTx_En) */
 983                 miscr |= 1 << (23 - i);
 984                 /* write new config with activated UART */
 985                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 986         }
 987
 988         if (ret <= 0) {
 989                 /* the device has no UARTs if we get here */
 990                 release_region(iobase->start, ITE_887x_IOSIZE);
 991         }
 992
 993         return ret;
 994 }
 995
 996 static void pci_ite887x_exit(struct pci_dev *dev)
 997 {
 998         u32 ioport;
 999         /* the ioport is bit 0-15 in POSIO0R */
1000         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1001         ioport &= 0xffff;
1002         release_region(ioport, ITE_887x_IOSIZE);
1003 }
1004
1005 /*
1006  * Oxford Semiconductor Inc.
1007  * Check that device is part of the Tornado range of devices, then determine
1008  * the number of ports available on the device.
1009  */
1010 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1011 {
1012         u8 __iomem *p;
1013         unsigned long deviceID;
1014         unsigned int  number_uarts = 0;
1015
1016         /* OxSemi Tornado devices are all 0xCxxx */
1017         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1018             (dev->device & 0xF000) != 0xC000)
1019                 return 0;
1020
1021         p = pci_iomap(dev, 0, 5);
1022         if (p == NULL)
1023                 return -ENOMEM;
1024
1025         deviceID = ioread32(p);
1026         /* Tornado device */
1027         if (deviceID == 0x07000200) {
1028                 number_uarts = ioread8(p + 4);
1029                 dev_dbg(&dev->dev,
1030                         "%d ports detected on Oxford PCI Express device\n",
1031                         number_uarts);
1032         }
1033         pci_iounmap(dev, p);
1034         return number_uarts;
1035 }
1036
1037 static int pci_asix_setup(struct serial_private *priv,
1038                   const struct pciserial_board *board,
1039                   struct uart_8250_port *port, int idx)
1040 {
1041         port->bugs |= UART_BUG_PARITY;
1042         return pci_default_setup(priv, board, port, idx);
1043 }
1044
1045 /* Quatech devices have their own extra interface features */
1046
1047 struct quatech_feature {
1048         u16 devid;
1049         bool amcc;
1050 };
1051
1052 #define QPCR_TEST_FOR1          0x3F
1053 #define QPCR_TEST_GET1          0x00
1054 #define QPCR_TEST_FOR2          0x40
1055 #define QPCR_TEST_GET2          0x40
1056 #define QPCR_TEST_FOR3          0x80
1057 #define QPCR_TEST_GET3          0x40
1058 #define QPCR_TEST_FOR4          0xC0
1059 #define QPCR_TEST_GET4          0x80
1060
1061 #define QOPR_CLOCK_X1           0x0000
1062 #define QOPR_CLOCK_X2           0x0001
1063 #define QOPR_CLOCK_X4           0x0002
1064 #define QOPR_CLOCK_X8           0x0003
1065 #define QOPR_CLOCK_RATE_MASK    0x0003
1066
1067
1068 static struct quatech_feature quatech_cards[] = {
1069         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1070         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1071         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1072         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1073         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1074         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1075         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1076         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1077         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1078         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1079         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1080         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1081         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1082         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1083         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1084         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1085         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1086         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1087         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1088         { 0, }
1089 };
1090
1091 static int pci_quatech_amcc(u16 devid)
1092 {
1093         struct quatech_feature *qf = &quatech_cards[0];
1094         while (qf->devid) {
1095                 if (qf->devid == devid)
1096                         return qf->amcc;
1097                 qf++;
1098         }
1099         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1100         return 0;
1101 };
1102
1103 static int pci_quatech_rqopr(struct uart_8250_port *port)
1104 {
1105         unsigned long base = port->port.iobase;
1106         u8 LCR, val;
1107
1108         LCR = inb(base + UART_LCR);
1109         outb(0xBF, base + UART_LCR);
1110         val = inb(base + UART_SCR);
1111         outb(LCR, base + UART_LCR);
1112         return val;
1113 }
1114
1115 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1116 {
1117         unsigned long base = port->port.iobase;
1118         u8 LCR, val;
1119
1120         LCR = inb(base + UART_LCR);
1121         outb(0xBF, base + UART_LCR);
1122         val = inb(base + UART_SCR);
1123         outb(qopr, base + UART_SCR);
1124         outb(LCR, base + UART_LCR);
1125 }
1126
1127 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1128 {
1129         unsigned long base = port->port.iobase;
1130         u8 LCR, val, qmcr;
1131
1132         LCR = inb(base + UART_LCR);
1133         outb(0xBF, base + UART_LCR);
1134         val = inb(base + UART_SCR);
1135         outb(val | 0x10, base + UART_SCR);
1136         qmcr = inb(base + UART_MCR);
1137         outb(val, base + UART_SCR);
1138         outb(LCR, base + UART_LCR);
1139
1140         return qmcr;
1141 }
1142
1143 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1144 {
1145         unsigned long base = port->port.iobase;
1146         u8 LCR, val;
1147
1148         LCR = inb(base + UART_LCR);
1149         outb(0xBF, base + UART_LCR);
1150         val = inb(base + UART_SCR);
1151         outb(val | 0x10, base + UART_SCR);
1152         outb(qmcr, base + UART_MCR);
1153         outb(val, base + UART_SCR);
1154         outb(LCR, base + UART_LCR);
1155 }
1156
1157 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1158 {
1159         unsigned long base = port->port.iobase;
1160         u8 LCR, val;
1161
1162         LCR = inb(base + UART_LCR);
1163         outb(0xBF, base + UART_LCR);
1164         val = inb(base + UART_SCR);
1165         if (val & 0x20) {
1166                 outb(0x80, UART_LCR);
1167                 if (!(inb(UART_SCR) & 0x20)) {
1168                         outb(LCR, base + UART_LCR);
1169                         return 1;
1170                 }
1171         }
1172         return 0;
1173 }
1174
1175 static int pci_quatech_test(struct uart_8250_port *port)
1176 {
1177         u8 reg;
1178         u8 qopr = pci_quatech_rqopr(port);
1179         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1180         reg = pci_quatech_rqopr(port) & 0xC0;
1181         if (reg != QPCR_TEST_GET1)
1182                 return -EINVAL;
1183         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1184         reg = pci_quatech_rqopr(port) & 0xC0;
1185         if (reg != QPCR_TEST_GET2)
1186                 return -EINVAL;
1187         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1188         reg = pci_quatech_rqopr(port) & 0xC0;
1189         if (reg != QPCR_TEST_GET3)
1190                 return -EINVAL;
1191         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1192         reg = pci_quatech_rqopr(port) & 0xC0;
1193         if (reg != QPCR_TEST_GET4)
1194                 return -EINVAL;
1195
1196         pci_quatech_wqopr(port, qopr);
1197         return 0;
1198 }
1199
1200 static int pci_quatech_clock(struct uart_8250_port *port)
1201 {
1202         u8 qopr, reg, set;
1203         unsigned long clock;
1204
1205         if (pci_quatech_test(port) < 0)
1206                 return 1843200;
1207
1208         qopr = pci_quatech_rqopr(port);
1209
1210         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1211         reg = pci_quatech_rqopr(port);
1212         if (reg & QOPR_CLOCK_X8) {
1213                 clock = 1843200;
1214                 goto out;
1215         }
1216         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1217         reg = pci_quatech_rqopr(port);
1218         if (!(reg & QOPR_CLOCK_X8)) {
1219                 clock = 1843200;
1220                 goto out;
1221         }
1222         reg &= QOPR_CLOCK_X8;
1223         if (reg == QOPR_CLOCK_X2) {
1224                 clock =  3685400;
1225                 set = QOPR_CLOCK_X2;
1226         } else if (reg == QOPR_CLOCK_X4) {
1227                 clock = 7372800;
1228                 set = QOPR_CLOCK_X4;
1229         } else if (reg == QOPR_CLOCK_X8) {
1230                 clock = 14745600;
1231                 set = QOPR_CLOCK_X8;
1232         } else {
1233                 clock = 1843200;
1234                 set = QOPR_CLOCK_X1;
1235         }
1236         qopr &= ~QOPR_CLOCK_RATE_MASK;
1237         qopr |= set;
1238
1239 out:
1240         pci_quatech_wqopr(port, qopr);
1241         return clock;
1242 }
1243
1244 static int pci_quatech_rs422(struct uart_8250_port *port)
1245 {
1246         u8 qmcr;
1247         int rs422 = 0;
1248
1249         if (!pci_quatech_has_qmcr(port))
1250                 return 0;
1251         qmcr = pci_quatech_rqmcr(port);
1252         pci_quatech_wqmcr(port, 0xFF);
1253         if (pci_quatech_rqmcr(port))
1254                 rs422 = 1;
1255         pci_quatech_wqmcr(port, qmcr);
1256         return rs422;
1257 }
1258
1259 static int pci_quatech_init(struct pci_dev *dev)
1260 {
1261         if (pci_quatech_amcc(dev->device)) {
1262                 unsigned long base = pci_resource_start(dev, 0);
1263                 if (base) {
1264                         u32 tmp;
1265                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1266                         tmp = inl(base + 0x3c);
1267                         outl(tmp | 0x01000000, base + 0x3c);
1268                         outl(tmp &= ~0x01000000, base + 0x3c);
1269                 }
1270         }
1271         return 0;
1272 }
1273
1274 static int pci_quatech_setup(struct serial_private *priv,
1275                   const struct pciserial_board *board,
1276                   struct uart_8250_port *port, int idx)
1277 {
1278         /* Needed by pci_quatech calls below */
1279         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1280         /* Set up the clocking */
1281         port->port.uartclk = pci_quatech_clock(port);
1282         /* For now just warn about RS422 */
1283         if (pci_quatech_rs422(port))
1284                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1285         return pci_default_setup(priv, board, port, idx);
1286 }
1287
1288 static void pci_quatech_exit(struct pci_dev *dev)
1289 {
1290 }
1291
1292 static int pci_default_setup(struct serial_private *priv,
1293                   const struct pciserial_board *board,
1294                   struct uart_8250_port *port, int idx)
1295 {
1296         unsigned int bar, offset = board->first_offset, maxnr;
1297
1298         bar = FL_GET_BASE(board->flags);
1299         if (board->flags & FL_BASE_BARS)
1300                 bar += idx;
1301         else
1302                 offset += idx * board->uart_offset;
1303
1304         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1305                 (board->reg_shift + 3);
1306
1307         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1308                 return 1;
1309
1310         return setup_port(priv, port, bar, offset, board->reg_shift);
1311 }
1312
1313 static int pci_pericom_setup(struct serial_private *priv,
1314                   const struct pciserial_board *board,
1315                   struct uart_8250_port *port, int idx)
1316 {
1317         unsigned int bar, offset = board->first_offset, maxnr;
1318
1319         bar = FL_GET_BASE(board->flags);
1320         if (board->flags & FL_BASE_BARS)
1321                 bar += idx;
1322         else
1323                 offset += idx * board->uart_offset;
1324
1325         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1326                 (board->reg_shift + 3);
1327
1328         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1329                 return 1;
1330
1331         port->port.uartclk = 14745600;
1332
1333         return setup_port(priv, port, bar, offset, board->reg_shift);
1334 }
1335
1336 static int
1337 ce4100_serial_setup(struct serial_private *priv,
1338                   const struct pciserial_board *board,
1339                   struct uart_8250_port *port, int idx)
1340 {
1341         int ret;
1342
1343         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1344         port->port.iotype = UPIO_MEM32;
1345         port->port.type = PORT_XSCALE;
1346         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1347         port->port.regshift = 2;
1348
1349         return ret;
1350 }
1351
1352 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1354
1355 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1357
1358 #define BYT_PRV_CLK                     0x800
1359 #define BYT_PRV_CLK_EN                  (1 << 0)
1360 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1361 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1362 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1363
1364 #define BYT_GENERAL_REG                 0x808
1365 #define BYT_GENERAL_DIS_RTS_N_OVERRIDE  (1 << 3)
1366
1367 #define BYT_TX_OVF_INT                  0x820
1368 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1369
1370 static void
1371 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1372                 struct ktermios *old)
1373 {
1374         unsigned int baud = tty_termios_baud_rate(termios);
1375         unsigned int m, n;
1376         u32 reg;
1377
1378         /*
1379          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1380          * dividers must be adjusted.
1381          *
1382          * uartclk = (m / n) * 100 MHz, where m <= n
1383          */
1384         switch (baud) {
1385         case 500000:
1386         case 1000000:
1387         case 2000000:
1388         case 4000000:
1389                 m = 64;
1390                 n = 100;
1391                 p->uartclk = 64000000;
1392                 break;
1393         case 3500000:
1394                 m = 56;
1395                 n = 100;
1396                 p->uartclk = 56000000;
1397                 break;
1398         case 1500000:
1399         case 3000000:
1400                 m = 48;
1401                 n = 100;
1402                 p->uartclk = 48000000;
1403                 break;
1404         case 2500000:
1405                 m = 40;
1406                 n = 100;
1407                 p->uartclk = 40000000;
1408                 break;
1409         default:
1410                 m = 2304;
1411                 n = 3125;
1412                 p->uartclk = 73728000;
1413         }
1414
1415         /* Reset the clock */
1416         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1417         writel(reg, p->membase + BYT_PRV_CLK);
1418         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1419         writel(reg, p->membase + BYT_PRV_CLK);
1420
1421         /*
1422          * If auto-handshake mechanism is not enabled,
1423          * disable rts_n override
1424          */
1425         reg = readl(p->membase + BYT_GENERAL_REG);
1426         reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1427         if (termios->c_cflag & CRTSCTS)
1428                 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1429         writel(reg, p->membase + BYT_GENERAL_REG);
1430
1431         serial8250_do_set_termios(p, termios, old);
1432 }
1433
1434 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1435 {
1436         struct dw_dma_slave *dws = param;
1437
1438         if (dws->dma_dev != chan->device->dev)
1439                 return false;
1440
1441         chan->private = dws;
1442         return true;
1443 }
1444
1445 static int
1446 byt_serial_setup(struct serial_private *priv,
1447                  const struct pciserial_board *board,
1448                  struct uart_8250_port *port, int idx)
1449 {
1450         struct pci_dev *pdev = priv->dev;
1451         struct device *dev = port->port.dev;
1452         struct uart_8250_dma *dma;
1453         struct dw_dma_slave *tx_param, *rx_param;
1454         struct pci_dev *dma_dev;
1455         int ret;
1456
1457         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1458         if (!dma)
1459                 return -ENOMEM;
1460
1461         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1462         if (!tx_param)
1463                 return -ENOMEM;
1464
1465         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1466         if (!rx_param)
1467                 return -ENOMEM;
1468
1469         switch (pdev->device) {
1470         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1471         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1472                 rx_param->src_id = 3;
1473                 tx_param->dst_id = 2;
1474                 break;
1475         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1476         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1477                 rx_param->src_id = 5;
1478                 tx_param->dst_id = 4;
1479                 break;
1480         default:
1481                 return -EINVAL;
1482         }
1483
1484         rx_param->src_master = 1;
1485         rx_param->dst_master = 0;
1486
1487         dma->rxconf.src_maxburst = 16;
1488
1489         tx_param->src_master = 1;
1490         tx_param->dst_master = 0;
1491
1492         dma->txconf.dst_maxburst = 16;
1493
1494         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1495         rx_param->dma_dev = &dma_dev->dev;
1496         tx_param->dma_dev = &dma_dev->dev;
1497
1498         dma->fn = byt_dma_filter;
1499         dma->rx_param = rx_param;
1500         dma->tx_param = tx_param;
1501
1502         ret = pci_default_setup(priv, board, port, idx);
1503         port->port.iotype = UPIO_MEM;
1504         port->port.type = PORT_16550A;
1505         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1506         port->port.set_termios = byt_set_termios;
1507         port->port.fifosize = 64;
1508         port->tx_loadsz = 64;
1509         port->dma = dma;
1510         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1511
1512         /* Disable Tx counter interrupts */
1513         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1514
1515         return ret;
1516 }
1517
1518 static int
1519 pci_omegapci_setup(struct serial_private *priv,
1520                       const struct pciserial_board *board,
1521                       struct uart_8250_port *port, int idx)
1522 {
1523         return setup_port(priv, port, 2, idx * 8, 0);
1524 }
1525
1526 static int
1527 pci_brcm_trumanage_setup(struct serial_private *priv,
1528                          const struct pciserial_board *board,
1529                          struct uart_8250_port *port, int idx)
1530 {
1531         int ret = pci_default_setup(priv, board, port, idx);
1532
1533         port->port.type = PORT_BRCM_TRUMANAGE;
1534         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1535         return ret;
1536 }
1537
1538 static int pci_fintek_setup(struct serial_private *priv,
1539                             const struct pciserial_board *board,
1540                             struct uart_8250_port *port, int idx)
1541 {
1542         struct pci_dev *pdev = priv->dev;
1543         unsigned long base;
1544         unsigned long iobase;
1545         unsigned long ciobase = 0;
1546         u8 config_base;
1547
1548         /*
1549          * We are supposed to be able to read these from the PCI config space,
1550          * but the values there don't seem to match what we need to use, so
1551          * just use these hard-coded values for now, as they are correct.
1552          */
1553         switch (idx) {
1554         case 0: iobase = 0xe000; config_base = 0x40; break;
1555         case 1: iobase = 0xe008; config_base = 0x48; break;
1556         case 2: iobase = 0xe010; config_base = 0x50; break;
1557         case 3: iobase = 0xe018; config_base = 0x58; break;
1558         case 4: iobase = 0xe020; config_base = 0x60; break;
1559         case 5: iobase = 0xe028; config_base = 0x68; break;
1560         case 6: iobase = 0xe030; config_base = 0x70; break;
1561         case 7: iobase = 0xe038; config_base = 0x78; break;
1562         case 8: iobase = 0xe040; config_base = 0x80; break;
1563         case 9: iobase = 0xe048; config_base = 0x88; break;
1564         case 10: iobase = 0xe050; config_base = 0x90; break;
1565         case 11: iobase = 0xe058; config_base = 0x98; break;
1566         default:
1567                 /* Unknown number of ports, get out of here */
1568                 return -EINVAL;
1569         }
1570
1571         if (idx < 4) {
1572                 base = pci_resource_start(priv->dev, 3);
1573                 ciobase = (int)(base + (0x8 * idx));
1574         }
1575
1576         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1577                 __func__, idx, iobase, ciobase, config_base);
1578
1579         /* Enable UART I/O port */
1580         pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1581
1582         /* Select 128-byte FIFO and 8x FIFO threshold */
1583         pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1584
1585         /* LSB UART */
1586         pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1587
1588         /* MSB UART */
1589         pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1590
1591         /* irq number, this usually fails, but the spec says to do it anyway. */
1592         pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1593
1594         port->port.iotype = UPIO_PORT;
1595         port->port.iobase = iobase;
1596         port->port.mapbase = 0;
1597         port->port.membase = NULL;
1598         port->port.regshift = 0;
1599
1600         return 0;
1601 }
1602
1603 static int skip_tx_en_setup(struct serial_private *priv,
1604                         const struct pciserial_board *board,
1605                         struct uart_8250_port *port, int idx)
1606 {
1607         port->port.flags |= UPF_NO_TXEN_TEST;
1608         dev_dbg(&priv->dev->dev,
1609                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1610                 priv->dev->vendor, priv->dev->device,
1611                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1612
1613         return pci_default_setup(priv, board, port, idx);
1614 }
1615
1616 static void kt_handle_break(struct uart_port *p)
1617 {
1618         struct uart_8250_port *up = up_to_u8250p(p);
1619         /*
1620          * On receipt of a BI, serial device in Intel ME (Intel
1621          * management engine) needs to have its fifos cleared for sane
1622          * SOL (Serial Over Lan) output.
1623          */
1624         serial8250_clear_and_reinit_fifos(up);
1625 }
1626
1627 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1628 {
1629         struct uart_8250_port *up = up_to_u8250p(p);
1630         unsigned int val;
1631
1632         /*
1633          * When the Intel ME (management engine) gets reset its serial
1634          * port registers could return 0 momentarily.  Functions like
1635          * serial8250_console_write, read and save the IER, perform
1636          * some operation and then restore it.  In order to avoid
1637          * setting IER register inadvertently to 0, if the value read
1638          * is 0, double check with ier value in uart_8250_port and use
1639          * that instead.  up->ier should be the same value as what is
1640          * currently configured.
1641          */
1642         val = inb(p->iobase + offset);
1643         if (offset == UART_IER) {
1644                 if (val == 0)
1645                         val = up->ier;
1646         }
1647         return val;
1648 }
1649
1650 static int kt_serial_setup(struct serial_private *priv,
1651                            const struct pciserial_board *board,
1652                            struct uart_8250_port *port, int idx)
1653 {
1654         port->port.flags |= UPF_BUG_THRE;
1655         port->port.serial_in = kt_serial_in;
1656         port->port.handle_break = kt_handle_break;
1657         return skip_tx_en_setup(priv, board, port, idx);
1658 }
1659
1660 static int pci_eg20t_init(struct pci_dev *dev)
1661 {
1662 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1663         return -ENODEV;
1664 #else
1665         return 0;
1666 #endif
1667 }
1668
1669 static int
1670 pci_xr17c154_setup(struct serial_private *priv,
1671                   const struct pciserial_board *board,
1672                   struct uart_8250_port *port, int idx)
1673 {
1674         port->port.flags |= UPF_EXAR_EFR;
1675         return pci_default_setup(priv, board, port, idx);
1676 }
1677
1678 static int
1679 pci_xr17v35x_setup(struct serial_private *priv,
1680                   const struct pciserial_board *board,
1681                   struct uart_8250_port *port, int idx)
1682 {
1683         u8 __iomem *p;
1684
1685         p = pci_ioremap_bar(priv->dev, 0);
1686         if (p == NULL)
1687                 return -ENOMEM;
1688
1689         port->port.flags |= UPF_EXAR_EFR;
1690
1691         /*
1692          * Setup Multipurpose Input/Output pins.
1693          */
1694         if (idx == 0) {
1695                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1696                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1697                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1698                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1699                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1700                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1701                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1702                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1703                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1704                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1705                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1706                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1707         }
1708         writeb(0x00, p + UART_EXAR_8XMODE);
1709         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1710         writeb(128, p + UART_EXAR_TXTRG);
1711         writeb(128, p + UART_EXAR_RXTRG);
1712         iounmap(p);
1713
1714         return pci_default_setup(priv, board, port, idx);
1715 }
1716
1717 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1718 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1719 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1720 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1721
1722 static int
1723 pci_fastcom335_setup(struct serial_private *priv,
1724                   const struct pciserial_board *board,
1725                   struct uart_8250_port *port, int idx)
1726 {
1727         u8 __iomem *p;
1728
1729         p = pci_ioremap_bar(priv->dev, 0);
1730         if (p == NULL)
1731                 return -ENOMEM;
1732
1733         port->port.flags |= UPF_EXAR_EFR;
1734
1735         /*
1736          * Setup Multipurpose Input/Output pins.
1737          */
1738         if (idx == 0) {
1739                 switch (priv->dev->device) {
1740                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1741                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1742                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1743                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1744                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1745                         break;
1746                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1747                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1748                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1749                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1750                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1751                         break;
1752                 }
1753                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1754                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1755                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1756         }
1757         writeb(0x00, p + UART_EXAR_8XMODE);
1758         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1759         writeb(32, p + UART_EXAR_TXTRG);
1760         writeb(32, p + UART_EXAR_RXTRG);
1761         iounmap(p);
1762
1763         return pci_default_setup(priv, board, port, idx);
1764 }
1765
1766 static int
1767 pci_wch_ch353_setup(struct serial_private *priv,
1768                     const struct pciserial_board *board,
1769                     struct uart_8250_port *port, int idx)
1770 {
1771         port->port.flags |= UPF_FIXED_TYPE;
1772         port->port.type = PORT_16550A;
1773         return pci_default_setup(priv, board, port, idx);
1774 }
1775
1776 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1777 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1778 #define PCI_DEVICE_ID_OCTPRO            0x0001
1779 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1780 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1781 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1782 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1783 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1784 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1785 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1786 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1787 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1788 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1789 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1790 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1791 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1792 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1793 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1794 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1795 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1796 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1797 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1798 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1799 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1800 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1801 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1802 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1803 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1804 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1805 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1806 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1807 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1808 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1809 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1810 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1811 #define PCI_VENDOR_ID_WCH               0x4348
1812 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1813 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1814 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1815 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1816 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1817 #define PCI_VENDOR_ID_AGESTAR           0x5372
1818 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1819 #define PCI_VENDOR_ID_ASIX              0x9710
1820 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1821 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1822 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1823 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1824 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1825
1826 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1827 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1828
1829
1830 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1831 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1832 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1833
1834 /*
1835  * Master list of serial port init/setup/exit quirks.
1836  * This does not describe the general nature of the port.
1837  * (ie, baud base, number and location of ports, etc)
1838  *
1839  * This list is ordered alphabetically by vendor then device.
1840  * Specific entries must come before more generic entries.
1841  */
1842 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1843         /*
1844         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1845         */
1846         {
1847                 .vendor         = PCI_VENDOR_ID_AMCC,
1848                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1849                 .subvendor      = PCI_ANY_ID,
1850                 .subdevice      = PCI_ANY_ID,
1851                 .setup          = addidata_apci7800_setup,
1852         },
1853         /*
1854          * AFAVLAB cards - these may be called via parport_serial
1855          *  It is not clear whether this applies to all products.
1856          */
1857         {
1858                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1859                 .device         = PCI_ANY_ID,
1860                 .subvendor      = PCI_ANY_ID,
1861                 .subdevice      = PCI_ANY_ID,
1862                 .setup          = afavlab_setup,
1863         },
1864         /*
1865          * HP Diva
1866          */
1867         {
1868                 .vendor         = PCI_VENDOR_ID_HP,
1869                 .device         = PCI_DEVICE_ID_HP_DIVA,
1870                 .subvendor      = PCI_ANY_ID,
1871                 .subdevice      = PCI_ANY_ID,
1872                 .init           = pci_hp_diva_init,
1873                 .setup          = pci_hp_diva_setup,
1874         },
1875         /*
1876          * Intel
1877          */
1878         {
1879                 .vendor         = PCI_VENDOR_ID_INTEL,
1880                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1881                 .subvendor      = 0xe4bf,
1882                 .subdevice      = PCI_ANY_ID,
1883                 .init           = pci_inteli960ni_init,
1884                 .setup          = pci_default_setup,
1885         },
1886         {
1887                 .vendor         = PCI_VENDOR_ID_INTEL,
1888                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1889                 .subvendor      = PCI_ANY_ID,
1890                 .subdevice      = PCI_ANY_ID,
1891                 .setup          = skip_tx_en_setup,
1892         },
1893         {
1894                 .vendor         = PCI_VENDOR_ID_INTEL,
1895                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1896                 .subvendor      = PCI_ANY_ID,
1897                 .subdevice      = PCI_ANY_ID,
1898                 .setup          = skip_tx_en_setup,
1899         },
1900         {
1901                 .vendor         = PCI_VENDOR_ID_INTEL,
1902                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1903                 .subvendor      = PCI_ANY_ID,
1904                 .subdevice      = PCI_ANY_ID,
1905                 .setup          = skip_tx_en_setup,
1906         },
1907         {
1908                 .vendor         = PCI_VENDOR_ID_INTEL,
1909                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1910                 .subvendor      = PCI_ANY_ID,
1911                 .subdevice      = PCI_ANY_ID,
1912                 .setup          = ce4100_serial_setup,
1913         },
1914         {
1915                 .vendor         = PCI_VENDOR_ID_INTEL,
1916                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1917                 .subvendor      = PCI_ANY_ID,
1918                 .subdevice      = PCI_ANY_ID,
1919                 .setup          = kt_serial_setup,
1920         },
1921         {
1922                 .vendor         = PCI_VENDOR_ID_INTEL,
1923                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
1924                 .subvendor      = PCI_ANY_ID,
1925                 .subdevice      = PCI_ANY_ID,
1926                 .setup          = byt_serial_setup,
1927         },
1928         {
1929                 .vendor         = PCI_VENDOR_ID_INTEL,
1930                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
1931                 .subvendor      = PCI_ANY_ID,
1932                 .subdevice      = PCI_ANY_ID,
1933                 .setup          = byt_serial_setup,
1934         },
1935         {
1936                 .vendor         = PCI_VENDOR_ID_INTEL,
1937                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
1938                 .subvendor      = PCI_ANY_ID,
1939                 .subdevice      = PCI_ANY_ID,
1940                 .setup          = byt_serial_setup,
1941         },
1942         {
1943                 .vendor         = PCI_VENDOR_ID_INTEL,
1944                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
1945                 .subvendor      = PCI_ANY_ID,
1946                 .subdevice      = PCI_ANY_ID,
1947                 .setup          = byt_serial_setup,
1948         },
1949         /*
1950          * ITE
1951          */
1952         {
1953                 .vendor         = PCI_VENDOR_ID_ITE,
1954                 .device         = PCI_DEVICE_ID_ITE_8872,
1955                 .subvendor      = PCI_ANY_ID,
1956                 .subdevice      = PCI_ANY_ID,
1957                 .init           = pci_ite887x_init,
1958                 .setup          = pci_default_setup,
1959                 .exit           = pci_ite887x_exit,
1960         },
1961         /*
1962          * National Instruments
1963          */
1964         {
1965                 .vendor         = PCI_VENDOR_ID_NI,
1966                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1967                 .subvendor      = PCI_ANY_ID,
1968                 .subdevice      = PCI_ANY_ID,
1969                 .init           = pci_ni8420_init,
1970                 .setup          = pci_default_setup,
1971                 .exit           = pci_ni8420_exit,
1972         },
1973         {
1974                 .vendor         = PCI_VENDOR_ID_NI,
1975                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1976                 .subvendor      = PCI_ANY_ID,
1977                 .subdevice      = PCI_ANY_ID,
1978                 .init           = pci_ni8420_init,
1979                 .setup          = pci_default_setup,
1980                 .exit           = pci_ni8420_exit,
1981         },
1982         {
1983                 .vendor         = PCI_VENDOR_ID_NI,
1984                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1985                 .subvendor      = PCI_ANY_ID,
1986                 .subdevice      = PCI_ANY_ID,
1987                 .init           = pci_ni8420_init,
1988                 .setup          = pci_default_setup,
1989                 .exit           = pci_ni8420_exit,
1990         },
1991         {
1992                 .vendor         = PCI_VENDOR_ID_NI,
1993                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1994                 .subvendor      = PCI_ANY_ID,
1995                 .subdevice      = PCI_ANY_ID,
1996                 .init           = pci_ni8420_init,
1997                 .setup          = pci_default_setup,
1998                 .exit           = pci_ni8420_exit,
1999         },
2000         {
2001                 .vendor         = PCI_VENDOR_ID_NI,
2002                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2003                 .subvendor      = PCI_ANY_ID,
2004                 .subdevice      = PCI_ANY_ID,
2005                 .init           = pci_ni8420_init,
2006                 .setup          = pci_default_setup,
2007                 .exit           = pci_ni8420_exit,
2008         },
2009         {
2010                 .vendor         = PCI_VENDOR_ID_NI,
2011                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2012                 .subvendor      = PCI_ANY_ID,
2013                 .subdevice      = PCI_ANY_ID,
2014                 .init           = pci_ni8420_init,
2015                 .setup          = pci_default_setup,
2016                 .exit           = pci_ni8420_exit,
2017         },
2018         {
2019                 .vendor         = PCI_VENDOR_ID_NI,
2020                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2021                 .subvendor      = PCI_ANY_ID,
2022                 .subdevice      = PCI_ANY_ID,
2023                 .init           = pci_ni8420_init,
2024                 .setup          = pci_default_setup,
2025                 .exit           = pci_ni8420_exit,
2026         },
2027         {
2028                 .vendor         = PCI_VENDOR_ID_NI,
2029                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2030                 .subvendor      = PCI_ANY_ID,
2031                 .subdevice      = PCI_ANY_ID,
2032                 .init           = pci_ni8420_init,
2033                 .setup          = pci_default_setup,
2034                 .exit           = pci_ni8420_exit,
2035         },
2036         {
2037                 .vendor         = PCI_VENDOR_ID_NI,
2038                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2039                 .subvendor      = PCI_ANY_ID,
2040                 .subdevice      = PCI_ANY_ID,
2041                 .init           = pci_ni8420_init,
2042                 .setup          = pci_default_setup,
2043                 .exit           = pci_ni8420_exit,
2044         },
2045         {
2046                 .vendor         = PCI_VENDOR_ID_NI,
2047                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2048                 .subvendor      = PCI_ANY_ID,
2049                 .subdevice      = PCI_ANY_ID,
2050                 .init           = pci_ni8420_init,
2051                 .setup          = pci_default_setup,
2052                 .exit           = pci_ni8420_exit,
2053         },
2054         {
2055                 .vendor         = PCI_VENDOR_ID_NI,
2056                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2057                 .subvendor      = PCI_ANY_ID,
2058                 .subdevice      = PCI_ANY_ID,
2059                 .init           = pci_ni8420_init,
2060                 .setup          = pci_default_setup,
2061                 .exit           = pci_ni8420_exit,
2062         },
2063         {
2064                 .vendor         = PCI_VENDOR_ID_NI,
2065                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2066                 .subvendor      = PCI_ANY_ID,
2067                 .subdevice      = PCI_ANY_ID,
2068                 .init           = pci_ni8420_init,
2069                 .setup          = pci_default_setup,
2070                 .exit           = pci_ni8420_exit,
2071         },
2072         {
2073                 .vendor         = PCI_VENDOR_ID_NI,
2074                 .device         = PCI_ANY_ID,
2075                 .subvendor      = PCI_ANY_ID,
2076                 .subdevice      = PCI_ANY_ID,
2077                 .init           = pci_ni8430_init,
2078                 .setup          = pci_ni8430_setup,
2079                 .exit           = pci_ni8430_exit,
2080         },
2081         /* Quatech */
2082         {
2083                 .vendor         = PCI_VENDOR_ID_QUATECH,
2084                 .device         = PCI_ANY_ID,
2085                 .subvendor      = PCI_ANY_ID,
2086                 .subdevice      = PCI_ANY_ID,
2087                 .init           = pci_quatech_init,
2088                 .setup          = pci_quatech_setup,
2089                 .exit           = pci_quatech_exit,
2090         },
2091         /*
2092          * Panacom
2093          */
2094         {
2095                 .vendor         = PCI_VENDOR_ID_PANACOM,
2096                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2097                 .subvendor      = PCI_ANY_ID,
2098                 .subdevice      = PCI_ANY_ID,
2099                 .init           = pci_plx9050_init,
2100                 .setup          = pci_default_setup,
2101                 .exit           = pci_plx9050_exit,
2102         },
2103         {
2104                 .vendor         = PCI_VENDOR_ID_PANACOM,
2105                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2106                 .subvendor      = PCI_ANY_ID,
2107                 .subdevice      = PCI_ANY_ID,
2108                 .init           = pci_plx9050_init,
2109                 .setup          = pci_default_setup,
2110                 .exit           = pci_plx9050_exit,
2111         },
2112         /*
2113          * Pericom
2114          */
2115         {
2116                 .vendor         = 0x12d8,
2117                 .device         = 0x7952,
2118                 .subvendor      = PCI_ANY_ID,
2119                 .subdevice      = PCI_ANY_ID,
2120                 .setup          = pci_pericom_setup,
2121         },
2122         {
2123                 .vendor         = 0x12d8,
2124                 .device         = 0x7954,
2125                 .subvendor      = PCI_ANY_ID,
2126                 .subdevice      = PCI_ANY_ID,
2127                 .setup          = pci_pericom_setup,
2128         },
2129         {
2130                 .vendor         = 0x12d8,
2131                 .device         = 0x7958,
2132                 .subvendor      = PCI_ANY_ID,
2133                 .subdevice      = PCI_ANY_ID,
2134                 .setup          = pci_pericom_setup,
2135         },
2136
2137         /*
2138          * PLX
2139          */
2140         {
2141                 .vendor         = PCI_VENDOR_ID_PLX,
2142                 .device         = PCI_DEVICE_ID_PLX_9030,
2143                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
2144                 .subdevice      = PCI_ANY_ID,
2145                 .setup          = pci_default_setup,
2146         },
2147         {
2148                 .vendor         = PCI_VENDOR_ID_PLX,
2149                 .device         = PCI_DEVICE_ID_PLX_9050,
2150                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2151                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2152                 .init           = pci_plx9050_init,
2153                 .setup          = pci_default_setup,
2154                 .exit           = pci_plx9050_exit,
2155         },
2156         {
2157                 .vendor         = PCI_VENDOR_ID_PLX,
2158                 .device         = PCI_DEVICE_ID_PLX_9050,
2159                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2160                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2161                 .init           = pci_plx9050_init,
2162                 .setup          = pci_default_setup,
2163                 .exit           = pci_plx9050_exit,
2164         },
2165         {
2166                 .vendor         = PCI_VENDOR_ID_PLX,
2167                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2168                 .subvendor      = PCI_VENDOR_ID_PLX,
2169                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2170                 .init           = pci_plx9050_init,
2171                 .setup          = pci_default_setup,
2172                 .exit           = pci_plx9050_exit,
2173         },
2174         /*
2175          * SBS Technologies, Inc., PMC-OCTALPRO 232
2176          */
2177         {
2178                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2179                 .device         = PCI_DEVICE_ID_OCTPRO,
2180                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2181                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2182                 .init           = sbs_init,
2183                 .setup          = sbs_setup,
2184                 .exit           = sbs_exit,
2185         },
2186         /*
2187          * SBS Technologies, Inc., PMC-OCTALPRO 422
2188          */
2189         {
2190                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2191                 .device         = PCI_DEVICE_ID_OCTPRO,
2192                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2193                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2194                 .init           = sbs_init,
2195                 .setup          = sbs_setup,
2196                 .exit           = sbs_exit,
2197         },
2198         /*
2199          * SBS Technologies, Inc., P-Octal 232
2200          */
2201         {
2202                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2203                 .device         = PCI_DEVICE_ID_OCTPRO,
2204                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2205                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2206                 .init           = sbs_init,
2207                 .setup          = sbs_setup,
2208                 .exit           = sbs_exit,
2209         },
2210         /*
2211          * SBS Technologies, Inc., P-Octal 422
2212          */
2213         {
2214                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2215                 .device         = PCI_DEVICE_ID_OCTPRO,
2216                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2217                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2218                 .init           = sbs_init,
2219                 .setup          = sbs_setup,
2220                 .exit           = sbs_exit,
2221         },
2222         /*
2223          * SIIG cards - these may be called via parport_serial
2224          */
2225         {
2226                 .vendor         = PCI_VENDOR_ID_SIIG,
2227                 .device         = PCI_ANY_ID,
2228                 .subvendor      = PCI_ANY_ID,
2229                 .subdevice      = PCI_ANY_ID,
2230                 .init           = pci_siig_init,
2231                 .setup          = pci_siig_setup,
2232         },
2233         /*
2234          * Titan cards
2235          */
2236         {
2237                 .vendor         = PCI_VENDOR_ID_TITAN,
2238                 .device         = PCI_DEVICE_ID_TITAN_400L,
2239                 .subvendor      = PCI_ANY_ID,
2240                 .subdevice      = PCI_ANY_ID,
2241                 .setup          = titan_400l_800l_setup,
2242         },
2243         {
2244                 .vendor         = PCI_VENDOR_ID_TITAN,
2245                 .device         = PCI_DEVICE_ID_TITAN_800L,
2246                 .subvendor      = PCI_ANY_ID,
2247                 .subdevice      = PCI_ANY_ID,
2248                 .setup          = titan_400l_800l_setup,
2249         },
2250         /*
2251          * Timedia cards
2252          */
2253         {
2254                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2255                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2256                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2257                 .subdevice      = PCI_ANY_ID,
2258                 .probe          = pci_timedia_probe,
2259                 .init           = pci_timedia_init,
2260                 .setup          = pci_timedia_setup,
2261         },
2262         {
2263                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2264                 .device         = PCI_ANY_ID,
2265                 .subvendor      = PCI_ANY_ID,
2266                 .subdevice      = PCI_ANY_ID,
2267                 .setup          = pci_timedia_setup,
2268         },
2269         /*
2270          * SUNIX (Timedia) cards
2271          * Do not "probe" for these cards as there is at least one combination
2272          * card that should be handled by parport_pc that doesn't match the
2273          * rule in pci_timedia_probe.
2274          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2275          * There are some boards with part number SER5037AL that report
2276          * subdevice ID 0x0002.
2277          */
2278         {
2279                 .vendor         = PCI_VENDOR_ID_SUNIX,
2280                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2281                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2282                 .subdevice      = PCI_ANY_ID,
2283                 .init           = pci_timedia_init,
2284                 .setup          = pci_timedia_setup,
2285         },
2286         /*
2287          * Exar cards
2288          */
2289         {
2290                 .vendor = PCI_VENDOR_ID_EXAR,
2291                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2292                 .subvendor      = PCI_ANY_ID,
2293                 .subdevice      = PCI_ANY_ID,
2294                 .setup          = pci_xr17c154_setup,
2295         },
2296         {
2297                 .vendor = PCI_VENDOR_ID_EXAR,
2298                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2299                 .subvendor      = PCI_ANY_ID,
2300                 .subdevice      = PCI_ANY_ID,
2301                 .setup          = pci_xr17c154_setup,
2302         },
2303         {
2304                 .vendor = PCI_VENDOR_ID_EXAR,
2305                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2306                 .subvendor      = PCI_ANY_ID,
2307                 .subdevice      = PCI_ANY_ID,
2308                 .setup          = pci_xr17c154_setup,
2309         },
2310         {
2311                 .vendor = PCI_VENDOR_ID_EXAR,
2312                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2313                 .subvendor      = PCI_ANY_ID,
2314                 .subdevice      = PCI_ANY_ID,
2315                 .setup          = pci_xr17v35x_setup,
2316         },
2317         {
2318                 .vendor = PCI_VENDOR_ID_EXAR,
2319                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2320                 .subvendor      = PCI_ANY_ID,
2321                 .subdevice      = PCI_ANY_ID,
2322                 .setup          = pci_xr17v35x_setup,
2323         },
2324         {
2325                 .vendor = PCI_VENDOR_ID_EXAR,
2326                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2327                 .subvendor      = PCI_ANY_ID,
2328                 .subdevice      = PCI_ANY_ID,
2329                 .setup          = pci_xr17v35x_setup,
2330         },
2331         /*
2332          * Xircom cards
2333          */
2334         {
2335                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2336                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2337                 .subvendor      = PCI_ANY_ID,
2338                 .subdevice      = PCI_ANY_ID,
2339                 .init           = pci_xircom_init,
2340                 .setup          = pci_default_setup,
2341         },
2342         /*
2343          * Netmos cards - these may be called via parport_serial
2344          */
2345         {
2346                 .vendor         = PCI_VENDOR_ID_NETMOS,
2347                 .device         = PCI_ANY_ID,
2348                 .subvendor      = PCI_ANY_ID,
2349                 .subdevice      = PCI_ANY_ID,
2350                 .init           = pci_netmos_init,
2351                 .setup          = pci_netmos_9900_setup,
2352         },
2353         /*
2354          * For Oxford Semiconductor Tornado based devices
2355          */
2356         {
2357                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2358                 .device         = PCI_ANY_ID,
2359                 .subvendor      = PCI_ANY_ID,
2360                 .subdevice      = PCI_ANY_ID,
2361                 .init           = pci_oxsemi_tornado_init,
2362                 .setup          = pci_default_setup,
2363         },
2364         {
2365                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2366                 .device         = PCI_ANY_ID,
2367                 .subvendor      = PCI_ANY_ID,
2368                 .subdevice      = PCI_ANY_ID,
2369                 .init           = pci_oxsemi_tornado_init,
2370                 .setup          = pci_default_setup,
2371         },
2372         {
2373                 .vendor         = PCI_VENDOR_ID_DIGI,
2374                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2375                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2376                 .subdevice              = PCI_ANY_ID,
2377                 .init                   = pci_oxsemi_tornado_init,
2378                 .setup          = pci_default_setup,
2379         },
2380         {
2381                 .vendor         = PCI_VENDOR_ID_INTEL,
2382                 .device         = 0x8811,
2383                 .subvendor      = PCI_ANY_ID,
2384                 .subdevice      = PCI_ANY_ID,
2385                 .init           = pci_eg20t_init,
2386                 .setup          = pci_default_setup,
2387         },
2388         {
2389                 .vendor         = PCI_VENDOR_ID_INTEL,
2390                 .device         = 0x8812,
2391                 .subvendor      = PCI_ANY_ID,
2392                 .subdevice      = PCI_ANY_ID,
2393                 .init           = pci_eg20t_init,
2394                 .setup          = pci_default_setup,
2395         },
2396         {
2397                 .vendor         = PCI_VENDOR_ID_INTEL,
2398                 .device         = 0x8813,
2399                 .subvendor      = PCI_ANY_ID,
2400                 .subdevice      = PCI_ANY_ID,
2401                 .init           = pci_eg20t_init,
2402                 .setup          = pci_default_setup,
2403         },
2404         {
2405                 .vendor         = PCI_VENDOR_ID_INTEL,
2406                 .device         = 0x8814,
2407                 .subvendor      = PCI_ANY_ID,
2408                 .subdevice      = PCI_ANY_ID,
2409                 .init           = pci_eg20t_init,
2410                 .setup          = pci_default_setup,
2411         },
2412         {
2413                 .vendor         = 0x10DB,
2414                 .device         = 0x8027,
2415                 .subvendor      = PCI_ANY_ID,
2416                 .subdevice      = PCI_ANY_ID,
2417                 .init           = pci_eg20t_init,
2418                 .setup          = pci_default_setup,
2419         },
2420         {
2421                 .vendor         = 0x10DB,
2422                 .device         = 0x8028,
2423                 .subvendor      = PCI_ANY_ID,
2424                 .subdevice      = PCI_ANY_ID,
2425                 .init           = pci_eg20t_init,
2426                 .setup          = pci_default_setup,
2427         },
2428         {
2429                 .vendor         = 0x10DB,
2430                 .device         = 0x8029,
2431                 .subvendor      = PCI_ANY_ID,
2432                 .subdevice      = PCI_ANY_ID,
2433                 .init           = pci_eg20t_init,
2434                 .setup          = pci_default_setup,
2435         },
2436         {
2437                 .vendor         = 0x10DB,
2438                 .device         = 0x800C,
2439                 .subvendor      = PCI_ANY_ID,
2440                 .subdevice      = PCI_ANY_ID,
2441                 .init           = pci_eg20t_init,
2442                 .setup          = pci_default_setup,
2443         },
2444         {
2445                 .vendor         = 0x10DB,
2446                 .device         = 0x800D,
2447                 .subvendor      = PCI_ANY_ID,
2448                 .subdevice      = PCI_ANY_ID,
2449                 .init           = pci_eg20t_init,
2450                 .setup          = pci_default_setup,
2451         },
2452         /*
2453          * Cronyx Omega PCI (PLX-chip based)
2454          */
2455         {
2456                 .vendor         = PCI_VENDOR_ID_PLX,
2457                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2458                 .subvendor      = PCI_ANY_ID,
2459                 .subdevice      = PCI_ANY_ID,
2460                 .setup          = pci_omegapci_setup,
2461         },
2462         /* WCH CH353 1S1P card (16550 clone) */
2463         {
2464                 .vendor         = PCI_VENDOR_ID_WCH,
2465                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2466                 .subvendor      = PCI_ANY_ID,
2467                 .subdevice      = PCI_ANY_ID,
2468                 .setup          = pci_wch_ch353_setup,
2469         },
2470         /* WCH CH353 2S1P card (16550 clone) */
2471         {
2472                 .vendor         = PCI_VENDOR_ID_WCH,
2473                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2474                 .subvendor      = PCI_ANY_ID,
2475                 .subdevice      = PCI_ANY_ID,
2476                 .setup          = pci_wch_ch353_setup,
2477         },
2478         /* WCH CH353 4S card (16550 clone) */
2479         {
2480                 .vendor         = PCI_VENDOR_ID_WCH,
2481                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2482                 .subvendor      = PCI_ANY_ID,
2483                 .subdevice      = PCI_ANY_ID,
2484                 .setup          = pci_wch_ch353_setup,
2485         },
2486         /* WCH CH353 2S1PF card (16550 clone) */
2487         {
2488                 .vendor         = PCI_VENDOR_ID_WCH,
2489                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2490                 .subvendor      = PCI_ANY_ID,
2491                 .subdevice      = PCI_ANY_ID,
2492                 .setup          = pci_wch_ch353_setup,
2493         },
2494         /* WCH CH352 2S card (16550 clone) */
2495         {
2496                 .vendor         = PCI_VENDOR_ID_WCH,
2497                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2498                 .subvendor      = PCI_ANY_ID,
2499                 .subdevice      = PCI_ANY_ID,
2500                 .setup          = pci_wch_ch353_setup,
2501         },
2502         /*
2503          * ASIX devices with FIFO bug
2504          */
2505         {
2506                 .vendor         = PCI_VENDOR_ID_ASIX,
2507                 .device         = PCI_ANY_ID,
2508                 .subvendor      = PCI_ANY_ID,
2509                 .subdevice      = PCI_ANY_ID,
2510                 .setup          = pci_asix_setup,
2511         },
2512         /*
2513          * Commtech, Inc. Fastcom adapters
2514          *
2515          */
2516         {
2517                 .vendor = PCI_VENDOR_ID_COMMTECH,
2518                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2519                 .subvendor      = PCI_ANY_ID,
2520                 .subdevice      = PCI_ANY_ID,
2521                 .setup          = pci_fastcom335_setup,
2522         },
2523         {
2524                 .vendor = PCI_VENDOR_ID_COMMTECH,
2525                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2526                 .subvendor      = PCI_ANY_ID,
2527                 .subdevice      = PCI_ANY_ID,
2528                 .setup          = pci_fastcom335_setup,
2529         },
2530         {
2531                 .vendor = PCI_VENDOR_ID_COMMTECH,
2532                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2533                 .subvendor      = PCI_ANY_ID,
2534                 .subdevice      = PCI_ANY_ID,
2535                 .setup          = pci_fastcom335_setup,
2536         },
2537         {
2538                 .vendor = PCI_VENDOR_ID_COMMTECH,
2539                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2540                 .subvendor      = PCI_ANY_ID,
2541                 .subdevice      = PCI_ANY_ID,
2542                 .setup          = pci_fastcom335_setup,
2543         },
2544         {
2545                 .vendor = PCI_VENDOR_ID_COMMTECH,
2546                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2547                 .subvendor      = PCI_ANY_ID,
2548                 .subdevice      = PCI_ANY_ID,
2549                 .setup          = pci_xr17v35x_setup,
2550         },
2551         {
2552                 .vendor = PCI_VENDOR_ID_COMMTECH,
2553                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2554                 .subvendor      = PCI_ANY_ID,
2555                 .subdevice      = PCI_ANY_ID,
2556                 .setup          = pci_xr17v35x_setup,
2557         },
2558         {
2559                 .vendor = PCI_VENDOR_ID_COMMTECH,
2560                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2561                 .subvendor      = PCI_ANY_ID,
2562                 .subdevice      = PCI_ANY_ID,
2563                 .setup          = pci_xr17v35x_setup,
2564         },
2565         /*
2566          * Broadcom TruManage (NetXtreme)
2567          */
2568         {
2569                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2570                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2571                 .subvendor      = PCI_ANY_ID,
2572                 .subdevice      = PCI_ANY_ID,
2573                 .setup          = pci_brcm_trumanage_setup,
2574         },
2575         {
2576                 .vendor         = 0x1c29,
2577                 .device         = 0x1104,
2578                 .subvendor      = PCI_ANY_ID,
2579                 .subdevice      = PCI_ANY_ID,
2580                 .setup          = pci_fintek_setup,
2581         },
2582         {
2583                 .vendor         = 0x1c29,
2584                 .device         = 0x1108,
2585                 .subvendor      = PCI_ANY_ID,
2586                 .subdevice      = PCI_ANY_ID,
2587                 .setup          = pci_fintek_setup,
2588         },
2589         {
2590                 .vendor         = 0x1c29,
2591                 .device         = 0x1112,
2592                 .subvendor      = PCI_ANY_ID,
2593                 .subdevice      = PCI_ANY_ID,
2594                 .setup          = pci_fintek_setup,
2595         },
2596
2597         /*
2598          * Default "match everything" terminator entry
2599          */
2600         {
2601                 .vendor         = PCI_ANY_ID,
2602                 .device         = PCI_ANY_ID,
2603                 .subvendor      = PCI_ANY_ID,
2604                 .subdevice      = PCI_ANY_ID,
2605                 .setup          = pci_default_setup,
2606         }
2607 };
2608
2609 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2610 {
2611         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2612 }
2613
2614 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2615 {
2616         struct pci_serial_quirk *quirk;
2617
2618         for (quirk = pci_serial_quirks; ; quirk++)
2619                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2620                     quirk_id_matches(quirk->device, dev->device) &&
2621                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2622                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2623                         break;
2624         return quirk;
2625 }
2626
2627 static inline int get_pci_irq(struct pci_dev *dev,
2628                                 const struct pciserial_board *board)
2629 {
2630         if (board->flags & FL_NOIRQ)
2631                 return 0;
2632         else
2633                 return dev->irq;
2634 }
2635
2636 /*
2637  * This is the configuration table for all of the PCI serial boards
2638  * which we support.  It is directly indexed by the pci_board_num_t enum
2639  * value, which is encoded in the pci_device_id PCI probe table's
2640  * driver_data member.
2641  *
2642  * The makeup of these names are:
2643  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2644  *
2645  *  bn          = PCI BAR number
2646  *  bt          = Index using PCI BARs
2647  *  n           = number of serial ports
2648  *  baud        = baud rate
2649  *  offsetinhex = offset for each sequential port (in hex)
2650  *
2651  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2652  *
2653  * Please note: in theory if n = 1, _bt infix should make no difference.
2654  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2655  */
2656 enum pci_board_num_t {
2657         pbn_default = 0,
2658
2659         pbn_b0_1_115200,
2660         pbn_b0_2_115200,
2661         pbn_b0_4_115200,
2662         pbn_b0_5_115200,
2663         pbn_b0_8_115200,
2664
2665         pbn_b0_1_921600,
2666         pbn_b0_2_921600,
2667         pbn_b0_4_921600,
2668
2669         pbn_b0_2_1130000,
2670
2671         pbn_b0_4_1152000,
2672
2673         pbn_b0_2_1152000_200,
2674         pbn_b0_4_1152000_200,
2675         pbn_b0_8_1152000_200,
2676
2677         pbn_b0_2_1843200,
2678         pbn_b0_4_1843200,
2679
2680         pbn_b0_2_1843200_200,
2681         pbn_b0_4_1843200_200,
2682         pbn_b0_8_1843200_200,
2683
2684         pbn_b0_1_4000000,
2685
2686         pbn_b0_bt_1_115200,
2687         pbn_b0_bt_2_115200,
2688         pbn_b0_bt_4_115200,
2689         pbn_b0_bt_8_115200,
2690
2691         pbn_b0_bt_1_460800,
2692         pbn_b0_bt_2_460800,
2693         pbn_b0_bt_4_460800,
2694
2695         pbn_b0_bt_1_921600,
2696         pbn_b0_bt_2_921600,
2697         pbn_b0_bt_4_921600,
2698         pbn_b0_bt_8_921600,
2699
2700         pbn_b1_1_115200,
2701         pbn_b1_2_115200,
2702         pbn_b1_4_115200,
2703         pbn_b1_8_115200,
2704         pbn_b1_16_115200,
2705
2706         pbn_b1_1_921600,
2707         pbn_b1_2_921600,
2708         pbn_b1_4_921600,
2709         pbn_b1_8_921600,
2710
2711         pbn_b1_2_1250000,
2712
2713         pbn_b1_bt_1_115200,
2714         pbn_b1_bt_2_115200,
2715         pbn_b1_bt_4_115200,
2716
2717         pbn_b1_bt_2_921600,
2718
2719         pbn_b1_1_1382400,
2720         pbn_b1_2_1382400,
2721         pbn_b1_4_1382400,
2722         pbn_b1_8_1382400,
2723
2724         pbn_b2_1_115200,
2725         pbn_b2_2_115200,
2726         pbn_b2_4_115200,
2727         pbn_b2_8_115200,
2728
2729         pbn_b2_1_460800,
2730         pbn_b2_4_460800,
2731         pbn_b2_8_460800,
2732         pbn_b2_16_460800,
2733
2734         pbn_b2_1_921600,
2735         pbn_b2_4_921600,
2736         pbn_b2_8_921600,
2737
2738         pbn_b2_8_1152000,
2739
2740         pbn_b2_bt_1_115200,
2741         pbn_b2_bt_2_115200,
2742         pbn_b2_bt_4_115200,
2743
2744         pbn_b2_bt_2_921600,
2745         pbn_b2_bt_4_921600,
2746
2747         pbn_b3_2_115200,
2748         pbn_b3_4_115200,
2749         pbn_b3_8_115200,
2750
2751         pbn_b4_bt_2_921600,
2752         pbn_b4_bt_4_921600,
2753         pbn_b4_bt_8_921600,
2754
2755         /*
2756          * Board-specific versions.
2757          */
2758         pbn_panacom,
2759         pbn_panacom2,
2760         pbn_panacom4,
2761         pbn_plx_romulus,
2762         pbn_oxsemi,
2763         pbn_oxsemi_1_4000000,
2764         pbn_oxsemi_2_4000000,
2765         pbn_oxsemi_4_4000000,
2766         pbn_oxsemi_8_4000000,
2767         pbn_intel_i960,
2768         pbn_sgi_ioc3,
2769         pbn_computone_4,
2770         pbn_computone_6,
2771         pbn_computone_8,
2772         pbn_sbsxrsio,
2773         pbn_exar_XR17C152,
2774         pbn_exar_XR17C154,
2775         pbn_exar_XR17C158,
2776         pbn_exar_XR17V352,
2777         pbn_exar_XR17V354,
2778         pbn_exar_XR17V358,
2779         pbn_exar_ibm_saturn,
2780         pbn_pasemi_1682M,
2781         pbn_ni8430_2,
2782         pbn_ni8430_4,
2783         pbn_ni8430_8,
2784         pbn_ni8430_16,
2785         pbn_ADDIDATA_PCIe_1_3906250,
2786         pbn_ADDIDATA_PCIe_2_3906250,
2787         pbn_ADDIDATA_PCIe_4_3906250,
2788         pbn_ADDIDATA_PCIe_8_3906250,
2789         pbn_ce4100_1_115200,
2790         pbn_byt,
2791         pbn_omegapci,
2792         pbn_NETMOS9900_2s_115200,
2793         pbn_brcm_trumanage,
2794         pbn_fintek_4,
2795         pbn_fintek_8,
2796         pbn_fintek_12,
2797 };
2798
2799 /*
2800  * uart_offset - the space between channels
2801  * reg_shift   - describes how the UART registers are mapped
2802  *               to PCI memory by the card.
2803  * For example IER register on SBS, Inc. PMC-OctPro is located at
2804  * offset 0x10 from the UART base, while UART_IER is defined as 1
2805  * in include/linux/serial_reg.h,
2806  * see first lines of serial_in() and serial_out() in 8250.c
2807 */
2808
2809 static struct pciserial_board pci_boards[] = {
2810         [pbn_default] = {
2811                 .flags          = FL_BASE0,
2812                 .num_ports      = 1,
2813                 .base_baud      = 115200,
2814                 .uart_offset    = 8,
2815         },
2816         [pbn_b0_1_115200] = {
2817                 .flags          = FL_BASE0,
2818                 .num_ports      = 1,
2819                 .base_baud      = 115200,
2820                 .uart_offset    = 8,
2821         },
2822         [pbn_b0_2_115200] = {
2823                 .flags          = FL_BASE0,
2824                 .num_ports      = 2,
2825                 .base_baud      = 115200,
2826                 .uart_offset    = 8,
2827         },
2828         [pbn_b0_4_115200] = {
2829                 .flags          = FL_BASE0,
2830                 .num_ports      = 4,
2831                 .base_baud      = 115200,
2832                 .uart_offset    = 8,
2833         },
2834         [pbn_b0_5_115200] = {
2835                 .flags          = FL_BASE0,
2836                 .num_ports      = 5,
2837                 .base_baud      = 115200,
2838                 .uart_offset    = 8,
2839         },
2840         [pbn_b0_8_115200] = {
2841                 .flags          = FL_BASE0,
2842                 .num_ports      = 8,
2843                 .base_baud      = 115200,
2844                 .uart_offset    = 8,
2845         },
2846         [pbn_b0_1_921600] = {
2847                 .flags          = FL_BASE0,
2848                 .num_ports      = 1,
2849                 .base_baud      = 921600,
2850                 .uart_offset    = 8,
2851         },
2852         [pbn_b0_2_921600] = {
2853                 .flags          = FL_BASE0,
2854                 .num_ports      = 2,
2855                 .base_baud      = 921600,
2856                 .uart_offset    = 8,
2857         },
2858         [pbn_b0_4_921600] = {
2859                 .flags          = FL_BASE0,
2860                 .num_ports      = 4,
2861                 .base_baud      = 921600,
2862                 .uart_offset    = 8,
2863         },
2864
2865         [pbn_b0_2_1130000] = {
2866                 .flags          = FL_BASE0,
2867                 .num_ports      = 2,
2868                 .base_baud      = 1130000,
2869                 .uart_offset    = 8,
2870         },
2871
2872         [pbn_b0_4_1152000] = {
2873                 .flags          = FL_BASE0,
2874                 .num_ports      = 4,
2875                 .base_baud      = 1152000,
2876                 .uart_offset    = 8,
2877         },
2878
2879         [pbn_b0_2_1152000_200] = {
2880                 .flags          = FL_BASE0,
2881                 .num_ports      = 2,
2882                 .base_baud      = 1152000,
2883                 .uart_offset    = 0x200,
2884         },
2885
2886         [pbn_b0_4_1152000_200] = {
2887                 .flags          = FL_BASE0,
2888                 .num_ports      = 4,
2889                 .base_baud      = 1152000,
2890                 .uart_offset    = 0x200,
2891         },
2892
2893         [pbn_b0_8_1152000_200] = {
2894                 .flags          = FL_BASE0,
2895                 .num_ports      = 8,
2896                 .base_baud      = 1152000,
2897                 .uart_offset    = 0x200,
2898         },
2899
2900         [pbn_b0_2_1843200] = {
2901                 .flags          = FL_BASE0,
2902                 .num_ports      = 2,
2903                 .base_baud      = 1843200,
2904                 .uart_offset    = 8,
2905         },
2906         [pbn_b0_4_1843200] = {
2907                 .flags          = FL_BASE0,
2908                 .num_ports      = 4,
2909                 .base_baud      = 1843200,
2910                 .uart_offset    = 8,
2911         },
2912
2913         [pbn_b0_2_1843200_200] = {
2914                 .flags          = FL_BASE0,
2915                 .num_ports      = 2,
2916                 .base_baud      = 1843200,
2917                 .uart_offset    = 0x200,
2918         },
2919         [pbn_b0_4_1843200_200] = {
2920                 .flags          = FL_BASE0,
2921                 .num_ports      = 4,
2922                 .base_baud      = 1843200,
2923                 .uart_offset    = 0x200,
2924         },
2925         [pbn_b0_8_1843200_200] = {
2926                 .flags          = FL_BASE0,
2927                 .num_ports      = 8,
2928                 .base_baud      = 1843200,
2929                 .uart_offset    = 0x200,
2930         },
2931         [pbn_b0_1_4000000] = {
2932                 .flags          = FL_BASE0,
2933                 .num_ports      = 1,
2934                 .base_baud      = 4000000,
2935                 .uart_offset    = 8,
2936         },
2937
2938         [pbn_b0_bt_1_115200] = {
2939                 .flags          = FL_BASE0|FL_BASE_BARS,
2940                 .num_ports      = 1,
2941                 .base_baud      = 115200,
2942                 .uart_offset    = 8,
2943         },
2944         [pbn_b0_bt_2_115200] = {
2945                 .flags          = FL_BASE0|FL_BASE_BARS,
2946                 .num_ports      = 2,
2947                 .base_baud      = 115200,
2948                 .uart_offset    = 8,
2949         },
2950         [pbn_b0_bt_4_115200] = {
2951                 .flags          = FL_BASE0|FL_BASE_BARS,
2952                 .num_ports      = 4,
2953                 .base_baud      = 115200,
2954                 .uart_offset    = 8,
2955         },
2956         [pbn_b0_bt_8_115200] = {
2957                 .flags          = FL_BASE0|FL_BASE_BARS,
2958                 .num_ports      = 8,
2959                 .base_baud      = 115200,
2960                 .uart_offset    = 8,
2961         },
2962
2963         [pbn_b0_bt_1_460800] = {
2964                 .flags          = FL_BASE0|FL_BASE_BARS,
2965                 .num_ports      = 1,
2966                 .base_baud      = 460800,
2967                 .uart_offset    = 8,
2968         },
2969         [pbn_b0_bt_2_460800] = {
2970                 .flags          = FL_BASE0|FL_BASE_BARS,
2971                 .num_ports      = 2,
2972                 .base_baud      = 460800,
2973                 .uart_offset    = 8,
2974         },
2975         [pbn_b0_bt_4_460800] = {
2976                 .flags          = FL_BASE0|FL_BASE_BARS,
2977                 .num_ports      = 4,
2978                 .base_baud      = 460800,
2979                 .uart_offset    = 8,
2980         },
2981
2982         [pbn_b0_bt_1_921600] = {
2983                 .flags          = FL_BASE0|FL_BASE_BARS,
2984                 .num_ports      = 1,
2985                 .base_baud      = 921600,
2986                 .uart_offset    = 8,
2987         },
2988         [pbn_b0_bt_2_921600] = {
2989                 .flags          = FL_BASE0|FL_BASE_BARS,
2990                 .num_ports      = 2,
2991                 .base_baud      = 921600,
2992                 .uart_offset    = 8,
2993         },
2994         [pbn_b0_bt_4_921600] = {
2995                 .flags          = FL_BASE0|FL_BASE_BARS,
2996                 .num_ports      = 4,
2997                 .base_baud      = 921600,
2998                 .uart_offset    = 8,
2999         },
3000         [pbn_b0_bt_8_921600] = {
3001                 .flags          = FL_BASE0|FL_BASE_BARS,
3002                 .num_ports      = 8,
3003                 .base_baud      = 921600,
3004                 .uart_offset    = 8,
3005         },
3006
3007         [pbn_b1_1_115200] = {
3008                 .flags          = FL_BASE1,
3009                 .num_ports      = 1,
3010                 .base_baud      = 115200,
3011                 .uart_offset    = 8,
3012         },
3013         [pbn_b1_2_115200] = {
3014                 .flags          = FL_BASE1,
3015                 .num_ports      = 2,
3016                 .base_baud      = 115200,
3017                 .uart_offset    = 8,
3018         },
3019         [pbn_b1_4_115200] = {
3020                 .flags          = FL_BASE1,
3021                 .num_ports      = 4,
3022                 .base_baud      = 115200,
3023                 .uart_offset    = 8,
3024         },
3025         [pbn_b1_8_115200] = {
3026                 .flags          = FL_BASE1,
3027                 .num_ports      = 8,
3028                 .base_baud      = 115200,
3029                 .uart_offset    = 8,
3030         },
3031         [pbn_b1_16_115200] = {
3032                 .flags          = FL_BASE1,
3033                 .num_ports      = 16,
3034                 .base_baud      = 115200,
3035                 .uart_offset    = 8,
3036         },
3037
3038         [pbn_b1_1_921600] = {
3039                 .flags          = FL_BASE1,
3040                 .num_ports      = 1,
3041                 .base_baud      = 921600,
3042                 .uart_offset    = 8,
3043         },
3044         [pbn_b1_2_921600] = {
3045                 .flags          = FL_BASE1,
3046                 .num_ports      = 2,
3047                 .base_baud      = 921600,
3048                 .uart_offset    = 8,
3049         },
3050         [pbn_b1_4_921600] = {
3051                 .flags          = FL_BASE1,
3052                 .num_ports      = 4,
3053                 .base_baud      = 921600,
3054                 .uart_offset    = 8,
3055         },
3056         [pbn_b1_8_921600] = {
3057                 .flags          = FL_BASE1,
3058                 .num_ports      = 8,
3059                 .base_baud      = 921600,
3060                 .uart_offset    = 8,
3061         },
3062         [pbn_b1_2_1250000] = {
3063                 .flags          = FL_BASE1,
3064                 .num_ports      = 2,
3065                 .base_baud      = 1250000,
3066                 .uart_offset    = 8,
3067         },
3068
3069         [pbn_b1_bt_1_115200] = {
3070                 .flags          = FL_BASE1|FL_BASE_BARS,
3071                 .num_ports      = 1,
3072                 .base_baud      = 115200,
3073                 .uart_offset    = 8,
3074         },
3075         [pbn_b1_bt_2_115200] = {
3076                 .flags          = FL_BASE1|FL_BASE_BARS,
3077                 .num_ports      = 2,
3078                 .base_baud      = 115200,
3079                 .uart_offset    = 8,
3080         },
3081         [pbn_b1_bt_4_115200] = {
3082                 .flags          = FL_BASE1|FL_BASE_BARS,
3083                 .num_ports      = 4,
3084                 .base_baud      = 115200,
3085                 .uart_offset    = 8,
3086         },
3087
3088         [pbn_b1_bt_2_921600] = {
3089                 .flags          = FL_BASE1|FL_BASE_BARS,
3090                 .num_ports      = 2,
3091                 .base_baud      = 921600,
3092                 .uart_offset    = 8,
3093         },
3094
3095         [pbn_b1_1_1382400] = {
3096                 .flags          = FL_BASE1,
3097                 .num_ports      = 1,
3098                 .base_baud      = 1382400,
3099                 .uart_offset    = 8,
3100         },
3101         [pbn_b1_2_1382400] = {
3102                 .flags          = FL_BASE1,
3103                 .num_ports      = 2,
3104                 .base_baud      = 1382400,
3105                 .uart_offset    = 8,
3106         },
3107         [pbn_b1_4_1382400] = {
3108                 .flags          = FL_BASE1,
3109                 .num_ports      = 4,
3110                 .base_baud      = 1382400,
3111                 .uart_offset    = 8,
3112         },
3113         [pbn_b1_8_1382400] = {
3114                 .flags          = FL_BASE1,
3115                 .num_ports      = 8,
3116                 .base_baud      = 1382400,
3117                 .uart_offset    = 8,
3118         },
3119
3120         [pbn_b2_1_115200] = {
3121                 .flags          = FL_BASE2,
3122                 .num_ports      = 1,
3123                 .base_baud      = 115200,
3124                 .uart_offset    = 8,
3125         },
3126         [pbn_b2_2_115200] = {
3127                 .flags          = FL_BASE2,
3128                 .num_ports      = 2,
3129                 .base_baud      = 115200,
3130                 .uart_offset    = 8,
3131         },
3132         [pbn_b2_4_115200] = {
3133                 .flags          = FL_BASE2,
3134                 .num_ports      = 4,
3135                 .base_baud      = 115200,
3136                 .uart_offset    = 8,
3137         },
3138         [pbn_b2_8_115200] = {
3139                 .flags          = FL_BASE2,
3140                 .num_ports      = 8,
3141                 .base_baud      = 115200,
3142                 .uart_offset    = 8,
3143         },
3144
3145         [pbn_b2_1_460800] = {
3146                 .flags          = FL_BASE2,
3147                 .num_ports      = 1,
3148                 .base_baud      = 460800,
3149                 .uart_offset    = 8,
3150         },
3151         [pbn_b2_4_460800] = {
3152                 .flags          = FL_BASE2,
3153                 .num_ports      = 4,
3154                 .base_baud      = 460800,
3155                 .uart_offset    = 8,
3156         },
3157         [pbn_b2_8_460800] = {
3158                 .flags          = FL_BASE2,
3159                 .num_ports      = 8,
3160                 .base_baud      = 460800,
3161                 .uart_offset    = 8,
3162         },
3163         [pbn_b2_16_460800] = {
3164                 .flags          = FL_BASE2,
3165                 .num_ports      = 16,
3166                 .base_baud      = 460800,
3167                 .uart_offset    = 8,
3168          },
3169
3170         [pbn_b2_1_921600] = {
3171                 .flags          = FL_BASE2,
3172                 .num_ports      = 1,
3173                 .base_baud      = 921600,
3174                 .uart_offset    = 8,
3175         },
3176         [pbn_b2_4_921600] = {
3177                 .flags          = FL_BASE2,
3178                 .num_ports      = 4,
3179                 .base_baud      = 921600,
3180                 .uart_offset    = 8,
3181         },
3182         [pbn_b2_8_921600] = {
3183                 .flags          = FL_BASE2,
3184                 .num_ports      = 8,
3185                 .base_baud      = 921600,
3186                 .uart_offset    = 8,
3187         },
3188
3189         [pbn_b2_8_1152000] = {
3190                 .flags          = FL_BASE2,
3191                 .num_ports      = 8,
3192                 .base_baud      = 1152000,
3193                 .uart_offset    = 8,
3194         },
3195
3196         [pbn_b2_bt_1_115200] = {
3197                 .flags          = FL_BASE2|FL_BASE_BARS,
3198                 .num_ports      = 1,
3199                 .base_baud      = 115200,
3200                 .uart_offset    = 8,
3201         },
3202         [pbn_b2_bt_2_115200] = {
3203                 .flags          = FL_BASE2|FL_BASE_BARS,
3204                 .num_ports      = 2,
3205                 .base_baud      = 115200,
3206                 .uart_offset    = 8,
3207         },
3208         [pbn_b2_bt_4_115200] = {
3209                 .flags          = FL_BASE2|FL_BASE_BARS,
3210                 .num_ports      = 4,
3211                 .base_baud      = 115200,
3212                 .uart_offset    = 8,
3213         },
3214
3215         [pbn_b2_bt_2_921600] = {
3216                 .flags          = FL_BASE2|FL_BASE_BARS,
3217                 .num_ports      = 2,
3218                 .base_baud      = 921600,
3219                 .uart_offset    = 8,
3220         },
3221         [pbn_b2_bt_4_921600] = {
3222                 .flags          = FL_BASE2|FL_BASE_BARS,
3223                 .num_ports      = 4,
3224                 .base_baud      = 921600,
3225                 .uart_offset    = 8,
3226         },
3227
3228         [pbn_b3_2_115200] = {
3229                 .flags          = FL_BASE3,
3230                 .num_ports      = 2,
3231                 .base_baud      = 115200,
3232                 .uart_offset    = 8,
3233         },
3234         [pbn_b3_4_115200] = {
3235                 .flags          = FL_BASE3,
3236                 .num_ports      = 4,
3237                 .base_baud      = 115200,
3238                 .uart_offset    = 8,
3239         },
3240         [pbn_b3_8_115200] = {
3241                 .flags          = FL_BASE3,
3242                 .num_ports      = 8,
3243                 .base_baud      = 115200,
3244                 .uart_offset    = 8,
3245         },
3246
3247         [pbn_b4_bt_2_921600] = {
3248                 .flags          = FL_BASE4,
3249                 .num_ports      = 2,
3250                 .base_baud      = 921600,
3251                 .uart_offset    = 8,
3252         },
3253         [pbn_b4_bt_4_921600] = {
3254                 .flags          = FL_BASE4,
3255                 .num_ports      = 4,
3256                 .base_baud      = 921600,
3257                 .uart_offset    = 8,
3258         },
3259         [pbn_b4_bt_8_921600] = {
3260                 .flags          = FL_BASE4,
3261                 .num_ports      = 8,
3262                 .base_baud      = 921600,
3263                 .uart_offset    = 8,
3264         },
3265
3266         /*
3267          * Entries following this are board-specific.
3268          */
3269
3270         /*
3271          * Panacom - IOMEM
3272          */
3273         [pbn_panacom] = {
3274                 .flags          = FL_BASE2,
3275                 .num_ports      = 2,
3276                 .base_baud      = 921600,
3277                 .uart_offset    = 0x400,
3278                 .reg_shift      = 7,
3279         },
3280         [pbn_panacom2] = {
3281                 .flags          = FL_BASE2|FL_BASE_BARS,
3282                 .num_ports      = 2,
3283                 .base_baud      = 921600,
3284                 .uart_offset    = 0x400,
3285                 .reg_shift      = 7,
3286         },
3287         [pbn_panacom4] = {
3288                 .flags          = FL_BASE2|FL_BASE_BARS,
3289                 .num_ports      = 4,
3290                 .base_baud      = 921600,
3291                 .uart_offset    = 0x400,
3292                 .reg_shift      = 7,
3293         },
3294
3295         /* I think this entry is broken - the first_offset looks wrong --rmk */
3296         [pbn_plx_romulus] = {
3297                 .flags          = FL_BASE2,
3298                 .num_ports      = 4,
3299                 .base_baud      = 921600,
3300                 .uart_offset    = 8 << 2,
3301                 .reg_shift      = 2,
3302                 .first_offset   = 0x03,
3303         },
3304
3305         /*
3306          * This board uses the size of PCI Base region 0 to
3307          * signal now many ports are available
3308          */
3309         [pbn_oxsemi] = {
3310                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3311                 .num_ports      = 32,
3312                 .base_baud      = 115200,
3313                 .uart_offset    = 8,
3314         },
3315         [pbn_oxsemi_1_4000000] = {
3316                 .flags          = FL_BASE0,
3317                 .num_ports      = 1,
3318                 .base_baud      = 4000000,
3319                 .uart_offset    = 0x200,
3320                 .first_offset   = 0x1000,
3321         },
3322         [pbn_oxsemi_2_4000000] = {
3323                 .flags          = FL_BASE0,
3324                 .num_ports      = 2,
3325                 .base_baud      = 4000000,
3326                 .uart_offset    = 0x200,
3327                 .first_offset   = 0x1000,
3328         },
3329         [pbn_oxsemi_4_4000000] = {
3330                 .flags          = FL_BASE0,
3331                 .num_ports      = 4,
3332                 .base_baud      = 4000000,
3333                 .uart_offset    = 0x200,
3334                 .first_offset   = 0x1000,
3335         },
3336         [pbn_oxsemi_8_4000000] = {
3337                 .flags          = FL_BASE0,
3338                 .num_ports      = 8,
3339                 .base_baud      = 4000000,
3340                 .uart_offset    = 0x200,
3341                 .first_offset   = 0x1000,
3342         },
3343
3344
3345         /*
3346          * EKF addition for i960 Boards form EKF with serial port.
3347          * Max 256 ports.
3348          */
3349         [pbn_intel_i960] = {
3350                 .flags          = FL_BASE0,
3351                 .num_ports      = 32,
3352                 .base_baud      = 921600,
3353                 .uart_offset    = 8 << 2,
3354                 .reg_shift      = 2,
3355                 .first_offset   = 0x10000,
3356         },
3357         [pbn_sgi_ioc3] = {
3358                 .flags          = FL_BASE0|FL_NOIRQ,
3359                 .num_ports      = 1,
3360                 .base_baud      = 458333,
3361                 .uart_offset    = 8,
3362                 .reg_shift      = 0,
3363                 .first_offset   = 0x20178,
3364         },
3365
3366         /*
3367          * Computone - uses IOMEM.
3368          */
3369         [pbn_computone_4] = {
3370                 .flags          = FL_BASE0,
3371                 .num_ports      = 4,
3372                 .base_baud      = 921600,
3373                 .uart_offset    = 0x40,
3374                 .reg_shift      = 2,
3375                 .first_offset   = 0x200,
3376         },
3377         [pbn_computone_6] = {
3378                 .flags          = FL_BASE0,
3379                 .num_ports      = 6,
3380                 .base_baud      = 921600,
3381                 .uart_offset    = 0x40,
3382                 .reg_shift      = 2,
3383                 .first_offset   = 0x200,
3384         },
3385         [pbn_computone_8] = {
3386                 .flags          = FL_BASE0,
3387                 .num_ports      = 8,
3388                 .base_baud      = 921600,
3389                 .uart_offset    = 0x40,
3390                 .reg_shift      = 2,
3391                 .first_offset   = 0x200,
3392         },
3393         [pbn_sbsxrsio] = {
3394                 .flags          = FL_BASE0,
3395                 .num_ports      = 8,
3396                 .base_baud      = 460800,
3397                 .uart_offset    = 256,
3398                 .reg_shift      = 4,
3399         },
3400         /*
3401          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3402          *  Only basic 16550A support.
3403          *  XR17C15[24] are not tested, but they should work.
3404          */
3405         [pbn_exar_XR17C152] = {
3406                 .flags          = FL_BASE0,
3407                 .num_ports      = 2,
3408                 .base_baud      = 921600,
3409                 .uart_offset    = 0x200,
3410         },
3411         [pbn_exar_XR17C154] = {
3412                 .flags          = FL_BASE0,
3413                 .num_ports      = 4,
3414                 .base_baud      = 921600,
3415                 .uart_offset    = 0x200,
3416         },
3417         [pbn_exar_XR17C158] = {
3418                 .flags          = FL_BASE0,
3419                 .num_ports      = 8,
3420                 .base_baud      = 921600,
3421                 .uart_offset    = 0x200,
3422         },
3423         [pbn_exar_XR17V352] = {
3424                 .flags          = FL_BASE0,
3425                 .num_ports      = 2,
3426                 .base_baud      = 7812500,
3427                 .uart_offset    = 0x400,
3428                 .reg_shift      = 0,
3429                 .first_offset   = 0,
3430         },
3431         [pbn_exar_XR17V354] = {
3432                 .flags          = FL_BASE0,
3433                 .num_ports      = 4,
3434                 .base_baud      = 7812500,
3435                 .uart_offset    = 0x400,
3436                 .reg_shift      = 0,
3437                 .first_offset   = 0,
3438         },
3439         [pbn_exar_XR17V358] = {
3440                 .flags          = FL_BASE0,
3441                 .num_ports      = 8,
3442                 .base_baud      = 7812500,
3443                 .uart_offset    = 0x400,
3444                 .reg_shift      = 0,
3445                 .first_offset   = 0,
3446         },
3447         [pbn_exar_ibm_saturn] = {
3448                 .flags          = FL_BASE0,
3449                 .num_ports      = 1,
3450                 .base_baud      = 921600,
3451                 .uart_offset    = 0x200,
3452         },
3453
3454         /*
3455          * PA Semi PWRficient PA6T-1682M on-chip UART
3456          */
3457         [pbn_pasemi_1682M] = {
3458                 .flags          = FL_BASE0,
3459                 .num_ports      = 1,
3460                 .base_baud      = 8333333,
3461         },
3462         /*
3463          * National Instruments 843x
3464          */
3465         [pbn_ni8430_16] = {
3466                 .flags          = FL_BASE0,
3467                 .num_ports      = 16,
3468                 .base_baud      = 3686400,
3469                 .uart_offset    = 0x10,
3470                 .first_offset   = 0x800,
3471         },
3472         [pbn_ni8430_8] = {
3473                 .flags          = FL_BASE0,
3474                 .num_ports      = 8,
3475                 .base_baud      = 3686400,
3476                 .uart_offset    = 0x10,
3477                 .first_offset   = 0x800,
3478         },
3479         [pbn_ni8430_4] = {
3480                 .flags          = FL_BASE0,
3481                 .num_ports      = 4,
3482                 .base_baud      = 3686400,
3483                 .uart_offset    = 0x10,
3484                 .first_offset   = 0x800,
3485         },
3486         [pbn_ni8430_2] = {
3487                 .flags          = FL_BASE0,
3488                 .num_ports      = 2,
3489                 .base_baud      = 3686400,
3490                 .uart_offset    = 0x10,
3491                 .first_offset   = 0x800,
3492         },
3493         /*
3494          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3495          */
3496         [pbn_ADDIDATA_PCIe_1_3906250] = {
3497                 .flags          = FL_BASE0,
3498                 .num_ports      = 1,
3499                 .base_baud      = 3906250,
3500                 .uart_offset    = 0x200,
3501                 .first_offset   = 0x1000,
3502         },
3503         [pbn_ADDIDATA_PCIe_2_3906250] = {
3504                 .flags          = FL_BASE0,
3505                 .num_ports      = 2,
3506                 .base_baud      = 3906250,
3507                 .uart_offset    = 0x200,
3508                 .first_offset   = 0x1000,
3509         },
3510         [pbn_ADDIDATA_PCIe_4_3906250] = {
3511                 .flags          = FL_BASE0,
3512                 .num_ports      = 4,
3513                 .base_baud      = 3906250,
3514                 .uart_offset    = 0x200,
3515                 .first_offset   = 0x1000,
3516         },
3517         [pbn_ADDIDATA_PCIe_8_3906250] = {
3518                 .flags          = FL_BASE0,
3519                 .num_ports      = 8,
3520                 .base_baud      = 3906250,
3521                 .uart_offset    = 0x200,
3522                 .first_offset   = 0x1000,
3523         },
3524         [pbn_ce4100_1_115200] = {
3525                 .flags          = FL_BASE_BARS,
3526                 .num_ports      = 2,
3527                 .base_baud      = 921600,
3528                 .reg_shift      = 2,
3529         },
3530         /*
3531          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3532          * but is overridden by byt_set_termios.
3533          */
3534         [pbn_byt] = {
3535                 .flags          = FL_BASE0,
3536                 .num_ports      = 1,
3537                 .base_baud      = 2764800,
3538                 .uart_offset    = 0x80,
3539                 .reg_shift      = 2,
3540         },
3541         [pbn_omegapci] = {
3542                 .flags          = FL_BASE0,
3543                 .num_ports      = 8,
3544                 .base_baud      = 115200,
3545                 .uart_offset    = 0x200,
3546         },
3547         [pbn_NETMOS9900_2s_115200] = {
3548                 .flags          = FL_BASE0,
3549                 .num_ports      = 2,
3550                 .base_baud      = 115200,
3551         },
3552         [pbn_brcm_trumanage] = {
3553                 .flags          = FL_BASE0,
3554                 .num_ports      = 1,
3555                 .reg_shift      = 2,
3556                 .base_baud      = 115200,
3557         },
3558         [pbn_fintek_4] = {
3559                 .num_ports      = 4,
3560                 .uart_offset    = 8,
3561                 .base_baud      = 115200,
3562                 .first_offset   = 0x40,
3563         },
3564         [pbn_fintek_8] = {
3565                 .num_ports      = 8,
3566                 .uart_offset    = 8,
3567                 .base_baud      = 115200,
3568                 .first_offset   = 0x40,
3569         },
3570         [pbn_fintek_12] = {
3571                 .num_ports      = 12,
3572                 .uart_offset    = 8,
3573                 .base_baud      = 115200,
3574                 .first_offset   = 0x40,
3575         },
3576 };
3577
3578 static const struct pci_device_id blacklist[] = {
3579         /* softmodems */
3580         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3581         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3582         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3583
3584         /* multi-io cards handled by parport_serial */
3585         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3586         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3587 };
3588
3589 /*
3590  * Given a complete unknown PCI device, try to use some heuristics to
3591  * guess what the configuration might be, based on the pitiful PCI
3592  * serial specs.  Returns 0 on success, 1 on failure.
3593  */
3594 static int
3595 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3596 {
3597         const struct pci_device_id *bldev;
3598         int num_iomem, num_port, first_port = -1, i;
3599
3600         /*
3601          * If it is not a communications device or the programming
3602          * interface is greater than 6, give up.
3603          *
3604          * (Should we try to make guesses for multiport serial devices
3605          * later?)
3606          */
3607         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3608              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3609             (dev->class & 0xff) > 6)
3610                 return -ENODEV;
3611
3612         /*
3613          * Do not access blacklisted devices that are known not to
3614          * feature serial ports or are handled by other modules.
3615          */
3616         for (bldev = blacklist;
3617              bldev < blacklist + ARRAY_SIZE(blacklist);
3618              bldev++) {
3619                 if (dev->vendor == bldev->vendor &&
3620                     dev->device == bldev->device)
3621                         return -ENODEV;
3622         }
3623
3624         num_iomem = num_port = 0;
3625         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3626                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3627                         num_port++;
3628                         if (first_port == -1)
3629                                 first_port = i;
3630                 }
3631                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3632                         num_iomem++;
3633         }
3634
3635         /*
3636          * If there is 1 or 0 iomem regions, and exactly one port,
3637          * use it.  We guess the number of ports based on the IO
3638          * region size.
3639          */
3640         if (num_iomem <= 1 && num_port == 1) {
3641                 board->flags = first_port;
3642                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3643                 return 0;
3644         }
3645
3646         /*
3647          * Now guess if we've got a board which indexes by BARs.
3648          * Each IO BAR should be 8 bytes, and they should follow
3649          * consecutively.
3650          */
3651         first_port = -1;
3652         num_port = 0;
3653         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3654                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3655                     pci_resource_len(dev, i) == 8 &&
3656                     (first_port == -1 || (first_port + num_port) == i)) {
3657                         num_port++;
3658                         if (first_port == -1)
3659                                 first_port = i;
3660                 }
3661         }
3662
3663         if (num_port > 1) {
3664                 board->flags = first_port | FL_BASE_BARS;
3665                 board->num_ports = num_port;
3666                 return 0;
3667         }
3668
3669         return -ENODEV;
3670 }
3671
3672 static inline int
3673 serial_pci_matches(const struct pciserial_board *board,
3674                    const struct pciserial_board *guessed)
3675 {
3676         return
3677             board->num_ports == guessed->num_ports &&
3678             board->base_baud == guessed->base_baud &&
3679             board->uart_offset == guessed->uart_offset &&
3680             board->reg_shift == guessed->reg_shift &&
3681             board->first_offset == guessed->first_offset;
3682 }
3683
3684 struct serial_private *
3685 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3686 {
3687         struct uart_8250_port uart;
3688         struct serial_private *priv;
3689         struct pci_serial_quirk *quirk;
3690         int rc, nr_ports, i;
3691
3692         nr_ports = board->num_ports;
3693
3694         /*
3695          * Find an init and setup quirks.
3696          */
3697         quirk = find_quirk(dev);
3698
3699         /*
3700          * Run the new-style initialization function.
3701          * The initialization function returns:
3702          *  <0  - error
3703          *   0  - use board->num_ports
3704          *  >0  - number of ports
3705          */
3706         if (quirk->init) {
3707                 rc = quirk->init(dev);
3708                 if (rc < 0) {
3709                         priv = ERR_PTR(rc);
3710                         goto err_out;
3711                 }
3712                 if (rc)
3713                         nr_ports = rc;
3714         }
3715
3716         priv = kzalloc(sizeof(struct serial_private) +
3717                        sizeof(unsigned int) * nr_ports,
3718                        GFP_KERNEL);
3719         if (!priv) {
3720                 priv = ERR_PTR(-ENOMEM);
3721                 goto err_deinit;
3722         }
3723
3724         priv->dev = dev;
3725         priv->quirk = quirk;
3726
3727         memset(&uart, 0, sizeof(uart));
3728         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3729         uart.port.uartclk = board->base_baud * 16;
3730         uart.port.irq = get_pci_irq(dev, board);
3731         uart.port.dev = &dev->dev;
3732
3733         for (i = 0; i < nr_ports; i++) {
3734                 if (quirk->setup(priv, board, &uart, i))
3735                         break;
3736
3737                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3738                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3739
3740                 priv->line[i] = serial8250_register_8250_port(&uart);
3741                 if (priv->line[i] < 0) {
3742                         dev_err(&dev->dev,
3743                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3744                                 uart.port.iobase, uart.port.irq,
3745                                 uart.port.iotype, priv->line[i]);
3746                         break;
3747                 }
3748         }
3749         priv->nr = i;
3750         return priv;
3751
3752 err_deinit:
3753         if (quirk->exit)
3754                 quirk->exit(dev);
3755 err_out:
3756         return priv;
3757 }
3758 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3759
3760 void pciserial_remove_ports(struct serial_private *priv)
3761 {
3762         struct pci_serial_quirk *quirk;
3763         int i;
3764
3765         for (i = 0; i < priv->nr; i++)
3766                 serial8250_unregister_port(priv->line[i]);
3767
3768         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3769                 if (priv->remapped_bar[i])
3770                         iounmap(priv->remapped_bar[i]);
3771                 priv->remapped_bar[i] = NULL;
3772         }
3773
3774         /*
3775          * Find the exit quirks.
3776          */
3777         quirk = find_quirk(priv->dev);
3778         if (quirk->exit)
3779                 quirk->exit(priv->dev);
3780
3781         kfree(priv);
3782 }
3783 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3784
3785 void pciserial_suspend_ports(struct serial_private *priv)
3786 {
3787         int i;
3788
3789         for (i = 0; i < priv->nr; i++)
3790                 if (priv->line[i] >= 0)
3791                         serial8250_suspend_port(priv->line[i]);
3792
3793         /*
3794          * Ensure that every init quirk is properly torn down
3795          */
3796         if (priv->quirk->exit)
3797                 priv->quirk->exit(priv->dev);
3798 }
3799 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3800
3801 void pciserial_resume_ports(struct serial_private *priv)
3802 {
3803         int i;
3804
3805         /*
3806          * Ensure that the board is correctly configured.
3807          */
3808         if (priv->quirk->init)
3809                 priv->quirk->init(priv->dev);
3810
3811         for (i = 0; i < priv->nr; i++)
3812                 if (priv->line[i] >= 0)
3813                         serial8250_resume_port(priv->line[i]);
3814 }
3815 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3816
3817 /*
3818  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
3819  * to the arrangement of serial ports on a PCI card.
3820  */
3821 static int
3822 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3823 {
3824         struct pci_serial_quirk *quirk;
3825         struct serial_private *priv;
3826         const struct pciserial_board *board;
3827         struct pciserial_board tmp;
3828         int rc;
3829
3830         quirk = find_quirk(dev);
3831         if (quirk->probe) {
3832                 rc = quirk->probe(dev);
3833                 if (rc)
3834                         return rc;
3835         }
3836
3837         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3838                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3839                         ent->driver_data);
3840                 return -EINVAL;
3841         }
3842
3843         board = &pci_boards[ent->driver_data];
3844
3845         rc = pci_enable_device(dev);
3846         pci_save_state(dev);
3847         if (rc)
3848                 return rc;
3849
3850         if (ent->driver_data == pbn_default) {
3851                 /*
3852                  * Use a copy of the pci_board entry for this;
3853                  * avoid changing entries in the table.
3854                  */
3855                 memcpy(&tmp, board, sizeof(struct pciserial_board));
3856                 board = &tmp;
3857
3858                 /*
3859                  * We matched one of our class entries.  Try to
3860                  * determine the parameters of this board.
3861                  */
3862                 rc = serial_pci_guess_board(dev, &tmp);
3863                 if (rc)
3864                         goto disable;
3865         } else {
3866                 /*
3867                  * We matched an explicit entry.  If we are able to
3868                  * detect this boards settings with our heuristic,
3869                  * then we no longer need this entry.
3870                  */
3871                 memcpy(&tmp, &pci_boards[pbn_default],
3872                        sizeof(struct pciserial_board));
3873                 rc = serial_pci_guess_board(dev, &tmp);
3874                 if (rc == 0 && serial_pci_matches(board, &tmp))
3875                         moan_device("Redundant entry in serial pci_table.",
3876                                     dev);
3877         }
3878
3879         priv = pciserial_init_ports(dev, board);
3880         if (!IS_ERR(priv)) {
3881                 pci_set_drvdata(dev, priv);
3882                 return 0;
3883         }
3884
3885         rc = PTR_ERR(priv);
3886
3887  disable:
3888         pci_disable_device(dev);
3889         return rc;
3890 }
3891
3892 static void pciserial_remove_one(struct pci_dev *dev)
3893 {
3894         struct serial_private *priv = pci_get_drvdata(dev);
3895
3896         pciserial_remove_ports(priv);
3897
3898         pci_disable_device(dev);
3899 }
3900
3901 #ifdef CONFIG_PM
3902 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3903 {
3904         struct serial_private *priv = pci_get_drvdata(dev);
3905
3906         if (priv)
3907                 pciserial_suspend_ports(priv);
3908
3909         pci_save_state(dev);
3910         pci_set_power_state(dev, pci_choose_state(dev, state));
3911         return 0;
3912 }
3913
3914 static int pciserial_resume_one(struct pci_dev *dev)
3915 {
3916         int err;
3917         struct serial_private *priv = pci_get_drvdata(dev);
3918
3919         pci_set_power_state(dev, PCI_D0);
3920         pci_restore_state(dev);
3921
3922         if (priv) {
3923                 /*
3924                  * The device may have been disabled.  Re-enable it.
3925                  */
3926                 err = pci_enable_device(dev);
3927                 /* FIXME: We cannot simply error out here */
3928                 if (err)
3929                         dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
3930                 pciserial_resume_ports(priv);
3931         }
3932         return 0;
3933 }
3934 #endif
3935
3936 static struct pci_device_id serial_pci_tbl[] = {
3937         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3938         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3939                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3940                 pbn_b2_8_921600 },
3941         /* Advantech also use 0x3618 and 0xf618 */
3942         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3943                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3944                 pbn_b0_4_921600 },
3945         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3946                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3947                 pbn_b0_4_921600 },
3948         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3949                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3950                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3951                 pbn_b1_8_1382400 },
3952         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3953                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3954                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3955                 pbn_b1_4_1382400 },
3956         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3957                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3958                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3959                 pbn_b1_2_1382400 },
3960         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3961                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3962                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3963                 pbn_b1_8_1382400 },
3964         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3965                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3966                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3967                 pbn_b1_4_1382400 },
3968         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3969                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3970                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3971                 pbn_b1_2_1382400 },
3972         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3973                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3974                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3975                 pbn_b1_8_921600 },
3976         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3977                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3978                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3979                 pbn_b1_8_921600 },
3980         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3981                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3982                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3983                 pbn_b1_4_921600 },
3984         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3985                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3986                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3987                 pbn_b1_4_921600 },
3988         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3989                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3990                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3991                 pbn_b1_2_921600 },
3992         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3993                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3994                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3995                 pbn_b1_8_921600 },
3996         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3997                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3998                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3999                 pbn_b1_8_921600 },
4000         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4001                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4002                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4003                 pbn_b1_4_921600 },
4004         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4005                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4006                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4007                 pbn_b1_2_1250000 },
4008         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4009                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4010                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4011                 pbn_b0_2_1843200 },
4012         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4013                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4014                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4015                 pbn_b0_4_1843200 },
4016         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4017                 PCI_VENDOR_ID_AFAVLAB,
4018                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4019                 pbn_b0_4_1152000 },
4020         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4021                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4022                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4023                 pbn_b0_2_1843200_200 },
4024         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4025                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4026                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4027                 pbn_b0_4_1843200_200 },
4028         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4029                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4030                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4031                 pbn_b0_8_1843200_200 },
4032         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4033                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4034                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4035                 pbn_b0_2_1843200_200 },
4036         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4037                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4038                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4039                 pbn_b0_4_1843200_200 },
4040         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4041                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4042                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4043                 pbn_b0_8_1843200_200 },
4044         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4045                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4046                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4047                 pbn_b0_2_1843200_200 },
4048         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4049                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4050                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4051                 pbn_b0_4_1843200_200 },
4052         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4053                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4054                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4055                 pbn_b0_8_1843200_200 },
4056         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4057                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4058                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4059                 pbn_b0_2_1843200_200 },
4060         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4061                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4062                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4063                 pbn_b0_4_1843200_200 },
4064         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4065                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4066                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4067                 pbn_b0_8_1843200_200 },
4068         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4069                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4070                 0, 0, pbn_exar_ibm_saturn },
4071
4072         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4073                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4074                 pbn_b2_bt_1_115200 },
4075         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4077                 pbn_b2_bt_2_115200 },
4078         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4080                 pbn_b2_bt_4_115200 },
4081         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083                 pbn_b2_bt_2_115200 },
4084         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4086                 pbn_b2_bt_4_115200 },
4087         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4089                 pbn_b2_8_115200 },
4090         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4092                 pbn_b2_8_460800 },
4093         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4095                 pbn_b2_8_115200 },
4096
4097         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4099                 pbn_b2_bt_2_115200 },
4100         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4101                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4102                 pbn_b2_bt_2_921600 },
4103         /*
4104          * VScom SPCOM800, from sl@s.pl
4105          */
4106         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4107                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4108                 pbn_b2_8_921600 },
4109         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4110                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4111                 pbn_b2_4_921600 },
4112         /* Unknown card - subdevice 0x1584 */
4113         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4114                 PCI_VENDOR_ID_PLX,
4115                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4116                 pbn_b2_4_115200 },
4117         /* Unknown card - subdevice 0x1588 */
4118         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4119                 PCI_VENDOR_ID_PLX,
4120                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4121                 pbn_b2_8_115200 },
4122         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4123                 PCI_SUBVENDOR_ID_KEYSPAN,
4124                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4125                 pbn_panacom },
4126         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128                 pbn_panacom4 },
4129         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4130                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131                 pbn_panacom2 },
4132         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4133                 PCI_VENDOR_ID_ESDGMBH,
4134                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4135                 pbn_b2_4_115200 },
4136         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4137                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4138                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4139                 pbn_b2_4_460800 },
4140         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4141                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4142                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4143                 pbn_b2_8_460800 },
4144         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4145                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4146                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4147                 pbn_b2_16_460800 },
4148         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4149                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4150                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4151                 pbn_b2_16_460800 },
4152         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4153                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4154                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4155                 pbn_b2_4_460800 },
4156         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4157                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4158                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4159                 pbn_b2_8_460800 },
4160         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4161                 PCI_SUBVENDOR_ID_EXSYS,
4162                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4163                 pbn_b2_4_115200 },
4164         /*
4165          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4166          * (Exoray@isys.ca)
4167          */
4168         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4169                 0x10b5, 0x106a, 0, 0,
4170                 pbn_plx_romulus },
4171         /*
4172          * Quatech cards. These actually have configurable clocks but for
4173          * now we just use the default.
4174          *
4175          * 100 series are RS232, 200 series RS422,
4176          */
4177         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179                 pbn_b1_4_115200 },
4180         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182                 pbn_b1_2_115200 },
4183         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4184                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4185                 pbn_b2_2_115200 },
4186         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4187                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4188                 pbn_b1_2_115200 },
4189         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4190                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4191                 pbn_b2_2_115200 },
4192         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4193                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4194                 pbn_b1_4_115200 },
4195         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4196                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4197                 pbn_b1_8_115200 },
4198         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4199                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4200                 pbn_b1_8_115200 },
4201         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4202                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4203                 pbn_b1_4_115200 },
4204         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4206                 pbn_b1_2_115200 },
4207         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4209                 pbn_b1_4_115200 },
4210         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4211                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4212                 pbn_b1_2_115200 },
4213         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4214                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215                 pbn_b2_4_115200 },
4216         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4217                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4218                 pbn_b2_2_115200 },
4219         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4220                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4221                 pbn_b2_1_115200 },
4222         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4223                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224                 pbn_b2_4_115200 },
4225         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4226                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4227                 pbn_b2_2_115200 },
4228         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4230                 pbn_b2_1_115200 },
4231         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4233                 pbn_b0_8_115200 },
4234
4235         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4236                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4237                 0, 0,
4238                 pbn_b0_4_921600 },
4239         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4240                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4241                 0, 0,
4242                 pbn_b0_4_1152000 },
4243         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4245                 pbn_b0_bt_2_921600 },
4246
4247                 /*
4248                  * The below card is a little controversial since it is the
4249                  * subject of a PCI vendor/device ID clash.  (See
4250                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4251                  * For now just used the hex ID 0x950a.
4252                  */
4253         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4254                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4255                 0, 0, pbn_b0_2_115200 },
4256         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4257                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4258                 0, 0, pbn_b0_2_115200 },
4259         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261                 pbn_b0_2_1130000 },
4262         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4263                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4264                 pbn_b0_1_921600 },
4265         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267                 pbn_b0_4_115200 },
4268         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270                 pbn_b0_bt_2_921600 },
4271         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4272                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4273                 pbn_b2_8_1152000 },
4274
4275         /*
4276          * Oxford Semiconductor Inc. Tornado PCI express device range.
4277          */
4278         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4279                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280                 pbn_b0_1_4000000 },
4281         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4282                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4283                 pbn_b0_1_4000000 },
4284         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4285                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286                 pbn_oxsemi_1_4000000 },
4287         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4288                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289                 pbn_oxsemi_1_4000000 },
4290         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292                 pbn_b0_1_4000000 },
4293         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4294                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4295                 pbn_b0_1_4000000 },
4296         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4297                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298                 pbn_oxsemi_1_4000000 },
4299         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4300                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301                 pbn_oxsemi_1_4000000 },
4302         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4303                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4304                 pbn_b0_1_4000000 },
4305         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307                 pbn_b0_1_4000000 },
4308         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4309                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4310                 pbn_b0_1_4000000 },
4311         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4312                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4313                 pbn_b0_1_4000000 },
4314         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4315                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316                 pbn_oxsemi_2_4000000 },
4317         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319                 pbn_oxsemi_2_4000000 },
4320         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322                 pbn_oxsemi_4_4000000 },
4323         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325                 pbn_oxsemi_4_4000000 },
4326         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328                 pbn_oxsemi_8_4000000 },
4329         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331                 pbn_oxsemi_8_4000000 },
4332         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334                 pbn_oxsemi_1_4000000 },
4335         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4337                 pbn_oxsemi_1_4000000 },
4338         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340                 pbn_oxsemi_1_4000000 },
4341         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4342                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4343                 pbn_oxsemi_1_4000000 },
4344         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4346                 pbn_oxsemi_1_4000000 },
4347         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4348                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4349                 pbn_oxsemi_1_4000000 },
4350         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4351                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4352                 pbn_oxsemi_1_4000000 },
4353         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4354                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355                 pbn_oxsemi_1_4000000 },
4356         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4357                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4358                 pbn_oxsemi_1_4000000 },
4359         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4361                 pbn_oxsemi_1_4000000 },
4362         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364                 pbn_oxsemi_1_4000000 },
4365         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4366                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4367                 pbn_oxsemi_1_4000000 },
4368         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4369                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4370                 pbn_oxsemi_1_4000000 },
4371         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4372                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373                 pbn_oxsemi_1_4000000 },
4374         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4375                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376                 pbn_oxsemi_1_4000000 },
4377         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4378                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379                 pbn_oxsemi_1_4000000 },
4380         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4381                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382                 pbn_oxsemi_1_4000000 },
4383         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4384                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385                 pbn_oxsemi_1_4000000 },
4386         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4387                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388                 pbn_oxsemi_1_4000000 },
4389         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391                 pbn_oxsemi_1_4000000 },
4392         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394                 pbn_oxsemi_1_4000000 },
4395         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397                 pbn_oxsemi_1_4000000 },
4398         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400                 pbn_oxsemi_1_4000000 },
4401         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403                 pbn_oxsemi_1_4000000 },
4404         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406                 pbn_oxsemi_1_4000000 },
4407         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409                 pbn_oxsemi_1_4000000 },
4410         /*
4411          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4412          */
4413         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4414                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4415                 pbn_oxsemi_1_4000000 },
4416         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4417                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4418                 pbn_oxsemi_2_4000000 },
4419         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4420                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4421                 pbn_oxsemi_4_4000000 },
4422         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4423                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4424                 pbn_oxsemi_8_4000000 },
4425
4426         /*
4427          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4428          */
4429         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4430                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4431                 pbn_oxsemi_2_4000000 },
4432
4433         /*
4434          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4435          * from skokodyn@yahoo.com
4436          */
4437         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4438                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4439                 pbn_sbsxrsio },
4440         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4441                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4442                 pbn_sbsxrsio },
4443         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4444                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4445                 pbn_sbsxrsio },
4446         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4447                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4448                 pbn_sbsxrsio },
4449
4450         /*
4451          * Digitan DS560-558, from jimd@esoft.com
4452          */
4453         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4454                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455                 pbn_b1_1_115200 },
4456
4457         /*
4458          * Titan Electronic cards
4459          *  The 400L and 800L have a custom setup quirk.
4460          */
4461         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463                 pbn_b0_1_921600 },
4464         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4465                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466                 pbn_b0_2_921600 },
4467         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4468                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469                 pbn_b0_4_921600 },
4470         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472                 pbn_b0_4_921600 },
4473         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4474                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475                 pbn_b1_1_921600 },
4476         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4477                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478                 pbn_b1_bt_2_921600 },
4479         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481                 pbn_b0_bt_4_921600 },
4482         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4483                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484                 pbn_b0_bt_8_921600 },
4485         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487                 pbn_b4_bt_2_921600 },
4488         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490                 pbn_b4_bt_4_921600 },
4491         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4492                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493                 pbn_b4_bt_8_921600 },
4494         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4495                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496                 pbn_b0_4_921600 },
4497         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4498                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499                 pbn_b0_4_921600 },
4500         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4501                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502                 pbn_b0_4_921600 },
4503         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4504                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505                 pbn_oxsemi_1_4000000 },
4506         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4507                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508                 pbn_oxsemi_2_4000000 },
4509         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4510                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511                 pbn_oxsemi_4_4000000 },
4512         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4513                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514                 pbn_oxsemi_8_4000000 },
4515         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517                 pbn_oxsemi_2_4000000 },
4518         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4519                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520                 pbn_oxsemi_2_4000000 },
4521         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4522                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523                 pbn_b0_bt_2_921600 },
4524         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4525                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526                 pbn_b0_4_921600 },
4527         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529                 pbn_b0_4_921600 },
4530         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4531                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532                 pbn_b0_4_921600 },
4533         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535                 pbn_b0_4_921600 },
4536
4537         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4538                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539                 pbn_b2_1_460800 },
4540         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4541                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542                 pbn_b2_1_460800 },
4543         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4544                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545                 pbn_b2_1_460800 },
4546         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4547                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548                 pbn_b2_bt_2_921600 },
4549         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4550                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551                 pbn_b2_bt_2_921600 },
4552         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4553                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554                 pbn_b2_bt_2_921600 },
4555         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4556                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557                 pbn_b2_bt_4_921600 },
4558         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4559                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560                 pbn_b2_bt_4_921600 },
4561         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4562                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563                 pbn_b2_bt_4_921600 },
4564         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4565                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566                 pbn_b0_1_921600 },
4567         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4568                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569                 pbn_b0_1_921600 },
4570         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4571                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572                 pbn_b0_1_921600 },
4573         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4574                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575                 pbn_b0_bt_2_921600 },
4576         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4577                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578                 pbn_b0_bt_2_921600 },
4579         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4580                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581                 pbn_b0_bt_2_921600 },
4582         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4583                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584                 pbn_b0_bt_4_921600 },
4585         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4586                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587                 pbn_b0_bt_4_921600 },
4588         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4589                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590                 pbn_b0_bt_4_921600 },
4591         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4592                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593                 pbn_b0_bt_8_921600 },
4594         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4595                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596                 pbn_b0_bt_8_921600 },
4597         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4598                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599                 pbn_b0_bt_8_921600 },
4600
4601         /*
4602          * Computone devices submitted by Doug McNash dmcnash@computone.com
4603          */
4604         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4605                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4606                 0, 0, pbn_computone_4 },
4607         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4608                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4609                 0, 0, pbn_computone_8 },
4610         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4611                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4612                 0, 0, pbn_computone_6 },
4613
4614         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616                 pbn_oxsemi },
4617         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4618                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4619                 pbn_b0_bt_1_921600 },
4620
4621         /*
4622          * SUNIX (TIMEDIA)
4623          */
4624         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4625                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4626                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4627                 pbn_b0_bt_1_921600 },
4628
4629         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4630                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4631                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4632                 pbn_b0_bt_1_921600 },
4633
4634         /*
4635          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4636          */
4637         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4638                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639                 pbn_b0_bt_8_115200 },
4640         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4641                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642                 pbn_b0_bt_8_115200 },
4643
4644         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4645                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646                 pbn_b0_bt_2_115200 },
4647         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4648                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649                 pbn_b0_bt_2_115200 },
4650         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4651                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652                 pbn_b0_bt_2_115200 },
4653         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655                 pbn_b0_bt_2_115200 },
4656         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658                 pbn_b0_bt_2_115200 },
4659         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4660                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661                 pbn_b0_bt_4_460800 },
4662         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4663                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664                 pbn_b0_bt_4_460800 },
4665         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4666                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667                 pbn_b0_bt_2_460800 },
4668         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4669                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670                 pbn_b0_bt_2_460800 },
4671         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4672                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673                 pbn_b0_bt_2_460800 },
4674         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4675                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676                 pbn_b0_bt_1_115200 },
4677         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4678                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4679                 pbn_b0_bt_1_460800 },
4680
4681         /*
4682          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4683          * Cards are identified by their subsystem vendor IDs, which
4684          * (in hex) match the model number.
4685          *
4686          * Note that JC140x are RS422/485 cards which require ox950
4687          * ACR = 0x10, and as such are not currently fully supported.
4688          */
4689         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4690                 0x1204, 0x0004, 0, 0,
4691                 pbn_b0_4_921600 },
4692         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4693                 0x1208, 0x0004, 0, 0,
4694                 pbn_b0_4_921600 },
4695 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4696                 0x1402, 0x0002, 0, 0,
4697                 pbn_b0_2_921600 }, */
4698 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4699                 0x1404, 0x0004, 0, 0,
4700                 pbn_b0_4_921600 }, */
4701         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4702                 0x1208, 0x0004, 0, 0,
4703                 pbn_b0_4_921600 },
4704
4705         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4706                 0x1204, 0x0004, 0, 0,
4707                 pbn_b0_4_921600 },
4708         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4709                 0x1208, 0x0004, 0, 0,
4710                 pbn_b0_4_921600 },
4711         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4712                 0x1208, 0x0004, 0, 0,
4713                 pbn_b0_4_921600 },
4714         /*
4715          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4716          */
4717         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4718                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719                 pbn_b1_1_1382400 },
4720
4721         /*
4722          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4723          */
4724         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4725                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726                 pbn_b1_1_1382400 },
4727
4728         /*
4729          * RAStel 2 port modem, gerg@moreton.com.au
4730          */
4731         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4732                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733                 pbn_b2_bt_2_115200 },
4734
4735         /*
4736          * EKF addition for i960 Boards form EKF with serial port
4737          */
4738         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4739                 0xE4BF, PCI_ANY_ID, 0, 0,
4740                 pbn_intel_i960 },
4741
4742         /*
4743          * Xircom Cardbus/Ethernet combos
4744          */
4745         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747                 pbn_b0_1_115200 },
4748         /*
4749          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4750          */
4751         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753                 pbn_b0_1_115200 },
4754
4755         /*
4756          * Untested PCI modems, sent in from various folks...
4757          */
4758
4759         /*
4760          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4761          */
4762         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4763                 0x1048, 0x1500, 0, 0,
4764                 pbn_b1_1_115200 },
4765
4766         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4767                 0xFF00, 0, 0, 0,
4768                 pbn_sgi_ioc3 },
4769
4770         /*
4771          * HP Diva card
4772          */
4773         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4774                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4775                 pbn_b1_1_115200 },
4776         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4777                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778                 pbn_b0_5_115200 },
4779         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4780                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781                 pbn_b2_1_115200 },
4782
4783         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4784                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785                 pbn_b3_2_115200 },
4786         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4787                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788                 pbn_b3_4_115200 },
4789         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4790                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791                 pbn_b3_8_115200 },
4792
4793         /*
4794          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4795          */
4796         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4797                 PCI_ANY_ID, PCI_ANY_ID,
4798                 0,
4799                 0, pbn_exar_XR17C152 },
4800         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4801                 PCI_ANY_ID, PCI_ANY_ID,
4802                 0,
4803                 0, pbn_exar_XR17C154 },
4804         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4805                 PCI_ANY_ID, PCI_ANY_ID,
4806                 0,
4807                 0, pbn_exar_XR17C158 },
4808         /*
4809          * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4810          */
4811         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4812                 PCI_ANY_ID, PCI_ANY_ID,
4813                 0,
4814                 0, pbn_exar_XR17V352 },
4815         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4816                 PCI_ANY_ID, PCI_ANY_ID,
4817                 0,
4818                 0, pbn_exar_XR17V354 },
4819         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4820                 PCI_ANY_ID, PCI_ANY_ID,
4821                 0,
4822                 0, pbn_exar_XR17V358 },
4823
4824         /*
4825          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4826          */
4827         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829                 pbn_b0_1_115200 },
4830         /*
4831          * ITE
4832          */
4833         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4834                 PCI_ANY_ID, PCI_ANY_ID,
4835                 0, 0,
4836                 pbn_b1_bt_1_115200 },
4837
4838         /*
4839          * IntaShield IS-200
4840          */
4841         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4842                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
4843                 pbn_b2_2_115200 },
4844         /*
4845          * IntaShield IS-400
4846          */
4847         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
4849                 pbn_b2_4_115200 },
4850         /*
4851          * Perle PCI-RAS cards
4852          */
4853         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4854                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4855                 0, 0, pbn_b2_4_921600 },
4856         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4857                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4858                 0, 0, pbn_b2_8_921600 },
4859
4860         /*
4861          * Mainpine series cards: Fairly standard layout but fools
4862          * parts of the autodetect in some cases and uses otherwise
4863          * unmatched communications subclasses in the PCI Express case
4864          */
4865
4866         {       /* RockForceDUO */
4867                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4868                 PCI_VENDOR_ID_MAINPINE, 0x0200,
4869                 0, 0, pbn_b0_2_115200 },
4870         {       /* RockForceQUATRO */
4871                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4872                 PCI_VENDOR_ID_MAINPINE, 0x0300,
4873                 0, 0, pbn_b0_4_115200 },
4874         {       /* RockForceDUO+ */
4875                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4876                 PCI_VENDOR_ID_MAINPINE, 0x0400,
4877                 0, 0, pbn_b0_2_115200 },
4878         {       /* RockForceQUATRO+ */
4879                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4880                 PCI_VENDOR_ID_MAINPINE, 0x0500,
4881                 0, 0, pbn_b0_4_115200 },
4882         {       /* RockForce+ */
4883                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4884                 PCI_VENDOR_ID_MAINPINE, 0x0600,
4885                 0, 0, pbn_b0_2_115200 },
4886         {       /* RockForce+ */
4887                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4888                 PCI_VENDOR_ID_MAINPINE, 0x0700,
4889                 0, 0, pbn_b0_4_115200 },
4890         {       /* RockForceOCTO+ */
4891                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4892                 PCI_VENDOR_ID_MAINPINE, 0x0800,
4893                 0, 0, pbn_b0_8_115200 },
4894         {       /* RockForceDUO+ */
4895                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4896                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4897                 0, 0, pbn_b0_2_115200 },
4898         {       /* RockForceQUARTRO+ */
4899                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4900                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4901                 0, 0, pbn_b0_4_115200 },
4902         {       /* RockForceOCTO+ */
4903                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4904                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4905                 0, 0, pbn_b0_8_115200 },
4906         {       /* RockForceD1 */
4907                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4908                 PCI_VENDOR_ID_MAINPINE, 0x2000,
4909                 0, 0, pbn_b0_1_115200 },
4910         {       /* RockForceF1 */
4911                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4912                 PCI_VENDOR_ID_MAINPINE, 0x2100,
4913                 0, 0, pbn_b0_1_115200 },
4914         {       /* RockForceD2 */
4915                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4916                 PCI_VENDOR_ID_MAINPINE, 0x2200,
4917                 0, 0, pbn_b0_2_115200 },
4918         {       /* RockForceF2 */
4919                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4920                 PCI_VENDOR_ID_MAINPINE, 0x2300,
4921                 0, 0, pbn_b0_2_115200 },
4922         {       /* RockForceD4 */
4923                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4924                 PCI_VENDOR_ID_MAINPINE, 0x2400,
4925                 0, 0, pbn_b0_4_115200 },
4926         {       /* RockForceF4 */
4927                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4928                 PCI_VENDOR_ID_MAINPINE, 0x2500,
4929                 0, 0, pbn_b0_4_115200 },
4930         {       /* RockForceD8 */
4931                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4932                 PCI_VENDOR_ID_MAINPINE, 0x2600,
4933                 0, 0, pbn_b0_8_115200 },
4934         {       /* RockForceF8 */
4935                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4936                 PCI_VENDOR_ID_MAINPINE, 0x2700,
4937                 0, 0, pbn_b0_8_115200 },
4938         {       /* IQ Express D1 */
4939                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4940                 PCI_VENDOR_ID_MAINPINE, 0x3000,
4941                 0, 0, pbn_b0_1_115200 },
4942         {       /* IQ Express F1 */
4943                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4944                 PCI_VENDOR_ID_MAINPINE, 0x3100,
4945                 0, 0, pbn_b0_1_115200 },
4946         {       /* IQ Express D2 */
4947                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4948                 PCI_VENDOR_ID_MAINPINE, 0x3200,
4949                 0, 0, pbn_b0_2_115200 },
4950         {       /* IQ Express F2 */
4951                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4952                 PCI_VENDOR_ID_MAINPINE, 0x3300,
4953                 0, 0, pbn_b0_2_115200 },
4954         {       /* IQ Express D4 */
4955                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4956                 PCI_VENDOR_ID_MAINPINE, 0x3400,
4957                 0, 0, pbn_b0_4_115200 },
4958         {       /* IQ Express F4 */
4959                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4960                 PCI_VENDOR_ID_MAINPINE, 0x3500,
4961                 0, 0, pbn_b0_4_115200 },
4962         {       /* IQ Express D8 */
4963                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4964                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4965                 0, 0, pbn_b0_8_115200 },
4966         {       /* IQ Express F8 */
4967                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4968                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4969                 0, 0, pbn_b0_8_115200 },
4970
4971
4972         /*
4973          * PA Semi PA6T-1682M on-chip UART
4974          */
4975         {       PCI_VENDOR_ID_PASEMI, 0xa004,
4976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977                 pbn_pasemi_1682M },
4978
4979         /*
4980          * National Instruments
4981          */
4982         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984                 pbn_b1_16_115200 },
4985         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4986                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987                 pbn_b1_8_115200 },
4988         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4989                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990                 pbn_b1_bt_4_115200 },
4991         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4992                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993                 pbn_b1_bt_2_115200 },
4994         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4995                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996                 pbn_b1_bt_4_115200 },
4997         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999                 pbn_b1_bt_2_115200 },
5000         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5001                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002                 pbn_b1_16_115200 },
5003         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005                 pbn_b1_8_115200 },
5006         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008                 pbn_b1_bt_4_115200 },
5009         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011                 pbn_b1_bt_2_115200 },
5012         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5013                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014                 pbn_b1_bt_4_115200 },
5015         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5016                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017                 pbn_b1_bt_2_115200 },
5018         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5019                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020                 pbn_ni8430_2 },
5021         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5022                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023                 pbn_ni8430_2 },
5024         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5025                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5026                 pbn_ni8430_4 },
5027         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5028                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5029                 pbn_ni8430_4 },
5030         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5031                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5032                 pbn_ni8430_8 },
5033         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5034                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035                 pbn_ni8430_8 },
5036         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5037                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038                 pbn_ni8430_16 },
5039         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5040                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041                 pbn_ni8430_16 },
5042         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5043                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044                 pbn_ni8430_2 },
5045         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5046                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047                 pbn_ni8430_2 },
5048         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5049                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050                 pbn_ni8430_4 },
5051         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5052                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053                 pbn_ni8430_4 },
5054
5055         /*
5056         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5057         */
5058         {       PCI_VENDOR_ID_ADDIDATA,
5059                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5060                 PCI_ANY_ID,
5061                 PCI_ANY_ID,
5062                 0,
5063                 0,
5064                 pbn_b0_4_115200 },
5065
5066         {       PCI_VENDOR_ID_ADDIDATA,
5067                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5068                 PCI_ANY_ID,
5069                 PCI_ANY_ID,
5070                 0,
5071                 0,
5072                 pbn_b0_2_115200 },
5073
5074         {       PCI_VENDOR_ID_ADDIDATA,
5075                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5076                 PCI_ANY_ID,
5077                 PCI_ANY_ID,
5078                 0,
5079                 0,
5080                 pbn_b0_1_115200 },
5081
5082         {       PCI_VENDOR_ID_AMCC,
5083                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5084                 PCI_ANY_ID,
5085                 PCI_ANY_ID,
5086                 0,
5087                 0,
5088                 pbn_b1_8_115200 },
5089
5090         {       PCI_VENDOR_ID_ADDIDATA,
5091                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5092                 PCI_ANY_ID,
5093                 PCI_ANY_ID,
5094                 0,
5095                 0,
5096                 pbn_b0_4_115200 },
5097
5098         {       PCI_VENDOR_ID_ADDIDATA,
5099                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5100                 PCI_ANY_ID,
5101                 PCI_ANY_ID,
5102                 0,
5103                 0,
5104                 pbn_b0_2_115200 },
5105
5106         {       PCI_VENDOR_ID_ADDIDATA,
5107                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5108                 PCI_ANY_ID,
5109                 PCI_ANY_ID,
5110                 0,
5111                 0,
5112                 pbn_b0_1_115200 },
5113
5114         {       PCI_VENDOR_ID_ADDIDATA,
5115                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5116                 PCI_ANY_ID,
5117                 PCI_ANY_ID,
5118                 0,
5119                 0,
5120                 pbn_b0_4_115200 },
5121
5122         {       PCI_VENDOR_ID_ADDIDATA,
5123                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5124                 PCI_ANY_ID,
5125                 PCI_ANY_ID,
5126                 0,
5127                 0,
5128                 pbn_b0_2_115200 },
5129
5130         {       PCI_VENDOR_ID_ADDIDATA,
5131                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5132                 PCI_ANY_ID,
5133                 PCI_ANY_ID,
5134                 0,
5135                 0,
5136                 pbn_b0_1_115200 },
5137
5138         {       PCI_VENDOR_ID_ADDIDATA,
5139                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5140                 PCI_ANY_ID,
5141                 PCI_ANY_ID,
5142                 0,
5143                 0,
5144                 pbn_b0_8_115200 },
5145
5146         {       PCI_VENDOR_ID_ADDIDATA,
5147                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5148                 PCI_ANY_ID,
5149                 PCI_ANY_ID,
5150                 0,
5151                 0,
5152                 pbn_ADDIDATA_PCIe_4_3906250 },
5153
5154         {       PCI_VENDOR_ID_ADDIDATA,
5155                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5156                 PCI_ANY_ID,
5157                 PCI_ANY_ID,
5158                 0,
5159                 0,
5160                 pbn_ADDIDATA_PCIe_2_3906250 },
5161
5162         {       PCI_VENDOR_ID_ADDIDATA,
5163                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5164                 PCI_ANY_ID,
5165                 PCI_ANY_ID,
5166                 0,
5167                 0,
5168                 pbn_ADDIDATA_PCIe_1_3906250 },
5169
5170         {       PCI_VENDOR_ID_ADDIDATA,
5171                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5172                 PCI_ANY_ID,
5173                 PCI_ANY_ID,
5174                 0,
5175                 0,
5176                 pbn_ADDIDATA_PCIe_8_3906250 },
5177
5178         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5179                 PCI_VENDOR_ID_IBM, 0x0299,
5180                 0, 0, pbn_b0_bt_2_115200 },
5181
5182         /*
5183          * other NetMos 9835 devices are most likely handled by the
5184          * parport_serial driver, check drivers/parport/parport_serial.c
5185          * before adding them here.
5186          */
5187
5188         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5189                 0xA000, 0x1000,
5190                 0, 0, pbn_b0_1_115200 },
5191
5192         /* the 9901 is a rebranded 9912 */
5193         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5194                 0xA000, 0x1000,
5195                 0, 0, pbn_b0_1_115200 },
5196
5197         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5198                 0xA000, 0x1000,
5199                 0, 0, pbn_b0_1_115200 },
5200
5201         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5202                 0xA000, 0x1000,
5203                 0, 0, pbn_b0_1_115200 },
5204
5205         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5206                 0xA000, 0x1000,
5207                 0, 0, pbn_b0_1_115200 },
5208
5209         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5210                 0xA000, 0x3002,
5211                 0, 0, pbn_NETMOS9900_2s_115200 },
5212
5213         /*
5214          * Best Connectivity and Rosewill PCI Multi I/O cards
5215          */
5216
5217         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5218                 0xA000, 0x1000,
5219                 0, 0, pbn_b0_1_115200 },
5220
5221         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5222                 0xA000, 0x3002,
5223                 0, 0, pbn_b0_bt_2_115200 },
5224
5225         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5226                 0xA000, 0x3004,
5227                 0, 0, pbn_b0_bt_4_115200 },
5228         /* Intel CE4100 */
5229         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5230                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5231                 pbn_ce4100_1_115200 },
5232         /* Intel BayTrail */
5233         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5234                 PCI_ANY_ID,  PCI_ANY_ID,
5235                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5236                 pbn_byt },
5237         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5238                 PCI_ANY_ID,  PCI_ANY_ID,
5239                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5240                 pbn_byt },
5241         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5242                 PCI_ANY_ID,  PCI_ANY_ID,
5243                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5244                 pbn_byt },
5245         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5246                 PCI_ANY_ID,  PCI_ANY_ID,
5247                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5248                 pbn_byt },
5249
5250         /*
5251          * Cronyx Omega PCI
5252          */
5253         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5254                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5255                 pbn_omegapci },
5256
5257         /*
5258          * Broadcom TruManage
5259          */
5260         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5262                 pbn_brcm_trumanage },
5263
5264         /*
5265          * AgeStar as-prs2-009
5266          */
5267         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5268                 PCI_ANY_ID, PCI_ANY_ID,
5269                 0, 0, pbn_b0_bt_2_115200 },
5270
5271         /*
5272          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5273          * so not listed here.
5274          */
5275         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5276                 PCI_ANY_ID, PCI_ANY_ID,
5277                 0, 0, pbn_b0_bt_4_115200 },
5278
5279         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5280                 PCI_ANY_ID, PCI_ANY_ID,
5281                 0, 0, pbn_b0_bt_2_115200 },
5282
5283         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5284                 PCI_ANY_ID, PCI_ANY_ID,
5285                 0, 0, pbn_b0_bt_2_115200 },
5286
5287         /*
5288          * Commtech, Inc. Fastcom adapters
5289          */
5290         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5291                 PCI_ANY_ID, PCI_ANY_ID,
5292                 0,
5293                 0, pbn_b0_2_1152000_200 },
5294         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5295                 PCI_ANY_ID, PCI_ANY_ID,
5296                 0,
5297                 0, pbn_b0_4_1152000_200 },
5298         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5299                 PCI_ANY_ID, PCI_ANY_ID,
5300                 0,
5301                 0, pbn_b0_4_1152000_200 },
5302         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5303                 PCI_ANY_ID, PCI_ANY_ID,
5304                 0,
5305                 0, pbn_b0_8_1152000_200 },
5306         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5307                 PCI_ANY_ID, PCI_ANY_ID,
5308                 0,
5309                 0, pbn_exar_XR17V352 },
5310         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5311                 PCI_ANY_ID, PCI_ANY_ID,
5312                 0,
5313                 0, pbn_exar_XR17V354 },
5314         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5315                 PCI_ANY_ID, PCI_ANY_ID,
5316                 0,
5317                 0, pbn_exar_XR17V358 },
5318
5319         /* Fintek PCI serial cards */
5320         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5321         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5322         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5323
5324         /*
5325          * These entries match devices with class COMMUNICATION_SERIAL,
5326          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5327          */
5328         {       PCI_ANY_ID, PCI_ANY_ID,
5329                 PCI_ANY_ID, PCI_ANY_ID,
5330                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5331                 0xffff00, pbn_default },
5332         {       PCI_ANY_ID, PCI_ANY_ID,
5333                 PCI_ANY_ID, PCI_ANY_ID,
5334                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5335                 0xffff00, pbn_default },
5336         {       PCI_ANY_ID, PCI_ANY_ID,
5337                 PCI_ANY_ID, PCI_ANY_ID,
5338                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5339                 0xffff00, pbn_default },
5340         { 0, }
5341 };
5342
5343 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5344                                                 pci_channel_state_t state)
5345 {
5346         struct serial_private *priv = pci_get_drvdata(dev);
5347
5348         if (state == pci_channel_io_perm_failure)
5349                 return PCI_ERS_RESULT_DISCONNECT;
5350
5351         if (priv)
5352                 pciserial_suspend_ports(priv);
5353
5354         pci_disable_device(dev);
5355
5356         return PCI_ERS_RESULT_NEED_RESET;
5357 }
5358
5359 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5360 {
5361         int rc;
5362
5363         rc = pci_enable_device(dev);
5364
5365         if (rc)
5366                 return PCI_ERS_RESULT_DISCONNECT;
5367
5368         pci_restore_state(dev);
5369         pci_save_state(dev);
5370
5371         return PCI_ERS_RESULT_RECOVERED;
5372 }
5373
5374 static void serial8250_io_resume(struct pci_dev *dev)
5375 {
5376         struct serial_private *priv = pci_get_drvdata(dev);
5377
5378         if (priv)
5379                 pciserial_resume_ports(priv);
5380 }
5381
5382 static const struct pci_error_handlers serial8250_err_handler = {
5383         .error_detected = serial8250_io_error_detected,
5384         .slot_reset = serial8250_io_slot_reset,
5385         .resume = serial8250_io_resume,
5386 };
5387
5388 static struct pci_driver serial_pci_driver = {
5389         .name           = "serial",
5390         .probe          = pciserial_init_one,
5391         .remove         = pciserial_remove_one,
5392 #ifdef CONFIG_PM
5393         .suspend        = pciserial_suspend_one,
5394         .resume         = pciserial_resume_one,
5395 #endif
5396         .id_table       = serial_pci_tbl,
5397         .err_handler    = &serial8250_err_handler,
5398 };
5399
5400 module_pci_driver(serial_pci_driver);
5401
5402 MODULE_LICENSE("GPL");
5403 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5404 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);