drivers/timer/cadence-ttc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
   4  */
   5
   6 #include <common.h>
   7 #include <bootstage.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <init.h>
  11 #include <timer.h>
  12 #include <asm/io.h>
  13 #include <linux/err.h>
  14
  15 #define CNT_CNTRL_RESET         BIT(4)
  16
  17 struct cadence_ttc_regs {
  18         u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
  19         u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
  20         u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
  21         u32 counter_cntrl1; /* 0xC - Counter Control 1 */
  22         u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
  23         u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
  24         u32 counter_val1; /* 0x18 - Counter Control 1 */
  25         u32 counter_val2; /* 0x1C - Counter Control 2 */
  26         u32 counter_val3; /* 0x20 - Counter Control 3 */
  27         u32 reserved[15];
  28         u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
  29         u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
  30         u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
  31 };
  32
  33 struct cadence_ttc_priv {
  34         struct cadence_ttc_regs *regs;
  35 };
  36
  37 #if CONFIG_IS_ENABLED(BOOTSTAGE)
  38 ulong timer_get_boot_us(void)
  39 {
  40         u64 ticks = 0;
  41         u32 rate = 1;
  42         u64 us;
  43         int ret;
  44
  45         ret = dm_timer_init();
  46         if (!ret) {
  47                 /* The timer is available */
  48                 rate = timer_get_rate(gd->timer);
  49                 timer_get_count(gd->timer, &ticks);
  50         } else {
  51                 return 0;
  52         }
  53
  54         us = (ticks * 1000) / rate;
  55         return us;
  56 }
  57 #endif
  58
  59 static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
  60 {
  61         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  62
  63         *count = readl(&priv->regs->counter_val1);
  64
  65         return 0;
  66 }
  67
  68 static int cadence_ttc_probe(struct udevice *dev)
  69 {
  70         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  71
  72         /* Disable interrupts for sure */
  73         writel(0, &priv->regs->interrupt_enable1);
  74         writel(0, &priv->regs->interrupt_enable2);
  75         writel(0, &priv->regs->interrupt_enable3);
  76
  77         /* Make sure that clocks are configured properly without prescaller */
  78         writel(0, &priv->regs->clk_cntrl1);
  79         writel(0, &priv->regs->clk_cntrl2);
  80         writel(0, &priv->regs->clk_cntrl3);
  81
  82         /* Reset and enable this counter */
  83         writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
  84
  85         return 0;
  86 }
  87
  88 static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
  89 {
  90         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  91
  92         priv->regs = map_physmem(dev_read_addr(dev),
  93                                  sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
  94         if (IS_ERR(priv->regs))
  95                 return PTR_ERR(priv->regs);
  96
  97         return 0;
  98 }
  99
 100 static const struct timer_ops cadence_ttc_ops = {
 101         .get_count = cadence_ttc_get_count,
 102 };
 103
 104 static const struct udevice_id cadence_ttc_ids[] = {
 105         { .compatible = "cdns,ttc" },
 106         {}
 107 };
 108
 109 U_BOOT_DRIVER(cadence_ttc) = {
 110         .name = "cadence_ttc",
 111         .id = UCLASS_TIMER,
 112         .of_match = cadence_ttc_ids,
 113         .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
 114         .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
 115         .probe = cadence_ttc_probe,
 116         .ops = &cadence_ttc_ops,
 117 };