drivers/staging/xgifb/vb_init.c

   1 #include <linux/types.h>
   2 #include <linux/delay.h> /* udelay */
   3 #include <linux/pci.h>
   4
   5 #include "vgatypes.h"
   6 #include "XGIfb.h"
   7
   8 #include "vb_def.h"
   9 #include "vb_struct.h"
  10 #include "vb_util.h"
  11 #include "vb_setmode.h"
  12 #include "vb_init.h"
  13 #include "vb_ext.h"
  14
  15
  16 #include <linux/io.h>
  17
  18 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
  19
  20 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
  21         { 2, 13, 9, 64, 0x45},
  22         { 2, 12, 9, 32, 0x35},
  23         { 2, 12, 8, 16, 0x31},
  24         { 2, 11, 8,  8, 0x21} };
  25
  26 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
  27         { 2, 14, 11, 128, 0x5D},
  28         { 2, 14, 10, 64, 0x59},
  29         { 2, 13, 11, 64, 0x4D},
  30         { 2, 14,  9, 32, 0x55},
  31         { 2, 13, 10, 32, 0x49},
  32         { 2, 12, 11, 32, 0x3D},
  33         { 2, 14,  8, 16, 0x51},
  34         { 2, 13,  9, 16, 0x45},
  35         { 2, 12, 10, 16, 0x39},
  36         { 2, 13,  8,  8, 0x41},
  37         { 2, 12,  9,  8, 0x35},
  38         { 2, 12,  8,  4, 0x31} };
  39
  40 static unsigned char
  41 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  42                        struct vb_device_info *pVBInfo)
  43 {
  44         unsigned char data, temp;
  45
  46         if (HwDeviceExtension->jChipType < XG20) {
  47                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  48                         data = *pVBInfo->pSoftSetting & 0x07;
  49                         return data;
  50                 } else {
  51                         data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  52                         if (data == 0)
  53                                 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  54                                        0x02) >> 1;
  55                         return data;
  56                 }
  57         } else if (HwDeviceExtension->jChipType == XG27) {
  58                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  59                         data = *pVBInfo->pSoftSetting & 0x07;
  60                         return data;
  61                 }
  62                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  63                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  64                 if ((temp & 0x88) == 0x80)
  65                         data = 0; /* DDR */
  66                 else
  67                         data = 1; /* DDRII */
  68                 return data;
  69         } else if (HwDeviceExtension->jChipType == XG21) {
  70                 /* Independent GPIO control */
  71                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  72                 udelay(800);
  73                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  74                 /* GPIOF 0:DVI 1:DVO */
  75                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  76                 /* HOTPLUG_SUPPORT */
  77                 /* for current XG20 & XG21, GPIOH is floating, driver will
  78                  * fix DDR temporarily */
  79                 if (temp & 0x01) /* DVI read GPIOH */
  80                         data = 1; /* DDRII */
  81                 else
  82                         data = 0; /* DDR */
  83                 /* ~HOTPLUG_SUPPORT */
  84                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  85                 return data;
  86         } else {
  87                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  88
  89                 if (data == 1)
  90                         data++;
  91
  92                 return data;
  93         }
  94 }
  95
  96 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  97                                  struct vb_device_info *pVBInfo)
  98 {
  99         xgifb_reg_set(P3c4, 0x18, 0x01);
 100         xgifb_reg_set(P3c4, 0x19, 0x20);
 101         xgifb_reg_set(P3c4, 0x16, 0x00);
 102         xgifb_reg_set(P3c4, 0x16, 0x80);
 103
 104         if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
 105                 mdelay(3);
 106                 xgifb_reg_set(P3c4, 0x18, 0x00);
 107                 xgifb_reg_set(P3c4, 0x19, 0x20);
 108                 xgifb_reg_set(P3c4, 0x16, 0x00);
 109                 xgifb_reg_set(P3c4, 0x16, 0x80);
 110         }
 111
 112         udelay(60);
 113         xgifb_reg_set(P3c4,
 114                       0x18,
 115                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 116         xgifb_reg_set(P3c4, 0x19, 0x01);
 117         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
 118         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
 119         mdelay(1);
 120         xgifb_reg_set(P3c4, 0x1B, 0x03);
 121         udelay(500);
 122         xgifb_reg_set(P3c4,
 123                       0x18,
 124                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 125         xgifb_reg_set(P3c4, 0x19, 0x00);
 126         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
 127         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
 128         xgifb_reg_set(P3c4, 0x1B, 0x00);
 129 }
 130
 131 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
 132                 struct vb_device_info *pVBInfo)
 133 {
 134
 135         xgifb_reg_set(pVBInfo->P3c4,
 136                       0x28,
 137                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 138         xgifb_reg_set(pVBInfo->P3c4,
 139                       0x29,
 140                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 141         xgifb_reg_set(pVBInfo->P3c4,
 142                       0x2A,
 143                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 144
 145         xgifb_reg_set(pVBInfo->P3c4,
 146                       0x2E,
 147                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
 148         xgifb_reg_set(pVBInfo->P3c4,
 149                       0x2F,
 150                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
 151         xgifb_reg_set(pVBInfo->P3c4,
 152                       0x30,
 153                       pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
 154
 155         /* [Vicent] 2004/07/07,
 156          * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
 157         /* [Hsuan] 2004/08/20,
 158          * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
 159          * Set SR32 D[1:0] = 10b */
 160         if (HwDeviceExtension->jChipType == XG42) {
 161                 if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
 162                     (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
 163                     (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
 164                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
 165                      ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
 166                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
 167                         xgifb_reg_set(pVBInfo->P3c4,
 168                                       0x32,
 169                                       ((unsigned char) xgifb_reg_get(
 170                                           pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
 171         }
 172 }
 173
 174 static void XGINew_DDRII_Bootup_XG27(
 175                         struct xgi_hw_device_info *HwDeviceExtension,
 176                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 177 {
 178         unsigned long P3d4 = P3c4 + 0x10;
 179         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 180         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 181
 182         /* Set Double Frequency */
 183         /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
 184         xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
 185
 186         udelay(200);
 187
 188         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 189         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 190         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 191         udelay(15);
 192         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 193         udelay(15);
 194
 195         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 196         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 197         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 198         udelay(15);
 199         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 200         udelay(15);
 201
 202         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 203         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 204         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 205         udelay(30);
 206         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 207         udelay(15);
 208
 209         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 210         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 211         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 212         udelay(30);
 213         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 214         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 215         /* udelay(15); */
 216
 217         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 218         udelay(60);
 219         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 220
 221         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 222         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 223         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 224
 225         udelay(30);
 226         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 227         udelay(15);
 228
 229         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 230         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 231         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 232         udelay(30);
 233         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 234         udelay(15);
 235
 236         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 237         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 238         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 239         udelay(30);
 240         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 241         udelay(15);
 242
 243         /* Set SR1B refresh control 000:close; 010:open */
 244         xgifb_reg_set(P3c4, 0x1B, 0x04);
 245         udelay(200);
 246
 247 }
 248
 249 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 250                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 251 {
 252         unsigned long P3d4 = P3c4 + 0x10;
 253
 254         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 255         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 256
 257         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 258
 259         udelay(200);
 260         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 261         xgifb_reg_set(P3c4, 0x19, 0x80);
 262         xgifb_reg_set(P3c4, 0x16, 0x05);
 263         xgifb_reg_set(P3c4, 0x16, 0x85);
 264
 265         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 266         xgifb_reg_set(P3c4, 0x19, 0xC0);
 267         xgifb_reg_set(P3c4, 0x16, 0x05);
 268         xgifb_reg_set(P3c4, 0x16, 0x85);
 269
 270         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 271         xgifb_reg_set(P3c4, 0x19, 0x40);
 272         xgifb_reg_set(P3c4, 0x16, 0x05);
 273         xgifb_reg_set(P3c4, 0x16, 0x85);
 274
 275         /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
 276         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 277         xgifb_reg_set(P3c4, 0x19, 0x02);
 278         xgifb_reg_set(P3c4, 0x16, 0x05);
 279         xgifb_reg_set(P3c4, 0x16, 0x85);
 280
 281         udelay(15);
 282         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 283         udelay(30);
 284         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 285         udelay(100);
 286
 287         /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
 288         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 289         xgifb_reg_set(P3c4, 0x19, 0x00);
 290         xgifb_reg_set(P3c4, 0x16, 0x05);
 291         xgifb_reg_set(P3c4, 0x16, 0x85);
 292
 293         udelay(200);
 294 }
 295
 296 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 297                                   struct vb_device_info *pVBInfo)
 298 {
 299         xgifb_reg_set(P3c4, 0x18, 0x01);
 300         xgifb_reg_set(P3c4, 0x19, 0x40);
 301         xgifb_reg_set(P3c4, 0x16, 0x00);
 302         xgifb_reg_set(P3c4, 0x16, 0x80);
 303         udelay(60);
 304
 305         xgifb_reg_set(P3c4, 0x18, 0x00);
 306         xgifb_reg_set(P3c4, 0x19, 0x40);
 307         xgifb_reg_set(P3c4, 0x16, 0x00);
 308         xgifb_reg_set(P3c4, 0x16, 0x80);
 309         udelay(60);
 310         xgifb_reg_set(P3c4,
 311                       0x18,
 312                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 313         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 314         xgifb_reg_set(P3c4, 0x19, 0x01);
 315         xgifb_reg_set(P3c4, 0x16, 0x03);
 316         xgifb_reg_set(P3c4, 0x16, 0x83);
 317         mdelay(1);
 318         xgifb_reg_set(P3c4, 0x1B, 0x03);
 319         udelay(500);
 320         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 321         xgifb_reg_set(P3c4,
 322                       0x18,
 323                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 324         xgifb_reg_set(P3c4, 0x19, 0x00);
 325         xgifb_reg_set(P3c4, 0x16, 0x03);
 326         xgifb_reg_set(P3c4, 0x16, 0x83);
 327         xgifb_reg_set(P3c4, 0x1B, 0x00);
 328 }
 329
 330 static void XGINew_DDR1x_DefaultRegister(
 331                 struct xgi_hw_device_info *HwDeviceExtension,
 332                 unsigned long Port, struct vb_device_info *pVBInfo)
 333 {
 334         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 335
 336         if (HwDeviceExtension->jChipType >= XG20) {
 337                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 338                 xgifb_reg_set(P3d4,
 339                               0x82,
 340                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 341                 xgifb_reg_set(P3d4,
 342                               0x85,
 343                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 344                 xgifb_reg_set(P3d4,
 345                               0x86,
 346                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 347
 348                 xgifb_reg_set(P3d4, 0x98, 0x01);
 349                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 350
 351                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 352         } else {
 353                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 354
 355                 switch (HwDeviceExtension->jChipType) {
 356                 case XG41:
 357                 case XG42:
 358                         /* CR82 */
 359                         xgifb_reg_set(P3d4,
 360                                       0x82,
 361                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 362                         /* CR85 */
 363                         xgifb_reg_set(P3d4,
 364                                       0x85,
 365                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 366                         /* CR86 */
 367                         xgifb_reg_set(P3d4,
 368                                       0x86,
 369                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 370                         break;
 371                 default:
 372                         xgifb_reg_set(P3d4, 0x82, 0x88);
 373                         xgifb_reg_set(P3d4, 0x86, 0x00);
 374                         /* Insert read command for delay */
 375                         xgifb_reg_get(P3d4, 0x86);
 376                         xgifb_reg_set(P3d4, 0x86, 0x88);
 377                         xgifb_reg_get(P3d4, 0x86);
 378                         xgifb_reg_set(P3d4,
 379                                       0x86,
 380                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 381                         xgifb_reg_set(P3d4, 0x82, 0x77);
 382                         xgifb_reg_set(P3d4, 0x85, 0x00);
 383
 384                         /* Insert read command for delay */
 385                         xgifb_reg_get(P3d4, 0x85);
 386                         xgifb_reg_set(P3d4, 0x85, 0x88);
 387
 388                         /* Insert read command for delay */
 389                         xgifb_reg_get(P3d4, 0x85);
 390                         /* CR85 */
 391                         xgifb_reg_set(P3d4,
 392                                       0x85,
 393                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 394                         /* CR82 */
 395                         xgifb_reg_set(P3d4,
 396                                       0x82,
 397                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 398                         break;
 399                 }
 400
 401                 xgifb_reg_set(P3d4, 0x97, 0x00);
 402                 xgifb_reg_set(P3d4, 0x98, 0x01);
 403                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 404                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 405         }
 406 }
 407
 408 static void XGINew_DDR2_DefaultRegister(
 409                 struct xgi_hw_device_info *HwDeviceExtension,
 410                 unsigned long Port, struct vb_device_info *pVBInfo)
 411 {
 412         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 413
 414         /* keep following setting sequence, each setting in
 415          * the same reg insert idle */
 416         xgifb_reg_set(P3d4, 0x82, 0x77);
 417         xgifb_reg_set(P3d4, 0x86, 0x00);
 418         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 419         xgifb_reg_set(P3d4, 0x86, 0x88);
 420         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 421         /* CR86 */
 422         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 423         xgifb_reg_set(P3d4, 0x82, 0x77);
 424         xgifb_reg_set(P3d4, 0x85, 0x00);
 425         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 426         xgifb_reg_set(P3d4, 0x85, 0x88);
 427         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 428         xgifb_reg_set(P3d4,
 429                       0x85,
 430                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 431         if (HwDeviceExtension->jChipType == XG27)
 432                 /* CR82 */
 433                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 434         else
 435                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 436
 437         xgifb_reg_set(P3d4, 0x98, 0x01);
 438         xgifb_reg_set(P3d4, 0x9A, 0x02);
 439         if (HwDeviceExtension->jChipType == XG27)
 440                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 441         else
 442                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 443 }
 444
 445 static void XGINew_SetDRAMDefaultRegister340(
 446                 struct xgi_hw_device_info *HwDeviceExtension,
 447                 unsigned long Port, struct vb_device_info *pVBInfo)
 448 {
 449         unsigned char temp, temp1, temp2, temp3, i, j, k;
 450
 451         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 452
 453         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 454         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 455         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 456         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 457
 458         temp2 = 0;
 459         for (i = 0; i < 4; i++) {
 460                 /* CR6B DQS fine tune delay */
 461                 temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
 462                 for (j = 0; j < 4; j++) {
 463                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 464                         temp2 |= temp1;
 465                         xgifb_reg_set(P3d4, 0x6B, temp2);
 466                         /* Insert read command for delay */
 467                         xgifb_reg_get(P3d4, 0x6B);
 468                         temp2 &= 0xF0;
 469                         temp2 += 0x10;
 470                 }
 471         }
 472
 473         temp2 = 0;
 474         for (i = 0; i < 4; i++) {
 475                 /* CR6E DQM fine tune delay */
 476                 temp = pVBInfo->CR6E[pVBInfo->ram_type][i];
 477                 for (j = 0; j < 4; j++) {
 478                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 479                         temp2 |= temp1;
 480                         xgifb_reg_set(P3d4, 0x6E, temp2);
 481                         /* Insert read command for delay */
 482                         xgifb_reg_get(P3d4, 0x6E);
 483                         temp2 &= 0xF0;
 484                         temp2 += 0x10;
 485                 }
 486         }
 487
 488         temp3 = 0;
 489         for (k = 0; k < 4; k++) {
 490                 /* CR6E_D[1:0] select channel */
 491                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 492                 temp2 = 0;
 493                 for (i = 0; i < 8; i++) {
 494                         /* CR6F DQ fine tune delay */
 495                         temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];
 496                         for (j = 0; j < 4; j++) {
 497                                 temp1 = (temp >> (2 * j)) & 0x03;
 498                                 temp2 |= temp1;
 499                                 xgifb_reg_set(P3d4, 0x6F, temp2);
 500                                 /* Insert read command for delay */
 501                                 xgifb_reg_get(P3d4, 0x6F);
 502                                 temp2 &= 0xF8;
 503                                 temp2 += 0x08;
 504                         }
 505                 }
 506                 temp3 += 0x01;
 507         }
 508
 509         xgifb_reg_set(P3d4,
 510                       0x80,
 511                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 512         xgifb_reg_set(P3d4,
 513                       0x81,
 514                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 515
 516         temp2 = 0x80;
 517         /* CR89 terminator type select */
 518         temp = pVBInfo->CR89[pVBInfo->ram_type][0];
 519         for (j = 0; j < 4; j++) {
 520                 temp1 = (temp >> (2 * j)) & 0x03;
 521                 temp2 |= temp1;
 522                 xgifb_reg_set(P3d4, 0x89, temp2);
 523                 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
 524                 temp2 &= 0xF0;
 525                 temp2 += 0x10;
 526         }
 527
 528         temp = pVBInfo->CR89[pVBInfo->ram_type][1];
 529         temp1 = temp & 0x03;
 530         temp2 |= temp1;
 531         xgifb_reg_set(P3d4, 0x89, temp2);
 532
 533         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 534         temp1 = temp & 0x0F;
 535         temp2 = (temp >> 4) & 0x07;
 536         temp3 = temp & 0x80;
 537         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 538         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 539         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 540         xgifb_reg_set(P3d4,
 541                       0x41,
 542                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 543
 544         if (HwDeviceExtension->jChipType == XG27)
 545                 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
 546
 547         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 548                 xgifb_reg_set(P3d4, (0x90 + j),
 549                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 550
 551         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 552                 xgifb_reg_set(P3d4, (0xC3 + j),
 553                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 554
 555         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 556                 xgifb_reg_set(P3d4, (0x8A + j),
 557                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 558
 559         if ((HwDeviceExtension->jChipType == XG41) ||
 560             (HwDeviceExtension->jChipType == XG42))
 561                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 562
 563         xgifb_reg_set(P3d4,
 564                       0x59,
 565                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 566
 567         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 568         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 569         xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
 570         if (pVBInfo->ram_type) {
 571                 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
 572                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 573                 if (HwDeviceExtension->jChipType == XG27)
 574                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 575
 576         } else {
 577                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 578         }
 579         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 580
 581         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 582         if (temp == 0) {
 583                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 584         } else {
 585                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 586                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 587         }
 588         xgifb_reg_set(P3c4,
 589                       0x1B,
 590                       pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
 591 }
 592
 593 static void XGINew_SetDRAMSizingType(int index,
 594                 unsigned short DRAMTYPE_TABLE[][5],
 595                 struct vb_device_info *pVBInfo)
 596 {
 597         unsigned short data;
 598
 599         data = DRAMTYPE_TABLE[index][4];
 600         xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
 601         udelay(15);
 602         /* should delay 50 ns */
 603 }
 604
 605 static unsigned short XGINew_SetDRAMSizeReg(int index,
 606                 unsigned short DRAMTYPE_TABLE[][5],
 607                 struct vb_device_info *pVBInfo)
 608 {
 609         unsigned short data = 0, memsize = 0;
 610         int RankSize;
 611         unsigned char ChannelNo;
 612
 613         RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
 614         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 615         data &= 0x80;
 616
 617         if (data == 0x80)
 618                 RankSize *= 2;
 619
 620         data = 0;
 621
 622         if (XGINew_ChannelAB == 3)
 623                 ChannelNo = 4;
 624         else
 625                 ChannelNo = XGINew_ChannelAB;
 626
 627         if (ChannelNo * RankSize <= 256) {
 628                 while ((RankSize >>= 1) > 0)
 629                         data += 0x10;
 630
 631                 memsize = data >> 4;
 632
 633                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 634                 xgifb_reg_set(pVBInfo->P3c4,
 635                               0x14,
 636                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 637                                (data & 0xF0));
 638
 639                 /* data |= XGINew_ChannelAB << 2; */
 640                 /* data |= (XGINew_DataBusWidth / 64) << 1; */
 641                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 642
 643                 /* should delay */
 644                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 645         }
 646         return memsize;
 647 }
 648
 649 static unsigned short XGINew_SetDRAMSize20Reg(int index,
 650                 unsigned short DRAMTYPE_TABLE[][5],
 651                 struct vb_device_info *pVBInfo)
 652 {
 653         unsigned short data = 0, memsize = 0;
 654         int RankSize;
 655         unsigned char ChannelNo;
 656
 657         RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
 658         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 659         data &= 0x80;
 660
 661         if (data == 0x80)
 662                 RankSize *= 2;
 663
 664         data = 0;
 665
 666         if (XGINew_ChannelAB == 3)
 667                 ChannelNo = 4;
 668         else
 669                 ChannelNo = XGINew_ChannelAB;
 670
 671         if (ChannelNo * RankSize <= 256) {
 672                 while ((RankSize >>= 1) > 0)
 673                         data += 0x10;
 674
 675                 memsize = data >> 4;
 676
 677                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 678                 xgifb_reg_set(pVBInfo->P3c4,
 679                               0x14,
 680                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 681                                 (data & 0xF0));
 682                 udelay(15);
 683
 684                 /* data |= XGINew_ChannelAB << 2; */
 685                 /* data |= (XGINew_DataBusWidth / 64) << 1; */
 686                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 687
 688                 /* should delay */
 689                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 690         }
 691         return memsize;
 692 }
 693
 694 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 695                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 696 {
 697         int i;
 698         unsigned long Position = 0;
 699         void __iomem *fbaddr = pVBInfo->FBAddr;
 700
 701         writel(Position, fbaddr + Position);
 702
 703         for (i = StartAddr; i <= StopAddr; i++) {
 704                 Position = 1 << i;
 705                 writel(Position, fbaddr + Position);
 706         }
 707
 708         udelay(500); /* [Vicent] 2004/04/16.
 709                         Fix #1759 Memory Size error in Multi-Adapter. */
 710
 711         Position = 0;
 712
 713         if (readl(fbaddr + Position) != Position)
 714                 return 0;
 715
 716         for (i = StartAddr; i <= StopAddr; i++) {
 717                 Position = 1 << i;
 718                 if (readl(fbaddr + Position) != Position)
 719                         return 0;
 720         }
 721         return 1;
 722 }
 723
 724 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 725 {
 726         unsigned char data;
 727
 728         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 729
 730         if ((data & 0x10) == 0) {
 731                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 732                 data = (data & 0x02) >> 1;
 733                 return data;
 734         } else {
 735                 return data & 0x01;
 736         }
 737 }
 738
 739 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 740                 struct vb_device_info *pVBInfo)
 741 {
 742         unsigned char data;
 743
 744         switch (HwDeviceExtension->jChipType) {
 745         case XG20:
 746         case XG21:
 747                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 748                 data = data & 0x01;
 749                 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
 750
 751                 if (data == 0) { /* Single_32_16 */
 752
 753                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 754                                         > 0x1000000) {
 755
 756                                 XGINew_DataBusWidth = 32; /* 32 bits */
 757                                 /* 22bit + 2 rank + 32bit */
 758                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 759                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 760                                 udelay(15);
 761
 762                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 763                                         return;
 764
 765                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 766                                     0x800000) {
 767                                         /* 22bit + 1 rank + 32bit */
 768                                         xgifb_reg_set(pVBInfo->P3c4,
 769                                                       0x13,
 770                                                       0x31);
 771                                         xgifb_reg_set(pVBInfo->P3c4,
 772                                                       0x14,
 773                                                       0x42);
 774                                         udelay(15);
 775
 776                                         if (XGINew_ReadWriteRest(23,
 777                                                                  23,
 778                                                                  pVBInfo) == 1)
 779                                                 return;
 780                                 }
 781                         }
 782
 783                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 784                             0x800000) {
 785                                 XGINew_DataBusWidth = 16; /* 16 bits */
 786                                 /* 22bit + 2 rank + 16bit */
 787                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 788                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 789                                 udelay(15);
 790
 791                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 792                                         return;
 793                                 else
 794                                         xgifb_reg_set(pVBInfo->P3c4,
 795                                                       0x13,
 796                                                       0x31);
 797                                 udelay(15);
 798                         }
 799
 800                 } else { /* Dual_16_8 */
 801                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 802                             0x800000) {
 803                                 XGINew_DataBusWidth = 16; /* 16 bits */
 804                                 /* (0x31:12x8x2) 22bit + 2 rank */
 805                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 806                                 /* 0x41:16Mx16 bit*/
 807                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 808                                 udelay(15);
 809
 810                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 811                                         return;
 812
 813                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 814                                     0x400000) {
 815                                         /* (0x31:12x8x2) 22bit + 1 rank */
 816                                         xgifb_reg_set(pVBInfo->P3c4,
 817                                                       0x13,
 818                                                       0x31);
 819                                         /* 0x31:8Mx16 bit*/
 820                                         xgifb_reg_set(pVBInfo->P3c4,
 821                                                       0x14,
 822                                                       0x31);
 823                                         udelay(15);
 824
 825                                         if (XGINew_ReadWriteRest(22,
 826                                                                  22,
 827                                                                  pVBInfo) == 1)
 828                                                 return;
 829                                 }
 830                         }
 831
 832                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 833                             0x400000) {
 834                                 XGINew_DataBusWidth = 8; /* 8 bits */
 835                                 /* (0x31:12x8x2) 22bit + 2 rank */
 836                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 837                                 /* 0x30:8Mx8 bit*/
 838                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 839                                 udelay(15);
 840
 841                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 842                                         return;
 843                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 844                                         xgifb_reg_set(pVBInfo->P3c4,
 845                                                       0x13,
 846                                                       0x31);
 847                                 udelay(15);
 848                         }
 849                 }
 850                 break;
 851
 852         case XG27:
 853                 XGINew_DataBusWidth = 16; /* 16 bits */
 854                 XGINew_ChannelAB = 1; /* Single channel */
 855                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 856                 break;
 857         case XG41:
 858                 if (XGINew_CheckFrequence(pVBInfo) == 1) {
 859                         XGINew_DataBusWidth = 32; /* 32 bits */
 860                         XGINew_ChannelAB = 3; /* Quad Channel */
 861                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 862                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 863
 864                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 865                                 return;
 866
 867                         XGINew_ChannelAB = 2; /* Dual channels */
 868                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 869
 870                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 871                                 return;
 872
 873                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
 874
 875                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 876                                 return;
 877
 878                         XGINew_ChannelAB = 3;
 879                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 880                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 881
 882                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 883                                 return;
 884
 885                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 886
 887                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
 888                                 return;
 889                         else
 890                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
 891                 } else { /* DDR */
 892                         XGINew_DataBusWidth = 64; /* 64 bits */
 893                         XGINew_ChannelAB = 2; /* Dual channels */
 894                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 895                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 896
 897                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
 898                                 return;
 899
 900                         XGINew_ChannelAB = 1; /* Single channels */
 901                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 902
 903                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 904                                 return;
 905
 906                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
 907
 908                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 909                                 return;
 910
 911                         XGINew_ChannelAB = 2; /* Dual channels */
 912                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 913                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 914
 915                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 916                                 return;
 917
 918                         XGINew_ChannelAB = 1; /* Single channels */
 919                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 920
 921                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
 922                                 return;
 923                         else
 924                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
 925                 }
 926
 927                 break;
 928
 929         case XG42:
 930                 /*
 931                  XG42 SR14 D[3] Reserve
 932                  D[2] = 1, Dual Channel
 933                  = 0, Single Channel
 934
 935                  It's Different from Other XG40 Series.
 936                  */
 937                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 938                         XGINew_DataBusWidth = 32; /* 32 bits */
 939                         XGINew_ChannelAB = 2; /* 2 Channel */
 940                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 941                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 942
 943                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 944                                 return;
 945
 946                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 947                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 948                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 949                                 return;
 950
 951                         XGINew_ChannelAB = 1; /* Single Channel */
 952                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 953                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 954
 955                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 956                                 return;
 957                         else {
 958                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 959                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 960                         }
 961                 } else { /* DDR */
 962                         XGINew_DataBusWidth = 64; /* 64 bits */
 963                         XGINew_ChannelAB = 1; /* 1 channels */
 964                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 965                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 966
 967                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 968                                 return;
 969                         else {
 970                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 971                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 972                         }
 973                 }
 974
 975                 break;
 976
 977         default: /* XG40 */
 978
 979                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 980                         XGINew_DataBusWidth = 32; /* 32 bits */
 981                         XGINew_ChannelAB = 3;
 982                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 983                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 984
 985                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 986                                 return;
 987
 988                         XGINew_ChannelAB = 2; /* 2 channels */
 989                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 990
 991                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 992                                 return;
 993
 994                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 995                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 996
 997                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 998                                 XGINew_ChannelAB = 3; /* 4 channels */
 999                         } else {
1000                                 XGINew_ChannelAB = 2; /* 2 channels */
1001                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
1002                         }
1003                 } else { /* DDR */
1004                         XGINew_DataBusWidth = 64; /* 64 bits */
1005                         XGINew_ChannelAB = 2; /* 2 channels */
1006                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
1007                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
1008
1009                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
1010                                 return;
1011                         } else {
1012                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
1013                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
1014                         }
1015                 }
1016                 break;
1017         }
1018 }
1019
1020 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1021                 struct vb_device_info *pVBInfo)
1022 {
1023         int i;
1024         unsigned short memsize, addr;
1025
1026         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1027         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
1028         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
1029
1030         if (HwDeviceExtension->jChipType >= XG20) {
1031                 for (i = 0; i < 12; i++) {
1032                         XGINew_SetDRAMSizingType(i,
1033                                                  XGINew_DDRDRAM_TYPE20,
1034                                                  pVBInfo);
1035                         memsize = XGINew_SetDRAMSize20Reg(i,
1036                                                           XGINew_DDRDRAM_TYPE20,
1037                                                           pVBInfo);
1038                         if (memsize == 0)
1039                                 continue;
1040
1041                         addr = memsize + (XGINew_ChannelAB - 2) + 20;
1042                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1043                             (unsigned long) (1 << addr))
1044                                 continue;
1045
1046                         if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1047                                 return 1;
1048                 }
1049         } else {
1050                 for (i = 0; i < 4; i++) {
1051                         XGINew_SetDRAMSizingType(i,
1052                                                  XGINew_DDRDRAM_TYPE340,
1053                                                  pVBInfo);
1054                         memsize = XGINew_SetDRAMSizeReg(i,
1055                                                         XGINew_DDRDRAM_TYPE340,
1056                                                         pVBInfo);
1057
1058                         if (memsize == 0)
1059                                 continue;
1060
1061                         addr = memsize + (XGINew_ChannelAB - 2) + 20;
1062                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1063                             (unsigned long) (1 << addr))
1064                                 continue;
1065
1066                         if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1067                                 return 1;
1068                 }
1069         }
1070         return 0;
1071 }
1072
1073 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1074                 struct vb_device_info *pVBInfo)
1075 {
1076         unsigned short data;
1077
1078         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1079         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1080
1081         XGISetModeNew(HwDeviceExtension, 0x2e);
1082
1083         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1084         /* disable read cache */
1085         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1086         XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1087
1088         /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1089         /* data |= 0x20 ; */
1090         /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1091         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1092         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1093         /* enable read cache */
1094         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1095 }
1096
1097 static void ReadVBIOSTablData(unsigned char ChipType,
1098                               struct vb_device_info *pVBInfo)
1099 {
1100         volatile unsigned char *pVideoMemory =
1101                 (unsigned char *) pVBInfo->ROMAddr;
1102         unsigned long i;
1103         unsigned char j, k;
1104         /* Volari customize data area end */
1105
1106         if (ChipType == XG21) {
1107                 pVBInfo->IF_DEF_LVDS = 0;
1108                 if (pVideoMemory[0x65] & 0x1) {
1109                         pVBInfo->IF_DEF_LVDS = 1;
1110                         i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1111                         j = pVideoMemory[i - 1];
1112                         if (j != 0xff) {
1113                                 k = 0;
1114                                 do {
1115                                         pVBInfo->XG21_LVDSCapList[k].
1116                                                  LVDS_Capability
1117                                                 = pVideoMemory[i] |
1118                                                  (pVideoMemory[i + 1] << 8);
1119                                         pVBInfo->XG21_LVDSCapList[k].LVDSHT
1120                                                 = pVideoMemory[i + 2] |
1121                                                   (pVideoMemory[i + 3] << 8);
1122                                         pVBInfo->XG21_LVDSCapList[k].LVDSVT
1123                                                 = pVideoMemory[i + 4] |
1124                                                   (pVideoMemory[i + 5] << 8);
1125                                         pVBInfo->XG21_LVDSCapList[k].LVDSHDE
1126                                                 = pVideoMemory[i + 6] |
1127                                                   (pVideoMemory[i + 7] << 8);
1128                                         pVBInfo->XG21_LVDSCapList[k].LVDSVDE
1129                                                 = pVideoMemory[i + 8] |
1130                                                   (pVideoMemory[i + 9] << 8);
1131                                         pVBInfo->XG21_LVDSCapList[k].LVDSHFP
1132                                                 = pVideoMemory[i + 10] |
1133                                                   (pVideoMemory[i + 11] << 8);
1134                                         pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1135                                                 = pVideoMemory[i + 12] |
1136                                                   (pVideoMemory[i + 13] << 8);
1137                                         pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1138                                                 = pVideoMemory[i + 14] |
1139                                                   (pVideoMemory[i + 15] << 8);
1140                                         pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1141                                                 = pVideoMemory[i + 16] |
1142                                                   (pVideoMemory[i + 17] << 8);
1143                                         pVBInfo->XG21_LVDSCapList[k].VCLKData1
1144                                                 = pVideoMemory[i + 18];
1145                                         pVBInfo->XG21_LVDSCapList[k].VCLKData2
1146                                                 = pVideoMemory[i + 19];
1147                                         pVBInfo->XG21_LVDSCapList[k].PSC_S1
1148                                                 = pVideoMemory[i + 20];
1149                                         pVBInfo->XG21_LVDSCapList[k].PSC_S2
1150                                                 = pVideoMemory[i + 21];
1151                                         pVBInfo->XG21_LVDSCapList[k].PSC_S3
1152                                                 = pVideoMemory[i + 22];
1153                                         pVBInfo->XG21_LVDSCapList[k].PSC_S4
1154                                                 = pVideoMemory[i + 23];
1155                                         pVBInfo->XG21_LVDSCapList[k].PSC_S5
1156                                                 = pVideoMemory[i + 24];
1157                                         i += 25;
1158                                         j--;
1159                                         k++;
1160                                 } while ((j > 0) &&
1161                                          (k < (sizeof(XGI21_LCDCapList) /
1162                                                sizeof(struct
1163                                                         XGI21_LVDSCapStruct))));
1164                         } else {
1165                                 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1166                                                 = pVideoMemory[i] |
1167                                                   (pVideoMemory[i + 1] << 8);
1168                                 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1169                                                 = pVideoMemory[i + 2] |
1170                                                   (pVideoMemory[i + 3] << 8);
1171                                 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1172                                                 = pVideoMemory[i + 4] |
1173                                                   (pVideoMemory[i + 5] << 8);
1174                                 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1175                                                 = pVideoMemory[i + 6] |
1176                                                   (pVideoMemory[i + 7] << 8);
1177                                 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1178                                                 = pVideoMemory[i + 8] |
1179                                                   (pVideoMemory[i + 9] << 8);
1180                                 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1181                                                 = pVideoMemory[i + 10] |
1182                                                   (pVideoMemory[i + 11] << 8);
1183                                 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1184                                                 = pVideoMemory[i + 12] |
1185                                                   (pVideoMemory[i + 13] << 8);
1186                                 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1187                                                 = pVideoMemory[i + 14] |
1188                                                   (pVideoMemory[i + 15] << 8);
1189                                 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1190                                                 = pVideoMemory[i + 16] |
1191                                                   (pVideoMemory[i + 17] << 8);
1192                                 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1193                                                 = pVideoMemory[i + 18];
1194                                 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1195                                                 = pVideoMemory[i + 19];
1196                                 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1197                                                 = pVideoMemory[i + 20];
1198                                 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1199                                                 = pVideoMemory[i + 21];
1200                                 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1201                                                 = pVideoMemory[i + 22];
1202                                 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1203                                                 = pVideoMemory[i + 23];
1204                                 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1205                                                 = pVideoMemory[i + 24];
1206                         }
1207                 }
1208         }
1209 }
1210
1211 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1212                 struct vb_device_info *pVBInfo)
1213 {
1214         unsigned short tempbx = 0, temp, tempcx, CR3CData;
1215
1216         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1217
1218         if (temp & Monitor1Sense)
1219                 tempbx |= ActiveCRT1;
1220         if (temp & LCDSense)
1221                 tempbx |= ActiveLCD;
1222         if (temp & Monitor2Sense)
1223                 tempbx |= ActiveCRT2;
1224         if (temp & TVSense) {
1225                 tempbx |= ActiveTV;
1226                 if (temp & AVIDEOSense)
1227                         tempbx |= (ActiveAVideo << 8);
1228                 if (temp & SVIDEOSense)
1229                         tempbx |= (ActiveSVideo << 8);
1230                 if (temp & SCARTSense)
1231                         tempbx |= (ActiveSCART << 8);
1232                 if (temp & HiTVSense)
1233                         tempbx |= (ActiveHiTV << 8);
1234                 if (temp & YPbPrSense)
1235                         tempbx |= (ActiveYPbPr << 8);
1236         }
1237
1238         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1239         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1240
1241         if (tempbx & tempcx) {
1242                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1243                 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1244                         tempcx = 0x1FF0;
1245                         if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1246                                 tempbx = 0x1FF0;
1247                 }
1248         } else {
1249                 tempcx = 0x1FF0;
1250                 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1251                         tempbx = 0x1FF0;
1252         }
1253
1254         tempbx &= tempcx;
1255         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1256         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1257 }
1258
1259 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1260                 struct vb_device_info *pVBInfo)
1261 {
1262         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1263
1264         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1265         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1266         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1267
1268         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1269                 if (temp & ActiveCRT2)
1270                         tempcl = SetCRT2ToRAMDAC;
1271         }
1272
1273         if (temp & ActiveLCD) {
1274                 tempcl |= SetCRT2ToLCD;
1275                 if (temp & DriverMode) {
1276                         if (temp & ActiveTV) {
1277                                 tempch = SetToLCDA | EnableDualEdge;
1278                                 temp ^= SetCRT2ToLCD;
1279
1280                                 if ((temp >> 8) & ActiveAVideo)
1281                                         tempcl |= SetCRT2ToAVIDEO;
1282                                 if ((temp >> 8) & ActiveSVideo)
1283                                         tempcl |= SetCRT2ToSVIDEO;
1284                                 if ((temp >> 8) & ActiveSCART)
1285                                         tempcl |= SetCRT2ToSCART;
1286
1287                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1288                                         if ((temp >> 8) & ActiveHiTV)
1289                                                 tempcl |= SetCRT2ToHiVisionTV;
1290                                 }
1291
1292                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1293                                         if ((temp >> 8) & ActiveYPbPr)
1294                                                 tempch |= SetYPbPr;
1295                                 }
1296                         }
1297                 }
1298         } else {
1299                 if ((temp >> 8) & ActiveAVideo)
1300                         tempcl |= SetCRT2ToAVIDEO;
1301                 if ((temp >> 8) & ActiveSVideo)
1302                         tempcl |= SetCRT2ToSVIDEO;
1303                 if ((temp >> 8) & ActiveSCART)
1304                         tempcl |= SetCRT2ToSCART;
1305
1306                 if (pVBInfo->IF_DEF_HiVision == 1) {
1307                         if ((temp >> 8) & ActiveHiTV)
1308                                 tempcl |= SetCRT2ToHiVisionTV;
1309                 }
1310
1311                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1312                         if ((temp >> 8) & ActiveYPbPr)
1313                                 tempch |= SetYPbPr;
1314                 }
1315         }
1316
1317         tempcl |= SetSimuScanMode;
1318         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1319                         || (temp & ActiveCRT2)))
1320                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1321         if ((temp & ActiveLCD) && (temp & ActiveTV))
1322                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1323         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1324
1325         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1326         CR31Data &= ~(SetNotSimuMode >> 8);
1327         if (!(temp & ActiveCRT1))
1328                 CR31Data |= (SetNotSimuMode >> 8);
1329         CR31Data &= ~(DisableCRT2Display >> 8);
1330         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1331                 CR31Data |= (DisableCRT2Display >> 8);
1332         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1333
1334         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1335         CR38Data &= ~SetYPbPr;
1336         CR38Data |= tempch;
1337         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1338
1339 }
1340
1341 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1342                 struct vb_device_info *pVBInfo)
1343 {
1344         unsigned char Temp;
1345         volatile unsigned char *pVideoMemory =
1346                         (unsigned char *) pVBInfo->ROMAddr;
1347
1348         pVBInfo->IF_DEF_LVDS = 0;
1349
1350 #if 1
1351         if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1352                 pVBInfo->IF_DEF_LVDS = 1;
1353                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1354                 /* LVDS on chip */
1355                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1356         } else {
1357 #endif
1358                 /* Enable GPIOA/B read  */
1359                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1360                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1361                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1362                         XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1363                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1364                         /* Enable read GPIOF */
1365                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1366                         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1367                         if (!Temp)
1368                                 xgifb_reg_and_or(pVBInfo->P3d4,
1369                                                  0x38,
1370                                                  ~0xE0,
1371                                                  0x80); /* TMDS on chip */
1372                         else
1373                                 xgifb_reg_and_or(pVBInfo->P3d4,
1374                                                  0x38,
1375                                                  ~0xE0,
1376                                                  0xA0); /* Only DVO on chip */
1377                         /* Disable read GPIOF */
1378                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1379                 }
1380 #if 1
1381         }
1382 #endif
1383 }
1384
1385 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1386                 struct vb_device_info *pVBInfo)
1387 {
1388         unsigned char Temp, bCR4A;
1389
1390         pVBInfo->IF_DEF_LVDS = 0;
1391         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1392         /* Enable GPIOA/B/C read  */
1393         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1394         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1395         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1396
1397         if (Temp <= 0x02) {
1398                 pVBInfo->IF_DEF_LVDS = 1;
1399                 /* LVDS setting */
1400                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1401                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1402         } else {
1403                 /* TMDS/DVO setting */
1404                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1405         }
1406         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1407
1408 }
1409
1410 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1411 {
1412         unsigned char CR38, CR4A, temp;
1413
1414         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1415         /* enable GPIOE read */
1416         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1417         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1418         temp = 0;
1419         if ((CR38 & 0xE0) > 0x80) {
1420                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1421                 temp &= 0x08;
1422                 temp >>= 3;
1423         }
1424
1425         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1426
1427         return temp;
1428 }
1429
1430 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1431 {
1432         unsigned char CR4A, temp;
1433
1434         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1435         /* enable GPIOA/B/C read */
1436         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1437         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1438         if (temp <= 2)
1439                 temp &= 0x03;
1440         else
1441                 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1442
1443         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1444
1445         return temp;
1446 }
1447
1448 unsigned char XGIInitNew(struct pci_dev *pdev)
1449 {
1450         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1451         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1452         struct vb_device_info VBINF;
1453         struct vb_device_info *pVBInfo = &VBINF;
1454         unsigned char i, temp = 0, temp1;
1455         /* VBIOSVersion[5]; */
1456         volatile unsigned char *pVideoMemory;
1457
1458         /* unsigned long j, k; */
1459
1460         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1461
1462         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1463
1464         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1465
1466         pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1467
1468         /* Newdebugcode(0x99); */
1469
1470
1471         /* if (pVBInfo->ROMAddr == 0) */
1472         /* return(0); */
1473
1474         if (pVBInfo->FBAddr == NULL) {
1475                 printk("\n pVBInfo->FBAddr == 0 ");
1476                 return 0;
1477         }
1478         printk("1");
1479         if (pVBInfo->BaseAddr == 0) {
1480                 printk("\npVBInfo->BaseAddr == 0 ");
1481                 return 0;
1482         }
1483         printk("2");
1484
1485         outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1486
1487         pVBInfo->ISXPDOS = 0;
1488         printk("3");
1489
1490         printk("4");
1491
1492         /* VBIOSVersion[4] = 0x0; */
1493
1494         /* 09/07/99 modify by domao */
1495
1496         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1497         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1498         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1499         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1500         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1501         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1502         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1503         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1504         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1505         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1506         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1507         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1508         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1509         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1510         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1511         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1512         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1513         printk("5");
1514
1515         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1516                 /* Run XGI_GetVBType before InitTo330Pointer */
1517                 XGI_GetVBType(pVBInfo);
1518
1519         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1520
1521         /* ReadVBIOSData */
1522         ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1523
1524         /* 1.Openkey */
1525         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1526         printk("6");
1527
1528         /* GetXG21Sense (GPIO) */
1529         if (HwDeviceExtension->jChipType == XG21)
1530                 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1531
1532         if (HwDeviceExtension->jChipType == XG27)
1533                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1534
1535         printk("7");
1536
1537         /* 2.Reset Extended register */
1538
1539         for (i = 0x06; i < 0x20; i++)
1540                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1541
1542         for (i = 0x21; i <= 0x27; i++)
1543                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1544
1545         /* for(i = 0x06; i <= 0x27; i++) */
1546         /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1547
1548         printk("8");
1549
1550         for (i = 0x31; i <= 0x3B; i++)
1551                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1552         printk("9");
1553
1554         /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1555         if (HwDeviceExtension->jChipType == XG42)
1556                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1557
1558         /* for (i = 0x30; i <= 0x3F; i++) */
1559         /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1560
1561         for (i = 0x79; i <= 0x7C; i++)
1562                 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1563
1564         printk("10");
1565
1566         if (HwDeviceExtension->jChipType >= XG20)
1567                 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1568
1569         /* 3.SetMemoryClock
1570
1571         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1572         */
1573
1574         printk("11");
1575
1576         /* 4.SetDefExt1Regs begin */
1577         xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1578         if (HwDeviceExtension->jChipType == XG27) {
1579                 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1580                 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1581         }
1582         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1583         xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1584         /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1585         /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1586         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1587         /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1588         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1589         if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1590                 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1591
1592         /* SR11 = 0x0F; */
1593         /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1594
1595         printk("12");
1596
1597         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1598                 u32 Temp;
1599
1600                 /* Set AGP Rate */
1601                 /*
1602                 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1603                 temp1 &= 0x02;
1604                 if (temp1 == 0x02) {
1605                         outl(0x80000000, 0xcf8);
1606                         ChipsetID = inl(0x0cfc);
1607                         outl(0x8000002C, 0xcf8);
1608                         VendorID = inl(0x0cfc);
1609                         VendorID &= 0x0000FFFF;
1610                         outl(0x8001002C, 0xcf8);
1611                         GraphicVendorID = inl(0x0cfc);
1612                         GraphicVendorID &= 0x0000FFFF;
1613
1614                         if (ChipsetID == 0x7301039)
1615                                 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1616
1617                         ChipsetID &= 0x0000FFFF;
1618
1619                         if ((ChipsetID == 0x700E) ||
1620                             (ChipsetID == 0x1022) ||
1621                             (ChipsetID == 0x1106) ||
1622                             (ChipsetID == 0x10DE)) {
1623                                 if (ChipsetID == 0x1106) {
1624                                         if ((VendorID == 0x1019) &&
1625                                             (GraphicVendorID == 0x1019))
1626                                                 xgifb_reg_set(pVBInfo->P3d4,
1627                                                               0x5F,
1628                                                               0x0D);
1629                                         else
1630                                                 xgifb_reg_set(pVBInfo->P3d4,
1631                                                               0x5F,
1632                                                               0x0B);
1633                                 } else {
1634                                         xgifb_reg_set(pVBInfo->P3d4,
1635                                                       0x5F,
1636                                                       0x0B);
1637                                 }
1638                         }
1639                 }
1640                 */
1641
1642                 printk("13");
1643
1644                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1645                 for (i = 0x47; i <= 0x4C; i++)
1646                         xgifb_reg_set(pVBInfo->P3d4,
1647                                       i,
1648                                       pVBInfo->AGPReg[i - 0x47]);
1649
1650                 for (i = 0x70; i <= 0x71; i++)
1651                         xgifb_reg_set(pVBInfo->P3d4,
1652                                       i,
1653                                       pVBInfo->AGPReg[6 + i - 0x70]);
1654
1655                 for (i = 0x74; i <= 0x77; i++)
1656                         xgifb_reg_set(pVBInfo->P3d4,
1657                                       i,
1658                                       pVBInfo->AGPReg[8 + i - 0x74]);
1659                 /* Set AGP customize registers (in SetDefAGPRegs) End */
1660                 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1661                 /*        outl(0x80000000, 0xcf8); */
1662                 /*        ChipsetID = inl(0x0cfc); */
1663                 /*        if (ChipsetID == 0x25308086) */
1664                 /*            xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1665
1666                 pci_read_config_dword(pdev, 0x50, &Temp);
1667                 Temp >>= 20;
1668                 Temp &= 0xF;
1669
1670                 if (Temp == 1)
1671                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1672                 printk("14");
1673         } /* != XG20 */
1674
1675         /* Set PCI */
1676         xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1677         xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1678         xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1679         printk("15");
1680
1681         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1682                 /* Set VB */
1683                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1684                 /* alan, disable VideoCapture */
1685                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1686                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1687                 /* chk if BCLK>=100MHz */
1688                 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1689                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1690
1691                 xgifb_reg_set(pVBInfo->Part1Port,
1692                               0x02,
1693                               (*pVBInfo->pCRT2Data_1_2));
1694
1695                 printk("16");
1696
1697                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1698         } /* != XG20 */
1699
1700         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1701
1702         if ((HwDeviceExtension->jChipType == XG42) &&
1703             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1704                 /* Not DDR */
1705                 xgifb_reg_set(pVBInfo->P3c4,
1706                               0x31,
1707                               (*pVBInfo->pSR31 & 0x3F) | 0x40);
1708                 xgifb_reg_set(pVBInfo->P3c4,
1709                               0x32,
1710                               (*pVBInfo->pSR32 & 0xFC) | 0x01);
1711         } else {
1712                 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1713                 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1714         }
1715         xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1716         printk("17");
1717
1718         /*
1719          SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4);    */
1720
1721         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1722                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1723                         if (pVBInfo->IF_DEF_LVDS == 0) {
1724                                 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1725                                 xgifb_reg_set(pVBInfo->Part4Port,
1726                                               0x0D,
1727                                               *pVBInfo->pCRT2Data_4_D);
1728                                 xgifb_reg_set(pVBInfo->Part4Port,
1729                                               0x0E,
1730                                               *pVBInfo->pCRT2Data_4_E);
1731                                 xgifb_reg_set(pVBInfo->Part4Port,
1732                                               0x10,
1733                                               *pVBInfo->pCRT2Data_4_10);
1734                                 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1735                         }
1736
1737                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1738                 }
1739         } /* != XG20 */
1740         printk("18");
1741
1742         printk("181");
1743
1744         printk("182");
1745
1746         XGI_SenseCRT1(pVBInfo);
1747
1748         printk("183");
1749         /* XGINew_DetectMonitor(HwDeviceExtension); */
1750         if (HwDeviceExtension->jChipType == XG21) {
1751                 printk("186");
1752
1753                 xgifb_reg_and_or(pVBInfo->P3d4,
1754                                  0x32,
1755                                  ~Monitor1Sense,
1756                                  Monitor1Sense); /* Z9 default has CRT */
1757                 temp = GetXG21FPBits(pVBInfo);
1758                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1759                 printk("187");
1760
1761         }
1762         if (HwDeviceExtension->jChipType == XG27) {
1763                 xgifb_reg_and_or(pVBInfo->P3d4,
1764                                  0x32,
1765                                  ~Monitor1Sense,
1766                                  Monitor1Sense); /* Z9 default has CRT */
1767                 temp = GetXG27FPBits(pVBInfo);
1768                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1769         }
1770         printk("19");
1771
1772         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1773
1774         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1775                                          pVBInfo->P3d4,
1776                                          pVBInfo);
1777
1778         printk("20");
1779         XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1780         printk("21");
1781
1782         printk("22");
1783
1784         /* SetDefExt2Regs begin */
1785         /*
1786         AGP = 1;
1787         temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1788         temp &= 0x30;
1789         if (temp == 0x30)
1790                 AGP = 0;
1791
1792         if (AGP == 0)
1793                 *pVBInfo->pSR21 &= 0xEF;
1794
1795         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1796         if (AGP == 1)
1797                 *pVBInfo->pSR22 &= 0x20;
1798         xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1799         */
1800         /* base = 0x80000000; */
1801         /* OutPortLong(0xcf8, base); */
1802         /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1803         /* if (Temp == 0x1039) { */
1804         xgifb_reg_set(pVBInfo->P3c4,
1805                       0x22,
1806                       (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1807         /* } else { */
1808         /*      xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1809         /* } */
1810
1811         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1812
1813         printk("23");
1814
1815         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1816         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1817
1818         printk("24");
1819
1820         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1821         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1822         printk("25");
1823
1824         return 1;
1825 } /* end of init */