1 #ifndef __WINBOND_WB35REG_S_H
2 #define __WINBOND_WB35REG_S_H
4 #include <linux/spinlock.h>
5 #include <linux/types.h>
6 #include <asm/atomic.h>
8 /* =========================================================================
10 * HAL setting function
12 * ========================================
13 * |Uxx| |Dxx| |Mxx| |BB| |RF|
14 * ========================================
16 * Wb35Reg_Read Wb35Reg_Write
18 * ----------------------------------------
19 * WbUsb_CallUSBDASync supplied By WbUsb module
20 * ==========================================================================
22 #define GetBit(dwData, i) (dwData & (0x00000001 << i))
23 #define SetBit(dwData, i) (dwData | (0x00000001 << i))
24 #define ClearBit(dwData, i) (dwData & ~(0x00000001 << i))
26 #define IGNORE_INCREMENT 0
27 #define AUTO_INCREMENT 0
28 #define NO_INCREMENT 1
29 #define REG_DIRECTION(_x, _y) ((_y)->DIRECT == 0 ? usb_rcvctrlpipe(_x, 0) : usb_sndctrlpipe(_x, 0))
30 #define REG_BUF_SIZE(_x) ((_x)->bRequest == 0x04 ? cpu_to_le16((_x)->wLength) : 4)
32 #define BB48_DEFAULT_AL2230_11B 0x0033447c
33 #define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF
34 #define BB48_DEFAULT_AL2230_11G 0x00332C1B
35 #define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF
38 #define BB48_DEFAULT_WB242_11B 0x00292315 /* backoff 2dB */
39 #define BB4C_DEFAULT_WB242_11B 0x0800FEFF /* backoff 2dB */
40 #define BB48_DEFAULT_WB242_11G 0x00453B24
41 #define BB4C_DEFAULT_WB242_11G 0x0E00FEFF
44 * ====================================
45 * Default setting for Mxx
46 * ====================================
48 #define DEFAULT_CWMIN 31 /* (M2C) CWmin. Its value is in the range 0-31. */
49 #define DEFAULT_CWMAX 1023 /* (M2C) CWmax. Its value is in the range 0-1023. */
50 #define DEFAULT_AID 1 /* (M34) AID. Its value is in the range 1-2007. */
52 #ifdef _USE_FALLBACK_RATE_
53 #define DEFAULT_RATE_RETRY_LIMIT 2 /* (M38) as named */
55 #define DEFAULT_RATE_RETRY_LIMIT 7 /* (M38) as named */
58 #define DEFAULT_LONG_RETRY_LIMIT 7 /* (M38) LongRetryLimit. Its value is in the range 0-15. */
59 #define DEFAULT_SHORT_RETRY_LIMIT 7 /* (M38) ShortRetryLimit. Its value is in the range 0-15. */
60 #define DEFAULT_PIFST 25 /* (M3C) PIFS Time. Its value is in the range 0-65535. */
61 #define DEFAULT_EIFST 354 /* (M3C) EIFS Time. Its value is in the range 0-1048575. */
62 #define DEFAULT_DIFST 45 /* (M3C) DIFS Time. Its value is in the range 0-65535. */
63 #define DEFAULT_SIFST 5 /* (M3C) SIFS Time. Its value is in the range 0-65535. */
64 #define DEFAULT_OSIFST 10 /* (M3C) Original SIFS Time. Its value is in the range 0-15. */
65 #define DEFAULT_ATIMWD 0 /* (M40) ATIM Window. Its value is in the range 0-65535. */
66 #define DEFAULT_SLOT_TIME 20 /* (M40) ($) SlotTime. Its value is in the range 0-255. */
67 #define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 /* (M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. */
68 #define DEFAULT_BEACON_INTERVAL 500 /* (M48) Beacon Interval. Its value is in the range 0-65535. */
69 #define DEFAULT_PROBE_DELAY_TIME 200 /* (M48) Probe Delay Time. Its value is in the range 0-65535. */
70 #define DEFAULT_PROTOCOL_VERSION 0 /* (M4C) */
71 #define DEFAULT_MAC_POWER_STATE 2 /* (M4C) 2: MAC at power active */
72 #define DEFAULT_DTIM_ALERT_TIME 0
75 struct wb35_reg_queue {
83 u8 RESERVED[4]; /* space reserved for communication */
84 u16 INDEX; /* For storing the register index */
85 u8 RESERVED_VALID; /* Indicate whether the RESERVED space is valid at this command. */
86 u8 DIRECT; /* 0:In 1:Out */
90 * ====================================
91 * Internal variable for module
92 * ====================================
94 #define MAX_SQ3_FILTER_SIZE 5
97 * ============================
98 * Register Bank backup
99 * ============================
101 u32 U1B0; /* bit16 record the h/w radio on/off status */
102 u32 U1BC_LEDConfigure;
107 u32 M04_MulticastAddress1;
108 u32 M08_MulticastAddress2;
110 u8 Multicast[8]; /* contents of card multicast registers */
126 u32 M78_ERPInformation;
133 /* Baseband register */
134 u32 BB0C; /* Used for LNA calculation */
136 u32 BB30; /* 11b acquisition control register */
140 u32 BB50; /* mode control register */
142 u32 BB58; /* IQ_ALPHA */
143 u32 BB5C; /* For test */
144 u32 BB60; /* for WTO read value */
147 spinlock_t EP0VM_spin_lock; /* 4B */
148 u32 EP0VM_status; /* $$ */
149 struct wb35_reg_queue *reg_first;
150 struct wb35_reg_queue *reg_last;
151 atomic_t RegFireCount;
153 /* Hardware status */
157 * 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
158 * 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
160 * 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
161 * 48 ~ 255 ARE RESERVED.
163 u8 EEPROMRegion; /* Region setting in EEPROM */
165 u32 SyncIoPause; /* If user use the Sync Io to access Hw, then pause the async access */
167 u8 LNAValue[4]; /* Table for speed up running */
168 u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];