2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * Derived from ca91c042.c by Michael Wyrick
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/module.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/pci.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/poll.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
31 #include <asm/uaccess.h>
34 #include "../vme_bridge.h"
35 #include "vme_ca91cx42.h"
37 static int __init ca91cx42_init(void);
38 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
39 static void ca91cx42_remove(struct pci_dev *);
40 static void __exit ca91cx42_exit(void);
42 /* Module parameters */
45 static char driver_name[] = "vme_ca91cx42";
47 static const struct pci_device_id ca91cx42_ids[] = {
48 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
52 static struct pci_driver ca91cx42_driver = {
54 .id_table = ca91cx42_ids,
55 .probe = ca91cx42_probe,
56 .remove = ca91cx42_remove,
59 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
61 wake_up(&(bridge->dma_queue));
63 return CA91CX42_LINT_DMA;
66 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
71 for (i = 0; i < 4; i++) {
72 if (stat & CA91CX42_LINT_LM[i]) {
73 /* We only enable interrupts if the callback is set */
74 bridge->lm_callback[i](i);
75 serviced |= CA91CX42_LINT_LM[i];
82 /* XXX This needs to be split into 4 queues */
83 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
85 wake_up(&(bridge->mbox_queue));
87 return CA91CX42_LINT_MBOX;
90 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
92 wake_up(&(bridge->iack_queue));
94 return CA91CX42_LINT_SW_IACK;
97 static u32 ca91cx42_VERR_irqhandler(struct ca91cx42_driver *bridge)
101 val = ioread32(bridge->base + DGCS);
103 if (!(val & 0x00000800)) {
104 printk(KERN_ERR "ca91c042: ca91cx42_VERR_irqhandler DMA Read "
105 "Error DGCS=%08X\n", val);
108 return CA91CX42_LINT_VERR;
111 static u32 ca91cx42_LERR_irqhandler(struct ca91cx42_driver *bridge)
115 val = ioread32(bridge->base + DGCS);
117 if (!(val & 0x00000800)) {
118 printk(KERN_ERR "ca91c042: ca91cx42_LERR_irqhandler DMA Read "
119 "Error DGCS=%08X\n", val);
123 return CA91CX42_LINT_LERR;
127 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
130 int vec, i, serviced = 0;
131 struct ca91cx42_driver *bridge;
133 bridge = ca91cx42_bridge->driver_priv;
136 for (i = 7; i > 0; i--) {
137 if (stat & (1 << i)) {
138 vec = ioread32(bridge->base +
139 CA91CX42_V_STATID[i]) & 0xff;
141 vme_irq_handler(ca91cx42_bridge, i, vec);
143 serviced |= (1 << i);
150 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
152 u32 stat, enable, serviced = 0;
153 struct vme_bridge *ca91cx42_bridge;
154 struct ca91cx42_driver *bridge;
156 ca91cx42_bridge = ptr;
158 bridge = ca91cx42_bridge->driver_priv;
160 enable = ioread32(bridge->base + LINT_EN);
161 stat = ioread32(bridge->base + LINT_STAT);
163 /* Only look at unmasked interrupts */
169 if (stat & CA91CX42_LINT_DMA)
170 serviced |= ca91cx42_DMA_irqhandler(bridge);
171 if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
173 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
174 if (stat & CA91CX42_LINT_MBOX)
175 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
176 if (stat & CA91CX42_LINT_SW_IACK)
177 serviced |= ca91cx42_IACK_irqhandler(bridge);
178 if (stat & CA91CX42_LINT_VERR)
179 serviced |= ca91cx42_VERR_irqhandler(bridge);
180 if (stat & CA91CX42_LINT_LERR)
181 serviced |= ca91cx42_LERR_irqhandler(bridge);
182 if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
183 CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
184 CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
185 CA91CX42_LINT_VIRQ7))
186 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
188 /* Clear serviced interrupts */
189 iowrite32(stat, bridge->base + LINT_STAT);
194 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
197 struct pci_dev *pdev;
198 struct ca91cx42_driver *bridge;
200 bridge = ca91cx42_bridge->driver_priv;
203 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
205 /* Initialise list for VME bus errors */
206 INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors));
208 mutex_init(&(ca91cx42_bridge->irq_mtx));
210 /* Disable interrupts from PCI to VME */
211 iowrite32(0, bridge->base + VINT_EN);
213 /* Disable PCI interrupts */
214 iowrite32(0, bridge->base + LINT_EN);
215 /* Clear Any Pending PCI Interrupts */
216 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
218 result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
219 driver_name, ca91cx42_bridge);
221 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
226 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
227 iowrite32(0, bridge->base + LINT_MAP0);
228 iowrite32(0, bridge->base + LINT_MAP1);
229 iowrite32(0, bridge->base + LINT_MAP2);
231 /* Enable DMA, mailbox & LM Interrupts */
232 tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
233 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
234 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
236 iowrite32(tmp, bridge->base + LINT_EN);
241 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
242 struct pci_dev *pdev)
244 /* Disable interrupts from PCI to VME */
245 iowrite32(0, bridge->base + VINT_EN);
247 /* Disable PCI interrupts */
248 iowrite32(0, bridge->base + LINT_EN);
249 /* Clear Any Pending PCI Interrupts */
250 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
252 free_irq(pdev->irq, pdev);
256 * Set up an VME interrupt
258 void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state,
262 struct pci_dev *pdev;
264 struct ca91cx42_driver *bridge;
266 bridge = ca91cx42_bridge->driver_priv;
268 /* Enable IRQ level */
269 tmp = ioread32(bridge->base + LINT_EN);
272 tmp &= ~CA91CX42_LINT_VIRQ[level];
274 tmp |= CA91CX42_LINT_VIRQ[level];
276 iowrite32(tmp, bridge->base + LINT_EN);
278 if ((state == 0) && (sync != 0)) {
279 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
282 synchronize_irq(pdev->irq);
286 int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
290 struct ca91cx42_driver *bridge;
292 bridge = ca91cx42_bridge->driver_priv;
294 /* Universe can only generate even vectors */
298 mutex_lock(&(bridge->vme_int));
300 tmp = ioread32(bridge->base + VINT_EN);
303 iowrite32(statid << 24, bridge->base + STATID);
305 /* Assert VMEbus IRQ */
306 tmp = tmp | (1 << (level + 24));
307 iowrite32(tmp, bridge->base + VINT_EN);
310 wait_event_interruptible(bridge->iack_queue, 0);
312 /* Return interrupt to low state */
313 tmp = ioread32(bridge->base + VINT_EN);
314 tmp = tmp & ~(1 << (level + 24));
315 iowrite32(tmp, bridge->base + VINT_EN);
317 mutex_unlock(&(bridge->vme_int));
322 int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
323 unsigned long long vme_base, unsigned long long size,
324 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
326 unsigned int i, addr = 0, granularity;
327 unsigned int temp_ctl = 0;
328 unsigned int vme_bound, pci_offset;
329 struct ca91cx42_driver *bridge;
331 bridge = image->parent->driver_priv;
337 addr |= CA91CX42_VSI_CTL_VAS_A16;
340 addr |= CA91CX42_VSI_CTL_VAS_A24;
343 addr |= CA91CX42_VSI_CTL_VAS_A32;
346 addr |= CA91CX42_VSI_CTL_VAS_USER1;
349 addr |= CA91CX42_VSI_CTL_VAS_USER2;
356 printk(KERN_ERR "Invalid address space\n");
362 * Bound address is a valid address for the window, adjust
365 vme_bound = vme_base + size;
366 pci_offset = pci_base - vme_base;
368 if ((i == 0) || (i == 4))
369 granularity = 0x1000;
371 granularity = 0x10000;
373 if (vme_base & (granularity - 1)) {
374 printk(KERN_ERR "Invalid VME base alignment\n");
377 if (vme_bound & (granularity - 1)) {
378 printk(KERN_ERR "Invalid VME bound alignment\n");
381 if (pci_offset & (granularity - 1)) {
382 printk(KERN_ERR "Invalid PCI Offset alignment\n");
386 /* Disable while we are mucking around */
387 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
388 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
389 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
392 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
393 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
394 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
396 /* Setup address space */
397 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
400 /* Setup cycle types */
401 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
402 if (cycle & VME_SUPER)
403 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
404 if (cycle & VME_USER)
405 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
406 if (cycle & VME_PROG)
407 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
408 if (cycle & VME_DATA)
409 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
411 /* Write ctl reg without enable */
412 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
415 temp_ctl |= CA91CX42_VSI_CTL_EN;
417 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
422 int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
423 unsigned long long *vme_base, unsigned long long *size,
424 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
426 unsigned int i, granularity = 0, ctl = 0;
427 unsigned long long vme_bound, pci_offset;
428 struct ca91cx42_driver *bridge;
430 bridge = image->parent->driver_priv;
434 if ((i == 0) || (i == 4))
435 granularity = 0x1000;
437 granularity = 0x10000;
440 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
442 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
443 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
444 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
446 *pci_base = (dma_addr_t)vme_base + pci_offset;
447 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
453 if (ctl & CA91CX42_VSI_CTL_EN)
456 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
458 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
460 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
462 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
464 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
467 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
469 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
471 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
473 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
480 * Allocate and map PCI Resource
482 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
483 unsigned long long size)
485 unsigned long long existing_size;
487 struct pci_dev *pdev;
488 struct vme_bridge *ca91cx42_bridge;
490 ca91cx42_bridge = image->parent;
492 /* Find pci_dev container of dev */
493 if (ca91cx42_bridge->parent == NULL) {
494 printk(KERN_ERR "Dev entry NULL\n");
497 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
499 existing_size = (unsigned long long)(image->bus_resource.end -
500 image->bus_resource.start);
502 /* If the existing size is OK, return */
503 if (existing_size == (size - 1))
506 if (existing_size != 0) {
507 iounmap(image->kern_base);
508 image->kern_base = NULL;
509 if (image->bus_resource.name != NULL)
510 kfree(image->bus_resource.name);
511 release_resource(&(image->bus_resource));
512 memset(&(image->bus_resource), 0, sizeof(struct resource));
515 if (image->bus_resource.name == NULL) {
516 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
517 if (image->bus_resource.name == NULL) {
518 printk(KERN_ERR "Unable to allocate memory for resource"
525 sprintf((char *)image->bus_resource.name, "%s.%d",
526 ca91cx42_bridge->name, image->number);
528 image->bus_resource.start = 0;
529 image->bus_resource.end = (unsigned long)size;
530 image->bus_resource.flags = IORESOURCE_MEM;
532 retval = pci_bus_alloc_resource(pdev->bus,
533 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
536 printk(KERN_ERR "Failed to allocate mem resource for "
537 "window %d size 0x%lx start 0x%lx\n",
538 image->number, (unsigned long)size,
539 (unsigned long)image->bus_resource.start);
543 image->kern_base = ioremap_nocache(
544 image->bus_resource.start, size);
545 if (image->kern_base == NULL) {
546 printk(KERN_ERR "Failed to remap resource\n");
553 iounmap(image->kern_base);
554 image->kern_base = NULL;
556 release_resource(&(image->bus_resource));
558 kfree(image->bus_resource.name);
559 memset(&(image->bus_resource), 0, sizeof(struct resource));
565 * Free and unmap PCI Resource
567 static void ca91cx42_free_resource(struct vme_master_resource *image)
569 iounmap(image->kern_base);
570 image->kern_base = NULL;
571 release_resource(&(image->bus_resource));
572 kfree(image->bus_resource.name);
573 memset(&(image->bus_resource), 0, sizeof(struct resource));
577 int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
578 unsigned long long vme_base, unsigned long long size,
579 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
582 unsigned int i, granularity = 0;
583 unsigned int temp_ctl = 0;
584 unsigned long long pci_bound, vme_offset, pci_base;
585 struct ca91cx42_driver *bridge;
587 bridge = image->parent->driver_priv;
591 if ((i == 0) || (i == 4))
592 granularity = 0x1000;
594 granularity = 0x10000;
596 /* Verify input data */
597 if (vme_base & (granularity - 1)) {
598 printk(KERN_ERR "Invalid VME Window alignment\n");
602 if (size & (granularity - 1)) {
603 printk(KERN_ERR "Invalid VME Window alignment\n");
608 spin_lock(&(image->lock));
611 * Let's allocate the resource here rather than further up the stack as
612 * it avoids pushing loads of bus dependant stuff up the stack
614 retval = ca91cx42_alloc_resource(image, size);
616 spin_unlock(&(image->lock));
617 printk(KERN_ERR "Unable to allocate memory for resource "
623 pci_base = (unsigned long long)image->bus_resource.start;
626 * Bound address is a valid address for the window, adjust
627 * according to window granularity.
629 pci_bound = pci_base + size;
630 vme_offset = vme_base - pci_base;
632 /* Disable while we are mucking around */
633 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
634 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
635 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
637 /* Setup cycle types */
638 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
640 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
641 if (cycle & VME_MBLT)
642 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
644 /* Setup data width */
645 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
648 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
651 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
654 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
657 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
660 spin_unlock(&(image->lock));
661 printk(KERN_ERR "Invalid data width\n");
667 /* Setup address space */
668 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
671 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
674 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
677 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
680 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
683 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
686 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
692 spin_unlock(&(image->lock));
693 printk(KERN_ERR "Invalid address space\n");
699 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
700 if (cycle & VME_SUPER)
701 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
702 if (cycle & VME_PROG)
703 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
706 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
707 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
708 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
710 /* Write ctl reg without enable */
711 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
714 temp_ctl |= CA91CX42_LSI_CTL_EN;
716 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
718 spin_unlock(&(image->lock));
723 ca91cx42_free_resource(image);
729 int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
730 unsigned long long *vme_base, unsigned long long *size,
731 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
734 unsigned long long pci_base, pci_bound, vme_offset;
735 struct ca91cx42_driver *bridge;
737 bridge = image->parent->driver_priv;
741 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
743 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
744 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
745 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
747 *vme_base = pci_base + vme_offset;
748 *size = (unsigned long long)(pci_bound - pci_base);
755 if (ctl & CA91CX42_LSI_CTL_EN)
758 /* Setup address space */
759 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
760 case CA91CX42_LSI_CTL_VAS_A16:
763 case CA91CX42_LSI_CTL_VAS_A24:
766 case CA91CX42_LSI_CTL_VAS_A32:
769 case CA91CX42_LSI_CTL_VAS_CRCSR:
772 case CA91CX42_LSI_CTL_VAS_USER1:
775 case CA91CX42_LSI_CTL_VAS_USER2:
780 /* XXX Not sure howto check for MBLT */
781 /* Setup cycle types */
782 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
787 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
792 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
797 /* Setup data width */
798 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
799 case CA91CX42_LSI_CTL_VDW_D8:
802 case CA91CX42_LSI_CTL_VDW_D16:
805 case CA91CX42_LSI_CTL_VDW_D32:
808 case CA91CX42_LSI_CTL_VDW_D64:
816 int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
817 unsigned long long *vme_base, unsigned long long *size,
818 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
822 spin_lock(&(image->lock));
824 retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
827 spin_unlock(&(image->lock));
832 ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf,
833 size_t count, loff_t offset)
837 spin_lock(&(image->lock));
839 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
842 spin_unlock(&(image->lock));
847 ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf,
848 size_t count, loff_t offset)
852 spin_lock(&(image->lock));
854 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
857 spin_unlock(&(image->lock));
862 unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
863 unsigned int mask, unsigned int compare, unsigned int swap,
866 u32 pci_addr, result;
868 struct ca91cx42_driver *bridge;
871 bridge = image->parent->driver_priv;
872 dev = image->parent->parent;
874 /* Find the PCI address that maps to the desired VME address */
877 /* Locking as we can only do one of these at a time */
878 mutex_lock(&(bridge->vme_rmw));
881 spin_lock(&(image->lock));
883 pci_addr = (u32)image->kern_base + offset;
885 /* Address must be 4-byte aligned */
886 if (pci_addr & 0x3) {
887 dev_err(dev, "RMW Address not 4-byte aligned\n");
891 /* Ensure RMW Disabled whilst configuring */
892 iowrite32(0, bridge->base + SCYC_CTL);
894 /* Configure registers */
895 iowrite32(mask, bridge->base + SCYC_EN);
896 iowrite32(compare, bridge->base + SCYC_CMP);
897 iowrite32(swap, bridge->base + SCYC_SWP);
898 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
901 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
903 /* Kick process off with a read to the required address. */
904 result = ioread32(image->kern_base + offset);
907 iowrite32(0, bridge->base + SCYC_CTL);
909 spin_unlock(&(image->lock));
911 mutex_unlock(&(bridge->vme_rmw));
916 int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
917 struct vme_dma_attr *dest, size_t count)
919 struct ca91cx42_dma_entry *entry, *prev;
920 struct vme_dma_pci *pci_attr;
921 struct vme_dma_vme *vme_attr;
925 /* XXX descriptor must be aligned on 64-bit boundaries */
926 entry = (struct ca91cx42_dma_entry *)
927 kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
929 printk(KERN_ERR "Failed to allocate memory for dma resource "
935 /* Test descriptor alignment */
936 if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) {
937 printk("Descriptor not aligned to 16 byte boundary as "
938 "required: %p\n", &(entry->descriptor));
943 memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor));
945 if (dest->type == VME_DMA_VME) {
946 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
947 vme_attr = (struct vme_dma_vme *)dest->private;
948 pci_attr = (struct vme_dma_pci *)src->private;
950 vme_attr = (struct vme_dma_vme *)src->private;
951 pci_attr = (struct vme_dma_pci *)dest->private;
954 /* Check we can do fullfill required attributes */
955 if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
958 printk(KERN_ERR "Unsupported cycle type\n");
963 if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
964 VME_PROG | VME_DATA)) != 0) {
966 printk(KERN_ERR "Unsupported cycle type\n");
971 /* Check to see if we can fullfill source and destination */
972 if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
973 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
975 printk(KERN_ERR "Cannot perform transfer with this "
976 "source-destination combination\n");
981 /* Setup cycle types */
982 if (vme_attr->cycle & VME_BLT)
983 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
985 /* Setup data width */
986 switch (vme_attr->dwidth) {
988 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
991 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
994 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
997 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1000 printk(KERN_ERR "Invalid data width\n");
1004 /* Setup address space */
1005 switch (vme_attr->aspace) {
1007 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1010 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1013 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1016 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1019 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1022 printk(KERN_ERR "Invalid address space\n");
1027 if (vme_attr->cycle & VME_SUPER)
1028 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1029 if (vme_attr->cycle & VME_PROG)
1030 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1032 entry->descriptor.dtbc = count;
1033 entry->descriptor.dla = pci_attr->address;
1034 entry->descriptor.dva = vme_attr->address;
1035 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1038 list_add_tail(&(entry->list), &(list->entries));
1040 /* Fill out previous descriptors "Next Address" */
1041 if (entry->list.prev != &(list->entries)) {
1042 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1044 /* We need the bus address for the pointer */
1045 desc_ptr = virt_to_bus(&(entry->descriptor));
1046 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1060 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1063 struct ca91cx42_driver *bridge;
1065 bridge = ca91cx42_bridge->driver_priv;
1067 tmp = ioread32(bridge->base + DGCS);
1069 if (tmp & CA91CX42_DGCS_ACT)
1075 int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1077 struct vme_dma_resource *ctrlr;
1078 struct ca91cx42_dma_entry *entry;
1080 dma_addr_t bus_addr;
1083 struct ca91cx42_driver *bridge;
1085 ctrlr = list->parent;
1087 bridge = ctrlr->parent->driver_priv;
1089 mutex_lock(&(ctrlr->mtx));
1091 if (!(list_empty(&(ctrlr->running)))) {
1093 * XXX We have an active DMA transfer and currently haven't
1094 * sorted out the mechanism for "pending" DMA transfers.
1097 /* Need to add to pending here */
1098 mutex_unlock(&(ctrlr->mtx));
1101 list_add(&(list->list), &(ctrlr->running));
1104 /* Get first bus address and write into registers */
1105 entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry,
1108 bus_addr = virt_to_bus(&(entry->descriptor));
1110 mutex_unlock(&(ctrlr->mtx));
1112 iowrite32(0, bridge->base + DTBC);
1113 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1115 /* Start the operation */
1116 val = ioread32(bridge->base + DGCS);
1118 /* XXX Could set VMEbus On and Off Counters here */
1119 val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1121 val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1122 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1123 CA91CX42_DGCS_PERR);
1125 iowrite32(val, bridge->base + DGCS);
1127 val |= CA91CX42_DGCS_GO;
1129 iowrite32(val, bridge->base + DGCS);
1131 wait_event_interruptible(bridge->dma_queue,
1132 ca91cx42_dma_busy(ctrlr->parent));
1135 * Read status register, this register is valid until we kick off a
1138 val = ioread32(bridge->base + DGCS);
1140 if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1141 CA91CX42_DGCS_PERR)) {
1143 printk(KERN_ERR "ca91c042: DMA Error. DGCS=%08X\n", val);
1144 val = ioread32(bridge->base + DCTL);
1147 /* Remove list from running list */
1148 mutex_lock(&(ctrlr->mtx));
1149 list_del(&(list->list));
1150 mutex_unlock(&(ctrlr->mtx));
1156 int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1158 struct list_head *pos, *temp;
1159 struct ca91cx42_dma_entry *entry;
1161 /* detach and free each entry */
1162 list_for_each_safe(pos, temp, &(list->entries)) {
1164 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1172 * All 4 location monitors reside at the same base - this is therefore a
1173 * system wide configuration.
1175 * This does not enable the LM monitor - that should be done when the first
1176 * callback is attached and disabled when the last callback is removed.
1178 int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1179 vme_address_t aspace, vme_cycle_t cycle)
1181 u32 temp_base, lm_ctl = 0;
1183 struct ca91cx42_driver *bridge;
1186 bridge = lm->parent->driver_priv;
1187 dev = lm->parent->parent;
1189 /* Check the alignment of the location monitor */
1190 temp_base = (u32)lm_base;
1191 if (temp_base & 0xffff) {
1192 dev_err(dev, "Location monitor must be aligned to 64KB "
1197 mutex_lock(&(lm->mtx));
1199 /* If we already have a callback attached, we can't move it! */
1200 for (i = 0; i < lm->monitors; i++) {
1201 if (bridge->lm_callback[i] != NULL) {
1202 mutex_unlock(&(lm->mtx));
1203 dev_err(dev, "Location monitor callback attached, "
1211 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1214 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1217 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1220 mutex_unlock(&(lm->mtx));
1221 dev_err(dev, "Invalid address space\n");
1226 if (cycle & VME_SUPER)
1227 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1228 if (cycle & VME_USER)
1229 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1230 if (cycle & VME_PROG)
1231 lm_ctl |= CA91CX42_LM_CTL_PGM;
1232 if (cycle & VME_DATA)
1233 lm_ctl |= CA91CX42_LM_CTL_DATA;
1235 iowrite32(lm_base, bridge->base + LM_BS);
1236 iowrite32(lm_ctl, bridge->base + LM_CTL);
1238 mutex_unlock(&(lm->mtx));
1243 /* Get configuration of the callback monitor and return whether it is enabled
1246 int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
1247 vme_address_t *aspace, vme_cycle_t *cycle)
1249 u32 lm_ctl, enabled = 0;
1250 struct ca91cx42_driver *bridge;
1252 bridge = lm->parent->driver_priv;
1254 mutex_lock(&(lm->mtx));
1256 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1257 lm_ctl = ioread32(bridge->base + LM_CTL);
1259 if (lm_ctl & CA91CX42_LM_CTL_EN)
1262 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1264 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1266 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1270 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1271 *cycle |= VME_SUPER;
1272 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1274 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1276 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1279 mutex_unlock(&(lm->mtx));
1285 * Attach a callback to a specific location monitor.
1287 * Callback will be passed the monitor triggered.
1289 int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1290 void (*callback)(int))
1293 struct ca91cx42_driver *bridge;
1296 bridge = lm->parent->driver_priv;
1297 dev = lm->parent->parent;
1299 mutex_lock(&(lm->mtx));
1301 /* Ensure that the location monitor is configured - need PGM or DATA */
1302 lm_ctl = ioread32(bridge->base + LM_CTL);
1303 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1304 mutex_unlock(&(lm->mtx));
1305 dev_err(dev, "Location monitor not properly configured\n");
1309 /* Check that a callback isn't already attached */
1310 if (bridge->lm_callback[monitor] != NULL) {
1311 mutex_unlock(&(lm->mtx));
1312 dev_err(dev, "Existing callback attached\n");
1316 /* Attach callback */
1317 bridge->lm_callback[monitor] = callback;
1319 /* Enable Location Monitor interrupt */
1320 tmp = ioread32(bridge->base + LINT_EN);
1321 tmp |= CA91CX42_LINT_LM[monitor];
1322 iowrite32(tmp, bridge->base + LINT_EN);
1324 /* Ensure that global Location Monitor Enable set */
1325 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1326 lm_ctl |= CA91CX42_LM_CTL_EN;
1327 iowrite32(lm_ctl, bridge->base + LM_CTL);
1330 mutex_unlock(&(lm->mtx));
1336 * Detach a callback function forn a specific location monitor.
1338 int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1341 struct ca91cx42_driver *bridge;
1343 bridge = lm->parent->driver_priv;
1345 mutex_lock(&(lm->mtx));
1347 /* Disable Location Monitor and ensure previous interrupts are clear */
1348 tmp = ioread32(bridge->base + LINT_EN);
1349 tmp &= ~CA91CX42_LINT_LM[monitor];
1350 iowrite32(tmp, bridge->base + LINT_EN);
1352 iowrite32(CA91CX42_LINT_LM[monitor],
1353 bridge->base + LINT_STAT);
1355 /* Detach callback */
1356 bridge->lm_callback[monitor] = NULL;
1358 /* If all location monitors disabled, disable global Location Monitor */
1359 if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1360 CA91CX42_LINT_LM3)) == 0) {
1361 tmp = ioread32(bridge->base + LM_CTL);
1362 tmp &= ~CA91CX42_LM_CTL_EN;
1363 iowrite32(tmp, bridge->base + LM_CTL);
1366 mutex_unlock(&(lm->mtx));
1371 int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1374 struct ca91cx42_driver *bridge;
1376 bridge = ca91cx42_bridge->driver_priv;
1379 slot = ioread32(bridge->base + VCSR_BS);
1380 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1388 static int __init ca91cx42_init(void)
1390 return pci_register_driver(&ca91cx42_driver);
1394 * Configure CR/CSR space
1396 * Access to the CR/CSR can be configured at power-up. The location of the
1397 * CR/CSR registers in the CR/CSR address space is determined by the boards
1398 * Auto-ID or Geographic address. This function ensures that the window is
1399 * enabled at an offset consistent with the boards geopgraphic address.
1401 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1402 struct pci_dev *pdev)
1404 unsigned int crcsr_addr;
1406 struct ca91cx42_driver *bridge;
1408 bridge = ca91cx42_bridge->driver_priv;
1410 slot = ca91cx42_slot_get(ca91cx42_bridge);
1412 /* Write CSR Base Address if slot ID is supplied as a module param */
1414 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1416 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1418 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1423 /* Allocate mem for CR/CSR image */
1424 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1425 &(bridge->crcsr_bus));
1426 if (bridge->crcsr_kernel == NULL) {
1427 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1432 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
1434 crcsr_addr = slot * (512 * 1024);
1435 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1437 tmp = ioread32(bridge->base + VCSR_CTL);
1438 tmp |= CA91CX42_VCSR_CTL_EN;
1439 iowrite32(tmp, bridge->base + VCSR_CTL);
1444 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1445 struct pci_dev *pdev)
1448 struct ca91cx42_driver *bridge;
1450 bridge = ca91cx42_bridge->driver_priv;
1452 /* Turn off CR/CSR space */
1453 tmp = ioread32(bridge->base + VCSR_CTL);
1454 tmp &= ~CA91CX42_VCSR_CTL_EN;
1455 iowrite32(tmp, bridge->base + VCSR_CTL);
1458 iowrite32(0, bridge->base + VCSR_TO);
1460 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1464 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1468 struct list_head *pos = NULL;
1469 struct vme_bridge *ca91cx42_bridge;
1470 struct ca91cx42_driver *ca91cx42_device;
1471 struct vme_master_resource *master_image;
1472 struct vme_slave_resource *slave_image;
1473 struct vme_dma_resource *dma_ctrlr;
1474 struct vme_lm_resource *lm;
1476 /* We want to support more than one of each bridge so we need to
1477 * dynamically allocate the bridge structure
1479 ca91cx42_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1481 if (ca91cx42_bridge == NULL) {
1482 dev_err(&pdev->dev, "Failed to allocate memory for device "
1488 memset(ca91cx42_bridge, 0, sizeof(struct vme_bridge));
1490 ca91cx42_device = kmalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1492 if (ca91cx42_device == NULL) {
1493 dev_err(&pdev->dev, "Failed to allocate memory for device "
1499 memset(ca91cx42_device, 0, sizeof(struct ca91cx42_driver));
1501 ca91cx42_bridge->driver_priv = ca91cx42_device;
1503 /* Enable the device */
1504 retval = pci_enable_device(pdev);
1506 dev_err(&pdev->dev, "Unable to enable device\n");
1511 retval = pci_request_regions(pdev, driver_name);
1513 dev_err(&pdev->dev, "Unable to reserve resources\n");
1517 /* map registers in BAR 0 */
1518 ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1520 if (!ca91cx42_device->base) {
1521 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1526 /* Check to see if the mapping worked out */
1527 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1528 if (data != PCI_VENDOR_ID_TUNDRA) {
1529 dev_err(&pdev->dev, "PCI_ID check failed\n");
1534 /* Initialize wait queues & mutual exclusion flags */
1535 init_waitqueue_head(&(ca91cx42_device->dma_queue));
1536 init_waitqueue_head(&(ca91cx42_device->iack_queue));
1537 mutex_init(&(ca91cx42_device->vme_int));
1538 mutex_init(&(ca91cx42_device->vme_rmw));
1540 ca91cx42_bridge->parent = &(pdev->dev);
1541 strcpy(ca91cx42_bridge->name, driver_name);
1544 retval = ca91cx42_irq_init(ca91cx42_bridge);
1546 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1550 /* Add master windows to list */
1551 INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources));
1552 for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1553 master_image = kmalloc(sizeof(struct vme_master_resource),
1555 if (master_image == NULL) {
1556 dev_err(&pdev->dev, "Failed to allocate memory for "
1557 "master resource structure\n");
1561 master_image->parent = ca91cx42_bridge;
1562 spin_lock_init(&(master_image->lock));
1563 master_image->locked = 0;
1564 master_image->number = i;
1565 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1566 VME_CRCSR | VME_USER1 | VME_USER2;
1567 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1568 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1569 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1570 memset(&(master_image->bus_resource), 0,
1571 sizeof(struct resource));
1572 master_image->kern_base = NULL;
1573 list_add_tail(&(master_image->list),
1574 &(ca91cx42_bridge->master_resources));
1577 /* Add slave windows to list */
1578 INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources));
1579 for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1580 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1582 if (slave_image == NULL) {
1583 dev_err(&pdev->dev, "Failed to allocate memory for "
1584 "slave resource structure\n");
1588 slave_image->parent = ca91cx42_bridge;
1589 mutex_init(&(slave_image->mtx));
1590 slave_image->locked = 0;
1591 slave_image->number = i;
1592 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1595 /* Only windows 0 and 4 support A16 */
1596 if (i == 0 || i == 4)
1597 slave_image->address_attr |= VME_A16;
1599 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1600 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1601 list_add_tail(&(slave_image->list),
1602 &(ca91cx42_bridge->slave_resources));
1605 /* Add dma engines to list */
1606 INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources));
1607 for (i = 0; i < CA91C142_MAX_DMA; i++) {
1608 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1610 if (dma_ctrlr == NULL) {
1611 dev_err(&pdev->dev, "Failed to allocate memory for "
1612 "dma resource structure\n");
1616 dma_ctrlr->parent = ca91cx42_bridge;
1617 mutex_init(&(dma_ctrlr->mtx));
1618 dma_ctrlr->locked = 0;
1619 dma_ctrlr->number = i;
1620 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1622 INIT_LIST_HEAD(&(dma_ctrlr->pending));
1623 INIT_LIST_HEAD(&(dma_ctrlr->running));
1624 list_add_tail(&(dma_ctrlr->list),
1625 &(ca91cx42_bridge->dma_resources));
1628 /* Add location monitor to list */
1629 INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources));
1630 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1632 dev_err(&pdev->dev, "Failed to allocate memory for "
1633 "location monitor resource structure\n");
1637 lm->parent = ca91cx42_bridge;
1638 mutex_init(&(lm->mtx));
1642 list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources));
1644 ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1645 ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1646 ca91cx42_bridge->master_get = ca91cx42_master_get;
1647 ca91cx42_bridge->master_set = ca91cx42_master_set;
1648 ca91cx42_bridge->master_read = ca91cx42_master_read;
1649 ca91cx42_bridge->master_write = ca91cx42_master_write;
1650 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1651 ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1652 ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1653 ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1654 ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1655 ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1656 ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1657 ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1658 ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1659 ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1660 ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1662 data = ioread32(ca91cx42_device->base + MISC_CTL);
1663 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1664 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1665 dev_info(&pdev->dev, "Slot ID is %d\n",
1666 ca91cx42_slot_get(ca91cx42_bridge));
1668 if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) {
1669 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1672 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1675 retval = vme_register_bridge(ca91cx42_bridge);
1677 dev_err(&pdev->dev, "Chip Registration failed.\n");
1681 pci_set_drvdata(pdev, ca91cx42_bridge);
1685 vme_unregister_bridge(ca91cx42_bridge);
1687 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1689 /* resources are stored in link list */
1690 list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1691 lm = list_entry(pos, struct vme_lm_resource, list);
1696 /* resources are stored in link list */
1697 list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1698 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1703 /* resources are stored in link list */
1704 list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1705 slave_image = list_entry(pos, struct vme_slave_resource, list);
1710 /* resources are stored in link list */
1711 list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1712 master_image = list_entry(pos, struct vme_master_resource,
1715 kfree(master_image);
1718 ca91cx42_irq_exit(ca91cx42_device, pdev);
1721 iounmap(ca91cx42_device->base);
1723 pci_release_regions(pdev);
1725 pci_disable_device(pdev);
1727 kfree(ca91cx42_device);
1729 kfree(ca91cx42_bridge);
1735 void ca91cx42_remove(struct pci_dev *pdev)
1737 struct list_head *pos = NULL;
1738 struct vme_master_resource *master_image;
1739 struct vme_slave_resource *slave_image;
1740 struct vme_dma_resource *dma_ctrlr;
1741 struct vme_lm_resource *lm;
1742 struct ca91cx42_driver *bridge;
1743 struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1745 bridge = ca91cx42_bridge->driver_priv;
1749 iowrite32(0, bridge->base + LINT_EN);
1751 /* Turn off the windows */
1752 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1753 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1754 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1755 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1756 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1757 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1758 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1759 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1760 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1761 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1762 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1763 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1764 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1765 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1766 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1767 iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1769 vme_unregister_bridge(ca91cx42_bridge);
1771 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1773 /* resources are stored in link list */
1774 list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1775 lm = list_entry(pos, struct vme_lm_resource, list);
1780 /* resources are stored in link list */
1781 list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1782 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1787 /* resources are stored in link list */
1788 list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1789 slave_image = list_entry(pos, struct vme_slave_resource, list);
1794 /* resources are stored in link list */
1795 list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1796 master_image = list_entry(pos, struct vme_master_resource,
1799 kfree(master_image);
1802 ca91cx42_irq_exit(bridge, pdev);
1804 iounmap(bridge->base);
1806 pci_release_regions(pdev);
1808 pci_disable_device(pdev);
1810 kfree(ca91cx42_bridge);
1813 static void __exit ca91cx42_exit(void)
1815 pci_unregister_driver(&ca91cx42_driver);
1818 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1819 module_param(geoid, int, 0);
1821 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1822 MODULE_LICENSE("GPL");
1824 module_init(ca91cx42_init);
1825 module_exit(ca91cx42_exit);