drivers/staging/vme/bridges/vme_ca91cx42.c

   1 /*
   2  * Support for the Tundra Universe I/II VME-PCI Bridge Chips
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * Derived from ca91c042.c by Michael Wyrick
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mm.h>
  20 #include <linux/types.h>
  21 #include <linux/errno.h>
  22 #include <linux/pci.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/poll.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/sched.h>
  28 #include <asm/time.h>
  29 #include <asm/io.h>
  30 #include <asm/uaccess.h>
  31
  32 #include "../vme.h"
  33 #include "../vme_bridge.h"
  34 #include "vme_ca91cx42.h"
  35
  36 static int __init ca91cx42_init(void);
  37 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
  38 static void ca91cx42_remove(struct pci_dev *);
  39 static void __exit ca91cx42_exit(void);
  40
  41 /* Module parameters */
  42 static int geoid;
  43
  44 static char driver_name[] = "vme_ca91cx42";
  45
  46 static const struct pci_device_id ca91cx42_ids[] = {
  47         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
  48         { },
  49 };
  50
  51 static struct pci_driver ca91cx42_driver = {
  52         .name = driver_name,
  53         .id_table = ca91cx42_ids,
  54         .probe = ca91cx42_probe,
  55         .remove = ca91cx42_remove,
  56 };
  57
  58 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
  59 {
  60         wake_up(&(bridge->dma_queue));
  61
  62         return CA91CX42_LINT_DMA;
  63 }
  64
  65 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
  66 {
  67         int i;
  68         u32 serviced = 0;
  69
  70         for (i = 0; i < 4; i++) {
  71                 if (stat & CA91CX42_LINT_LM[i]) {
  72                         /* We only enable interrupts if the callback is set */
  73                         bridge->lm_callback[i](i);
  74                         serviced |= CA91CX42_LINT_LM[i];
  75                 }
  76         }
  77
  78         return serviced;
  79 }
  80
  81 /* XXX This needs to be split into 4 queues */
  82 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
  83 {
  84         wake_up(&(bridge->mbox_queue));
  85
  86         return CA91CX42_LINT_MBOX;
  87 }
  88
  89 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
  90 {
  91         wake_up(&(bridge->iack_queue));
  92
  93         return CA91CX42_LINT_SW_IACK;
  94 }
  95
  96 #if 0
  97 int ca91cx42_bus_error_chk(int clrflag)
  98 {
  99         int tmp;
 100         tmp = ioread32(bridge->base + PCI_COMMAND);
 101         if (tmp & 0x08000000) { /* S_TA is Set */
 102                 if (clrflag)
 103                         iowrite32(tmp | 0x08000000,
 104                                bridge->base + PCI_COMMAND);
 105                 return 1;
 106         }
 107         return 0;
 108 }
 109 #endif
 110
 111 static u32 ca91cx42_VERR_irqhandler(struct ca91cx42_driver *bridge)
 112 {
 113         int val;
 114
 115         val = ioread32(bridge->base + DGCS);
 116
 117         if (!(val & 0x00000800)) {
 118                 printk(KERN_ERR "ca91c042: ca91cx42_VERR_irqhandler DMA Read "
 119                         "Error DGCS=%08X\n", val);
 120         }
 121
 122         return CA91CX42_LINT_VERR;
 123 }
 124
 125 static u32 ca91cx42_LERR_irqhandler(struct ca91cx42_driver *bridge)
 126 {
 127         int val;
 128
 129         val = ioread32(bridge->base + DGCS);
 130
 131         if (!(val & 0x00000800)) {
 132                 printk(KERN_ERR "ca91c042: ca91cx42_LERR_irqhandler DMA Read "
 133                         "Error DGCS=%08X\n", val);
 134
 135         }
 136
 137         return CA91CX42_LINT_LERR;
 138 }
 139
 140
 141 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
 142         int stat)
 143 {
 144         int vec, i, serviced = 0;
 145         struct ca91cx42_driver *bridge;
 146
 147         bridge = ca91cx42_bridge->driver_priv;
 148
 149
 150         for (i = 7; i > 0; i--) {
 151                 if (stat & (1 << i)) {
 152                         vec = ioread32(bridge->base +
 153                                 CA91CX42_V_STATID[i]) & 0xff;
 154
 155                         vme_irq_handler(ca91cx42_bridge, i, vec);
 156
 157                         serviced |= (1 << i);
 158                 }
 159         }
 160
 161         return serviced;
 162 }
 163
 164 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
 165 {
 166         u32 stat, enable, serviced = 0;
 167         struct vme_bridge *ca91cx42_bridge;
 168         struct ca91cx42_driver *bridge;
 169
 170         ca91cx42_bridge = ptr;
 171
 172         bridge = ca91cx42_bridge->driver_priv;
 173
 174         enable = ioread32(bridge->base + LINT_EN);
 175         stat = ioread32(bridge->base + LINT_STAT);
 176
 177         /* Only look at unmasked interrupts */
 178         stat &= enable;
 179
 180         if (unlikely(!stat))
 181                 return IRQ_NONE;
 182
 183         if (stat & CA91CX42_LINT_DMA)
 184                 serviced |= ca91cx42_DMA_irqhandler(bridge);
 185         if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
 186                         CA91CX42_LINT_LM3))
 187                 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
 188         if (stat & CA91CX42_LINT_MBOX)
 189                 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
 190         if (stat & CA91CX42_LINT_SW_IACK)
 191                 serviced |= ca91cx42_IACK_irqhandler(bridge);
 192         if (stat & CA91CX42_LINT_VERR)
 193                 serviced |= ca91cx42_VERR_irqhandler(bridge);
 194         if (stat & CA91CX42_LINT_LERR)
 195                 serviced |= ca91cx42_LERR_irqhandler(bridge);
 196         if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
 197                         CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
 198                         CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
 199                         CA91CX42_LINT_VIRQ7))
 200                 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
 201
 202         /* Clear serviced interrupts */
 203         iowrite32(stat, bridge->base + LINT_STAT);
 204
 205         return IRQ_HANDLED;
 206 }
 207
 208 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
 209 {
 210         int result, tmp;
 211         struct pci_dev *pdev;
 212         struct ca91cx42_driver *bridge;
 213
 214         bridge = ca91cx42_bridge->driver_priv;
 215
 216         /* Need pdev */
 217         pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
 218
 219         /* Initialise list for VME bus errors */
 220         INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors));
 221
 222         mutex_init(&(ca91cx42_bridge->irq_mtx));
 223
 224         /* Disable interrupts from PCI to VME */
 225         iowrite32(0, bridge->base + VINT_EN);
 226
 227         /* Disable PCI interrupts */
 228         iowrite32(0, bridge->base + LINT_EN);
 229         /* Clear Any Pending PCI Interrupts */
 230         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 231
 232         result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
 233                         driver_name, ca91cx42_bridge);
 234         if (result) {
 235                 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
 236                        pdev->irq);
 237                 return result;
 238         }
 239
 240         /* Ensure all interrupts are mapped to PCI Interrupt 0 */
 241         iowrite32(0, bridge->base + LINT_MAP0);
 242         iowrite32(0, bridge->base + LINT_MAP1);
 243         iowrite32(0, bridge->base + LINT_MAP2);
 244
 245         /* Enable DMA, mailbox & LM Interrupts */
 246         tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
 247                 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
 248                 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
 249
 250         iowrite32(tmp, bridge->base + LINT_EN);
 251
 252         return 0;
 253 }
 254
 255 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
 256         struct pci_dev *pdev)
 257 {
 258         /* Disable interrupts from PCI to VME */
 259         iowrite32(0, bridge->base + VINT_EN);
 260
 261         /* Disable PCI interrupts */
 262         iowrite32(0, bridge->base + LINT_EN);
 263         /* Clear Any Pending PCI Interrupts */
 264         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 265
 266         free_irq(pdev->irq, pdev);
 267 }
 268
 269 /*
 270  * Set up an VME interrupt
 271  */
 272 void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state,
 273         int sync)
 274
 275 {
 276         struct pci_dev *pdev;
 277         u32 tmp;
 278         struct ca91cx42_driver *bridge;
 279
 280         bridge = ca91cx42_bridge->driver_priv;
 281
 282         /* Enable IRQ level */
 283         tmp = ioread32(bridge->base + LINT_EN);
 284
 285         if (state == 0)
 286                 tmp &= ~CA91CX42_LINT_VIRQ[level];
 287         else
 288                 tmp |= CA91CX42_LINT_VIRQ[level];
 289
 290         iowrite32(tmp, bridge->base + LINT_EN);
 291
 292         if ((state == 0) && (sync != 0)) {
 293                 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
 294                         dev);
 295
 296                 synchronize_irq(pdev->irq);
 297         }
 298 }
 299
 300 int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
 301         int statid)
 302 {
 303         u32 tmp;
 304         struct ca91cx42_driver *bridge;
 305
 306         bridge = ca91cx42_bridge->driver_priv;
 307
 308         /* Universe can only generate even vectors */
 309         if (statid & 1)
 310                 return -EINVAL;
 311
 312         mutex_lock(&(bridge->vme_int));
 313
 314         tmp = ioread32(bridge->base + VINT_EN);
 315
 316         /* Set Status/ID */
 317         iowrite32(statid << 24, bridge->base + STATID);
 318
 319         /* Assert VMEbus IRQ */
 320         tmp = tmp | (1 << (level + 24));
 321         iowrite32(tmp, bridge->base + VINT_EN);
 322
 323         /* Wait for IACK */
 324         wait_event_interruptible(bridge->iack_queue, 0);
 325
 326         /* Return interrupt to low state */
 327         tmp = ioread32(bridge->base + VINT_EN);
 328         tmp = tmp & ~(1 << (level + 24));
 329         iowrite32(tmp, bridge->base + VINT_EN);
 330
 331         mutex_unlock(&(bridge->vme_int));
 332
 333         return 0;
 334 }
 335
 336 int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
 337         unsigned long long vme_base, unsigned long long size,
 338         dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
 339 {
 340         unsigned int i, addr = 0, granularity;
 341         unsigned int temp_ctl = 0;
 342         unsigned int vme_bound, pci_offset;
 343         struct ca91cx42_driver *bridge;
 344
 345         bridge = image->parent->driver_priv;
 346
 347         i = image->number;
 348
 349         switch (aspace) {
 350         case VME_A16:
 351                 addr |= CA91CX42_VSI_CTL_VAS_A16;
 352                 break;
 353         case VME_A24:
 354                 addr |= CA91CX42_VSI_CTL_VAS_A24;
 355                 break;
 356         case VME_A32:
 357                 addr |= CA91CX42_VSI_CTL_VAS_A32;
 358                 break;
 359         case VME_USER1:
 360                 addr |= CA91CX42_VSI_CTL_VAS_USER1;
 361                 break;
 362         case VME_USER2:
 363                 addr |= CA91CX42_VSI_CTL_VAS_USER2;
 364                 break;
 365         case VME_A64:
 366         case VME_CRCSR:
 367         case VME_USER3:
 368         case VME_USER4:
 369         default:
 370                 printk(KERN_ERR "Invalid address space\n");
 371                 return -EINVAL;
 372                 break;
 373         }
 374
 375         /*
 376          * Bound address is a valid address for the window, adjust
 377          * accordingly
 378          */
 379         vme_bound = vme_base + size;
 380         pci_offset = pci_base - vme_base;
 381
 382         /* XXX Need to check that vme_base, vme_bound and pci_offset aren't
 383          * too big for registers
 384          */
 385
 386         if ((i == 0) || (i == 4))
 387                 granularity = 0x1000;
 388         else
 389                 granularity = 0x10000;
 390
 391         if (vme_base & (granularity - 1)) {
 392                 printk(KERN_ERR "Invalid VME base alignment\n");
 393                 return -EINVAL;
 394         }
 395         if (vme_bound & (granularity - 1)) {
 396                 printk(KERN_ERR "Invalid VME bound alignment\n");
 397                 return -EINVAL;
 398         }
 399         if (pci_offset & (granularity - 1)) {
 400                 printk(KERN_ERR "Invalid PCI Offset alignment\n");
 401                 return -EINVAL;
 402         }
 403
 404         /* Disable while we are mucking around */
 405         temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 406         temp_ctl &= ~CA91CX42_VSI_CTL_EN;
 407         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 408
 409         /* Setup mapping */
 410         iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
 411         iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
 412         iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
 413
 414 /* XXX Prefetch stuff currently unsupported */
 415 #if 0
 416         if (vmeIn->wrPostEnable)
 417                 temp_ctl |= CA91CX42_VSI_CTL_PWEN;
 418         if (vmeIn->prefetchEnable)
 419                 temp_ctl |= CA91CX42_VSI_CTL_PREN;
 420         if (vmeIn->rmwLock)
 421                 temp_ctl |= CA91CX42_VSI_CTL_LLRMW;
 422         if (vmeIn->data64BitCapable)
 423                 temp_ctl |= CA91CX42_VSI_CTL_LD64EN;
 424 #endif
 425
 426         /* Setup address space */
 427         temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
 428         temp_ctl |= addr;
 429
 430         /* Setup cycle types */
 431         temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
 432         if (cycle & VME_SUPER)
 433                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
 434         if (cycle & VME_USER)
 435                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
 436         if (cycle & VME_PROG)
 437                 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
 438         if (cycle & VME_DATA)
 439                 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
 440
 441         /* Write ctl reg without enable */
 442         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 443
 444         if (enabled)
 445                 temp_ctl |= CA91CX42_VSI_CTL_EN;
 446
 447         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 448
 449         return 0;
 450 }
 451
 452 int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
 453         unsigned long long *vme_base, unsigned long long *size,
 454         dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
 455 {
 456         unsigned int i, granularity = 0, ctl = 0;
 457         unsigned long long vme_bound, pci_offset;
 458         struct ca91cx42_driver *bridge;
 459
 460         bridge = image->parent->driver_priv;
 461
 462         i = image->number;
 463
 464         if ((i == 0) || (i == 4))
 465                 granularity = 0x1000;
 466         else
 467                 granularity = 0x10000;
 468
 469         /* Read Registers */
 470         ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 471
 472         *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
 473         vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
 474         pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
 475
 476         *pci_base = (dma_addr_t)vme_base + pci_offset;
 477         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 478
 479         *enabled = 0;
 480         *aspace = 0;
 481         *cycle = 0;
 482
 483         if (ctl & CA91CX42_VSI_CTL_EN)
 484                 *enabled = 1;
 485
 486         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
 487                 *aspace = VME_A16;
 488         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
 489                 *aspace = VME_A24;
 490         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
 491                 *aspace = VME_A32;
 492         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
 493                 *aspace = VME_USER1;
 494         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
 495                 *aspace = VME_USER2;
 496
 497         if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
 498                 *cycle |= VME_SUPER;
 499         if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
 500                 *cycle |= VME_USER;
 501         if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
 502                 *cycle |= VME_PROG;
 503         if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
 504                 *cycle |= VME_DATA;
 505
 506         return 0;
 507 }
 508
 509 /*
 510  * Allocate and map PCI Resource
 511  */
 512 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
 513         unsigned long long size)
 514 {
 515         unsigned long long existing_size;
 516         int retval = 0;
 517         struct pci_dev *pdev;
 518         struct vme_bridge *ca91cx42_bridge;
 519
 520         ca91cx42_bridge = image->parent;
 521
 522         /* Find pci_dev container of dev */
 523         if (ca91cx42_bridge->parent == NULL) {
 524                 printk(KERN_ERR "Dev entry NULL\n");
 525                 return -EINVAL;
 526         }
 527         pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
 528
 529         existing_size = (unsigned long long)(image->bus_resource.end -
 530                 image->bus_resource.start);
 531
 532         /* If the existing size is OK, return */
 533         if (existing_size == (size - 1))
 534                 return 0;
 535
 536         if (existing_size != 0) {
 537                 iounmap(image->kern_base);
 538                 image->kern_base = NULL;
 539                 if (image->bus_resource.name != NULL)
 540                         kfree(image->bus_resource.name);
 541                 release_resource(&(image->bus_resource));
 542                 memset(&(image->bus_resource), 0, sizeof(struct resource));
 543         }
 544
 545         if (image->bus_resource.name == NULL) {
 546                 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
 547                 if (image->bus_resource.name == NULL) {
 548                         printk(KERN_ERR "Unable to allocate memory for resource"
 549                                 " name\n");
 550                         retval = -ENOMEM;
 551                         goto err_name;
 552                 }
 553         }
 554
 555         sprintf((char *)image->bus_resource.name, "%s.%d",
 556                 ca91cx42_bridge->name, image->number);
 557
 558         image->bus_resource.start = 0;
 559         image->bus_resource.end = (unsigned long)size;
 560         image->bus_resource.flags = IORESOURCE_MEM;
 561
 562         retval = pci_bus_alloc_resource(pdev->bus,
 563                 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
 564                 0, NULL, NULL);
 565         if (retval) {
 566                 printk(KERN_ERR "Failed to allocate mem resource for "
 567                         "window %d size 0x%lx start 0x%lx\n",
 568                         image->number, (unsigned long)size,
 569                         (unsigned long)image->bus_resource.start);
 570                 goto err_resource;
 571         }
 572
 573         image->kern_base = ioremap_nocache(
 574                 image->bus_resource.start, size);
 575         if (image->kern_base == NULL) {
 576                 printk(KERN_ERR "Failed to remap resource\n");
 577                 retval = -ENOMEM;
 578                 goto err_remap;
 579         }
 580
 581         return 0;
 582
 583         iounmap(image->kern_base);
 584         image->kern_base = NULL;
 585 err_remap:
 586         release_resource(&(image->bus_resource));
 587 err_resource:
 588         kfree(image->bus_resource.name);
 589         memset(&(image->bus_resource), 0, sizeof(struct resource));
 590 err_name:
 591         return retval;
 592 }
 593
 594 /*
 595  * Free and unmap PCI Resource
 596  */
 597 static void ca91cx42_free_resource(struct vme_master_resource *image)
 598 {
 599         iounmap(image->kern_base);
 600         image->kern_base = NULL;
 601         release_resource(&(image->bus_resource));
 602         kfree(image->bus_resource.name);
 603         memset(&(image->bus_resource), 0, sizeof(struct resource));
 604 }
 605
 606
 607 int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
 608         unsigned long long vme_base, unsigned long long size,
 609         vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
 610 {
 611         int retval = 0;
 612         unsigned int i, granularity = 0;
 613         unsigned int temp_ctl = 0;
 614         unsigned long long pci_bound, vme_offset, pci_base;
 615         struct ca91cx42_driver *bridge;
 616
 617         bridge = image->parent->driver_priv;
 618
 619         i = image->number;
 620
 621         if ((i == 0) || (i == 4))
 622                 granularity = 0x1000;
 623         else
 624                 granularity = 0x10000;
 625
 626         /* Verify input data */
 627         if (vme_base & (granularity - 1)) {
 628                 printk(KERN_ERR "Invalid VME Window alignment\n");
 629                 retval = -EINVAL;
 630                 goto err_window;
 631         }
 632         if (size & (granularity - 1)) {
 633                 printk(KERN_ERR "Invalid VME Window alignment\n");
 634                 retval = -EINVAL;
 635                 goto err_window;
 636         }
 637
 638         spin_lock(&(image->lock));
 639
 640         /* XXX We should do this much later, so that we can exit without
 641          *     needing to redo the mapping...
 642          */
 643         /*
 644          * Let's allocate the resource here rather than further up the stack as
 645          * it avoids pushing loads of bus dependant stuff up the stack
 646          */
 647         retval = ca91cx42_alloc_resource(image, size);
 648         if (retval) {
 649                 spin_unlock(&(image->lock));
 650                 printk(KERN_ERR "Unable to allocate memory for resource "
 651                         "name\n");
 652                 retval = -ENOMEM;
 653                 goto err_res;
 654         }
 655
 656         pci_base = (unsigned long long)image->bus_resource.start;
 657
 658         /*
 659          * Bound address is a valid address for the window, adjust
 660          * according to window granularity.
 661          */
 662         pci_bound = pci_base + size;
 663         vme_offset = vme_base - pci_base;
 664
 665         /* Disable while we are mucking around */
 666         temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 667         temp_ctl &= ~CA91CX42_LSI_CTL_EN;
 668         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 669
 670 /* XXX Prefetch stuff currently unsupported */
 671 #if 0
 672         if (vmeOut->wrPostEnable)
 673                 temp_ctl |= 0x40000000;
 674 #endif
 675
 676         /* Setup cycle types */
 677         temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
 678         if (cycle & VME_BLT)
 679                 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
 680         if (cycle & VME_MBLT)
 681                 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
 682
 683         /* Setup data width */
 684         temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
 685         switch (dwidth) {
 686         case VME_D8:
 687                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
 688                 break;
 689         case VME_D16:
 690                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
 691                 break;
 692         case VME_D32:
 693                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
 694                 break;
 695         case VME_D64:
 696                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
 697                 break;
 698         default:
 699                 spin_unlock(&(image->lock));
 700                 printk(KERN_ERR "Invalid data width\n");
 701                 retval = -EINVAL;
 702                 goto err_dwidth;
 703                 break;
 704         }
 705
 706         /* Setup address space */
 707         temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
 708         switch (aspace) {
 709         case VME_A16:
 710                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
 711                 break;
 712         case VME_A24:
 713                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
 714                 break;
 715         case VME_A32:
 716                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
 717                 break;
 718         case VME_CRCSR:
 719                 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
 720                 break;
 721         case VME_USER1:
 722                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
 723                 break;
 724         case VME_USER2:
 725                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
 726                 break;
 727         case VME_A64:
 728         case VME_USER3:
 729         case VME_USER4:
 730         default:
 731                 spin_unlock(&(image->lock));
 732                 printk(KERN_ERR "Invalid address space\n");
 733                 retval = -EINVAL;
 734                 goto err_aspace;
 735                 break;
 736         }
 737
 738         temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
 739         if (cycle & VME_SUPER)
 740                 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
 741         if (cycle & VME_PROG)
 742                 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
 743
 744         /* Setup mapping */
 745         iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
 746         iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
 747         iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
 748
 749         /* Write ctl reg without enable */
 750         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 751
 752         if (enabled)
 753                 temp_ctl |= CA91CX42_LSI_CTL_EN;
 754
 755         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 756
 757         spin_unlock(&(image->lock));
 758         return 0;
 759
 760 err_aspace:
 761 err_dwidth:
 762         ca91cx42_free_resource(image);
 763 err_res:
 764 err_window:
 765         return retval;
 766 }
 767
 768 int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
 769         unsigned long long *vme_base, unsigned long long *size,
 770         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
 771 {
 772         unsigned int i, ctl;
 773         unsigned long long pci_base, pci_bound, vme_offset;
 774         struct ca91cx42_driver *bridge;
 775
 776         bridge = image->parent->driver_priv;
 777
 778         i = image->number;
 779
 780         ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 781
 782         pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
 783         vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
 784         pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
 785
 786         *vme_base = pci_base + vme_offset;
 787         *size = (unsigned long long)(pci_bound - pci_base);
 788
 789         *enabled = 0;
 790         *aspace = 0;
 791         *cycle = 0;
 792         *dwidth = 0;
 793
 794         if (ctl & CA91CX42_LSI_CTL_EN)
 795                 *enabled = 1;
 796
 797         /* Setup address space */
 798         switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
 799         case CA91CX42_LSI_CTL_VAS_A16:
 800                 *aspace = VME_A16;
 801                 break;
 802         case CA91CX42_LSI_CTL_VAS_A24:
 803                 *aspace = VME_A24;
 804                 break;
 805         case CA91CX42_LSI_CTL_VAS_A32:
 806                 *aspace = VME_A32;
 807                 break;
 808         case CA91CX42_LSI_CTL_VAS_CRCSR:
 809                 *aspace = VME_CRCSR;
 810                 break;
 811         case CA91CX42_LSI_CTL_VAS_USER1:
 812                 *aspace = VME_USER1;
 813                 break;
 814         case CA91CX42_LSI_CTL_VAS_USER2:
 815                 *aspace = VME_USER2;
 816                 break;
 817         }
 818
 819         /* XXX Not sure howto check for MBLT */
 820         /* Setup cycle types */
 821         if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
 822                 *cycle |= VME_BLT;
 823         else
 824                 *cycle |= VME_SCT;
 825
 826         if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
 827                 *cycle |= VME_SUPER;
 828         else
 829                 *cycle |= VME_USER;
 830
 831         if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
 832                 *cycle = VME_PROG;
 833         else
 834                 *cycle = VME_DATA;
 835
 836         /* Setup data width */
 837         switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
 838         case CA91CX42_LSI_CTL_VDW_D8:
 839                 *dwidth = VME_D8;
 840                 break;
 841         case CA91CX42_LSI_CTL_VDW_D16:
 842                 *dwidth = VME_D16;
 843                 break;
 844         case CA91CX42_LSI_CTL_VDW_D32:
 845                 *dwidth = VME_D32;
 846                 break;
 847         case CA91CX42_LSI_CTL_VDW_D64:
 848                 *dwidth = VME_D64;
 849                 break;
 850         }
 851
 852 /* XXX Prefetch stuff currently unsupported */
 853 #if 0
 854         if (ctl & 0x40000000)
 855                 vmeOut->wrPostEnable = 1;
 856 #endif
 857
 858         return 0;
 859 }
 860
 861 int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
 862         unsigned long long *vme_base, unsigned long long *size,
 863         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
 864 {
 865         int retval;
 866
 867         spin_lock(&(image->lock));
 868
 869         retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
 870                 cycle, dwidth);
 871
 872         spin_unlock(&(image->lock));
 873
 874         return retval;
 875 }
 876
 877 ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf,
 878         size_t count, loff_t offset)
 879 {
 880         ssize_t retval;
 881
 882         spin_lock(&(image->lock));
 883
 884         memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
 885         retval = count;
 886
 887         spin_unlock(&(image->lock));
 888
 889         return retval;
 890 }
 891
 892 ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf,
 893         size_t count, loff_t offset)
 894 {
 895         int retval = 0;
 896
 897         spin_lock(&(image->lock));
 898
 899         memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
 900         retval = count;
 901
 902         spin_unlock(&(image->lock));
 903
 904         return retval;
 905 }
 906
 907 unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
 908         unsigned int mask, unsigned int compare, unsigned int swap,
 909         loff_t offset)
 910 {
 911         u32 pci_addr, result;
 912         int i;
 913         struct ca91cx42_driver *bridge;
 914         struct device *dev;
 915
 916         bridge = image->parent->driver_priv;
 917         dev = image->parent->parent;
 918
 919         /* Find the PCI address that maps to the desired VME address */
 920         i = image->number;
 921
 922         /* Locking as we can only do one of these at a time */
 923         mutex_lock(&(bridge->vme_rmw));
 924
 925         /* Lock image */
 926         spin_lock(&(image->lock));
 927
 928         pci_addr = (u32)image->kern_base + offset;
 929
 930         /* Address must be 4-byte aligned */
 931         if (pci_addr & 0x3) {
 932                 dev_err(dev, "RMW Address not 4-byte aligned\n");
 933                 return -EINVAL;
 934         }
 935
 936         /* Ensure RMW Disabled whilst configuring */
 937         iowrite32(0, bridge->base + SCYC_CTL);
 938
 939         /* Configure registers */
 940         iowrite32(mask, bridge->base + SCYC_EN);
 941         iowrite32(compare, bridge->base + SCYC_CMP);
 942         iowrite32(swap, bridge->base + SCYC_SWP);
 943         iowrite32(pci_addr, bridge->base + SCYC_ADDR);
 944
 945         /* Enable RMW */
 946         iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
 947
 948         /* Kick process off with a read to the required address. */
 949         result = ioread32(image->kern_base + offset);
 950
 951         /* Disable RMW */
 952         iowrite32(0, bridge->base + SCYC_CTL);
 953
 954         spin_unlock(&(image->lock));
 955
 956         mutex_unlock(&(bridge->vme_rmw));
 957
 958         return result;
 959 }
 960
 961 int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
 962         struct vme_dma_attr *dest, size_t count)
 963 {
 964         struct ca91cx42_dma_entry *entry, *prev;
 965         struct vme_dma_pci *pci_attr;
 966         struct vme_dma_vme *vme_attr;
 967         dma_addr_t desc_ptr;
 968         int retval = 0;
 969
 970         /* XXX descriptor must be aligned on 64-bit boundaries */
 971         entry = (struct ca91cx42_dma_entry *)
 972                 kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
 973         if (entry == NULL) {
 974                 printk(KERN_ERR "Failed to allocate memory for dma resource "
 975                         "structure\n");
 976                 retval = -ENOMEM;
 977                 goto err_mem;
 978         }
 979
 980         /* Test descriptor alignment */
 981         if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) {
 982                 printk("Descriptor not aligned to 16 byte boundary as "
 983                         "required: %p\n", &(entry->descriptor));
 984                 retval = -EINVAL;
 985                 goto err_align;
 986         }
 987
 988         memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor));
 989
 990         if (dest->type == VME_DMA_VME) {
 991                 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
 992                 vme_attr = (struct vme_dma_vme *)dest->private;
 993                 pci_attr = (struct vme_dma_pci *)src->private;
 994         } else {
 995                 vme_attr = (struct vme_dma_vme *)src->private;
 996                 pci_attr = (struct vme_dma_pci *)dest->private;
 997         }
 998
 999         /* Check we can do fullfill required attributes */
1000         if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1001                 VME_USER2)) != 0) {
1002
1003                 printk(KERN_ERR "Unsupported cycle type\n");
1004                 retval = -EINVAL;
1005                 goto err_aspace;
1006         }
1007
1008         if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1009                 VME_PROG | VME_DATA)) != 0) {
1010
1011                 printk(KERN_ERR "Unsupported cycle type\n");
1012                 retval = -EINVAL;
1013                 goto err_cycle;
1014         }
1015
1016         /* Check to see if we can fullfill source and destination */
1017         if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1018                 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1019
1020                 printk(KERN_ERR "Cannot perform transfer with this "
1021                         "source-destination combination\n");
1022                 retval = -EINVAL;
1023                 goto err_direct;
1024         }
1025
1026         /* Setup cycle types */
1027         if (vme_attr->cycle & VME_BLT)
1028                 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1029
1030         /* Setup data width */
1031         switch (vme_attr->dwidth) {
1032         case VME_D8:
1033                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1034                 break;
1035         case VME_D16:
1036                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1037                 break;
1038         case VME_D32:
1039                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1040                 break;
1041         case VME_D64:
1042                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1043                 break;
1044         default:
1045                 printk(KERN_ERR "Invalid data width\n");
1046                 return -EINVAL;
1047         }
1048
1049         /* Setup address space */
1050         switch (vme_attr->aspace) {
1051         case VME_A16:
1052                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1053                 break;
1054         case VME_A24:
1055                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1056                 break;
1057         case VME_A32:
1058                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1059                 break;
1060         case VME_USER1:
1061                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1062                 break;
1063         case VME_USER2:
1064                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1065                 break;
1066         default:
1067                 printk(KERN_ERR "Invalid address space\n");
1068                 return -EINVAL;
1069                 break;
1070         }
1071
1072         if (vme_attr->cycle & VME_SUPER)
1073                 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1074         if (vme_attr->cycle & VME_PROG)
1075                 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1076
1077         entry->descriptor.dtbc = count;
1078         entry->descriptor.dla = pci_attr->address;
1079         entry->descriptor.dva = vme_attr->address;
1080         entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1081
1082         /* Add to list */
1083         list_add_tail(&(entry->list), &(list->entries));
1084
1085         /* Fill out previous descriptors "Next Address" */
1086         if (entry->list.prev != &(list->entries)) {
1087                 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1088                         list);
1089                 /* We need the bus address for the pointer */
1090                 desc_ptr = virt_to_bus(&(entry->descriptor));
1091                 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1092         }
1093
1094         return 0;
1095
1096 err_cycle:
1097 err_aspace:
1098 err_direct:
1099 err_align:
1100         kfree(entry);
1101 err_mem:
1102         return retval;
1103 }
1104
1105 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1106 {
1107         u32 tmp;
1108         struct ca91cx42_driver *bridge;
1109
1110         bridge = ca91cx42_bridge->driver_priv;
1111
1112         tmp = ioread32(bridge->base + DGCS);
1113
1114         if (tmp & CA91CX42_DGCS_ACT)
1115                 return 0;
1116         else
1117                 return 1;
1118 }
1119
1120 int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1121 {
1122         struct vme_dma_resource *ctrlr;
1123         struct ca91cx42_dma_entry *entry;
1124         int retval = 0;
1125         dma_addr_t bus_addr;
1126         u32 val;
1127
1128         struct ca91cx42_driver *bridge;
1129
1130         ctrlr = list->parent;
1131
1132         bridge = ctrlr->parent->driver_priv;
1133
1134         mutex_lock(&(ctrlr->mtx));
1135
1136         if (!(list_empty(&(ctrlr->running)))) {
1137                 /*
1138                  * XXX We have an active DMA transfer and currently haven't
1139                  *     sorted out the mechanism for "pending" DMA transfers.
1140                  *     Return busy.
1141                  */
1142                 /* Need to add to pending here */
1143                 mutex_unlock(&(ctrlr->mtx));
1144                 return -EBUSY;
1145         } else {
1146                 list_add(&(list->list), &(ctrlr->running));
1147         }
1148
1149         /* Get first bus address and write into registers */
1150         entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry,
1151                 list);
1152
1153         bus_addr = virt_to_bus(&(entry->descriptor));
1154
1155         mutex_unlock(&(ctrlr->mtx));
1156
1157         iowrite32(0, bridge->base + DTBC);
1158         iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1159
1160         /* Start the operation */
1161         val = ioread32(bridge->base + DGCS);
1162
1163         /* XXX Could set VMEbus On and Off Counters here */
1164         val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1165
1166         val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1167                 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1168                 CA91CX42_DGCS_PERR);
1169
1170         iowrite32(val, bridge->base + DGCS);
1171
1172         val |= CA91CX42_DGCS_GO;
1173
1174         iowrite32(val, bridge->base + DGCS);
1175
1176         wait_event_interruptible(bridge->dma_queue,
1177                 ca91cx42_dma_busy(ctrlr->parent));
1178
1179         /*
1180          * Read status register, this register is valid until we kick off a
1181          * new transfer.
1182          */
1183         val = ioread32(bridge->base + DGCS);
1184
1185         if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1186                 CA91CX42_DGCS_PERR)) {
1187
1188                 printk(KERN_ERR "ca91c042: DMA Error. DGCS=%08X\n", val);
1189                 val = ioread32(bridge->base + DCTL);
1190         }
1191
1192         /* Remove list from running list */
1193         mutex_lock(&(ctrlr->mtx));
1194         list_del(&(list->list));
1195         mutex_unlock(&(ctrlr->mtx));
1196
1197         return retval;
1198
1199 }
1200
1201 int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1202 {
1203         struct list_head *pos, *temp;
1204         struct ca91cx42_dma_entry *entry;
1205
1206         /* detach and free each entry */
1207         list_for_each_safe(pos, temp, &(list->entries)) {
1208                 list_del(pos);
1209                 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1210                 kfree(entry);
1211         }
1212
1213         return 0;
1214 }
1215
1216 /*
1217  * All 4 location monitors reside at the same base - this is therefore a
1218  * system wide configuration.
1219  *
1220  * This does not enable the LM monitor - that should be done when the first
1221  * callback is attached and disabled when the last callback is removed.
1222  */
1223 int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1224         vme_address_t aspace, vme_cycle_t cycle)
1225 {
1226         u32 temp_base, lm_ctl = 0;
1227         int i;
1228         struct ca91cx42_driver *bridge;
1229         struct device *dev;
1230
1231         bridge = lm->parent->driver_priv;
1232         dev = lm->parent->parent;
1233
1234         /* Check the alignment of the location monitor */
1235         temp_base = (u32)lm_base;
1236         if (temp_base & 0xffff) {
1237                 dev_err(dev, "Location monitor must be aligned to 64KB "
1238                         "boundary");
1239                 return -EINVAL;
1240         }
1241
1242         mutex_lock(&(lm->mtx));
1243
1244         /* If we already have a callback attached, we can't move it! */
1245         for (i = 0; i < lm->monitors; i++) {
1246                 if (bridge->lm_callback[i] != NULL) {
1247                         mutex_unlock(&(lm->mtx));
1248                         dev_err(dev, "Location monitor callback attached, "
1249                                 "can't reset\n");
1250                         return -EBUSY;
1251                 }
1252         }
1253
1254         switch (aspace) {
1255         case VME_A16:
1256                 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1257                 break;
1258         case VME_A24:
1259                 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1260                 break;
1261         case VME_A32:
1262                 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1263                 break;
1264         default:
1265                 mutex_unlock(&(lm->mtx));
1266                 dev_err(dev, "Invalid address space\n");
1267                 return -EINVAL;
1268                 break;
1269         }
1270
1271         if (cycle & VME_SUPER)
1272                 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1273         if (cycle & VME_USER)
1274                 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1275         if (cycle & VME_PROG)
1276                 lm_ctl |= CA91CX42_LM_CTL_PGM;
1277         if (cycle & VME_DATA)
1278                 lm_ctl |= CA91CX42_LM_CTL_DATA;
1279
1280         iowrite32(lm_base, bridge->base + LM_BS);
1281         iowrite32(lm_ctl, bridge->base + LM_CTL);
1282
1283         mutex_unlock(&(lm->mtx));
1284
1285         return 0;
1286 }
1287
1288 /* Get configuration of the callback monitor and return whether it is enabled
1289  * or disabled.
1290  */
1291 int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
1292         vme_address_t *aspace, vme_cycle_t *cycle)
1293 {
1294         u32 lm_ctl, enabled = 0;
1295         struct ca91cx42_driver *bridge;
1296
1297         bridge = lm->parent->driver_priv;
1298
1299         mutex_lock(&(lm->mtx));
1300
1301         *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1302         lm_ctl = ioread32(bridge->base + LM_CTL);
1303
1304         if (lm_ctl & CA91CX42_LM_CTL_EN)
1305                 enabled = 1;
1306
1307         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1308                 *aspace = VME_A16;
1309         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1310                 *aspace = VME_A24;
1311         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1312                 *aspace = VME_A32;
1313
1314         *cycle = 0;
1315         if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1316                 *cycle |= VME_SUPER;
1317         if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1318                 *cycle |= VME_USER;
1319         if (lm_ctl & CA91CX42_LM_CTL_PGM)
1320                 *cycle |= VME_PROG;
1321         if (lm_ctl & CA91CX42_LM_CTL_DATA)
1322                 *cycle |= VME_DATA;
1323
1324         mutex_unlock(&(lm->mtx));
1325
1326         return enabled;
1327 }
1328
1329 /*
1330  * Attach a callback to a specific location monitor.
1331  *
1332  * Callback will be passed the monitor triggered.
1333  */
1334 int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1335         void (*callback)(int))
1336 {
1337         u32 lm_ctl, tmp;
1338         struct ca91cx42_driver *bridge;
1339         struct device *dev;
1340
1341         bridge = lm->parent->driver_priv;
1342         dev = lm->parent->parent;
1343
1344         mutex_lock(&(lm->mtx));
1345
1346         /* Ensure that the location monitor is configured - need PGM or DATA */
1347         lm_ctl = ioread32(bridge->base + LM_CTL);
1348         if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1349                 mutex_unlock(&(lm->mtx));
1350                 dev_err(dev, "Location monitor not properly configured\n");
1351                 return -EINVAL;
1352         }
1353
1354         /* Check that a callback isn't already attached */
1355         if (bridge->lm_callback[monitor] != NULL) {
1356                 mutex_unlock(&(lm->mtx));
1357                 dev_err(dev, "Existing callback attached\n");
1358                 return -EBUSY;
1359         }
1360
1361         /* Attach callback */
1362         bridge->lm_callback[monitor] = callback;
1363
1364         /* Enable Location Monitor interrupt */
1365         tmp = ioread32(bridge->base + LINT_EN);
1366         tmp |= CA91CX42_LINT_LM[monitor];
1367         iowrite32(tmp, bridge->base + LINT_EN);
1368
1369         /* Ensure that global Location Monitor Enable set */
1370         if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1371                 lm_ctl |= CA91CX42_LM_CTL_EN;
1372                 iowrite32(lm_ctl, bridge->base + LM_CTL);
1373         }
1374
1375         mutex_unlock(&(lm->mtx));
1376
1377         return 0;
1378 }
1379
1380 /*
1381  * Detach a callback function forn a specific location monitor.
1382  */
1383 int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1384 {
1385         u32 tmp;
1386         struct ca91cx42_driver *bridge;
1387
1388         bridge = lm->parent->driver_priv;
1389
1390         mutex_lock(&(lm->mtx));
1391
1392         /* Disable Location Monitor and ensure previous interrupts are clear */
1393         tmp = ioread32(bridge->base + LINT_EN);
1394         tmp &= ~CA91CX42_LINT_LM[monitor];
1395         iowrite32(tmp, bridge->base + LINT_EN);
1396
1397         iowrite32(CA91CX42_LINT_LM[monitor],
1398                  bridge->base + LINT_STAT);
1399
1400         /* Detach callback */
1401         bridge->lm_callback[monitor] = NULL;
1402
1403         /* If all location monitors disabled, disable global Location Monitor */
1404         if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1405                         CA91CX42_LINT_LM3)) == 0) {
1406                 tmp = ioread32(bridge->base + LM_CTL);
1407                 tmp &= ~CA91CX42_LM_CTL_EN;
1408                 iowrite32(tmp, bridge->base + LM_CTL);
1409         }
1410
1411         mutex_unlock(&(lm->mtx));
1412
1413         return 0;
1414 }
1415
1416 int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1417 {
1418         u32 slot = 0;
1419         struct ca91cx42_driver *bridge;
1420
1421         bridge = ca91cx42_bridge->driver_priv;
1422
1423         if (!geoid) {
1424                 slot = ioread32(bridge->base + VCSR_BS);
1425                 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1426         } else
1427                 slot = geoid;
1428
1429         return (int)slot;
1430
1431 }
1432
1433 static int __init ca91cx42_init(void)
1434 {
1435         return pci_register_driver(&ca91cx42_driver);
1436 }
1437
1438 /*
1439  * Configure CR/CSR space
1440  *
1441  * Access to the CR/CSR can be configured at power-up. The location of the
1442  * CR/CSR registers in the CR/CSR address space is determined by the boards
1443  * Auto-ID or Geographic address. This function ensures that the window is
1444  * enabled at an offset consistent with the boards geopgraphic address.
1445  */
1446 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1447         struct pci_dev *pdev)
1448 {
1449         unsigned int crcsr_addr;
1450         int tmp, slot;
1451         struct ca91cx42_driver *bridge;
1452
1453         bridge = ca91cx42_bridge->driver_priv;
1454
1455         slot = ca91cx42_slot_get(ca91cx42_bridge);
1456
1457         /* Write CSR Base Address if slot ID is supplied as a module param */
1458         if (geoid)
1459                 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1460
1461         dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1462         if (slot == 0) {
1463                 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1464                         "CR/CSR space\n");
1465                 return -EINVAL;
1466         }
1467
1468         /* Allocate mem for CR/CSR image */
1469         bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1470                 &(bridge->crcsr_bus));
1471         if (bridge->crcsr_kernel == NULL) {
1472                 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1473                         "image\n");
1474                 return -ENOMEM;
1475         }
1476
1477         memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
1478
1479         crcsr_addr = slot * (512 * 1024);
1480         iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1481
1482         tmp = ioread32(bridge->base + VCSR_CTL);
1483         tmp |= CA91CX42_VCSR_CTL_EN;
1484         iowrite32(tmp, bridge->base + VCSR_CTL);
1485
1486         return 0;
1487 }
1488
1489 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1490         struct pci_dev *pdev)
1491 {
1492         u32 tmp;
1493         struct ca91cx42_driver *bridge;
1494
1495         bridge = ca91cx42_bridge->driver_priv;
1496
1497         /* Turn off CR/CSR space */
1498         tmp = ioread32(bridge->base + VCSR_CTL);
1499         tmp &= ~CA91CX42_VCSR_CTL_EN;
1500         iowrite32(tmp, bridge->base + VCSR_CTL);
1501
1502         /* Free image */
1503         iowrite32(0, bridge->base + VCSR_TO);
1504
1505         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1506                 bridge->crcsr_bus);
1507 }
1508
1509 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1510 {
1511         int retval, i;
1512         u32 data;
1513         struct list_head *pos = NULL;
1514         struct vme_bridge *ca91cx42_bridge;
1515         struct ca91cx42_driver *ca91cx42_device;
1516         struct vme_master_resource *master_image;
1517         struct vme_slave_resource *slave_image;
1518         struct vme_dma_resource *dma_ctrlr;
1519         struct vme_lm_resource *lm;
1520
1521         /* We want to support more than one of each bridge so we need to
1522          * dynamically allocate the bridge structure
1523          */
1524         ca91cx42_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1525
1526         if (ca91cx42_bridge == NULL) {
1527                 dev_err(&pdev->dev, "Failed to allocate memory for device "
1528                         "structure\n");
1529                 retval = -ENOMEM;
1530                 goto err_struct;
1531         }
1532
1533         memset(ca91cx42_bridge, 0, sizeof(struct vme_bridge));
1534
1535         ca91cx42_device = kmalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1536
1537         if (ca91cx42_device == NULL) {
1538                 dev_err(&pdev->dev, "Failed to allocate memory for device "
1539                         "structure\n");
1540                 retval = -ENOMEM;
1541                 goto err_driver;
1542         }
1543
1544         memset(ca91cx42_device, 0, sizeof(struct ca91cx42_driver));
1545
1546         ca91cx42_bridge->driver_priv = ca91cx42_device;
1547
1548         /* Enable the device */
1549         retval = pci_enable_device(pdev);
1550         if (retval) {
1551                 dev_err(&pdev->dev, "Unable to enable device\n");
1552                 goto err_enable;
1553         }
1554
1555         /* Map Registers */
1556         retval = pci_request_regions(pdev, driver_name);
1557         if (retval) {
1558                 dev_err(&pdev->dev, "Unable to reserve resources\n");
1559                 goto err_resource;
1560         }
1561
1562         /* map registers in BAR 0 */
1563         ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1564                 4096);
1565         if (!ca91cx42_device->base) {
1566                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1567                 retval = -EIO;
1568                 goto err_remap;
1569         }
1570
1571         /* Check to see if the mapping worked out */
1572         data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1573         if (data != PCI_VENDOR_ID_TUNDRA) {
1574                 dev_err(&pdev->dev, "PCI_ID check failed\n");
1575                 retval = -EIO;
1576                 goto err_test;
1577         }
1578
1579         /* Initialize wait queues & mutual exclusion flags */
1580         init_waitqueue_head(&(ca91cx42_device->dma_queue));
1581         init_waitqueue_head(&(ca91cx42_device->iack_queue));
1582         mutex_init(&(ca91cx42_device->vme_int));
1583         mutex_init(&(ca91cx42_device->vme_rmw));
1584
1585         ca91cx42_bridge->parent = &(pdev->dev);
1586         strcpy(ca91cx42_bridge->name, driver_name);
1587
1588         /* Setup IRQ */
1589         retval = ca91cx42_irq_init(ca91cx42_bridge);
1590         if (retval != 0) {
1591                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1592                 goto err_irq;
1593         }
1594
1595         /* Add master windows to list */
1596         INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources));
1597         for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1598                 master_image = kmalloc(sizeof(struct vme_master_resource),
1599                         GFP_KERNEL);
1600                 if (master_image == NULL) {
1601                         dev_err(&pdev->dev, "Failed to allocate memory for "
1602                         "master resource structure\n");
1603                         retval = -ENOMEM;
1604                         goto err_master;
1605                 }
1606                 master_image->parent = ca91cx42_bridge;
1607                 spin_lock_init(&(master_image->lock));
1608                 master_image->locked = 0;
1609                 master_image->number = i;
1610                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1611                         VME_CRCSR | VME_USER1 | VME_USER2;
1612                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1613                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1614                 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1615                 memset(&(master_image->bus_resource), 0,
1616                         sizeof(struct resource));
1617                 master_image->kern_base  = NULL;
1618                 list_add_tail(&(master_image->list),
1619                         &(ca91cx42_bridge->master_resources));
1620         }
1621
1622         /* Add slave windows to list */
1623         INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources));
1624         for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1625                 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1626                         GFP_KERNEL);
1627                 if (slave_image == NULL) {
1628                         dev_err(&pdev->dev, "Failed to allocate memory for "
1629                         "slave resource structure\n");
1630                         retval = -ENOMEM;
1631                         goto err_slave;
1632                 }
1633                 slave_image->parent = ca91cx42_bridge;
1634                 mutex_init(&(slave_image->mtx));
1635                 slave_image->locked = 0;
1636                 slave_image->number = i;
1637                 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1638                         VME_USER2;
1639
1640                 /* Only windows 0 and 4 support A16 */
1641                 if (i == 0 || i == 4)
1642                         slave_image->address_attr |= VME_A16;
1643
1644                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1645                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1646                 list_add_tail(&(slave_image->list),
1647                         &(ca91cx42_bridge->slave_resources));
1648         }
1649
1650         /* Add dma engines to list */
1651         INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources));
1652         for (i = 0; i < CA91C142_MAX_DMA; i++) {
1653                 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1654                         GFP_KERNEL);
1655                 if (dma_ctrlr == NULL) {
1656                         dev_err(&pdev->dev, "Failed to allocate memory for "
1657                         "dma resource structure\n");
1658                         retval = -ENOMEM;
1659                         goto err_dma;
1660                 }
1661                 dma_ctrlr->parent = ca91cx42_bridge;
1662                 mutex_init(&(dma_ctrlr->mtx));
1663                 dma_ctrlr->locked = 0;
1664                 dma_ctrlr->number = i;
1665                 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1666                         VME_DMA_MEM_TO_VME;
1667                 INIT_LIST_HEAD(&(dma_ctrlr->pending));
1668                 INIT_LIST_HEAD(&(dma_ctrlr->running));
1669                 list_add_tail(&(dma_ctrlr->list),
1670                         &(ca91cx42_bridge->dma_resources));
1671         }
1672
1673         /* Add location monitor to list */
1674         INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources));
1675         lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1676         if (lm == NULL) {
1677                 dev_err(&pdev->dev, "Failed to allocate memory for "
1678                 "location monitor resource structure\n");
1679                 retval = -ENOMEM;
1680                 goto err_lm;
1681         }
1682         lm->parent = ca91cx42_bridge;
1683         mutex_init(&(lm->mtx));
1684         lm->locked = 0;
1685         lm->number = 1;
1686         lm->monitors = 4;
1687         list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources));
1688
1689         ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1690         ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1691         ca91cx42_bridge->master_get = ca91cx42_master_get;
1692         ca91cx42_bridge->master_set = ca91cx42_master_set;
1693         ca91cx42_bridge->master_read = ca91cx42_master_read;
1694         ca91cx42_bridge->master_write = ca91cx42_master_write;
1695         ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1696         ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1697         ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1698         ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1699         ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1700         ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1701         ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1702         ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1703         ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1704         ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1705         ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1706
1707         data = ioread32(ca91cx42_device->base + MISC_CTL);
1708         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1709                 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1710         dev_info(&pdev->dev, "Slot ID is %d\n",
1711                 ca91cx42_slot_get(ca91cx42_bridge));
1712
1713         if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) {
1714                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1715         }
1716
1717         /* Need to save ca91cx42_bridge pointer locally in link list for use in
1718          * ca91cx42_remove()
1719          */
1720         retval = vme_register_bridge(ca91cx42_bridge);
1721         if (retval != 0) {
1722                 dev_err(&pdev->dev, "Chip Registration failed.\n");
1723                 goto err_reg;
1724         }
1725
1726         pci_set_drvdata(pdev, ca91cx42_bridge);
1727
1728         return 0;
1729
1730         vme_unregister_bridge(ca91cx42_bridge);
1731 err_reg:
1732         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1733 err_lm:
1734         /* resources are stored in link list */
1735         list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1736                 lm = list_entry(pos, struct vme_lm_resource, list);
1737                 list_del(pos);
1738                 kfree(lm);
1739         }
1740 err_dma:
1741         /* resources are stored in link list */
1742         list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1743                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1744                 list_del(pos);
1745                 kfree(dma_ctrlr);
1746         }
1747 err_slave:
1748         /* resources are stored in link list */
1749         list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1750                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1751                 list_del(pos);
1752                 kfree(slave_image);
1753         }
1754 err_master:
1755         /* resources are stored in link list */
1756         list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1757                 master_image = list_entry(pos, struct vme_master_resource,
1758                         list);
1759                 list_del(pos);
1760                 kfree(master_image);
1761         }
1762
1763         ca91cx42_irq_exit(ca91cx42_device, pdev);
1764 err_irq:
1765 err_test:
1766         iounmap(ca91cx42_device->base);
1767 err_remap:
1768         pci_release_regions(pdev);
1769 err_resource:
1770         pci_disable_device(pdev);
1771 err_enable:
1772         kfree(ca91cx42_device);
1773 err_driver:
1774         kfree(ca91cx42_bridge);
1775 err_struct:
1776         return retval;
1777
1778 }
1779
1780 void ca91cx42_remove(struct pci_dev *pdev)
1781 {
1782         struct list_head *pos = NULL;
1783         struct vme_master_resource *master_image;
1784         struct vme_slave_resource *slave_image;
1785         struct vme_dma_resource *dma_ctrlr;
1786         struct vme_lm_resource *lm;
1787         struct ca91cx42_driver *bridge;
1788         struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1789
1790         bridge = ca91cx42_bridge->driver_priv;
1791
1792
1793         /* Turn off Ints */
1794         iowrite32(0, bridge->base + LINT_EN);
1795
1796         /* Turn off the windows */
1797         iowrite32(0x00800000, bridge->base + LSI0_CTL);
1798         iowrite32(0x00800000, bridge->base + LSI1_CTL);
1799         iowrite32(0x00800000, bridge->base + LSI2_CTL);
1800         iowrite32(0x00800000, bridge->base + LSI3_CTL);
1801         iowrite32(0x00800000, bridge->base + LSI4_CTL);
1802         iowrite32(0x00800000, bridge->base + LSI5_CTL);
1803         iowrite32(0x00800000, bridge->base + LSI6_CTL);
1804         iowrite32(0x00800000, bridge->base + LSI7_CTL);
1805         iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1806         iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1807         iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1808         iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1809         iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1810         iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1811         iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1812         iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1813
1814         vme_unregister_bridge(ca91cx42_bridge);
1815 #if 0
1816         ca91cx42_crcsr_exit(pdev);
1817 #endif
1818         /* resources are stored in link list */
1819         list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1820                 lm = list_entry(pos, struct vme_lm_resource, list);
1821                 list_del(pos);
1822                 kfree(lm);
1823         }
1824
1825         /* resources are stored in link list */
1826         list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1827                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1828                 list_del(pos);
1829                 kfree(dma_ctrlr);
1830         }
1831
1832         /* resources are stored in link list */
1833         list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1834                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1835                 list_del(pos);
1836                 kfree(slave_image);
1837         }
1838
1839         /* resources are stored in link list */
1840         list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1841                 master_image = list_entry(pos, struct vme_master_resource,
1842                         list);
1843                 list_del(pos);
1844                 kfree(master_image);
1845         }
1846
1847         ca91cx42_irq_exit(bridge, pdev);
1848
1849         iounmap(bridge->base);
1850
1851         pci_release_regions(pdev);
1852
1853         pci_disable_device(pdev);
1854
1855         kfree(ca91cx42_bridge);
1856 }
1857
1858 static void __exit ca91cx42_exit(void)
1859 {
1860         pci_unregister_driver(&ca91cx42_driver);
1861 }
1862
1863 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1864 module_param(geoid, int, 0);
1865
1866 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1867 MODULE_LICENSE("GPL");
1868
1869 module_init(ca91cx42_init);
1870 module_exit(ca91cx42_exit);
1871
1872 /*----------------------------------------------------------------------------
1873  * STAGING
1874  *--------------------------------------------------------------------------*/
1875
1876 #if 0
1877
1878 int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb)
1879 {
1880         int temp_ctl = 0;
1881         int vbto = 0;
1882
1883         temp_ctl = ioread32(bridge->base + MISC_CTL);
1884         temp_ctl &= 0x00FFFFFF;
1885
1886         if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) {
1887                 vbto = 7;
1888         } else if (vmeArb->globalTimeoutTimer > 1024) {
1889                 return -EINVAL;
1890         } else if (vmeArb->globalTimeoutTimer == 0) {
1891                 vbto = 0;
1892         } else {
1893                 vbto = 1;
1894                 while ((16 * (1 << (vbto - 1))) < vmeArb->globalTimeoutTimer)
1895                         vbto += 1;
1896         }
1897         temp_ctl |= (vbto << 28);
1898
1899         if (vmeArb->arbiterMode == VME_PRIORITY_MODE)
1900                 temp_ctl |= 1 << 26;
1901
1902         if (vmeArb->arbiterTimeoutFlag)
1903                 temp_ctl |= 2 << 24;
1904
1905         iowrite32(temp_ctl, bridge->base + MISC_CTL);
1906         return 0;
1907 }
1908
1909 int ca91cx42_get_arbiter(vmeArbiterCfg_t *vmeArb)
1910 {
1911         int temp_ctl = 0;
1912         int vbto = 0;
1913
1914         temp_ctl = ioread32(bridge->base + MISC_CTL);
1915
1916         vbto = (temp_ctl >> 28) & 0xF;
1917         if (vbto != 0)
1918                 vmeArb->globalTimeoutTimer = (16 * (1 << (vbto - 1)));
1919
1920         if (temp_ctl & (1 << 26))
1921                 vmeArb->arbiterMode = VME_PRIORITY_MODE;
1922         else
1923                 vmeArb->arbiterMode = VME_R_ROBIN_MODE;
1924
1925         if (temp_ctl & (3 << 24))
1926                 vmeArb->arbiterTimeoutFlag = 1;
1927
1928         return 0;
1929 }
1930
1931 int ca91cx42_set_requestor(vmeRequesterCfg_t *vmeReq)
1932 {
1933         int temp_ctl = 0;
1934
1935         temp_ctl = ioread32(bridge->base + MAST_CTL);
1936         temp_ctl &= 0xFF0FFFFF;
1937
1938         if (vmeReq->releaseMode == 1)
1939                 temp_ctl |= (1 << 20);
1940
1941         if (vmeReq->fairMode == 1)
1942                 temp_ctl |= (1 << 21);
1943
1944         temp_ctl |= (vmeReq->requestLevel << 22);
1945
1946         iowrite32(temp_ctl, bridge->base + MAST_CTL);
1947         return 0;
1948 }
1949
1950 int ca91cx42_get_requestor(vmeRequesterCfg_t *vmeReq)
1951 {
1952         int temp_ctl = 0;
1953
1954         temp_ctl = ioread32(bridge->base + MAST_CTL);
1955
1956         if (temp_ctl & (1 << 20))
1957                 vmeReq->releaseMode = 1;
1958
1959         if (temp_ctl & (1 << 21))
1960                 vmeReq->fairMode = 1;
1961
1962         vmeReq->requestLevel = (temp_ctl & 0xC00000) >> 22;
1963
1964         return 0;
1965 }
1966
1967
1968 #endif