4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
6 * Clock and Timer services.
8 * Copyright (C) 2005-2006 Texas Instruments, Inc.
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
19 #include <linux/types.h>
21 /* ----------------------------------- Host OS */
22 #include <dspbridge/host_os.h>
23 #include <plat/dmtimer.h>
24 #include <plat/mcbsp.h>
26 /* ----------------------------------- DSP/BIOS Bridge */
27 #include <dspbridge/dbdefs.h>
28 #include <dspbridge/drv.h>
29 #include <dspbridge/dev.h>
32 /* ----------------------------------- Trace & Debug */
33 #include <dspbridge/dbc.h>
35 /* ----------------------------------- This */
36 #include <dspbridge/clk.h>
38 /* ----------------------------------- Defines, Data Structures, Typedefs */
40 #define OMAP_SSI_OFFSET 0x58000
41 #define OMAP_SSI_SIZE 0x1000
42 #define OMAP_SSI_SYSCONFIG_OFFSET 0x10
44 #define SSI_AUTOIDLE (1 << 0)
45 #define SSI_SIDLE_SMARTIDLE (2 << 3)
46 #define SSI_MIDLE_NOIDLE (1 << 12)
48 /* Clk types requested by the dsp */
55 /* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */
56 #define DMT_ID(id) ((id) + 4)
58 /* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (0 - 4) */
59 #define MCBSP_ID(id) ((id) - 6)
61 static struct omap_dm_timer *timer[4];
71 static struct dsp_ssi ssi;
73 static u32 dsp_clocks;
75 static inline u32 is_dsp_clk_active(u32 clk, u8 id)
77 return clk & (1 << id);
80 static inline void set_dsp_clk_active(u32 *clk, u8 id)
85 static inline void set_dsp_clk_inactive(u32 *clk, u8 id)
90 static s8 get_clk_type(u8 id)
94 if (id == DSP_CLK_IVA2)
96 else if (id <= DSP_CLK_GPT8)
98 else if (id == DSP_CLK_WDT3)
100 else if (id <= DSP_CLK_MCBSP5)
102 else if (id == DSP_CLK_SSI)
111 * ======== dsp_clk_exit ========
113 * Cleanup CLK module.
115 void dsp_clk_exit(void)
117 dsp_clock_disable_all(dsp_clocks);
120 clk_put(ssi.sst_fck);
121 clk_put(ssi.ssr_fck);
126 * ======== dsp_clk_init ========
128 * Initialize CLK module.
130 void dsp_clk_init(void)
132 static struct platform_device dspbridge_device;
134 dspbridge_device.dev.bus = &platform_bus_type;
136 iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
137 if (IS_ERR(iva2_clk))
138 dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
140 ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
141 ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
142 ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
144 if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick))
145 dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
146 ssi.sst_fck, ssi.ssr_fck, ssi.ick);
150 * dsp_gpt_wait_overflow - set gpt overflow and wait for fixed timeout
151 * @clk_id: GP Timer clock id.
152 * @load: Overflow value.
154 * Sets an overflow interrupt for the desired GPT waiting for a timeout
155 * of 5 msecs for the interrupt to occur.
157 void dsp_gpt_wait_overflow(short int clk_id, unsigned int load)
159 struct omap_dm_timer *gpt = timer[clk_id - 1];
160 unsigned long timeout;
165 /* Enable overflow interrupt */
166 omap_dm_timer_set_int_enable(gpt, OMAP_TIMER_INT_OVERFLOW);
169 * Set counter value to overflow counter after
170 * one tick and start timer.
172 omap_dm_timer_set_load_start(gpt, 0, load);
174 /* Wait 80us for timer to overflow */
177 timeout = msecs_to_jiffies(5);
178 /* Check interrupt status and wait for interrupt */
179 while (!(omap_dm_timer_read_status(gpt) & OMAP_TIMER_INT_OVERFLOW)) {
180 if (time_is_after_jiffies(timeout)) {
181 pr_err("%s: GPTimer interrupt failed\n", __func__);
188 * ======== dsp_clk_enable ========
193 int dsp_clk_enable(enum dsp_clk_id clk_id)
197 if (is_dsp_clk_active(dsp_clocks, clk_id)) {
198 dev_err(bridge, "WARN: clock id %d already enabled\n", clk_id);
202 switch (get_clk_type(clk_id)) {
204 clk_enable(iva2_clk);
208 omap_dm_timer_request_specific(DMT_ID(clk_id));
210 #ifdef CONFIG_OMAP_MCBSP
212 omap_mcbsp_request(MCBSP_ID(clk_id));
213 omap2_mcbsp_set_clks_src(MCBSP_ID(clk_id), MCBSP_CLKS_PAD_SRC);
217 dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
220 clk_enable(ssi.sst_fck);
221 clk_enable(ssi.ssr_fck);
225 * The SSI module need to configured not to have the Forced
226 * idle for master interface. If it is set to forced idle,
227 * the SSI module is transitioning to standby thereby causing
228 * the client in the DSP hang waiting for the SSI module to
229 * be active after enabling the clocks
231 ssi_clk_prepare(true);
234 dev_err(bridge, "Invalid clock id for enable\n");
239 set_dsp_clk_active(&dsp_clocks, clk_id);
246 * dsp_clock_enable_all - Enable clocks used by the DSP
247 * @dev_context Driver's device context strucure
249 * This function enables all the peripheral clocks that were requested by DSP.
251 u32 dsp_clock_enable_all(u32 dsp_per_clocks)
256 for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
257 if (is_dsp_clk_active(dsp_per_clocks, clk_id))
258 status = dsp_clk_enable(clk_id);
265 * ======== dsp_clk_disable ========
270 int dsp_clk_disable(enum dsp_clk_id clk_id)
274 if (!is_dsp_clk_active(dsp_clocks, clk_id)) {
275 dev_err(bridge, "ERR: clock id %d already disabled\n", clk_id);
279 switch (get_clk_type(clk_id)) {
281 clk_disable(iva2_clk);
284 omap_dm_timer_free(timer[clk_id - 1]);
286 #ifdef CONFIG_OMAP_MCBSP
288 omap2_mcbsp_set_clks_src(MCBSP_ID(clk_id), MCBSP_CLKS_PRCM_SRC);
289 omap_mcbsp_free(MCBSP_ID(clk_id));
293 dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
296 ssi_clk_prepare(false);
297 ssi_clk_prepare(false);
298 clk_disable(ssi.sst_fck);
299 clk_disable(ssi.ssr_fck);
300 clk_disable(ssi.ick);
303 dev_err(bridge, "Invalid clock id for disable\n");
308 set_dsp_clk_inactive(&dsp_clocks, clk_id);
315 * dsp_clock_disable_all - Disable all active clocks
316 * @dev_context Driver's device context structure
318 * This function disables all the peripheral clocks that were enabled by DSP.
319 * It is meant to be called only when DSP is entering hibernation or when DSP
322 u32 dsp_clock_disable_all(u32 dsp_per_clocks)
327 for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
328 if (is_dsp_clk_active(dsp_per_clocks, clk_id))
329 status = dsp_clk_disable(clk_id);
335 u32 dsp_clk_get_iva2_rate(void)
339 clk_speed_khz = clk_get_rate(iva2_clk);
340 clk_speed_khz /= 1000;
341 dev_dbg(bridge, "%s: clk speed Khz = %d\n", __func__, clk_speed_khz);
343 return clk_speed_khz;
346 void ssi_clk_prepare(bool FLAG)
348 void __iomem *ssi_base;
351 ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
353 pr_err("%s: error, SSI not configured\n", __func__);
358 /* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
361 value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
363 /* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
366 value = SSI_AUTOIDLE;
369 __raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);