1 /**************************************************************************
3 * Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
5 * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
22 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * The views and conclusions contained in the software and documentation
32 * are those of the authors and should not be interpreted as representing
33 * official policies, either expressed or implied, of Alacritech, Inc.
35 **************************************************************************/
40 * This is the base set of header definitions for the SXG driver.
42 #ifndef __SXG_DRIVER_H__
43 #define __SXG_DRIVER_H__
45 #define SLIC_DUMP_ENABLED 0
47 #define SXG_DRV_NAME "sxg" /* TBD: This might be removed eventually */
48 #define SXG_DRV_VERSION "1.0.1"
50 extern char sxg_driver_name[];
52 * struct sxg_stats - Probably move these to someplace where
53 * the slicstat (sxgstat?) program can get them.
57 u32 XmtNBL; /* Offload send NBL count */
58 u64 DumbXmtBytes; /* Dumbnic send bytes */
59 u64 SlowXmtBytes; /* Slowpath send bytes */
60 u64 FastXmtBytes; /* Fastpath send bytes */
61 u64 DumbXmtPkts; /* Dumbnic send packets */
62 u64 SlowXmtPkts; /* Slowpath send packets */
63 u64 FastXmtPkts; /* Fastpath send packets */
64 u64 DumbXmtUcastPkts; /* directed packets */
65 u64 DumbXmtMcastPkts; /* Multicast packets */
66 u64 DumbXmtBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
67 u64 DumbXmtUcastBytes; /* OID_GEN_DIRECTED_BYTES_XMIT */
68 u64 DumbXmtMcastBytes; /* OID_GEN_MULTICAST_BYTES_XMIT */
69 u64 DumbXmtBcastBytes; /* OID_GEN_BROADCAST_BYTES_XMIT */
70 u64 XmtErrors; /* OID_GEN_XMIT_ERROR */
71 u64 XmtDiscards; /* OID_GEN_XMIT_DISCARDS */
72 u64 XmtOk; /* OID_GEN_XMIT_OK */
73 u64 XmtQLen; /* OID_GEN_TRANSMIT_QUEUE_LENGTH */
74 u64 XmtZeroFull; /* Transmit ring zero full */
76 u32 RcvNBL; /* Offload recieve NBL count */
77 u64 DumbRcvBytes; /* dumbnic recv bytes */
78 u64 DumbRcvUcastBytes; /* OID_GEN_DIRECTED_BYTES_RCV */
79 u64 DumbRcvMcastBytes; /* OID_GEN_MULTICAST_BYTES_RCV */
80 u64 DumbRcvBcastBytes; /* OID_GEN_BROADCAST_BYTES_RCV */
81 u64 SlowRcvBytes; /* Slowpath recv bytes */
82 u64 FastRcvBytes; /* Fastpath recv bytes */
83 u64 DumbRcvPkts; /* OID_GEN_DIRECTED_FRAMES_RCV */
84 u64 DumbRcvTcpPkts; /* See SxgCollectStats */
85 u64 DumbRcvUcastPkts; /* directed packets */
86 u64 DumbRcvMcastPkts; /* Multicast packets */
87 u64 DumbRcvBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
88 u64 SlowRcvPkts; /* OID_GEN_DIRECTED_FRAMES_RCV */
89 u64 RcvErrors; /* OID_GEN_RCV_ERROR */
90 u64 RcvDiscards; /* OID_GEN_RCV_DISCARDS */
91 u64 RcvNoBuffer; /* OID_GEN_RCV_NO_BUFFER */
92 u64 PdqFull; /* Processed Data Queue Full */
93 u64 EventRingFull; /* Event ring full */
95 u64 MaxSends; /* Max sends outstanding */
96 u64 NoSglBuf; /* SGL buffer allocation failure */
97 u64 SglFail; /* NDIS SGL failure */
98 u64 SglAsync; /* NDIS SGL failure */
99 u64 NoMem; /* Memory allocation failure */
100 u64 NumInts; /* Interrupts */
101 u64 FalseInts; /* Interrupt with ISR == 0 */
102 u64 XmtDrops; /* No sahara DRAM buffer for xmt */
103 /* Sahara receive status */
104 u64 TransportCsum; /* SXG_RCV_STATUS_TRANSPORT_CSUM */
105 u64 TransportUflow; /* SXG_RCV_STATUS_TRANSPORT_UFLOW */
106 u64 TransportHdrLen; /* SXG_RCV_STATUS_TRANSPORT_HDRLEN */
107 u64 NetworkCsum; /* SXG_RCV_STATUS_NETWORK_CSUM: */
108 u64 NetworkUflow; /* SXG_RCV_STATUS_NETWORK_UFLOW: */
109 u64 NetworkHdrLen; /* SXG_RCV_STATUS_NETWORK_HDRLEN: */
110 u64 Parity; /* SXG_RCV_STATUS_PARITY */
111 u64 LinkParity; /* SXG_RCV_STATUS_LINK_PARITY: */
112 u64 LinkEarly; /* SXG_RCV_STATUS_LINK_EARLY: */
113 u64 LinkBufOflow; /* SXG_RCV_STATUS_LINK_BUFOFLOW: */
114 u64 LinkCode; /* SXG_RCV_STATUS_LINK_CODE: */
115 u64 LinkDribble; /* SXG_RCV_STATUS_LINK_DRIBBLE: */
116 u64 LinkCrc; /* SXG_RCV_STATUS_LINK_CRC: */
117 u64 LinkOflow; /* SXG_RCV_STATUS_LINK_OFLOW: */
118 u64 LinkUflow; /* SXG_RCV_STATUS_LINK_UFLOW: */
122 /* DUMB-NIC Send path definitions */
124 #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) { \
126 dev_kfree_skb_irq(_skb); \
129 #define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \
131 dev_kfree_skb(_skb); \
135 * Locate current receive header buffer location. Use this
136 * instead of RcvDataHdr->VirtualAddress since the data
137 * may have been offset by SXG_ADVANCE_MDL_OFFSET
139 #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
141 /* Dumb-NIC receive processing */
142 /* Define an SXG_PACKET as an NDIS_PACKET */
143 #define PSXG_PACKET struct sk_buff *
144 /* Indications array size */
145 #define SXG_RCV_ARRAYSIZE 64
147 #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr, BufferSize) {\
148 struct sk_buff * skb; \
149 skb = netdev_alloc_skb(_pAdapt->netdev, BufferSize); \
151 (_RcvDataBufferHdr)->skb = skb; \
153 _RcvDataBufferHdr->PhysicalAddress = pci_map_single(adapter->pcidev,\
154 _RcvDataBufferHdr->skb->data, BufferSize, PCI_DMA_FROMDEVICE); \
156 (_RcvDataBufferHdr)->skb = NULL; \
160 #define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \
161 if((_RcvDataBufferHdr)->skb) { \
162 dev_kfree_skb((_RcvDataBufferHdr)->skb); \
167 * Macro to add a NDIS_PACKET to an indication array
168 * If we fill up our array of packet pointers, then indicate this
169 * block up now and start on a new one.
171 #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, \
173 (_IndicationList)[_NumPackets] = (_Packet); \
175 if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
176 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
177 (_NumPackets), 0, 0, 0); \
178 netif_rx((_IndicationList),(_NumPackets)); \
183 #define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \
185 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
186 (_NumPackets), 0, 0, 0); \
187 netif_rx((_IndicationList),(_NumPackets)); \
192 #define SXG_REINIATIALIZE_PACKET(_Packet) \
193 {} /*_NdisReinitializePacket(_Packet)*/
194 /* this is not necessary with an skb */
196 /* Definitions to initialize Dumb-nic Receive NBLs */
197 #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)\
198 ((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
200 #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
201 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), \
202 TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
204 #define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
205 NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
206 NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \
207 NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \
210 #define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \
211 NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \
212 _Packet8021qInfo.TagHeader.VlanId = (_VlanId); \
213 _Packet8021qInfo.TagHeader.UserPriority = (_Priority); \
214 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \
215 _Packet8021qInfo.Value; \
218 #define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \
219 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \
220 (_RcvDataBufferHdr), (_Packet), \
221 (_Event)->Status, 0); \
222 /* ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); */ \
223 skb_put(Packet, (_Event)->Length); \
227 * Macros to free a receive data buffer and receive data descriptor block
228 * NOTE - Lock must be held with RCV macros
230 #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
231 struct list_entry *_ple; \
233 if((_pAdapt)->FreeRcvBufferCount) { \
234 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
235 _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
236 (_Hdr) = container_of(_ple, struct sxg_rcv_data_buffer_hdr, \
238 (_pAdapt)->FreeRcvBufferCount--; \
239 ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
243 #define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
244 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \
245 (_Hdr), (_pAdapt)->FreeRcvBufferCount, \
246 (_Hdr)->State, 0/*(_Hdr)->VirtualAddress*/); \
247 /* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
248 (_pAdapt)->FreeRcvBufferCount++; \
249 ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) \
250 >= (_pAdapt)->FreeRcvBufferCount); \
251 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
252 (_Hdr)->State = SXG_BUFFER_FREE; \
253 InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
256 #define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \
257 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
258 (_Hdr)->State = SXG_BUFFER_FREE; \
259 (_pAdapt)->FreeRcvBlockCount++; \
260 ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \
261 InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
265 #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \
266 spin_lock(&(_pAdapt)->SglQLock); \
267 (_pAdapt)->FreeSglBufferCount++; \
268 ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount); \
269 ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
270 (_Sgl)->State = SXG_BUFFER_FREE; \
271 InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
272 spin_unlock(&(_pAdapt)->SglQLock); \
276 * Get an SGL buffer from the free queue. The first part of this macro
277 * attempts to keep ahead of buffer depletion by allocating more when
278 * we hit a minimum threshold. Note that we don't grab the lock
279 * until after that. We're dealing with round numbers here, so we don't need to,
280 * and not grabbing it avoids a possible double-trip.
282 #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \
283 struct list_entry *_ple; \
284 if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
285 (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
286 (_pAdapt->AllocationsPending == 0)) { \
287 sxg_allocate_buffer_memory(_pAdapt, \
288 (sizeof(struct sxg_scatter_gather) + SXG_SGL_BUF_SIZE),\
289 SXG_BUFFER_TYPE_SGL); \
292 spin_lock(&(_pAdapt)->SglQLock); \
293 if((_pAdapt)->FreeSglBufferCount) { \
294 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
295 _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
296 (_Sgl) = container_of(_ple, struct sxg_scatter_gather, \
298 (_pAdapt)->FreeSglBufferCount--; \
299 ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
300 (_Sgl)->State = SXG_BUFFER_BUSY; \
301 (_Sgl)->pSgl = NULL; \
303 spin_unlock(&(_pAdapt)->SglQLock); \
307 * struct sxg_multicast_address
308 * Linked list of multicast addresses.
310 struct sxg_multicast_address {
311 unsigned char Address[6];
312 struct sxg_multicast_address *Next;
316 * Structure to maintain chimney send and receive buffer queues.
317 * This structure maintains NET_BUFFER_LIST queues that are
318 * given to us via the Chimney MiniportTcpOffloadSend and
319 * MiniportTcpOffloadReceive routines. This structure DOES NOT
320 * manage our data buffer queue
322 struct sxg_buffer_queue {
323 u32 Type; /* Slow or fast - See below */
324 u32 Direction; /* Xmt or Rcv */
325 u32 Bytes; /* Byte count */
326 u32 * Head; /* Send queue head */
327 u32 * Tail; /* Send queue tail */
328 /* PNET_BUFFER_LIST NextNBL;*/ /* Short cut - next NBL */
329 /* PNET_BUFFER NextNB; */ /* Short cut - next NB */
332 #define SXG_SLOW_SEND_BUFFER 0
333 #define SXG_FAST_SEND_BUFFER 1
334 #define SXG_RECEIVE_BUFFER 2
336 #define SXG_INIT_BUFFER(_Buffer, _Type) { \
337 (_Buffer)->Type = (_Type); \
338 if((_Type) == SXG_RECEIVE_BUFFER) { \
339 (_Buffer)->Direction = 0; \
341 (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \
343 (_Buffer)->Bytes = 0; \
344 (_Buffer)->Head = NULL; \
345 (_Buffer)->Tail = NULL; \
349 #define SXG_RSS_CPU_COUNT(_pAdapt) \
350 ((_pAdapt)->RssEnabled ? NR_CPUS : 1)
352 /* DRIVER and ADAPTER structures */
355 * Adapter states - These states closely match the adapter states
356 * documented in the DDK (with a few exceptions).
359 SXG_STATE_INITIALIZING, /* Initializing */
360 SXG_STATE_BOOTDIAG, /* Boot-Diagnostic mode */
361 SXG_STATE_PAUSING, /* Pausing */
362 SXG_STATE_PAUSED, /* Paused */
363 SXG_STATE_RUNNING, /* Running */
364 SXG_STATE_RESETTING, /* Reset in progress */
365 SXG_STATE_SLEEP, /* Sleeping */
366 SXG_STATE_DIAG, /* Diagnostic mode */
367 SXG_STATE_HALTING, /* Halting */
368 SXG_STATE_HALTED, /* Down or not-initialized */
369 SXG_STATE_SHUTDOWN /* shutdown */
373 enum SXG_LINK_STATE {
378 /* Link initialization timeout in 100us units */
379 #define SXG_LINK_TIMEOUT 100000 /* 10 Seconds - REDUCE! */
382 /* Microcode file selection codes */
384 SXG_UCODE_SAHARA, /* Sahara ucode */
385 SXG_UCODE_SDIAGCPU, /* Sahara CPU diagnostic ucode */
386 SXG_UCODE_SDIAGSYS /* Sahara system diagnostic ucode */
390 #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
391 #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
393 /* This probably lives in a proto.h file. Move later */
394 #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
395 #define SXG_BROADCAST_PACKET(_pether) \
396 ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
397 (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
400 #define SXG_ID DPFLTR_IHVNETWORK_ID
401 #define SXG_ERROR DPFLTR_ERROR_LEVEL
404 * struct sxg_driver structure -
406 * contains information about the sxg driver. There is only
407 * one of these, and it is defined as a global.
411 struct adapter_t *Adapters; /* Linked list of adapters */
412 ushort AdapterID; /* Maintain unique adapter ID */
415 #ifdef STATUS_SUCCESS
416 #undef STATUS_SUCCESS
419 #define STATUS_SUCCESS 0
420 #define STATUS_PENDING 0
421 #define STATUS_FAILURE -1
422 #define STATUS_ERROR -2
423 #define STATUS_NOT_SUPPORTED -3
424 #define STATUS_BUFFER_TOO_SHORT -4
425 #define STATUS_RESOURCES -5
427 #define SLIC_MAX_CARDS 32
428 #define SLIC_MAX_PORTS 4 /* Max # of ports per card */
429 #if SLIC_DUMP_ENABLED
433 * This cannot be bigger than the max DMA size the card supports,
434 * given the current code structure in the host and ucode.
435 * Mojave supports 16K, Oasis supports 16K-1, so
436 * just set this at 15K, shouldnt make that much of a diff.
438 #define DUMP_BUF_SIZE 0x3C00
441 #define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
442 #define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
444 struct mcast_address {
445 unsigned char address[6];
446 struct mcast_address *next;
449 #define CARD_DOWN 0x00000000
450 #define CARD_UP 0x00000001
451 #define CARD_FAIL 0x00000002
452 #define CARD_DIAG 0x00000003
453 #define CARD_SLEEP 0x00000004
455 #define ADAPT_DOWN 0x00
456 #define ADAPT_UP 0x01
457 #define ADAPT_FAIL 0x02
458 #define ADAPT_RESET 0x03
459 #define ADAPT_SLEEP 0x04
461 #define ADAPT_FLAGS_BOOTTIME 0x0001
462 #define ADAPT_FLAGS_IS64BIT 0x0002
463 #define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
464 #define ADAPT_FLAGS_FIBERMEDIA 0x0008
465 #define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
466 #define ADAPT_FLAGS_INT_REGISTERED 0x0020
467 #define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
468 #define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
469 #define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
471 #define LINK_DOWN 0x00
472 #define LINK_CONFIG 0x01
475 #define LINK_10MB 0x00
476 #define LINK_100MB 0x01
477 #define LINK_AUTOSPEED 0x02
478 #define LINK_1000MB 0x03
479 #define LINK_10000MB 0x04
481 #define LINK_HALFD 0x00
482 #define LINK_FULLD 0x01
483 #define LINK_AUTOD 0x02
485 #define MAC_DIRECTED 0x00000001
486 #define MAC_BCAST 0x00000002
487 #define MAC_MCAST 0x00000004
488 #define MAC_PROMISC 0x00000008
489 #define MAC_LOOPBACK 0x00000010
490 #define MAC_ALLMCAST 0x00000020
492 #define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
493 #define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : \
494 ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
495 #define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
496 #define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
497 #define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
500 struct ether_header {
501 unsigned char ether_dhost[6];
502 unsigned char ether_shost[6];
507 #define NUM_CFG_SPACES 2
508 #define NUM_CFG_REGS 64
511 struct adapter_t *adapter[SLIC_MAX_PORTS];
512 struct physcard *next;
513 unsigned int adapters_allocd;
516 struct sxgbase_driver {
517 spinlock_t driver_lock;
518 unsigned long flags; /* irqsave for spinlock */
521 u32 num_sxg_ports_active;
523 struct physcard *phys_card;
530 struct physcard *physcard;
531 unsigned int physport;
532 unsigned int slotnumber;
533 unsigned int functionnumber;
539 void __iomem * base_addr;
543 unsigned int activated;
545 unsigned int isp_initialized;
547 unsigned char linkstate;
549 unsigned char macaddr[6];
550 unsigned char currmacaddr[6];
552 ushort devflags_prev;
554 struct mcast_address *mcastaddrs;
555 struct timer_list pingtimer;
557 struct timer_list statstimer;
559 struct timer_list vpci_timer;
561 struct timer_list loadtimer;
568 u32 error_interrupts;
569 u32 error_rmiss_interrupts;
574 u32 linkevent_interrupts;
577 u32 false_interrupts;
586 u32 rcv_interrupt_yields;
588 struct net_device_stats stats;
589 u32 * MiniportHandle; /* Our miniport handle */
590 enum SXG_STATE State; /* Adapter state */
591 enum SXG_LINK_STATE LinkState; /* Link state */
592 u64 LinkSpeed; /* Link Speed */
593 u32 PowerState; /* NDIS power state */
594 struct adapter_t *Next; /* Linked list */
595 ushort AdapterID; /* 1..n */
596 struct net_device * netdev;
597 struct net_device * next_netdevice;
598 struct pci_dev *pcidev;
600 struct sxg_multicast_address *MulticastAddrs; /* Multicast list */
601 u64 MulticastMask; /* Multicast mask */
602 u32 *InterruptHandle; /* Register Interrupt handle */
603 u32 InterruptLevel; /* From Resource list */
604 u32 InterruptVector; /* From Resource list */
605 spinlock_t AdapterLock; /* Serialize access adapter routines */
606 spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
607 struct sxg_hw_regs *HwRegs; /* Sahara HW Register Memory (BAR0/1) */
608 struct sxg_ucode_regs *UcodeRegs; /* Microcode Register Memory (BAR2/3) */
609 struct sxg_tcb_regs *TcbRegs; /* Same as Ucode regs - See sxghw.h */
610 ushort FrameSize; /* Maximum frame size */
611 u32 * DmaHandle; /* NDIS DMA handle */
612 u32 * PacketPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
613 u32 * BufferPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
614 u32 MacFilter; /* NDIS MAC Filter */
615 struct sxg_event_ring *EventRings; /* Host event rings. 1/CPU to 16 max */
616 dma_addr_t PEventRings; /* Physical address */
617 u32 NextEvent[SXG_MAX_RSS]; /* Current location in ring */
618 dma_addr_t PTcbBuffers; /* TCB Buffers - physical address */
619 dma_addr_t PTcbCompBuffers; /* TCB Composite Buffers - phys addr */
620 struct sxg_xmt_ring *XmtRings; /* Transmit rings */
621 dma_addr_t PXmtRings; /* Transmit rings - physical address */
622 struct sxg_ring_info XmtRingZeroInfo; /* Transmit ring 0 info */
624 spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
625 u32 * XmtRingZeroIndex; /* Shared XMT ring 0 index */
626 dma_addr_t PXmtRingZeroIndex; /* Shared XMT ring 0 index - physical */
627 struct list_entry FreeProtocolHeaders;/* Free protocol headers */
628 u32 FreeProtoHdrCount; /* Count */
629 void * ProtocolHeaders; /* Block of protocol header */
630 dma_addr_t PProtocolHeaders; /* Block of protocol headers - phys */
632 struct sxg_rcv_ring *RcvRings; /* Receive rings */
633 dma_addr_t PRcvRings; /* Receive rings - physical address */
634 struct sxg_ring_info RcvRingZeroInfo; /* Receive ring 0 info */
636 u32 * Isr; /* Interrupt status register */
637 dma_addr_t PIsr; /* ISR - physical address */
638 u32 IsrCopy[SXG_MAX_RSS]; /* Copy of ISR */
639 ushort InterruptsEnabled; /* Bitmask of enabled vectors */
640 unsigned char *IndirectionTable; /* RSS indirection table */
641 dma_addr_t PIndirectionTable; /* Physical address */
642 ushort RssTableSize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
643 ushort HashKeySize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
644 unsigned char HashSecretKey[40]; /* rss key */
646 /* Receive buffer queues */
647 spinlock_t RcvQLock; /* Receive Queue Lock */
648 struct list_entry FreeRcvBuffers; /* Free SXG_DATA_BUFFER queue */
649 struct list_entry FreeRcvBlocks; /* Free SXG_RCV_DESCRIPTOR_BLOCK Q */
650 struct list_entry AllRcvBlocks; /* All SXG_RCV_BLOCKs */
651 ushort FreeRcvBufferCount; /* Number of free rcv data buffers */
652 ushort FreeRcvBlockCount; /* # of free rcv descriptor blocks */
653 ushort AllRcvBlockCount; /* Number of total receive blocks */
654 ushort ReceiveBufferSize; /* SXG_RCV_DATA/JUMBO_BUFFER_SIZE only */
655 u32 AllocationsPending; /* Receive allocation pending */
656 u32 RcvBuffersOnCard; /* SXG_DATA_BUFFERS owned by card */
658 spinlock_t SglQLock; /* SGL Queue Lock */
659 struct list_entry FreeSglBuffers; /* Free struct sxg_scatter_gather */
660 struct list_entry AllSglBuffers; /* All struct sxg_scatter_gather */
661 ushort FreeSglBufferCount; /* Number of free SGL buffers */
662 ushort AllSglBufferCount; /* Number of total SGL buffers */
663 u32 CurrentTime; /* Tick count */
664 u32 FastpathConnections;/* # of fastpath connections */
665 /* Various single-bit flags: */
666 u32 BasicAllocations:1; /* Locks and listheads */
667 u32 IntRegistered:1; /* Interrupt registered */
668 u32 PingOutstanding:1; /* Ping outstanding to card */
669 u32 Dead:1; /* Card dead */
670 u32 DumpDriver:1; /* OID_SLIC_DRIVER_DUMP request */
671 u32 DumpCard:1; /* OID_SLIC_CARD_DUMP request */
672 u32 DumpCmdRunning:1; /* Dump command in progress */
673 u32 DebugRunning:1; /* AGDB debug in progress */
674 u32 JumboEnabled:1; /* Jumbo frames enabled */
675 u32 MsiEnabled:1; /* MSI interrupt enabled */
676 u32 RssEnabled:1; /* RSS Enabled */
677 u32 FailOnBadEeprom:1; /* Fail on Bad Eeprom */
678 u32 DiagStart:1; /* Init adapter for diagnostic start */
680 u32 PendingRcvCount; /* Outstanding rcv indications */
681 u32 PendingXmtCount; /* Outstanding send requests */
682 struct sxg_stats Stats; /* Statistics */
683 u32 ReassBufs; /* Number of reassembly buffers */
684 /* Card Crash Info */
685 ushort CrashLocation; /* Microcode crash location */
686 unsigned char CrashCpu; /* Sahara CPU ID */
688 /* PDIAG_CMD DiagCmds; */ /* List of free diagnostic commands */
689 /* PDIAG_BUFFER DiagBuffers; */ /* List of free diagnostic buffers */
690 /* PDIAG_REQ DiagReqQ; */ /* List of outstanding (asynchronous) diag requests */
691 /* u32 DiagCmdTimeout; */ /* Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? */
692 /* unsigned char DiagDmaDesc[DMA_CPU_CTXS]; */ /* Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) */
694 * Put preprocessor-conditional fields at the end so we don't
695 * have to recompile sxgdbg everytime we reconfigure the driver
697 #if defined(CONFIG_X86)
698 u32 AddrUpper; /* Upper 32 bits of 64-bit register */
700 /*#if SXG_FAILURE_DUMP */
701 /* NDIS_EVENT DumpThreadEvent; */ /* syncronize dump thread */
702 /* BOOLEAN DumpThreadRunning; */ /* termination flag */
703 /* PSXG_DUMP_CMD DumpBuffer; */ /* 68k - Cmd and Buffer */
704 /* dma_addr_t PDumpBuffer; */ /* Physical address */
705 /*#endif */ /* SXG_FAILURE_DUMP */
708 #if SLIC_DUMP_ENABLED
709 #define SLIC_DUMP_REQUESTED 1
710 #define SLIC_DUMP_IN_PROGRESS 2
711 #define SLIC_DUMP_DONE 3
714 * Microcode crash information structure. This
715 * structure is written out to the card's SRAM when the microcode panic's.
717 struct slic_crash_info {
722 #define CRASH_INFO_OFFSET 0x155C
726 #define UPDATE_STATS(largestat, newstat, oldstat) \
728 if ((newstat) < (oldstat)) \
729 (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
731 (largestat) += ((newstat) - (oldstat)); \
734 #define UPDATE_STATS_GB(largestat, newstat, oldstat) \
736 (largestat) += ((newstat) - (oldstat)); \
739 #define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
742 if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
744 if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
748 #define ETHERMAXFRAME 1514
749 #define JUMBOMAXFRAME 9014
751 #if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
752 #define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
753 #define SXG_GET_ADDR_HIGH(_addr) \
754 (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
756 #define SXG_GET_ADDR_LOW(_addr) (u32)_addr
757 #define SXG_GET_ADDR_HIGH(_addr) (u32)0
761 #define DONT_FLUSH FALSE
763 #define SIOCSLICDUMPCARD (SIOCDEVPRIVATE+9)
764 #define SIOCSLICSETINTAGG (SIOCDEVPRIVATE+10)
765 #define SIOCSLICTRACEDUMP (SIOCDEVPRIVATE+11)
767 extern struct ethtool_ops sxg_nic_ethtool_ops;
768 #endif /* __SXG_DRIVER_H__ */