1 /**************************************************************************
3 * Copyright (C) 2000-2008 Alacritech, Inc. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above
12 * copyright notice, this list of conditions and the following
13 * disclaimer in the documentation and/or other materials provided
14 * with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * The views and conclusions contained in the software and documentation
30 * are those of the authors and should not be interpreted as representing
31 * official policies, either expressed or implied, of Alacritech, Inc.
33 **************************************************************************/
38 * The SXG driver for Alacritech's 10Gbe products.
40 * NOTE: This is the standard, non-accelerated version of Alacritech's
44 #include <linux/kernel.h>
45 #include <linux/string.h>
46 #include <linux/errno.h>
47 #include <linux/module.h>
48 #include <linux/moduleparam.h>
49 #include <linux/ioport.h>
50 #include <linux/slab.h>
51 #include <linux/interrupt.h>
52 #include <linux/timer.h>
53 #include <linux/pci.h>
54 #include <linux/spinlock.h>
55 #include <linux/init.h>
56 #include <linux/netdevice.h>
57 #include <linux/etherdevice.h>
58 #include <linux/ethtool.h>
59 #include <linux/skbuff.h>
60 #include <linux/delay.h>
61 #include <linux/types.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/mii.h>
65 #define SLIC_DUMP_ENABLED 0
66 #define SLIC_GET_STATS_ENABLED 0
67 #define LINUX_FREES_ADAPTER_RESOURCES 1
68 #define SXG_OFFLOAD_IP_CHECKSUM 0
69 #define SXG_POWER_MANAGEMENT_ENABLED 0
80 #include "sxgphycode.h"
81 #include "saharadbgdownload.h"
83 static int sxg_allocate_buffer_memory(struct adapter_t *adapter, u32 Size,
84 enum sxg_buffer_type BufferType);
85 static void sxg_allocate_rcvblock_complete(struct adapter_t *adapter, void *RcvBlock,
86 dma_addr_t PhysicalAddress,
88 static void sxg_allocate_sgl_buffer_complete(struct adapter_t *adapter,
89 struct sxg_scatter_gather *SxgSgl,
90 dma_addr_t PhysicalAddress,
93 static void sxg_mcast_init_crc32(void);
95 static int sxg_entry_open(struct net_device *dev);
96 static int sxg_entry_halt(struct net_device *dev);
97 static int sxg_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
98 static int sxg_send_packets(struct sk_buff *skb, struct net_device *dev);
99 static int sxg_transmit_packet(struct adapter_t *adapter, struct sk_buff *skb);
100 static void sxg_dumb_sgl(struct sxg_x64_sgl *pSgl, struct sxg_scatter_gather *SxgSgl);
102 static void sxg_handle_interrupt(struct adapter_t *adapter);
103 static int sxg_process_isr(struct adapter_t *adapter, u32 MessageId);
104 static u32 sxg_process_event_queue(struct adapter_t *adapter, u32 RssId);
105 static void sxg_complete_slow_send(struct adapter_t *adapter);
106 static struct sk_buff *sxg_slow_receive(struct adapter_t *adapter, struct sxg_event *Event);
107 static void sxg_process_rcv_error(struct adapter_t *adapter, u32 ErrorStatus);
108 static bool sxg_mac_filter(struct adapter_t *adapter,
109 struct ether_header *EtherHdr, ushort length);
111 #if SLIC_GET_STATS_ENABLED
112 static struct net_device_stats *sxg_get_stats(struct net_device *dev);
117 static int sxg_mac_set_address(struct net_device *dev, void *ptr);
118 static void sxg_mcast_set_list(struct net_device *dev);
120 static void sxg_adapter_set_hwaddr(struct adapter_t *adapter);
122 static void sxg_unmap_mmio_space(struct adapter_t *adapter);
124 static int sxg_initialize_adapter(struct adapter_t *adapter);
125 static void sxg_stock_rcv_buffers(struct adapter_t *adapter);
126 static void sxg_complete_descriptor_blocks(struct adapter_t *adapter,
127 unsigned char Index);
128 static int sxg_initialize_link(struct adapter_t *adapter);
129 static int sxg_phy_init(struct adapter_t *adapter);
130 static void sxg_link_event(struct adapter_t *adapter);
131 static enum SXG_LINK_STATE sxg_get_link_state(struct adapter_t *adapter);
132 static void sxg_link_state(struct adapter_t *adapter, enum SXG_LINK_STATE LinkState);
133 static int sxg_write_mdio_reg(struct adapter_t *adapter,
134 u32 DevAddr, u32 RegAddr, u32 Value);
135 static int sxg_read_mdio_reg(struct adapter_t *adapter,
136 u32 DevAddr, u32 RegAddr, u32 *pValue);
138 static unsigned int sxg_first_init = 1;
139 static char *sxg_banner =
140 "Alacritech SLIC Technology(tm) Server and Storage 10Gbe Accelerator (Non-Accelerated)\n";
142 static int sxg_debug = 1;
143 static int debug = -1;
144 static struct net_device *head_netdevice = NULL;
146 static struct sxgbase_driver sxg_global = {
149 static int intagg_delay = 100;
150 static u32 dynamic_intagg = 0;
152 #define DRV_NAME "sxg"
153 #define DRV_VERSION "1.0.1"
154 #define DRV_AUTHOR "Alacritech, Inc. Engineering"
155 #define DRV_DESCRIPTION "Alacritech SLIC Techonology(tm) Non-Accelerated 10Gbe Driver"
156 #define DRV_COPYRIGHT "Copyright 2000-2008 Alacritech, Inc. All rights reserved."
158 MODULE_AUTHOR(DRV_AUTHOR);
159 MODULE_DESCRIPTION(DRV_DESCRIPTION);
160 MODULE_LICENSE("GPL");
162 module_param(dynamic_intagg, int, 0);
163 MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting");
164 module_param(intagg_delay, int, 0);
165 MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay");
167 static struct pci_device_id sxg_pci_tbl[] __devinitdata = {
168 {PCI_DEVICE(SXG_VENDOR_ID, SXG_DEVICE_ID)},
172 MODULE_DEVICE_TABLE(pci, sxg_pci_tbl);
174 /***********************************************************************
175 ************************************************************************
176 ************************************************************************
177 ************************************************************************
178 ************************************************************************/
180 static inline void sxg_reg32_write(void __iomem *reg, u32 value, bool flush)
187 static inline void sxg_reg64_write(struct adapter_t *adapter, void __iomem *reg,
190 u32 value_high = (u32) (value >> 32);
191 u32 value_low = (u32) (value & 0x00000000FFFFFFFF);
194 spin_lock_irqsave(&adapter->Bit64RegLock, flags);
195 writel(value_high, (void __iomem *)(&adapter->UcodeRegs[cpu].Upper));
196 writel(value_low, reg);
197 spin_unlock_irqrestore(&adapter->Bit64RegLock, flags);
200 static void sxg_init_driver(void)
202 if (sxg_first_init) {
203 DBG_ERROR("sxg: %s sxg_first_init set jiffies[%lx]\n",
206 spin_lock_init(&sxg_global.driver_lock);
210 static void sxg_dbg_macaddrs(struct adapter_t *adapter)
212 DBG_ERROR(" (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
213 adapter->netdev->name, adapter->currmacaddr[0],
214 adapter->currmacaddr[1], adapter->currmacaddr[2],
215 adapter->currmacaddr[3], adapter->currmacaddr[4],
216 adapter->currmacaddr[5]);
217 DBG_ERROR(" (%s) mac %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
218 adapter->netdev->name, adapter->macaddr[0],
219 adapter->macaddr[1], adapter->macaddr[2],
220 adapter->macaddr[3], adapter->macaddr[4],
221 adapter->macaddr[5]);
226 static struct sxg_driver SxgDriver;
229 static struct sxg_trace_buffer LSxgTraceBuffer;
231 static struct sxg_trace_buffer *SxgTraceBuffer = NULL;
234 * sxg_download_microcode
236 * Download Microcode to Sahara adapter
239 * adapter - A pointer to our adapter structure
240 * UcodeSel - microcode file selection
245 static bool sxg_download_microcode(struct adapter_t *adapter, enum SXG_UCODE_SEL UcodeSel)
247 struct sxg_hw_regs *HwRegs = adapter->HwRegs;
250 u32 *Instruction = NULL;
251 u32 BaseAddress, AddressOffset, Address;
257 u32 sectionStart[16];
259 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DnldUcod",
261 DBG_ERROR("sxg: %s ENTER\n", __func__);
264 case SXG_UCODE_SAHARA: /* Sahara operational ucode */
265 numSections = SNumSections;
266 for (i = 0; i < numSections; i++) {
267 sectionSize[i] = SSectionSize[i];
268 sectionStart[i] = SSectionStart[i];
272 printk(KERN_ERR KBUILD_MODNAME
273 ": Woah, big error with the microcode!\n");
277 DBG_ERROR("sxg: RESET THE CARD\n");
278 /* First, reset the card */
279 WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH);
281 /* Download each section of the microcode as specified in */
282 /* its download file. The *download.c file is generated using */
283 /* the saharaobjtoc facility which converts the metastep .obj */
284 /* file to a .c file which contains a two dimentional array. */
285 for (Section = 0; Section < numSections; Section++) {
286 DBG_ERROR("sxg: SECTION # %d\n", Section);
288 case SXG_UCODE_SAHARA:
289 Instruction = (u32 *) & SaharaUCode[Section][0];
295 BaseAddress = sectionStart[Section];
296 ThisSectionSize = sectionSize[Section] / 12; /* Size in instructions */
297 for (AddressOffset = 0; AddressOffset < ThisSectionSize;
299 Address = BaseAddress + AddressOffset;
300 ASSERT((Address & ~MICROCODE_ADDRESS_MASK) == 0);
301 /* Write instruction bits 31 - 0 */
302 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH);
303 /* Write instruction bits 63-32 */
304 WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1),
306 /* Write instruction bits 95-64 */
307 WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2),
309 /* Write instruction address with the WRITE bit set */
310 WRITE_REG(HwRegs->UcodeAddr,
311 (Address | MICROCODE_ADDRESS_WRITE), FLUSH);
312 /* Sahara bug in the ucode download logic - the write to DataLow */
313 /* for the next instruction could get corrupted. To avoid this, */
314 /* write to DataLow again for this instruction (which may get */
315 /* corrupted, but it doesn't matter), then increment the address */
316 /* and write the data for the next instruction to DataLow. That */
317 /* write should succeed. */
318 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE);
319 /* Advance 3 u32S to start of next instruction */
323 /* Now repeat the entire operation reading the instruction back and */
324 /* checking for parity errors */
325 for (Section = 0; Section < numSections; Section++) {
326 DBG_ERROR("sxg: check SECTION # %d\n", Section);
328 case SXG_UCODE_SAHARA:
329 Instruction = (u32 *) & SaharaUCode[Section][0];
335 BaseAddress = sectionStart[Section];
336 ThisSectionSize = sectionSize[Section] / 12; /* Size in instructions */
337 for (AddressOffset = 0; AddressOffset < ThisSectionSize;
339 Address = BaseAddress + AddressOffset;
340 /* Write the address with the READ bit set */
341 WRITE_REG(HwRegs->UcodeAddr,
342 (Address | MICROCODE_ADDRESS_READ), FLUSH);
343 /* Read it back and check parity bit. */
344 READ_REG(HwRegs->UcodeAddr, ValueRead);
345 if (ValueRead & MICROCODE_ADDRESS_PARITY) {
346 DBG_ERROR("sxg: %s PARITY ERROR\n",
349 return (FALSE); /* Parity error */
351 ASSERT((ValueRead & MICROCODE_ADDRESS_MASK) == Address);
352 /* Read the instruction back and compare */
353 READ_REG(HwRegs->UcodeDataLow, ValueRead);
354 if (ValueRead != *Instruction) {
355 DBG_ERROR("sxg: %s MISCOMPARE LOW\n",
357 return (FALSE); /* Miscompare */
359 READ_REG(HwRegs->UcodeDataMiddle, ValueRead);
360 if (ValueRead != *(Instruction + 1)) {
361 DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n",
363 return (FALSE); /* Miscompare */
365 READ_REG(HwRegs->UcodeDataHigh, ValueRead);
366 if (ValueRead != *(Instruction + 2)) {
367 DBG_ERROR("sxg: %s MISCOMPARE HIGH\n",
369 return (FALSE); /* Miscompare */
371 /* Advance 3 u32S to start of next instruction */
376 /* Everything OK, Go. */
377 WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH);
379 /* Poll the CardUp register to wait for microcode to initialize */
380 /* Give up after 10,000 attemps (500ms). */
381 for (i = 0; i < 10000; i++) {
383 READ_REG(adapter->UcodeRegs[0].CardUp, ValueRead);
384 if (ValueRead == 0xCAFE) {
385 DBG_ERROR("sxg: %s BOO YA 0xCAFE\n", __func__);
390 DBG_ERROR("sxg: %s TIMEOUT\n", __func__);
392 return (FALSE); /* Timeout */
394 /* Now write the LoadSync register. This is used to */
395 /* synchronize with the card so it can scribble on the memory */
396 /* that contained 0xCAFE from the "CardUp" step above */
397 if (UcodeSel == SXG_UCODE_SAHARA) {
398 WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH);
401 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDnldUcd",
403 DBG_ERROR("sxg: %s EXIT\n", __func__);
409 * sxg_allocate_resources - Allocate memory and locks
412 * adapter - A pointer to our adapter structure
417 static int sxg_allocate_resources(struct adapter_t *adapter)
421 u32 RssIds, IsrCount;
422 /* struct sxg_xmt_ring *XmtRing; */
423 /* struct sxg_rcv_ring *RcvRing; */
425 DBG_ERROR("%s ENTER\n", __func__);
427 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocRes",
430 /* Windows tells us how many CPUs it plans to use for */
432 RssIds = SXG_RSS_CPU_COUNT(adapter);
433 IsrCount = adapter->MsiEnabled ? RssIds : 1;
435 DBG_ERROR("%s Setup the spinlocks\n", __func__);
437 /* Allocate spinlocks and initialize listheads first. */
438 spin_lock_init(&adapter->RcvQLock);
439 spin_lock_init(&adapter->SglQLock);
440 spin_lock_init(&adapter->XmtZeroLock);
441 spin_lock_init(&adapter->Bit64RegLock);
442 spin_lock_init(&adapter->AdapterLock);
444 DBG_ERROR("%s Setup the lists\n", __func__);
446 InitializeListHead(&adapter->FreeRcvBuffers);
447 InitializeListHead(&adapter->FreeRcvBlocks);
448 InitializeListHead(&adapter->AllRcvBlocks);
449 InitializeListHead(&adapter->FreeSglBuffers);
450 InitializeListHead(&adapter->AllSglBuffers);
452 /* Mark these basic allocations done. This flags essentially */
453 /* tells the SxgFreeResources routine that it can grab spinlocks */
454 /* and reference listheads. */
455 adapter->BasicAllocations = TRUE;
456 /* Main allocation loop. Start with the maximum supported by */
457 /* the microcode and back off if memory allocation */
458 /* fails. If we hit a minimum, fail. */
461 DBG_ERROR("%s Allocate XmtRings size[%x]\n", __func__,
462 (unsigned int)(sizeof(struct sxg_xmt_ring) * 1));
464 /* Start with big items first - receive and transmit rings. At the moment */
465 /* I'm going to keep the ring size fixed and adjust the number of */
466 /* TCBs if we fail. Later we might consider reducing the ring size as well.. */
467 adapter->XmtRings = pci_alloc_consistent(adapter->pcidev,
468 sizeof(struct sxg_xmt_ring) *
470 &adapter->PXmtRings);
471 DBG_ERROR("%s XmtRings[%p]\n", __func__, adapter->XmtRings);
473 if (!adapter->XmtRings) {
474 goto per_tcb_allocation_failed;
476 memset(adapter->XmtRings, 0, sizeof(struct sxg_xmt_ring) * 1);
478 DBG_ERROR("%s Allocate RcvRings size[%x]\n", __func__,
479 (unsigned int)(sizeof(struct sxg_rcv_ring) * 1));
481 pci_alloc_consistent(adapter->pcidev,
482 sizeof(struct sxg_rcv_ring) * 1,
483 &adapter->PRcvRings);
484 DBG_ERROR("%s RcvRings[%p]\n", __func__, adapter->RcvRings);
485 if (!adapter->RcvRings) {
486 goto per_tcb_allocation_failed;
488 memset(adapter->RcvRings, 0, sizeof(struct sxg_rcv_ring) * 1);
491 per_tcb_allocation_failed:
492 /* an allocation failed. Free any successful allocations. */
493 if (adapter->XmtRings) {
494 pci_free_consistent(adapter->pcidev,
495 sizeof(struct sxg_xmt_ring) * 1,
498 adapter->XmtRings = NULL;
500 if (adapter->RcvRings) {
501 pci_free_consistent(adapter->pcidev,
502 sizeof(struct sxg_rcv_ring) * 1,
505 adapter->RcvRings = NULL;
507 /* Loop around and try again.... */
510 DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __func__);
511 /* Initialize rcv zero and xmt zero rings */
512 SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE);
513 SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE);
515 /* Sanity check receive data structure format */
516 ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
517 (adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
518 ASSERT(sizeof(struct sxg_rcv_descriptor_block) ==
519 SXG_RCV_DESCRIPTOR_BLOCK_SIZE);
521 /* Allocate receive data buffers. We allocate a block of buffers and */
522 /* a corresponding descriptor block at once. See sxghw.h:SXG_RCV_BLOCK */
523 for (i = 0; i < SXG_INITIAL_RCV_DATA_BUFFERS;
524 i += SXG_RCV_DESCRIPTORS_PER_BLOCK) {
525 sxg_allocate_buffer_memory(adapter,
526 SXG_RCV_BLOCK_SIZE(adapter->
528 SXG_BUFFER_TYPE_RCV);
530 /* NBL resource allocation can fail in the 'AllocateComplete' routine, which */
531 /* doesn't return status. Make sure we got the number of buffers we requested */
532 if (adapter->FreeRcvBufferCount < SXG_INITIAL_RCV_DATA_BUFFERS) {
533 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6",
534 adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES,
536 return (STATUS_RESOURCES);
539 DBG_ERROR("%s Allocate EventRings size[%x]\n", __func__,
540 (unsigned int)(sizeof(struct sxg_event_ring) * RssIds));
542 /* Allocate event queues. */
543 adapter->EventRings = pci_alloc_consistent(adapter->pcidev,
544 sizeof(struct sxg_event_ring) *
546 &adapter->PEventRings);
548 if (!adapter->EventRings) {
549 /* Caller will call SxgFreeAdapter to clean up above allocations */
550 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF8",
551 adapter, SXG_MAX_ENTRIES, 0, 0);
552 status = STATUS_RESOURCES;
553 goto per_tcb_allocation_failed;
555 memset(adapter->EventRings, 0, sizeof(struct sxg_event_ring) * RssIds);
557 DBG_ERROR("%s Allocate ISR size[%x]\n", __func__, IsrCount);
559 adapter->Isr = pci_alloc_consistent(adapter->pcidev,
560 IsrCount, &adapter->PIsr);
562 /* Caller will call SxgFreeAdapter to clean up above allocations */
563 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF9",
564 adapter, SXG_MAX_ENTRIES, 0, 0);
565 status = STATUS_RESOURCES;
566 goto per_tcb_allocation_failed;
568 memset(adapter->Isr, 0, sizeof(u32) * IsrCount);
570 DBG_ERROR("%s Allocate shared XMT ring zero index location size[%x]\n",
571 __func__, (unsigned int)sizeof(u32));
573 /* Allocate shared XMT ring zero index location */
574 adapter->XmtRingZeroIndex = pci_alloc_consistent(adapter->pcidev,
578 if (!adapter->XmtRingZeroIndex) {
579 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF10",
580 adapter, SXG_MAX_ENTRIES, 0, 0);
581 status = STATUS_RESOURCES;
582 goto per_tcb_allocation_failed;
584 memset(adapter->XmtRingZeroIndex, 0, sizeof(u32));
586 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlcResS",
587 adapter, SXG_MAX_ENTRIES, 0, 0);
589 DBG_ERROR("%s EXIT\n", __func__);
590 return (STATUS_SUCCESS);
596 * Set up PCI Configuration space
599 * pcidev - A pointer to our adapter structure
602 static void sxg_config_pci(struct pci_dev *pcidev)
607 pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
608 DBG_ERROR("sxg: %s PCI command[%4.4x]\n", __func__, pci_command);
609 /* Set the command register */
610 new_command = pci_command | (PCI_COMMAND_MEMORY | /* Memory Space Enable */
611 PCI_COMMAND_MASTER | /* Bus master enable */
612 PCI_COMMAND_INVALIDATE | /* Memory write and invalidate */
613 PCI_COMMAND_PARITY | /* Parity error response */
614 PCI_COMMAND_SERR | /* System ERR */
615 PCI_COMMAND_FAST_BACK); /* Fast back-to-back */
616 if (pci_command != new_command) {
617 DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n",
618 __func__, pci_command, new_command);
619 pci_write_config_word(pcidev, PCI_COMMAND, new_command);
623 static unsigned char temp_mac_address[6] = { 0x00, 0xab, 0xcd, 0xef, 0x12, 0x69 };
626 * @adapter : Pointer to the adapter structure for the card
627 * This function will read the configuration data from EEPROM/FLASH
629 static inline int sxg_read_config(struct adapter_t *adapter)
631 //struct sxg_config data;
632 struct sw_cfg_data *data;
634 unsigned long status;
637 data = pci_alloc_consistent(adapter->pcidev, sizeof(struct sw_cfg_data), &p_addr);
639 /* We cant get even this much memory. Raise a hell
642 printk(KERN_ERR"%s : Could not allocate memory for reading EEPROM\n", __FUNCTION__);
646 WRITE_REG(adapter->UcodeRegs[0].ConfigStat, SXG_CFG_TIMEOUT, TRUE);
648 WRITE_REG64(adapter, adapter->UcodeRegs[0].Config, p_addr, 0);
649 for(i=0; i<1000; i++) {
650 READ_REG(adapter->UcodeRegs[0].ConfigStat, status);
651 if (status != SXG_CFG_TIMEOUT)
653 mdelay(1); /* Do we really need this */
657 case SXG_CFG_LOAD_EEPROM: /*Config read from EEPROM succeeded */
658 case SXG_CFG_LOAD_FLASH: /* onfig read from Flash succeeded */
659 /* Copy the MAC address to adapter structure */
660 memcpy(temp_mac_address, data->MacAddr[0].MacAddr, 6);
661 /* TODO: We are not doing the remaining part : FRU, etc */
664 case SXG_CFG_TIMEOUT:
665 case SXG_CFG_LOAD_INVALID:
666 case SXG_CFG_LOAD_ERROR:
667 default: /* Fix default handler later */
668 printk(KERN_WARNING"%s : We could not read the config word."
669 "Status = %ld\n", __FUNCTION__, status);
672 pci_free_consistent(adapter->pcidev, sizeof(struct sw_cfg_data), data, p_addr);
673 if (adapter->netdev) {
674 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6);
675 memcpy(adapter->netdev->perm_addr, adapter->currmacaddr, 6);
677 printk("LINSYS : These are the new MAC address\n");
678 sxg_dbg_macaddrs(adapter);
683 static int sxg_entry_probe(struct pci_dev *pcidev,
684 const struct pci_device_id *pci_tbl_entry)
686 static int did_version = 0;
688 struct net_device *netdev;
689 struct adapter_t *adapter;
690 void __iomem *memmapped_ioaddr;
692 ulong mmio_start = 0;
695 DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n",
696 __func__, jiffies, smp_processor_id());
698 /* Initialize trace buffer */
700 SxgTraceBuffer = &LSxgTraceBuffer;
701 SXG_TRACE_INIT(SxgTraceBuffer, TRACE_NOISY);
704 sxg_global.dynamic_intagg = dynamic_intagg;
706 err = pci_enable_device(pcidev);
708 DBG_ERROR("Call pci_enable_device(%p) status[%x]\n", pcidev, err);
713 if (sxg_debug > 0 && did_version++ == 0) {
714 printk(KERN_INFO "%s\n", sxg_banner);
715 printk(KERN_INFO "%s\n", DRV_VERSION);
718 if (!(err = pci_set_dma_mask(pcidev, DMA_64BIT_MASK))) {
719 DBG_ERROR("pci_set_dma_mask(DMA_64BIT_MASK) successful\n");
721 if ((err = pci_set_dma_mask(pcidev, DMA_32BIT_MASK))) {
723 ("No usable DMA configuration, aborting err[%x]\n",
727 DBG_ERROR("pci_set_dma_mask(DMA_32BIT_MASK) successful\n");
730 DBG_ERROR("Call pci_request_regions\n");
732 err = pci_request_regions(pcidev, DRV_NAME);
734 DBG_ERROR("pci_request_regions FAILED err[%x]\n", err);
738 DBG_ERROR("call pci_set_master\n");
739 pci_set_master(pcidev);
741 DBG_ERROR("call alloc_etherdev\n");
742 netdev = alloc_etherdev(sizeof(struct adapter_t));
745 goto err_out_exit_sxg_probe;
747 DBG_ERROR("alloc_etherdev for slic netdev[%p]\n", netdev);
749 SET_NETDEV_DEV(netdev, &pcidev->dev);
751 pci_set_drvdata(pcidev, netdev);
752 adapter = netdev_priv(netdev);
753 adapter->netdev = netdev;
754 adapter->pcidev = pcidev;
756 mmio_start = pci_resource_start(pcidev, 0);
757 mmio_len = pci_resource_len(pcidev, 0);
759 DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
760 mmio_start, mmio_len);
762 memmapped_ioaddr = ioremap(mmio_start, mmio_len);
763 DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__,
765 if (!memmapped_ioaddr) {
766 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
767 __func__, mmio_len, mmio_start);
768 goto err_out_free_mmio_region;
772 ("sxg: %s found Alacritech SXG PCI, MMIO at %p, start[%lx] len[%lx], IRQ %d.\n",
773 __func__, memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq);
775 adapter->HwRegs = (void *)memmapped_ioaddr;
776 adapter->base_addr = memmapped_ioaddr;
778 mmio_start = pci_resource_start(pcidev, 2);
779 mmio_len = pci_resource_len(pcidev, 2);
781 DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
782 mmio_start, mmio_len);
784 memmapped_ioaddr = ioremap(mmio_start, mmio_len);
785 DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__,
787 if (!memmapped_ioaddr) {
788 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
789 __func__, mmio_len, mmio_start);
790 goto err_out_free_mmio_region;
793 DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, "
794 "start[%lx] len[%lx], IRQ %d.\n", __func__,
795 memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq);
797 adapter->UcodeRegs = (void *)memmapped_ioaddr;
799 adapter->State = SXG_STATE_INITIALIZING;
800 /* Maintain a list of all adapters anchored by */
801 /* the global SxgDriver structure. */
802 adapter->Next = SxgDriver.Adapters;
803 SxgDriver.Adapters = adapter;
804 adapter->AdapterID = ++SxgDriver.AdapterID;
806 /* Initialize CRC table used to determine multicast hash */
807 sxg_mcast_init_crc32();
809 adapter->JumboEnabled = FALSE;
810 adapter->RssEnabled = FALSE;
811 if (adapter->JumboEnabled) {
812 adapter->FrameSize = JUMBOMAXFRAME;
813 adapter->ReceiveBufferSize = SXG_RCV_JUMBO_BUFFER_SIZE;
815 adapter->FrameSize = ETHERMAXFRAME;
816 adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE;
819 /* status = SXG_READ_EEPROM(adapter); */
821 /* goto sxg_init_bad; */
824 DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __func__);
825 sxg_config_pci(pcidev);
826 DBG_ERROR("sxg: %s EXIT sxg_config_pci\n", __func__);
828 DBG_ERROR("sxg: %s ENTER sxg_init_driver\n", __func__);
830 DBG_ERROR("sxg: %s EXIT sxg_init_driver\n", __func__);
832 adapter->vendid = pci_tbl_entry->vendor;
833 adapter->devid = pci_tbl_entry->device;
834 adapter->subsysid = pci_tbl_entry->subdevice;
835 adapter->slotnumber = ((pcidev->devfn >> 3) & 0x1F);
836 adapter->functionnumber = (pcidev->devfn & 0x7);
837 adapter->memorylength = pci_resource_len(pcidev, 0);
838 adapter->irq = pcidev->irq;
839 adapter->next_netdevice = head_netdevice;
840 head_netdevice = netdev;
841 adapter->port = 0; /*adapter->functionnumber; */
843 /* Allocate memory and other resources */
844 DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __func__);
845 status = sxg_allocate_resources(adapter);
846 DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n",
848 if (status != STATUS_SUCCESS) {
852 DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __func__);
853 if (sxg_download_microcode(adapter, SXG_UCODE_SAHARA)) {
854 DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
856 sxg_read_config(adapter);
857 sxg_adapter_set_hwaddr(adapter);
859 adapter->state = ADAPT_FAIL;
860 adapter->linkstate = LINK_DOWN;
861 DBG_ERROR("sxg_download_microcode FAILED status[%x]\n", status);
864 netdev->base_addr = (unsigned long)adapter->base_addr;
865 netdev->irq = adapter->irq;
866 netdev->open = sxg_entry_open;
867 netdev->stop = sxg_entry_halt;
868 netdev->hard_start_xmit = sxg_send_packets;
869 netdev->do_ioctl = sxg_ioctl;
871 netdev->set_mac_address = sxg_mac_set_address;
872 #if SLIC_GET_STATS_ENABLED
873 netdev->get_stats = sxg_get_stats;
876 netdev->set_multicast_list = sxg_mcast_set_list;
878 strcpy(netdev->name, "eth%d");
879 /* strcpy(netdev->name, pci_name(pcidev)); */
880 if ((err = register_netdev(netdev))) {
881 DBG_ERROR("Cannot register net device, aborting. %s\n",
887 ("sxg: %s addr 0x%lx, irq %d, MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
888 netdev->name, netdev->base_addr, pcidev->irq, netdev->dev_addr[0],
889 netdev->dev_addr[1], netdev->dev_addr[2], netdev->dev_addr[3],
890 netdev->dev_addr[4], netdev->dev_addr[5]);
893 ASSERT(status == FALSE);
894 /* sxg_free_adapter(adapter); */
896 DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __func__,
897 status, jiffies, smp_processor_id());
901 iounmap((void *)memmapped_ioaddr);
903 err_out_free_mmio_region:
904 release_mem_region(mmio_start, mmio_len);
906 err_out_exit_sxg_probe:
908 DBG_ERROR("%s EXIT jiffies[%lx] cpu %d\n", __func__, jiffies,
914 /***********************************************************************
915 * LINE BASE Interrupt routines..
916 ***********************************************************************/
919 * sxg_disable_interrupt
921 * DisableInterrupt Handler
925 * adapter: Our adapter structure
930 static void sxg_disable_interrupt(struct adapter_t *adapter)
932 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DisIntr",
933 adapter, adapter->InterruptsEnabled, 0, 0);
934 /* For now, RSS is disabled with line based interrupts */
935 ASSERT(adapter->RssEnabled == FALSE);
936 ASSERT(adapter->MsiEnabled == FALSE);
938 /* Turn off interrupts by writing to the icr register. */
940 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE);
942 adapter->InterruptsEnabled = 0;
944 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDisIntr",
945 adapter, adapter->InterruptsEnabled, 0, 0);
950 * sxg_enable_interrupt
952 * EnableInterrupt Handler
956 * adapter: Our adapter structure
961 static void sxg_enable_interrupt(struct adapter_t *adapter)
963 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "EnIntr",
964 adapter, adapter->InterruptsEnabled, 0, 0);
965 /* For now, RSS is disabled with line based interrupts */
966 ASSERT(adapter->RssEnabled == FALSE);
967 ASSERT(adapter->MsiEnabled == FALSE);
969 /* Turn on interrupts by writing to the icr register. */
971 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_ENABLE), TRUE);
973 adapter->InterruptsEnabled = 1;
975 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XEnIntr",
981 * sxg_isr - Process an line-based interrupt
984 * Context - Our adapter structure
985 * QueueDefault - Output parameter to queue to default CPU
986 * TargetCpus - Output bitmap to schedule DPC's
989 * TRUE if our interrupt
991 static irqreturn_t sxg_isr(int irq, void *dev_id)
993 struct net_device *dev = (struct net_device *) dev_id;
994 struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
995 /* u32 CpuMask = 0, i; */
997 adapter->Stats.NumInts++;
998 if (adapter->Isr[0] == 0) {
999 /* The SLIC driver used to experience a number of spurious interrupts */
1000 /* due to the delay associated with the masking of the interrupt */
1001 /* (we'd bounce back in here). If we see that again with Sahara, */
1002 /* add a READ_REG of the Icr register after the WRITE_REG below. */
1003 adapter->Stats.FalseInts++;
1007 /* Move the Isr contents and clear the value in */
1008 /* shared memory, and mask interrupts */
1010 adapter->IsrCopy[0] = adapter->Isr[0];
1011 adapter->Isr[0] = 0;
1012 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_MASK), TRUE);
1013 /* ASSERT(adapter->IsrDpcsPending == 0); */
1014 #if XXXTODO /* RSS Stuff */
1015 /* If RSS is enabled and the ISR specifies */
1016 /* SXG_ISR_EVENT, then schedule DPC's */
1017 /* based on event queues. */
1018 if (adapter->RssEnabled && (adapter->IsrCopy[0] & SXG_ISR_EVENT)) {
1020 i < adapter->RssSystemInfo->ProcessorInfo.RssCpuCount;
1022 struct sxg_event_ring *EventRing = &adapter->EventRings[i];
1023 struct sxg_event *Event =
1024 &EventRing->Ring[adapter->NextEvent[i]];
1026 adapter->RssSystemInfo->RssIdToCpu[i];
1027 if (Event->Status & EVENT_STATUS_VALID) {
1028 adapter->IsrDpcsPending++;
1029 CpuMask |= (1 << Cpu);
1033 /* Now, either schedule the CPUs specified by the CpuMask, */
1034 /* or queue default */
1036 *QueueDefault = FALSE;
1038 adapter->IsrDpcsPending = 1;
1039 *QueueDefault = TRUE;
1041 *TargetCpus = CpuMask;
1044 /* There are no DPCs in Linux, so call the handler now */
1046 sxg_handle_interrupt(adapter);
1051 int debug_inthandler = 0;
1053 static void sxg_handle_interrupt(struct adapter_t *adapter)
1055 /* unsigned char RssId = 0; */
1058 if (++debug_inthandler < 20) {
1059 DBG_ERROR("Enter sxg_handle_interrupt ISR[%x]\n",
1060 adapter->IsrCopy[0]);
1062 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "HndlIntr",
1063 adapter, adapter->IsrCopy[0], 0, 0);
1064 /* For now, RSS is disabled with line based interrupts */
1065 ASSERT(adapter->RssEnabled == FALSE);
1066 ASSERT(adapter->MsiEnabled == FALSE);
1067 ASSERT(adapter->IsrCopy[0]);
1068 /*/////////////////////////// */
1070 /* Always process the event queue. */
1071 sxg_process_event_queue(adapter,
1072 (adapter->RssEnabled ? /*RssId */ 0 : 0));
1074 #if XXXTODO /* RSS stuff */
1075 if (--adapter->IsrDpcsPending) {
1077 ASSERT(adapter->RssEnabled);
1078 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DPCsPend",
1084 /* Last (or only) DPC processes the ISR and clears the interrupt. */
1086 NewIsr = sxg_process_isr(adapter, 0);
1088 /* Reenable interrupts */
1090 adapter->IsrCopy[0] = 0;
1091 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ClearIsr",
1092 adapter, NewIsr, 0, 0);
1094 if (debug_inthandler < 20) {
1096 ("Exit sxg_handle_interrupt2 after enabling interrupt\n");
1099 WRITE_REG(adapter->UcodeRegs[0].Isr, NewIsr, TRUE);
1101 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XHndlInt",
1107 * sxg_process_isr - Process an interrupt. Called from the line-based and
1108 * message based interrupt DPC routines
1111 * adapter - Our adapter structure
1112 * Queue - The ISR that needs processing
1117 static int sxg_process_isr(struct adapter_t *adapter, u32 MessageId)
1119 u32 Isr = adapter->IsrCopy[MessageId];
1122 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ProcIsr",
1123 adapter, Isr, 0, 0);
1126 if (Isr & SXG_ISR_ERR) {
1127 if (Isr & SXG_ISR_PDQF) {
1128 adapter->Stats.PdqFull++;
1129 DBG_ERROR("%s: SXG_ISR_ERR PDQF!!\n", __func__);
1131 /* No host buffer */
1132 if (Isr & SXG_ISR_RMISS) {
1133 /* There is a bunch of code in the SLIC driver which */
1134 /* attempts to process more receive events per DPC */
1135 /* if we start to fall behind. We'll probably */
1136 /* need to do something similar here, but hold */
1137 /* off for now. I don't want to make the code more */
1138 /* complicated than strictly needed. */
1139 adapter->Stats.RcvNoBuffer++;
1140 if (adapter->Stats.RcvNoBuffer < 5) {
1141 DBG_ERROR("%s: SXG_ISR_ERR RMISS!!\n",
1146 if (Isr & SXG_ISR_DEAD) {
1147 /* Set aside the crash info and set the adapter state to RESET */
1149 (unsigned char)((Isr & SXG_ISR_CPU) >>
1151 adapter->CrashLocation = (ushort) (Isr & SXG_ISR_CRASH);
1152 adapter->Dead = TRUE;
1153 DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __func__,
1154 adapter->CrashLocation, adapter->CrashCpu);
1156 /* Event ring full */
1157 if (Isr & SXG_ISR_ERFULL) {
1158 /* Same issue as RMISS, really. This means the */
1159 /* host is falling behind the card. Need to increase */
1160 /* event ring size, process more events per interrupt, */
1161 /* and/or reduce/remove interrupt aggregation. */
1162 adapter->Stats.EventRingFull++;
1163 DBG_ERROR("%s: SXG_ISR_ERR EVENT RING FULL!!\n",
1166 /* Transmit drop - no DRAM buffers or XMT error */
1167 if (Isr & SXG_ISR_XDROP) {
1168 adapter->Stats.XmtDrops++;
1169 adapter->Stats.XmtErrors++;
1170 DBG_ERROR("%s: SXG_ISR_ERR XDROP!!\n", __func__);
1173 /* Slowpath send completions */
1174 if (Isr & SXG_ISR_SPSEND) {
1175 sxg_complete_slow_send(adapter);
1178 if (Isr & SXG_ISR_UPC) {
1179 ASSERT(adapter->DumpCmdRunning); /* Maybe change when debug is added.. */
1180 adapter->DumpCmdRunning = FALSE;
1183 if (Isr & SXG_ISR_LINK) {
1184 sxg_link_event(adapter);
1186 /* Debug - breakpoint hit */
1187 if (Isr & SXG_ISR_BREAK) {
1188 /* At the moment AGDB isn't written to support interactive */
1189 /* debug sessions. When it is, this interrupt will be used */
1190 /* to signal AGDB that it has hit a breakpoint. For now, ASSERT. */
1193 /* Heartbeat response */
1194 if (Isr & SXG_ISR_PING) {
1195 adapter->PingOutstanding = FALSE;
1197 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XProcIsr",
1198 adapter, Isr, NewIsr, 0);
1205 * sxg_process_event_queue - Process our event queue
1208 * - adapter - Adapter structure
1209 * - RssId - The event queue requiring processing
1214 static u32 sxg_process_event_queue(struct adapter_t *adapter, u32 RssId)
1216 struct sxg_event_ring *EventRing = &adapter->EventRings[RssId];
1217 struct sxg_event *Event = &EventRing->Ring[adapter->NextEvent[RssId]];
1218 u32 EventsProcessed = 0, Batches = 0;
1220 struct sk_buff *skb;
1221 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1222 struct sk_buff *prev_skb = NULL;
1223 struct sk_buff *IndicationList[SXG_RCV_ARRAYSIZE];
1225 struct sxg_rcv_data_buffer_hdr *RcvDataBufferHdr;
1227 u32 ReturnStatus = 0;
1229 ASSERT((adapter->State == SXG_STATE_RUNNING) ||
1230 (adapter->State == SXG_STATE_PAUSING) ||
1231 (adapter->State == SXG_STATE_PAUSED) ||
1232 (adapter->State == SXG_STATE_HALTING));
1233 /* We may still have unprocessed events on the queue if */
1234 /* the card crashed. Don't process them. */
1235 if (adapter->Dead) {
1238 /* In theory there should only be a single processor that */
1239 /* accesses this queue, and only at interrupt-DPC time. So */
1240 /* we shouldn't need a lock for any of this. */
1241 while (Event->Status & EVENT_STATUS_VALID) {
1242 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "Event",
1243 Event, Event->Code, Event->Status,
1244 adapter->NextEvent);
1245 switch (Event->Code) {
1246 case EVENT_CODE_BUFFERS:
1247 ASSERT(!(Event->CommandIndex & 0xFF00)); /* struct sxg_ring_info Head & Tail == unsigned char */
1249 sxg_complete_descriptor_blocks(adapter,
1250 Event->CommandIndex);
1253 case EVENT_CODE_SLOWRCV:
1254 --adapter->RcvBuffersOnCard;
1255 if ((skb = sxg_slow_receive(adapter, Event))) {
1257 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1258 /* Add it to our indication list */
1259 SXG_ADD_RCV_PACKET(adapter, skb, prev_skb,
1260 IndicationList, num_skbs);
1261 /* In Linux, we just pass up each skb to the protocol above at this point, */
1262 /* there is no capability of an indication list. */
1264 /* CHECK skb_pull(skb, INIC_RCVBUF_HEADSIZE); */
1265 rx_bytes = Event->Length; /* (rcvbuf->length & IRHDDR_FLEN_MSK); */
1266 adapter->stats.rx_packets++;
1267 adapter->stats.rx_bytes += rx_bytes;
1268 #if SXG_OFFLOAD_IP_CHECKSUM
1269 skb->ip_summed = CHECKSUM_UNNECESSARY;
1271 skb->dev = adapter->netdev;
1277 DBG_ERROR("%s: ERROR Invalid EventCode %d\n",
1278 __func__, Event->Code);
1281 /* See if we need to restock card receive buffers. */
1282 /* There are two things to note here: */
1283 /* First - This test is not SMP safe. The */
1284 /* adapter->BuffersOnCard field is protected via atomic interlocked calls, but */
1285 /* we do not protect it with respect to these tests. The only way to do that */
1286 /* is with a lock, and I don't want to grab a lock every time we adjust the */
1287 /* BuffersOnCard count. Instead, we allow the buffer replenishment to be off */
1288 /* once in a while. The worst that can happen is the card is given one */
1289 /* more-or-less descriptor block than the arbitrary value we've chosen. */
1291 /* In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard is adjusted. */
1292 /* Second - We expect this test to rarely evaluate to true. We attempt to */
1293 /* refill descriptor blocks as they are returned to us */
1294 /* (sxg_complete_descriptor_blocks), so The only time this should evaluate */
1295 /* to true is when sxg_complete_descriptor_blocks failed to allocate */
1296 /* receive buffers. */
1297 if (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
1298 sxg_stock_rcv_buffers(adapter);
1300 /* It's more efficient to just set this to zero. */
1301 /* But clearing the top bit saves potential debug info... */
1302 Event->Status &= ~EVENT_STATUS_VALID;
1303 /* Advanct to the next event */
1304 SXG_ADVANCE_INDEX(adapter->NextEvent[RssId], EVENT_RING_SIZE);
1305 Event = &EventRing->Ring[adapter->NextEvent[RssId]];
1307 if (EventsProcessed == EVENT_RING_BATCH) {
1308 /* Release a batch of events back to the card */
1309 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1310 EVENT_RING_BATCH, FALSE);
1311 EventsProcessed = 0;
1312 /* If we've processed our batch limit, break out of the */
1313 /* loop and return SXG_ISR_EVENT to arrange for us to */
1314 /* be called again */
1315 if (Batches++ == EVENT_BATCH_LIMIT) {
1316 SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
1317 TRACE_NOISY, "EvtLimit", Batches,
1318 adapter->NextEvent, 0, 0);
1319 ReturnStatus = SXG_ISR_EVENT;
1324 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1326 /* Indicate any received dumb-nic frames */
1328 SXG_INDICATE_PACKETS(adapter, IndicationList, num_skbs);
1331 /* Release events back to the card. */
1333 if (EventsProcessed) {
1334 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1335 EventsProcessed, FALSE);
1337 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XPrcEvnt",
1338 Batches, EventsProcessed, adapter->NextEvent, num_skbs);
1340 return (ReturnStatus);
1344 * sxg_complete_slow_send - Complete slowpath or dumb-nic sends
1347 * adapter - A pointer to our adapter structure
1352 static void sxg_complete_slow_send(struct adapter_t *adapter)
1354 struct sxg_xmt_ring *XmtRing = &adapter->XmtRings[0];
1355 struct sxg_ring_info *XmtRingInfo = &adapter->XmtRingZeroInfo;
1357 struct sxg_cmd *XmtCmd;
1359 /* NOTE - This lock is dropped and regrabbed in this loop. */
1360 /* This means two different processors can both be running */
1361 /* through this loop. Be *very* careful. */
1362 spin_lock(&adapter->XmtZeroLock);
1363 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnds",
1364 adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
1366 while (XmtRingInfo->Tail != *adapter->XmtRingZeroIndex) {
1367 /* Locate the current Cmd (ring descriptor entry), and */
1368 /* associated SGL, and advance the tail */
1369 SXG_RETURN_CMD(XmtRing, XmtRingInfo, XmtCmd, ContextType);
1370 ASSERT(ContextType);
1371 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
1372 XmtRingInfo->Head, XmtRingInfo->Tail, XmtCmd, 0);
1373 /* Clear the SGL field. */
1376 switch (*ContextType) {
1379 struct sk_buff *skb;
1380 struct sxg_scatter_gather *SxgSgl = (struct sxg_scatter_gather *)ContextType;
1382 /* Dumb-nic send. Command context is the dumb-nic SGL */
1383 skb = (struct sk_buff *)ContextType;
1384 skb = SxgSgl->DumbPacket;
1385 /* Complete the send */
1386 SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
1387 TRACE_IMPORTANT, "DmSndCmp", skb, 0,
1389 printk("ASK:sxg_complete_slow_send: freeing an skb [%p]\n", skb);
1390 ASSERT(adapter->Stats.XmtQLen);
1391 adapter->Stats.XmtQLen--; /* within XmtZeroLock */
1392 adapter->Stats.XmtOk++;
1393 /* Now drop the lock and complete the send back to */
1394 /* Microsoft. We need to drop the lock because */
1395 /* Microsoft can come back with a chimney send, which */
1396 /* results in a double trip in SxgTcpOuput */
1397 spin_unlock(&adapter->XmtZeroLock);
1398 SXG_COMPLETE_DUMB_SEND(adapter, skb);
1399 /* and reacquire.. */
1400 spin_lock(&adapter->XmtZeroLock);
1407 spin_unlock(&adapter->XmtZeroLock);
1408 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
1409 adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
1416 * adapter - A pointer to our adapter structure
1417 * Event - Receive event
1422 static struct sk_buff *sxg_slow_receive(struct adapter_t *adapter, struct sxg_event *Event)
1424 struct sxg_rcv_data_buffer_hdr *RcvDataBufferHdr;
1425 struct sk_buff *Packet;
1431 RcvDataBufferHdr = (struct sxg_rcv_data_buffer_hdr *) Event->HostHandle;
1432 ASSERT(RcvDataBufferHdr);
1433 ASSERT(RcvDataBufferHdr->State == SXG_BUFFER_ONCARD);
1434 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "SlowRcv", Event,
1435 RcvDataBufferHdr, RcvDataBufferHdr->State,
1436 RcvDataBufferHdr->VirtualAddress);
1437 /* Drop rcv frames in non-running state */
1438 switch (adapter->State) {
1439 case SXG_STATE_RUNNING:
1441 case SXG_STATE_PAUSING:
1442 case SXG_STATE_PAUSED:
1443 case SXG_STATE_HALTING:
1450 printk("ASK:sxg_slow_receive: event host handle %p\n", RcvDataBufferHdr);
1451 data = SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr);
1452 for (i = 0; i < 32; i++)
1453 dptr += sprintf(dptr, "%02x ", (unsigned)data[i]);
1454 printk("ASK:sxg_slow_receive: data %s\n", dstr);
1455 //memcpy(SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr), RcvDataBufferHdr->VirtualAddress, Event->Length);
1457 /* Change buffer state to UPSTREAM */
1458 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM;
1459 if (Event->Status & EVENT_STATUS_RCVERR) {
1460 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError",
1461 Event, Event->Status, Event->HostHandle, 0);
1462 /* XXXTODO - Remove this print later */
1463 DBG_ERROR("SXG: Receive error %x\n", *(u32 *)
1464 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr));
1465 sxg_process_rcv_error(adapter, *(u32 *)
1466 SXG_RECEIVE_DATA_LOCATION
1467 (RcvDataBufferHdr));
1470 #if XXXTODO /* VLAN stuff */
1471 /* If there's a VLAN tag, extract it and validate it */
1472 if (((struct ether_header*) (SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)))->
1473 EtherType == ETHERTYPE_VLAN) {
1474 if (SxgExtractVlanHeader(adapter, RcvDataBufferHdr, Event) !=
1476 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY,
1478 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1485 /* Dumb-nic frame. See if it passes our mac filter and update stats */
1487 /* ASK if (!sxg_mac_filter(adapter,
1488 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1490 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvFiltr",
1491 Event, SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1496 Packet = RcvDataBufferHdr->SxgDumbRcvPacket;
1497 SXG_ADJUST_RCV_PACKET(Packet, RcvDataBufferHdr, Event);
1498 Packet->protocol = eth_type_trans(Packet, adapter->netdev);
1499 printk("ASK:sxg_slow_receive: protocol %x\n", (unsigned) Packet->protocol);
1501 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumbRcv",
1502 RcvDataBufferHdr, Packet, Event->Length, 0);
1504 /* Lastly adjust the receive packet length. */
1506 RcvDataBufferHdr->SxgDumbRcvPacket = NULL;
1508 SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
1512 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DropRcv",
1513 RcvDataBufferHdr, Event->Length, 0, 0);
1514 adapter->Stats.RcvDiscards++;
1515 spin_lock(&adapter->RcvQLock);
1516 SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
1517 spin_unlock(&adapter->RcvQLock);
1522 * sxg_process_rcv_error - process receive error and update
1526 * adapter - Adapter structure
1527 * ErrorStatus - 4-byte receive error status
1532 static void sxg_process_rcv_error(struct adapter_t *adapter, u32 ErrorStatus)
1536 adapter->Stats.RcvErrors++;
1538 if (ErrorStatus & SXG_RCV_STATUS_TRANSPORT_ERROR) {
1539 Error = ErrorStatus & SXG_RCV_STATUS_TRANSPORT_MASK;
1541 case SXG_RCV_STATUS_TRANSPORT_CSUM:
1542 adapter->Stats.TransportCsum++;
1544 case SXG_RCV_STATUS_TRANSPORT_UFLOW:
1545 adapter->Stats.TransportUflow++;
1547 case SXG_RCV_STATUS_TRANSPORT_HDRLEN:
1548 adapter->Stats.TransportHdrLen++;
1552 if (ErrorStatus & SXG_RCV_STATUS_NETWORK_ERROR) {
1553 Error = ErrorStatus & SXG_RCV_STATUS_NETWORK_MASK;
1555 case SXG_RCV_STATUS_NETWORK_CSUM:
1556 adapter->Stats.NetworkCsum++;
1558 case SXG_RCV_STATUS_NETWORK_UFLOW:
1559 adapter->Stats.NetworkUflow++;
1561 case SXG_RCV_STATUS_NETWORK_HDRLEN:
1562 adapter->Stats.NetworkHdrLen++;
1566 if (ErrorStatus & SXG_RCV_STATUS_PARITY) {
1567 adapter->Stats.Parity++;
1569 if (ErrorStatus & SXG_RCV_STATUS_LINK_ERROR) {
1570 Error = ErrorStatus & SXG_RCV_STATUS_LINK_MASK;
1572 case SXG_RCV_STATUS_LINK_PARITY:
1573 adapter->Stats.LinkParity++;
1575 case SXG_RCV_STATUS_LINK_EARLY:
1576 adapter->Stats.LinkEarly++;
1578 case SXG_RCV_STATUS_LINK_BUFOFLOW:
1579 adapter->Stats.LinkBufOflow++;
1581 case SXG_RCV_STATUS_LINK_CODE:
1582 adapter->Stats.LinkCode++;
1584 case SXG_RCV_STATUS_LINK_DRIBBLE:
1585 adapter->Stats.LinkDribble++;
1587 case SXG_RCV_STATUS_LINK_CRC:
1588 adapter->Stats.LinkCrc++;
1590 case SXG_RCV_STATUS_LINK_OFLOW:
1591 adapter->Stats.LinkOflow++;
1593 case SXG_RCV_STATUS_LINK_UFLOW:
1594 adapter->Stats.LinkUflow++;
1604 * adapter - Adapter structure
1605 * pether - Ethernet header
1606 * length - Frame length
1609 * TRUE if the frame is to be allowed
1611 static bool sxg_mac_filter(struct adapter_t *adapter, struct ether_header *EtherHdr,
1616 if (SXG_MULTICAST_PACKET(EtherHdr)) {
1617 if (SXG_BROADCAST_PACKET(EtherHdr)) {
1619 if (adapter->MacFilter & MAC_BCAST) {
1620 adapter->Stats.DumbRcvBcastPkts++;
1621 adapter->Stats.DumbRcvBcastBytes += length;
1622 adapter->Stats.DumbRcvPkts++;
1623 adapter->Stats.DumbRcvBytes += length;
1628 if (adapter->MacFilter & MAC_ALLMCAST) {
1629 adapter->Stats.DumbRcvMcastPkts++;
1630 adapter->Stats.DumbRcvMcastBytes += length;
1631 adapter->Stats.DumbRcvPkts++;
1632 adapter->Stats.DumbRcvBytes += length;
1635 if (adapter->MacFilter & MAC_MCAST) {
1636 struct sxg_multicast_address *MulticastAddrs =
1637 adapter->MulticastAddrs;
1638 while (MulticastAddrs) {
1639 ETHER_EQ_ADDR(MulticastAddrs->Address,
1640 EtherHdr->ether_dhost,
1646 DumbRcvMcastBytes += length;
1647 adapter->Stats.DumbRcvPkts++;
1648 adapter->Stats.DumbRcvBytes +=
1652 MulticastAddrs = MulticastAddrs->Next;
1656 } else if (adapter->MacFilter & MAC_DIRECTED) {
1657 /* Not broadcast or multicast. Must be directed at us or */
1658 /* the card is in promiscuous mode. Either way, consider it */
1659 /* ours if MAC_DIRECTED is set */
1660 adapter->Stats.DumbRcvUcastPkts++;
1661 adapter->Stats.DumbRcvUcastBytes += length;
1662 adapter->Stats.DumbRcvPkts++;
1663 adapter->Stats.DumbRcvBytes += length;
1666 if (adapter->MacFilter & MAC_PROMISC) {
1667 /* Whatever it is, keep it. */
1668 adapter->Stats.DumbRcvPkts++;
1669 adapter->Stats.DumbRcvBytes += length;
1672 adapter->Stats.RcvDiscards++;
1676 static int sxg_register_interrupt(struct adapter_t *adapter)
1678 if (!adapter->intrregistered) {
1682 ("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x] %x\n",
1683 __func__, adapter, adapter->netdev->irq, NR_IRQS);
1685 spin_unlock_irqrestore(&sxg_global.driver_lock,
1688 retval = request_irq(adapter->netdev->irq,
1691 adapter->netdev->name, adapter->netdev);
1693 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
1696 DBG_ERROR("sxg: request_irq (%s) FAILED [%x]\n",
1697 adapter->netdev->name, retval);
1700 adapter->intrregistered = 1;
1701 adapter->IntRegistered = TRUE;
1702 /* Disable RSS with line-based interrupts */
1703 adapter->MsiEnabled = FALSE;
1704 adapter->RssEnabled = FALSE;
1705 DBG_ERROR("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x]\n",
1706 __func__, adapter, adapter->netdev->irq);
1708 return (STATUS_SUCCESS);
1711 static void sxg_deregister_interrupt(struct adapter_t *adapter)
1713 DBG_ERROR("sxg: %s ENTER adapter[%p]\n", __func__, adapter);
1715 slic_init_cleanup(adapter);
1717 memset(&adapter->stats, 0, sizeof(struct net_device_stats));
1718 adapter->error_interrupts = 0;
1719 adapter->rcv_interrupts = 0;
1720 adapter->xmit_interrupts = 0;
1721 adapter->linkevent_interrupts = 0;
1722 adapter->upr_interrupts = 0;
1723 adapter->num_isrs = 0;
1724 adapter->xmit_completes = 0;
1725 adapter->rcv_broadcasts = 0;
1726 adapter->rcv_multicasts = 0;
1727 adapter->rcv_unicasts = 0;
1728 DBG_ERROR("sxg: %s EXIT\n", __func__);
1734 * Perform initialization of our slic interface.
1737 static int sxg_if_init(struct adapter_t *adapter)
1739 struct net_device *dev = adapter->netdev;
1742 DBG_ERROR("sxg: %s (%s) ENTER states[%d:%d] flags[%x]\n",
1743 __func__, adapter->netdev->name,
1745 adapter->linkstate, dev->flags);
1747 /* adapter should be down at this point */
1748 if (adapter->state != ADAPT_DOWN) {
1749 DBG_ERROR("sxg_if_init adapter->state != ADAPT_DOWN\n");
1752 ASSERT(adapter->linkstate == LINK_DOWN);
1754 adapter->devflags_prev = dev->flags;
1755 adapter->macopts = MAC_DIRECTED;
1757 DBG_ERROR("sxg: %s (%s) Set MAC options: ", __func__,
1758 adapter->netdev->name);
1759 if (dev->flags & IFF_BROADCAST) {
1760 adapter->macopts |= MAC_BCAST;
1761 DBG_ERROR("BCAST ");
1763 if (dev->flags & IFF_PROMISC) {
1764 adapter->macopts |= MAC_PROMISC;
1765 DBG_ERROR("PROMISC ");
1767 if (dev->flags & IFF_ALLMULTI) {
1768 adapter->macopts |= MAC_ALLMCAST;
1769 DBG_ERROR("ALL_MCAST ");
1771 if (dev->flags & IFF_MULTICAST) {
1772 adapter->macopts |= MAC_MCAST;
1773 DBG_ERROR("MCAST ");
1777 status = sxg_register_interrupt(adapter);
1778 if (status != STATUS_SUCCESS) {
1779 DBG_ERROR("sxg_if_init: sxg_register_interrupt FAILED %x\n",
1781 sxg_deregister_interrupt(adapter);
1785 adapter->state = ADAPT_UP;
1788 * clear any pending events, then enable interrupts
1790 DBG_ERROR("sxg: %s ENABLE interrupts(slic)\n", __func__);
1792 return (STATUS_SUCCESS);
1795 static int sxg_entry_open(struct net_device *dev)
1797 struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
1801 DBG_ERROR("sxg: %s adapter->activated[%d]\n", __func__,
1802 adapter->activated);
1804 ("sxg: %s (%s): [jiffies[%lx] cpu %d] dev[%p] adapt[%p] port[%d]\n",
1805 __func__, adapter->netdev->name, jiffies, smp_processor_id(),
1806 adapter->netdev, adapter, adapter->port);
1808 netif_stop_queue(adapter->netdev);
1810 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
1811 if (!adapter->activated) {
1812 sxg_global.num_sxg_ports_active++;
1813 adapter->activated = 1;
1815 /* Initialize the adapter */
1816 DBG_ERROR("sxg: %s ENTER sxg_initialize_adapter\n", __func__);
1817 status = sxg_initialize_adapter(adapter);
1818 DBG_ERROR("sxg: %s EXIT sxg_initialize_adapter status[%x]\n",
1821 if (status == STATUS_SUCCESS) {
1822 DBG_ERROR("sxg: %s ENTER sxg_if_init\n", __func__);
1823 status = sxg_if_init(adapter);
1824 DBG_ERROR("sxg: %s EXIT sxg_if_init status[%x]\n", __func__,
1828 if (status != STATUS_SUCCESS) {
1829 if (adapter->activated) {
1830 sxg_global.num_sxg_ports_active--;
1831 adapter->activated = 0;
1833 spin_unlock_irqrestore(&sxg_global.driver_lock,
1837 DBG_ERROR("sxg: %s ENABLE ALL INTERRUPTS\n", __func__);
1839 /* Enable interrupts */
1840 SXG_ENABLE_ALL_INTERRUPTS(adapter);
1842 DBG_ERROR("sxg: %s EXIT\n", __func__);
1844 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
1845 return STATUS_SUCCESS;
1848 static void __devexit sxg_entry_remove(struct pci_dev *pcidev)
1850 struct net_device *dev = pci_get_drvdata(pcidev);
1852 unsigned int mmio_len = 0;
1853 struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
1856 DBG_ERROR("sxg: %s ENTER dev[%p] adapter[%p]\n", __func__, dev,
1858 sxg_deregister_interrupt(adapter);
1859 sxg_unmap_mmio_space(adapter);
1860 DBG_ERROR("sxg: %s unregister_netdev\n", __func__);
1861 unregister_netdev(dev);
1863 mmio_start = pci_resource_start(pcidev, 0);
1864 mmio_len = pci_resource_len(pcidev, 0);
1866 DBG_ERROR("sxg: %s rel_region(0) start[%x] len[%x]\n", __func__,
1867 mmio_start, mmio_len);
1868 release_mem_region(mmio_start, mmio_len);
1870 DBG_ERROR("sxg: %s iounmap dev->base_addr[%x]\n", __func__,
1871 (unsigned int)dev->base_addr);
1872 iounmap((char *)dev->base_addr);
1874 DBG_ERROR("sxg: %s deallocate device\n", __func__);
1876 DBG_ERROR("sxg: %s EXIT\n", __func__);
1879 static int sxg_entry_halt(struct net_device *dev)
1881 struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
1883 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
1884 DBG_ERROR("sxg: %s (%s) ENTER\n", __func__, dev->name);
1886 netif_stop_queue(adapter->netdev);
1887 adapter->state = ADAPT_DOWN;
1888 adapter->linkstate = LINK_DOWN;
1889 adapter->devflags_prev = 0;
1890 DBG_ERROR("sxg: %s (%s) set adapter[%p] state to ADAPT_DOWN(%d)\n",
1891 __func__, dev->name, adapter, adapter->state);
1893 DBG_ERROR("sxg: %s (%s) EXIT\n", __func__, dev->name);
1894 DBG_ERROR("sxg: %s EXIT\n", __func__);
1895 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
1896 return (STATUS_SUCCESS);
1899 static int sxg_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1902 /* DBG_ERROR("sxg: %s cmd[%x] rq[%p] dev[%p]\n", __func__, cmd, rq, dev); */
1904 case SIOCSLICSETINTAGG:
1906 /* struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev); */
1910 if (copy_from_user(data, rq->ifr_data, 28)) {
1912 ("copy_from_user FAILED getting initial params\n");
1917 "%s: set interrupt aggregation to %d\n",
1923 /* DBG_ERROR("sxg: %s UNSUPPORTED[%x]\n", __func__, cmd); */
1929 #define NORMAL_ETHFRAME 0
1933 * sxg_send_packets - Send a skb packet
1936 * skb - The packet to send
1937 * dev - Our linux net device that refs our adapter
1940 * 0 regardless of outcome XXXTODO refer to e1000 driver
1942 static int sxg_send_packets(struct sk_buff *skb, struct net_device *dev)
1944 struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
1945 u32 status = STATUS_SUCCESS;
1947 //DBG_ERROR("sxg: %s ENTER sxg_send_packets skb[%p]\n", __FUNCTION__,
1949 printk("ASK:sxg_send_packets: skb[%p]\n", skb);
1951 /* Check the adapter state */
1952 switch (adapter->State) {
1953 case SXG_STATE_INITIALIZING:
1954 case SXG_STATE_HALTED:
1955 case SXG_STATE_SHUTDOWN:
1956 ASSERT(0); /* unexpected */
1958 case SXG_STATE_RESETTING:
1959 case SXG_STATE_SLEEP:
1960 case SXG_STATE_BOOTDIAG:
1961 case SXG_STATE_DIAG:
1962 case SXG_STATE_HALTING:
1963 status = STATUS_FAILURE;
1965 case SXG_STATE_RUNNING:
1966 if (adapter->LinkState != SXG_LINK_UP) {
1967 status = STATUS_FAILURE;
1972 status = STATUS_FAILURE;
1974 if (status != STATUS_SUCCESS) {
1978 status = sxg_transmit_packet(adapter, skb);
1979 if (status == STATUS_SUCCESS) {
1984 /* reject & complete all the packets if they cant be sent */
1985 if (status != STATUS_SUCCESS) {
1987 /* sxg_send_packets_fail(adapter, skb, status); */
1989 SXG_DROP_DUMB_SEND(adapter, skb);
1990 adapter->stats.tx_dropped++;
1993 DBG_ERROR("sxg: %s EXIT sxg_send_packets status[%x]\n", __func__,
2001 * sxg_transmit_packet
2003 * This function transmits a single packet.
2006 * adapter - Pointer to our adapter structure
2007 * skb - The packet to be sent
2012 static int sxg_transmit_packet(struct adapter_t *adapter, struct sk_buff *skb)
2014 struct sxg_x64_sgl *pSgl;
2015 struct sxg_scatter_gather *SxgSgl;
2017 u32 SglBufferLength;
2019 /* The vast majority of work is done in the shared */
2020 /* sxg_dumb_sgl routine. */
2021 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSend",
2022 adapter, skb, 0, 0);
2024 /* Allocate a SGL buffer */
2025 SXG_GET_SGL_BUFFER(adapter, SxgSgl);
2027 adapter->Stats.NoSglBuf++;
2028 adapter->Stats.XmtErrors++;
2029 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "SndPktF1",
2030 adapter, skb, 0, 0);
2031 return (STATUS_RESOURCES);
2033 ASSERT(SxgSgl->adapter == adapter);
2034 SglBuffer = SXG_SGL_BUFFER(SxgSgl);
2035 SglBufferLength = SXG_SGL_BUF_SIZE;
2036 SxgSgl->VlanTag.VlanTci = 0;
2037 SxgSgl->VlanTag.VlanTpid = 0;
2038 SxgSgl->Type = SXG_SGL_DUMB;
2039 SxgSgl->DumbPacket = skb;
2042 /* Call the common sxg_dumb_sgl routine to complete the send. */
2043 sxg_dumb_sgl(pSgl, SxgSgl);
2044 /* Return success sxg_dumb_sgl (or something later) will complete it. */
2045 return (STATUS_SUCCESS);
2053 * SxgSgl - struct sxg_scatter_gather
2058 static void sxg_dumb_sgl(struct sxg_x64_sgl *pSgl, struct sxg_scatter_gather *SxgSgl)
2060 struct adapter_t *adapter = SxgSgl->adapter;
2061 struct sk_buff *skb = SxgSgl->DumbPacket;
2062 /* For now, all dumb-nic sends go on RSS queue zero */
2063 struct sxg_xmt_ring *XmtRing = &adapter->XmtRings[0];
2064 struct sxg_ring_info *XmtRingInfo = &adapter->XmtRingZeroInfo;
2065 struct sxg_cmd *XmtCmd = NULL;
2066 /* u32 Index = 0; */
2067 u32 DataLength = skb->len;
2068 /* unsigned int BufLen; */
2069 /* u32 SglOffset; */
2076 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSgl",
2077 pSgl, SxgSgl, 0, 0);
2079 for (i = 0; i < 32; i++)
2080 dptr += sprintf(dptr, "%02x ", (unsigned)data[i]);
2081 printk("ASK:sxg_dumb_sgl: data %s\n", dstr);
2083 /* Set aside a pointer to the sgl */
2084 SxgSgl->pSgl = pSgl;
2086 /* Sanity check that our SGL format is as we expect. */
2087 ASSERT(sizeof(struct sxg_x64_sge) == sizeof(struct sxg_x64_sge));
2088 /* Shouldn't be a vlan tag on this frame */
2089 ASSERT(SxgSgl->VlanTag.VlanTci == 0);
2090 ASSERT(SxgSgl->VlanTag.VlanTpid == 0);
2092 /* From here below we work with the SGL placed in our */
2095 SxgSgl->Sgl.NumberOfElements = 1;
2097 /* Grab the spinlock and acquire a command */
2098 spin_lock(&adapter->XmtZeroLock);
2099 SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
2100 if (XmtCmd == NULL) {
2101 /* Call sxg_complete_slow_send to see if we can */
2102 /* free up any XmtRingZero entries and then try again */
2103 spin_unlock(&adapter->XmtZeroLock);
2104 sxg_complete_slow_send(adapter);
2105 spin_lock(&adapter->XmtZeroLock);
2106 SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
2107 if (XmtCmd == NULL) {
2108 adapter->Stats.XmtZeroFull++;
2112 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbCmd",
2113 XmtCmd, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
2115 adapter->Stats.DumbXmtPkts++;
2116 adapter->Stats.DumbXmtBytes += DataLength;
2117 #if XXXTODO /* Stats stuff */
2118 if (SXG_MULTICAST_PACKET(EtherHdr)) {
2119 if (SXG_BROADCAST_PACKET(EtherHdr)) {
2120 adapter->Stats.DumbXmtBcastPkts++;
2121 adapter->Stats.DumbXmtBcastBytes += DataLength;
2123 adapter->Stats.DumbXmtMcastPkts++;
2124 adapter->Stats.DumbXmtMcastBytes += DataLength;
2127 adapter->Stats.DumbXmtUcastPkts++;
2128 adapter->Stats.DumbXmtUcastBytes += DataLength;
2131 /* Fill in the command */
2132 /* Copy out the first SGE to the command and adjust for offset */
2134 pci_map_single(adapter->pcidev, skb->data, skb->len,
2136 memset(XmtCmd, '\0', sizeof(*XmtCmd));
2137 XmtCmd->Buffer.FirstSgeAddress = phys_addr;
2138 XmtCmd->Buffer.FirstSgeLength = DataLength;
2139 XmtCmd->Buffer.SgeOffset = 0;
2140 XmtCmd->Buffer.TotalLength = DataLength;
2141 XmtCmd->SgEntries = 1;
2143 printk("ASK:sxg_dumb_sgl: wrote to xmit register\n");
2145 /* Advance transmit cmd descripter by 1. */
2146 /* NOTE - See comments in SxgTcpOutput where we write */
2147 /* to the XmtCmd register regarding CPU ID values and/or */
2148 /* multiple commands. */
2151 WRITE_REG(adapter->UcodeRegs[0].XmtCmd, 1, TRUE);
2154 adapter->Stats.XmtQLen++; /* Stats within lock */
2155 spin_unlock(&adapter->XmtZeroLock);
2156 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDumSgl2",
2157 XmtCmd, pSgl, SxgSgl, 0);
2161 /* NOTE - Only jump to this label AFTER grabbing the */
2162 /* XmtZeroLock, and DO NOT DROP IT between the */
2163 /* command allocation and the following abort. */
2165 SXG_ABORT_CMD(XmtRingInfo);
2167 spin_unlock(&adapter->XmtZeroLock);
2170 /* Jump to this label if failure occurs before the */
2171 /* XmtZeroLock is grabbed */
2172 adapter->Stats.XmtErrors++;
2173 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumSGFal",
2174 pSgl, SxgSgl, XmtRingInfo->Head, XmtRingInfo->Tail);
2176 SXG_COMPLETE_DUMB_SEND(adapter, SxgSgl->DumbPacket); /* SxgSgl->DumbPacket is the skb */
2179 /***************************************************************
2180 * Link management functions
2181 ***************************************************************/
2184 * sxg_initialize_link - Initialize the link stuff
2187 * adapter - A pointer to our adapter structure
2192 static int sxg_initialize_link(struct adapter_t *adapter)
2194 struct sxg_hw_regs *HwRegs = adapter->HwRegs;
2200 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitLink",
2203 /* Reset PHY and XGXS module */
2204 WRITE_REG(HwRegs->LinkStatus, LS_SERDES_POWER_DOWN, TRUE);
2206 /* Reset transmit configuration register */
2207 WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_RESET, TRUE);
2209 /* Reset receive configuration register */
2210 WRITE_REG(HwRegs->RcvConfig, RCV_CONFIG_RESET, TRUE);
2212 /* Reset all MAC modules */
2213 WRITE_REG(HwRegs->MacConfig0, AXGMAC_CFG0_SUB_RESET, TRUE);
2215 /* Link address 0 */
2216 /* XXXTODO - This assumes the MAC address (0a:0b:0c:0d:0e:0f) */
2217 /* is stored with the first nibble (0a) in the byte 0 */
2218 /* of the Mac address. Possibly reverse? */
2219 Value = *(u32 *) adapter->macaddr;
2220 WRITE_REG(HwRegs->LinkAddress0Low, Value, TRUE);
2221 /* also write the MAC address to the MAC. Endian is reversed. */
2222 WRITE_REG(HwRegs->MacAddressLow, ntohl(Value), TRUE);
2223 Value = (*(u16 *) & adapter->macaddr[4] & 0x0000FFFF);
2224 WRITE_REG(HwRegs->LinkAddress0High, Value | LINK_ADDRESS_ENABLE, TRUE);
2225 /* endian swap for the MAC (put high bytes in bits [31:16], swapped) */
2226 Value = ntohl(Value);
2227 WRITE_REG(HwRegs->MacAddressHigh, Value, TRUE);
2228 /* Link address 1 */
2229 WRITE_REG(HwRegs->LinkAddress1Low, 0, TRUE);
2230 WRITE_REG(HwRegs->LinkAddress1High, 0, TRUE);
2231 /* Link address 2 */
2232 WRITE_REG(HwRegs->LinkAddress2Low, 0, TRUE);
2233 WRITE_REG(HwRegs->LinkAddress2High, 0, TRUE);
2234 /* Link address 3 */
2235 WRITE_REG(HwRegs->LinkAddress3Low, 0, TRUE);
2236 WRITE_REG(HwRegs->LinkAddress3High, 0, TRUE);
2238 /* Enable MAC modules */
2239 WRITE_REG(HwRegs->MacConfig0, 0, TRUE);
2242 WRITE_REG(HwRegs->MacConfig1, (AXGMAC_CFG1_XMT_PAUSE | /* Allow sending of pause */
2243 AXGMAC_CFG1_XMT_EN | /* Enable XMT */
2244 AXGMAC_CFG1_RCV_PAUSE | /* Enable detection of pause */
2245 AXGMAC_CFG1_RCV_EN | /* Enable receive */
2246 AXGMAC_CFG1_SHORT_ASSERT | /* short frame detection */
2247 AXGMAC_CFG1_CHECK_LEN | /* Verify frame length */
2248 AXGMAC_CFG1_GEN_FCS | /* Generate FCS */
2249 AXGMAC_CFG1_PAD_64), /* Pad frames to 64 bytes */
2252 /* Set AXGMAC max frame length if jumbo. Not needed for standard MTU */
2253 if (adapter->JumboEnabled) {
2254 WRITE_REG(HwRegs->MacMaxFrameLen, AXGMAC_MAXFRAME_JUMBO, TRUE);
2256 /* AMIIM Configuration Register - */
2257 /* The value placed in the AXGMAC_AMIIM_CFG_HALF_CLOCK portion */
2258 /* (bottom bits) of this register is used to determine the */
2259 /* MDC frequency as specified in the A-XGMAC Design Document. */
2260 /* This value must not be zero. The following value (62 or 0x3E) */
2261 /* is based on our MAC transmit clock frequency (MTCLK) of 312.5 MHz. */
2262 /* Given a maximum MDIO clock frequency of 2.5 MHz (see the PHY spec), */
2263 /* we get: 312.5/(2*(X+1)) < 2.5 ==> X = 62. */
2264 /* This value happens to be the default value for this register, */
2265 /* so we really don't have to do this. */
2266 WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE);
2268 /* Power up and enable PHY and XAUI/XGXS/Serdes logic */
2269 WRITE_REG(HwRegs->LinkStatus,
2272 LS_XGXS_CTL | LS_PHY_CLK_EN | LS_ATTN_ALARM), TRUE);
2273 DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n");
2275 /* Per information given by Aeluros, wait 100 ms after removing reset. */
2276 /* It's not enough to wait for the self-clearing reset bit in reg 0 to clear. */
2279 /* Verify the PHY has come up by checking that the Reset bit has cleared. */
2280 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2281 PHY_PMA_CONTROL1, /* PMA/PMD control register */
2283 DBG_ERROR("After sxg_read_mdio_reg Value[%x] fail=%x\n", Value, (Value & PMA_CONTROL1_RESET));
2284 if (status != STATUS_SUCCESS)
2285 return (STATUS_FAILURE);
2286 if (Value & PMA_CONTROL1_RESET) /* reset complete if bit is 0 */
2287 return (STATUS_FAILURE);
2289 /* The SERDES should be initialized by now - confirm */
2290 READ_REG(HwRegs->LinkStatus, Value);
2291 if (Value & LS_SERDES_DOWN) /* verify SERDES is initialized */
2292 return (STATUS_FAILURE);
2294 /* The XAUI link should also be up - confirm */
2295 if (!(Value & LS_XAUI_LINK_UP)) /* verify XAUI link is up */
2296 return (STATUS_FAILURE);
2298 /* Initialize the PHY */
2299 status = sxg_phy_init(adapter);
2300 if (status != STATUS_SUCCESS)
2301 return (STATUS_FAILURE);
2303 /* Enable the Link Alarm */
2304 status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2305 LASI_CONTROL, /* LASI control register */
2306 LASI_CTL_LS_ALARM_ENABLE); /* enable link alarm bit */
2307 if (status != STATUS_SUCCESS)
2308 return (STATUS_FAILURE);
2310 /* XXXTODO - temporary - verify bit is set */
2311 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2312 LASI_CONTROL, /* LASI control register */
2314 if (status != STATUS_SUCCESS)
2315 return (STATUS_FAILURE);
2316 if (!(Value & LASI_CTL_LS_ALARM_ENABLE)) {
2317 DBG_ERROR("Error! LASI Control Alarm Enable bit not set!\n");
2319 /* Enable receive */
2320 MaxFrame = adapter->JumboEnabled ? JUMBOMAXFRAME : ETHERMAXFRAME;
2321 ConfigData = (RCV_CONFIG_ENABLE |
2322 RCV_CONFIG_ENPARSE |
2324 RCV_CONFIG_RCVPAUSE |
2327 RCV_CONFIG_HASH_16 |
2328 RCV_CONFIG_SOCKET | RCV_CONFIG_BUFSIZE(MaxFrame));
2329 WRITE_REG(HwRegs->RcvConfig, ConfigData, TRUE);
2331 WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_ENABLE, TRUE);
2333 /* Mark the link as down. We'll get a link event when it comes up. */
2334 sxg_link_state(adapter, SXG_LINK_DOWN);
2336 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInitLnk",
2338 return (STATUS_SUCCESS);
2342 * sxg_phy_init - Initialize the PHY
2345 * adapter - A pointer to our adapter structure
2350 static int sxg_phy_init(struct adapter_t *adapter)
2353 struct phy_ucode *p;
2356 DBG_ERROR("ENTER %s\n", __func__);
2358 /* Read a register to identify the PHY type */
2359 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2360 0xC205, /* PHY ID register (?) */
2361 &Value); /* XXXTODO - add def */
2362 if (status != STATUS_SUCCESS)
2363 return (STATUS_FAILURE);
2365 if (Value == 0x0012) { /* 0x0012 == AEL2005C PHY(?) - XXXTODO - add def */
2367 ("AEL2005C PHY detected. Downloading PHY microcode.\n");
2369 /* Initialize AEL2005C PHY and download PHY microcode */
2370 for (p = PhyUcode; p->Addr != 0xFFFF; p++) {
2372 /* if address == 0, data == sleep time in ms */
2375 /* write the given data to the specified address */
2376 status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2377 p->Addr, /* PHY address */
2378 p->Data); /* PHY data */
2379 if (status != STATUS_SUCCESS)
2380 return (STATUS_FAILURE);
2384 DBG_ERROR("EXIT %s\n", __func__);
2386 return (STATUS_SUCCESS);
2390 * sxg_link_event - Process a link event notification from the card
2393 * adapter - A pointer to our adapter structure
2398 static void sxg_link_event(struct adapter_t *adapter)
2400 struct sxg_hw_regs *HwRegs = adapter->HwRegs;
2401 enum SXG_LINK_STATE LinkState;
2405 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "LinkEvnt",
2407 DBG_ERROR("ENTER %s\n", __func__);
2409 /* Check the Link Status register. We should have a Link Alarm. */
2410 READ_REG(HwRegs->LinkStatus, Value);
2411 if (Value & LS_LINK_ALARM) {
2412 /* We got a Link Status alarm. First, pause to let the */
2413 /* link state settle (it can bounce a number of times) */
2416 /* Now clear the alarm by reading the LASI status register. */
2417 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2418 LASI_STATUS, /* LASI status register */
2420 if (status != STATUS_SUCCESS) {
2421 DBG_ERROR("Error reading LASI Status MDIO register!\n");
2422 sxg_link_state(adapter, SXG_LINK_DOWN);
2425 ASSERT(Value & LASI_STATUS_LS_ALARM);
2427 /* Now get and set the link state */
2428 LinkState = sxg_get_link_state(adapter);
2429 sxg_link_state(adapter, LinkState);
2430 DBG_ERROR("SXG: Link Alarm occurred. Link is %s\n",
2431 ((LinkState == SXG_LINK_UP) ? "UP" : "DOWN"));
2433 /* XXXTODO - Assuming Link Attention is only being generated for the */
2434 /* Link Alarm pin (and not for a XAUI Link Status change), then it's */
2435 /* impossible to get here. Yet we've gotten here twice (under extreme */
2436 /* conditions - bouncing the link up and down many times a second). */
2437 /* Needs further investigation. */
2438 DBG_ERROR("SXG: sxg_link_event: Can't get here!\n");
2439 DBG_ERROR("SXG: Link Status == 0x%08X.\n", Value);
2442 DBG_ERROR("EXIT %s\n", __func__);
2447 * sxg_get_link_state - Determine if the link is up or down
2450 * adapter - A pointer to our adapter structure
2455 static enum SXG_LINK_STATE sxg_get_link_state(struct adapter_t *adapter)
2460 DBG_ERROR("ENTER %s\n", __func__);
2462 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "GetLink",
2465 /* Per the Xenpak spec (and the IEEE 10Gb spec?), the link is up if */
2466 /* the following 3 bits (from 3 different MDIO registers) are all true. */
2467 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2468 PHY_PMA_RCV_DET, /* PMA/PMD Receive Signal Detect register */
2470 if (status != STATUS_SUCCESS)
2473 /* If PMA/PMD receive signal detect is 0, then the link is down */
2474 if (!(Value & PMA_RCV_DETECT))
2475 return (SXG_LINK_DOWN);
2477 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PCS, /* PHY PCS module */
2478 PHY_PCS_10G_STATUS1, /* PCS 10GBASE-R Status 1 register */
2480 if (status != STATUS_SUCCESS)
2483 /* If PCS is not locked to receive blocks, then the link is down */
2484 if (!(Value & PCS_10B_BLOCK_LOCK))
2485 return (SXG_LINK_DOWN);
2487 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_XS, /* PHY XS module */
2488 PHY_XS_LANE_STATUS, /* XS Lane Status register */
2490 if (status != STATUS_SUCCESS)
2493 /* If XS transmit lanes are not aligned, then the link is down */
2494 if (!(Value & XS_LANE_ALIGN))
2495 return (SXG_LINK_DOWN);
2497 /* All 3 bits are true, so the link is up */
2498 DBG_ERROR("EXIT %s\n", __func__);
2500 return (SXG_LINK_UP);
2503 /* An error occurred reading an MDIO register. This shouldn't happen. */
2504 DBG_ERROR("Error reading an MDIO register!\n");
2506 return (SXG_LINK_DOWN);
2509 static void sxg_indicate_link_state(struct adapter_t *adapter,
2510 enum SXG_LINK_STATE LinkState)
2512 if (adapter->LinkState == SXG_LINK_UP) {
2513 DBG_ERROR("%s: LINK now UP, call netif_start_queue\n",
2515 netif_start_queue(adapter->netdev);
2517 DBG_ERROR("%s: LINK now DOWN, call netif_stop_queue\n",
2519 netif_stop_queue(adapter->netdev);
2524 * sxg_link_state - Set the link state and if necessary, indicate.
2525 * This routine the central point of processing for all link state changes.
2526 * Nothing else in the driver should alter the link state or perform
2527 * link state indications
2530 * adapter - A pointer to our adapter structure
2531 * LinkState - The link state
2536 static void sxg_link_state(struct adapter_t *adapter, enum SXG_LINK_STATE LinkState)
2538 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "LnkINDCT",
2539 adapter, LinkState, adapter->LinkState, adapter->State);
2541 DBG_ERROR("ENTER %s\n", __func__);
2543 /* Hold the adapter lock during this routine. Maybe move */
2544 /* the lock to the caller. */
2545 spin_lock(&adapter->AdapterLock);
2546 if (LinkState == adapter->LinkState) {
2547 /* Nothing changed.. */
2548 spin_unlock(&adapter->AdapterLock);
2549 DBG_ERROR("EXIT #0 %s\n", __func__);
2552 /* Save the adapter state */
2553 adapter->LinkState = LinkState;
2555 /* Drop the lock and indicate link state */
2556 spin_unlock(&adapter->AdapterLock);
2557 DBG_ERROR("EXIT #1 %s\n", __func__);
2559 sxg_indicate_link_state(adapter, LinkState);
2563 * sxg_write_mdio_reg - Write to a register on the MDIO bus
2566 * adapter - A pointer to our adapter structure
2567 * DevAddr - MDIO device number being addressed
2568 * RegAddr - register address for the specified MDIO device
2569 * Value - value to write to the MDIO register
2574 static int sxg_write_mdio_reg(struct adapter_t *adapter,
2575 u32 DevAddr, u32 RegAddr, u32 Value)
2577 struct sxg_hw_regs *HwRegs = adapter->HwRegs;
2578 u32 AddrOp; /* Address operation (written to MIIM field reg) */
2579 u32 WriteOp; /* Write operation (written to MIIM field reg) */
2580 u32 Cmd; /* Command (written to MIIM command reg) */
2584 /* DBG_ERROR("ENTER %s\n", __func__); */
2586 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
2589 /* Ensure values don't exceed field width */
2590 DevAddr &= 0x001F; /* 5-bit field */
2591 RegAddr &= 0xFFFF; /* 16-bit field */
2592 Value &= 0xFFFF; /* 16-bit field */
2594 /* Set MIIM field register bits for an MIIM address operation */
2595 AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2596 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2597 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2598 (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
2600 /* Set MIIM field register bits for an MIIM write operation */
2601 WriteOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2602 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2603 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2604 (MIIM_OP_WRITE << AXGMAC_AMIIM_FIELD_OP_SHIFT) | Value;
2606 /* Set MIIM command register bits to execute an MIIM command */
2607 Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
2609 /* Reset the command register command bit (in case it's not 0) */
2610 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2612 /* MIIM write to set the address of the specified MDIO register */
2613 WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
2615 /* Write to MIIM Command Register to execute to address operation */
2616 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2618 /* Poll AMIIM Indicator register to wait for completion */
2619 Timeout = SXG_LINK_TIMEOUT;
2621 udelay(100); /* Timeout in 100us units */
2622 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2623 if (--Timeout == 0) {
2624 return (STATUS_FAILURE);
2626 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2628 /* Reset the command register command bit */
2629 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2631 /* MIIM write to set up an MDIO write operation */
2632 WRITE_REG(HwRegs->MacAmiimField, WriteOp, TRUE);
2634 /* Write to MIIM Command Register to execute the write operation */
2635 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2637 /* Poll AMIIM Indicator register to wait for completion */
2638 Timeout = SXG_LINK_TIMEOUT;
2640 udelay(100); /* Timeout in 100us units */
2641 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2642 if (--Timeout == 0) {
2643 return (STATUS_FAILURE);
2645 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2647 /* DBG_ERROR("EXIT %s\n", __func__); */
2649 return (STATUS_SUCCESS);
2653 * sxg_read_mdio_reg - Read a register on the MDIO bus
2656 * adapter - A pointer to our adapter structure
2657 * DevAddr - MDIO device number being addressed
2658 * RegAddr - register address for the specified MDIO device
2659 * pValue - pointer to where to put data read from the MDIO register
2664 static int sxg_read_mdio_reg(struct adapter_t *adapter,
2665 u32 DevAddr, u32 RegAddr, u32 *pValue)
2667 struct sxg_hw_regs *HwRegs = adapter->HwRegs;
2668 u32 AddrOp; /* Address operation (written to MIIM field reg) */
2669 u32 ReadOp; /* Read operation (written to MIIM field reg) */
2670 u32 Cmd; /* Command (written to MIIM command reg) */
2674 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
2676 DBG_ERROR("ENTER %s\n", __FUNCTION__);
2678 /* Ensure values don't exceed field width */
2679 DevAddr &= 0x001F; /* 5-bit field */
2680 RegAddr &= 0xFFFF; /* 16-bit field */
2682 /* Set MIIM field register bits for an MIIM address operation */
2683 AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2684 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2685 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2686 (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
2688 /* Set MIIM field register bits for an MIIM read operation */
2689 ReadOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2690 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2691 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2692 (MIIM_OP_READ << AXGMAC_AMIIM_FIELD_OP_SHIFT);
2694 /* Set MIIM command register bits to execute an MIIM command */
2695 Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
2697 /* Reset the command register command bit (in case it's not 0) */
2698 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2700 /* MIIM write to set the address of the specified MDIO register */
2701 WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
2703 /* Write to MIIM Command Register to execute to address operation */
2704 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2706 /* Poll AMIIM Indicator register to wait for completion */
2707 Timeout = SXG_LINK_TIMEOUT;
2709 udelay(100); /* Timeout in 100us units */
2710 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2711 if (--Timeout == 0) {
2712 DBG_ERROR("EXIT %s with STATUS_FAILURE 1\n", __FUNCTION__);
2714 return (STATUS_FAILURE);
2716 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2718 /* Reset the command register command bit */
2719 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2721 /* MIIM write to set up an MDIO register read operation */
2722 WRITE_REG(HwRegs->MacAmiimField, ReadOp, TRUE);
2724 /* Write to MIIM Command Register to execute the read operation */
2725 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2727 /* Poll AMIIM Indicator register to wait for completion */
2728 Timeout = SXG_LINK_TIMEOUT;
2730 udelay(100); /* Timeout in 100us units */
2731 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2732 if (--Timeout == 0) {
2733 DBG_ERROR("EXIT %s with STATUS_FAILURE 2\n", __FUNCTION__);
2735 return (STATUS_FAILURE);
2737 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2739 /* Read the MDIO register data back from the field register */
2740 READ_REG(HwRegs->MacAmiimField, *pValue);
2741 *pValue &= 0xFFFF; /* data is in the lower 16 bits */
2743 DBG_ERROR("EXIT %s\n", __FUNCTION__);
2745 return (STATUS_SUCCESS);
2749 * Functions to obtain the CRC corresponding to the destination mac address.
2750 * This is a standard ethernet CRC in that it is a 32-bit, reflected CRC using
2752 * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1.
2754 * After the CRC for the 6 bytes is generated (but before the value is complemented),
2755 * we must then transpose the value and return bits 30-23.
2758 static u32 sxg_crc_table[256]; /* Table of CRC's for all possible byte values */
2761 * Contruct the CRC32 table
2763 static void sxg_mcast_init_crc32(void)
2765 u32 c; /* CRC shit reg */
2766 u32 e = 0; /* Poly X-or pattern */
2767 int i; /* counter */
2768 int k; /* byte being shifted into crc */
2770 static int p[] = { 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26 };
2772 for (i = 0; i < sizeof(p) / sizeof(int); i++) {
2773 e |= 1L << (31 - p[i]);
2776 for (i = 1; i < 256; i++) {
2778 for (k = 8; k; k--) {
2779 c = c & 1 ? (c >> 1) ^ e : c >> 1;
2781 sxg_crc_table[i] = c;
2785 static u32 sxg_crc_init; /* Is table initialized */
2787 * Return the MAC hast as described above.
2789 static unsigned char sxg_mcast_get_mac_hash(char *macaddr)
2794 unsigned char machash = 0;
2796 if (!sxg_crc_init) {
2797 sxg_mcast_init_crc32();
2801 crc = 0xFFFFFFFF; /* Preload shift register, per crc-32 spec */
2802 for (i = 0, p = macaddr; i < 6; ++p, ++i) {
2803 crc = (crc >> 8) ^ sxg_crc_table[(crc ^ *p) & 0xFF];
2806 /* Return bits 1-8, transposed */
2807 for (i = 1; i < 9; i++) {
2808 machash |= (((crc >> i) & 1) << (8 - i));
2814 static void sxg_mcast_set_mask(struct adapter_t *adapter)
2816 struct sxg_ucode_regs *sxg_regs = adapter->UcodeRegs;
2818 DBG_ERROR("%s ENTER (%s) macopts[%x] mask[%llx]\n", __func__,
2819 adapter->netdev->name, (unsigned int)adapter->MacFilter,
2820 adapter->MulticastMask);
2822 if (adapter->MacFilter & (MAC_ALLMCAST | MAC_PROMISC)) {
2823 /* Turn on all multicast addresses. We have to do this for promiscuous
2824 * mode as well as ALLMCAST mode. It saves the Microcode from having
2825 * to keep state about the MAC configuration.
2827 /* DBG_ERROR("sxg: %s macopts = MAC_ALLMCAST | MAC_PROMISC\n SLUT MODE!!!\n",__func__); */
2828 WRITE_REG(sxg_regs->McastLow, 0xFFFFFFFF, FLUSH);
2829 WRITE_REG(sxg_regs->McastHigh, 0xFFFFFFFF, FLUSH);
2830 /* DBG_ERROR("%s (%s) WRITE to slic_regs slic_mcastlow&high 0xFFFFFFFF\n",__func__, adapter->netdev->name); */
2833 /* Commit our multicast mast to the SLIC by writing to the multicast
2834 * address mask registers
2836 DBG_ERROR("%s (%s) WRITE mcastlow[%lx] mcasthigh[%lx]\n",
2837 __func__, adapter->netdev->name,
2838 ((ulong) (adapter->MulticastMask & 0xFFFFFFFF)),
2840 ((adapter->MulticastMask >> 32) & 0xFFFFFFFF)));
2842 WRITE_REG(sxg_regs->McastLow,
2843 (u32) (adapter->MulticastMask & 0xFFFFFFFF), FLUSH);
2844 WRITE_REG(sxg_regs->McastHigh,
2846 MulticastMask >> 32) & 0xFFFFFFFF), FLUSH);
2851 * Allocate a mcast_address structure to hold the multicast address.
2854 static int sxg_mcast_add_list(struct adapter_t *adapter, char *address)
2856 struct mcast_address *mcaddr, *mlist;
2859 /* Check to see if it already exists */
2860 mlist = adapter->mcastaddrs;
2862 ETHER_EQ_ADDR(mlist->address, address, equaladdr);
2864 return (STATUS_SUCCESS);
2866 mlist = mlist->next;
2869 /* Doesn't already exist. Allocate a structure to hold it */
2870 mcaddr = kmalloc(sizeof(struct mcast_address), GFP_ATOMIC);
2874 memcpy(mcaddr->address, address, 6);
2876 mcaddr->next = adapter->mcastaddrs;
2877 adapter->mcastaddrs = mcaddr;
2879 return (STATUS_SUCCESS);
2882 static void sxg_mcast_set_bit(struct adapter_t *adapter, char *address)
2884 unsigned char crcpoly;
2886 /* Get the CRC polynomial for the mac address */
2887 crcpoly = sxg_mcast_get_mac_hash(address);
2889 /* We only have space on the SLIC for 64 entries. Lop
2890 * off the top two bits. (2^6 = 64)
2894 /* OR in the new bit into our 64 bit mask. */
2895 adapter->MulticastMask |= (u64) 1 << crcpoly;
2898 static void sxg_mcast_set_list(struct net_device *dev)
2900 struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
2901 int status = STATUS_SUCCESS;
2904 if (dev->flags & IFF_PROMISC) {
2905 adapter->MacFilter |= MAC_PROMISC;
2907 //XXX handle other flags as well
2908 sxg_mcast_set_mask(adapter);
2911 static void sxg_unmap_mmio_space(struct adapter_t *adapter)
2913 #if LINUX_FREES_ADAPTER_RESOURCES
2914 /* if (adapter->Regs) { */
2915 /* iounmap(adapter->Regs); */
2917 /* adapter->slic_regs = NULL; */
2923 * SxgFreeResources - Free everything allocated in SxgAllocateResources
2926 * adapter - A pointer to our adapter structure
2931 void SxgFreeResources(struct adapter_t *adapter)
2933 u32 RssIds, IsrCount;
2934 PTCP_OBJECT TcpObject;
2936 BOOLEAN TimerCancelled;
2938 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FreeRes",
2939 adapter, adapter->MaxTcbs, 0, 0);
2941 RssIds = SXG_RSS_CPU_COUNT(adapter);
2942 IsrCount = adapter->MsiEnabled ? RssIds : 1;
2944 if (adapter->BasicAllocations == FALSE) {
2945 /* No allocations have been made, including spinlocks, */
2946 /* or listhead initializations. Return. */
2950 if (!(IsListEmpty(&adapter->AllRcvBlocks))) {
2951 SxgFreeRcvBlocks(adapter);
2953 if (!(IsListEmpty(&adapter->AllSglBuffers))) {
2954 SxgFreeSglBuffers(adapter);
2956 /* Free event queues. */
2957 if (adapter->EventRings) {
2958 pci_free_consistent(adapter->pcidev,
2959 sizeof(struct sxg_event_ring) * RssIds,
2960 adapter->EventRings, adapter->PEventRings);
2963 pci_free_consistent(adapter->pcidev,
2964 sizeof(u32) * IsrCount,
2965 adapter->Isr, adapter->PIsr);
2967 if (adapter->XmtRingZeroIndex) {
2968 pci_free_consistent(adapter->pcidev,
2970 adapter->XmtRingZeroIndex,
2971 adapter->PXmtRingZeroIndex);
2973 if (adapter->IndirectionTable) {
2974 pci_free_consistent(adapter->pcidev,
2975 SXG_MAX_RSS_TABLE_SIZE,
2976 adapter->IndirectionTable,
2977 adapter->PIndirectionTable);
2980 SXG_FREE_PACKET_POOL(adapter->PacketPoolHandle);
2981 SXG_FREE_BUFFER_POOL(adapter->BufferPoolHandle);
2983 /* Unmap register spaces */
2984 SxgUnmapResources(adapter);
2986 /* Deregister DMA */
2987 if (adapter->DmaHandle) {
2988 SXG_DEREGISTER_DMA(adapter->DmaHandle);
2990 /* Deregister interrupt */
2991 SxgDeregisterInterrupt(adapter);
2993 /* Possibly free system info (5.2 only) */
2994 SXG_RELEASE_SYSTEM_INFO(adapter);
2996 SxgDiagFreeResources(adapter);
2998 SxgFreeMCastAddrs(adapter);
3000 if (SXG_TIMER_ALLOCATED(adapter->ResetTimer)) {
3001 SXG_CANCEL_TIMER(adapter->ResetTimer, TimerCancelled);
3002 SXG_FREE_TIMER(adapter->ResetTimer);
3004 if (SXG_TIMER_ALLOCATED(adapter->RssTimer)) {
3005 SXG_CANCEL_TIMER(adapter->RssTimer, TimerCancelled);
3006 SXG_FREE_TIMER(adapter->RssTimer);
3008 if (SXG_TIMER_ALLOCATED(adapter->OffloadTimer)) {
3009 SXG_CANCEL_TIMER(adapter->OffloadTimer, TimerCancelled);
3010 SXG_FREE_TIMER(adapter->OffloadTimer);
3013 adapter->BasicAllocations = FALSE;
3015 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFreeRes",
3016 adapter, adapter->MaxTcbs, 0, 0);
3021 * sxg_allocate_complete -
3023 * This routine is called when a memory allocation has completed.
3026 * struct adapter_t * - Our adapter structure
3027 * VirtualAddress - Memory virtual address
3028 * PhysicalAddress - Memory physical address
3029 * Length - Length of memory allocated (or 0)
3030 * Context - The type of buffer allocated
3035 static void sxg_allocate_complete(struct adapter_t *adapter,
3036 void *VirtualAddress,
3037 dma_addr_t PhysicalAddress,
3038 u32 Length, enum sxg_buffer_type Context)
3040 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocCmp",
3041 adapter, VirtualAddress, Length, Context);
3042 ASSERT(adapter->AllocationsPending);
3043 --adapter->AllocationsPending;
3047 case SXG_BUFFER_TYPE_RCV:
3048 sxg_allocate_rcvblock_complete(adapter,
3050 PhysicalAddress, Length);
3052 case SXG_BUFFER_TYPE_SGL:
3053 sxg_allocate_sgl_buffer_complete(adapter, (struct sxg_scatter_gather *)
3055 PhysicalAddress, Length);
3058 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocCmp",
3059 adapter, VirtualAddress, Length, Context);
3063 * sxg_allocate_buffer_memory - Shared memory allocation routine used for
3064 * synchronous and asynchronous buffer allocations
3067 * adapter - A pointer to our adapter structure
3068 * Size - block size to allocate
3069 * BufferType - Type of buffer to allocate
3074 static int sxg_allocate_buffer_memory(struct adapter_t *adapter,
3075 u32 Size, enum sxg_buffer_type BufferType)
3081 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocMem",
3082 adapter, Size, BufferType, 0);
3083 /* Grab the adapter lock and check the state. */
3084 /* If we're in anything other than INITIALIZING or */
3085 /* RUNNING state, fail. This is to prevent */
3086 /* allocations in an improper driver state */
3087 spin_lock(&adapter->AdapterLock);
3089 /* Increment the AllocationsPending count while holding */
3090 /* the lock. Pause processing relies on this */
3091 ++adapter->AllocationsPending;
3092 spin_unlock(&adapter->AdapterLock);
3094 /* At initialization time allocate resources synchronously. */
3095 Buffer = pci_alloc_consistent(adapter->pcidev, Size, &pBuffer);
3096 if (Buffer == NULL) {
3097 spin_lock(&adapter->AdapterLock);
3098 /* Decrement the AllocationsPending count while holding */
3099 /* the lock. Pause processing relies on this */
3100 --adapter->AllocationsPending;
3101 spin_unlock(&adapter->AdapterLock);
3102 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlcMemF1",
3103 adapter, Size, BufferType, 0);
3104 return (STATUS_RESOURCES);
3106 sxg_allocate_complete(adapter, Buffer, pBuffer, Size, BufferType);
3107 status = STATUS_SUCCESS;
3109 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocMem",
3110 adapter, Size, BufferType, status);
3115 * sxg_allocate_rcvblock_complete - Complete a receive descriptor block allocation
3118 * adapter - A pointer to our adapter structure
3119 * RcvBlock - receive block virtual address
3120 * PhysicalAddress - Physical address
3121 * Length - Memory length
3126 static void sxg_allocate_rcvblock_complete(struct adapter_t *adapter,
3128 dma_addr_t PhysicalAddress,
3132 u32 BufferSize = adapter->ReceiveBufferSize;
3134 struct sxg_rcv_block_hdr *RcvBlockHdr;
3135 unsigned char *RcvDataBuffer;
3136 struct sxg_rcv_data_buffer_hdr *RcvDataBufferHdr;
3137 struct sxg_rcv_descriptor_block *RcvDescriptorBlock;
3138 struct sxg_rcv_descriptor_block_hdr *RcvDescriptorBlockHdr;
3140 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlRcvBlk",
3141 adapter, RcvBlock, Length, 0);
3142 if (RcvBlock == NULL) {
3145 memset(RcvBlock, 0, Length);
3146 ASSERT((BufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
3147 (BufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
3148 ASSERT(Length == SXG_RCV_BLOCK_SIZE(BufferSize));
3149 /* First, initialize the contained pool of receive data */
3150 /* buffers. This initialization requires NBL/NB/MDL allocations, */
3151 /* If any of them fail, free the block and return without */
3152 /* queueing the shared memory */
3153 RcvDataBuffer = RcvBlock;
3155 for (i = 0, Paddr = *PhysicalAddress;
3156 i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3157 i++, Paddr.LowPart += BufferSize, RcvDataBuffer += BufferSize)
3159 for (i = 0, Paddr = PhysicalAddress;
3160 i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3161 i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) {
3164 (struct sxg_rcv_data_buffer_hdr*) (RcvDataBuffer +
3165 SXG_RCV_DATA_BUFFER_HDR_OFFSET
3167 RcvDataBufferHdr->VirtualAddress = RcvDataBuffer;
3168 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM; /* For FREE macro assertion */
3169 RcvDataBufferHdr->Size =
3170 SXG_RCV_BUFFER_DATA_SIZE(BufferSize);
3172 SXG_ALLOCATE_RCV_PACKET(adapter, RcvDataBufferHdr);
3173 //ASK hardcoded 2048
3174 RcvDataBufferHdr->PhysicalAddress = pci_map_single(adapter->pcidev,
3175 RcvDataBufferHdr->SxgDumbRcvPacket->data,
3177 PCI_DMA_FROMDEVICE);
3178 if (RcvDataBufferHdr->SxgDumbRcvPacket == NULL)
3183 /* Place this entire block of memory on the AllRcvBlocks queue so it can be */
3186 (struct sxg_rcv_block_hdr*) ((unsigned char *)RcvBlock +
3187 SXG_RCV_BLOCK_HDR_OFFSET(BufferSize));
3188 RcvBlockHdr->VirtualAddress = RcvBlock;
3189 RcvBlockHdr->PhysicalAddress = PhysicalAddress;
3190 spin_lock(&adapter->RcvQLock);
3191 adapter->AllRcvBlockCount++;
3192 InsertTailList(&adapter->AllRcvBlocks, &RcvBlockHdr->AllList);
3193 spin_unlock(&adapter->RcvQLock);
3195 /* Now free the contained receive data buffers that we initialized above */
3196 RcvDataBuffer = RcvBlock;
3197 for (i = 0, Paddr = PhysicalAddress;
3198 i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3199 i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) {
3200 RcvDataBufferHdr = (struct sxg_rcv_data_buffer_hdr*) (RcvDataBuffer +
3201 SXG_RCV_DATA_BUFFER_HDR_OFFSET
3203 spin_lock(&adapter->RcvQLock);
3204 SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
3205 spin_unlock(&adapter->RcvQLock);
3208 /* Locate the descriptor block and put it on a separate free queue */
3209 RcvDescriptorBlock =
3210 (struct sxg_rcv_descriptor_block *) ((unsigned char *)RcvBlock +
3211 SXG_RCV_DESCRIPTOR_BLOCK_OFFSET
3213 RcvDescriptorBlockHdr =
3214 (struct sxg_rcv_descriptor_block_hdr *) ((unsigned char *)RcvBlock +
3215 SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET
3217 RcvDescriptorBlockHdr->VirtualAddress = RcvDescriptorBlock;
3218 RcvDescriptorBlockHdr->PhysicalAddress = Paddr;
3219 spin_lock(&adapter->RcvQLock);
3220 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, RcvDescriptorBlockHdr);
3221 spin_unlock(&adapter->RcvQLock);
3222 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlRBlk",
3223 adapter, RcvBlock, Length, 0);
3226 /* Free any allocated resources */
3228 RcvDataBuffer = RcvBlock;
3229 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3230 i++, RcvDataBuffer += BufferSize) {
3232 (struct sxg_rcv_data_buffer_hdr *) (RcvDataBuffer +
3233 SXG_RCV_DATA_BUFFER_HDR_OFFSET
3235 SXG_FREE_RCV_PACKET(RcvDataBufferHdr);
3237 pci_free_consistent(adapter->pcidev,
3238 Length, RcvBlock, PhysicalAddress);
3240 DBG_ERROR("%s: OUT OF RESOURCES\n", __func__);
3241 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "RcvAFail",
3242 adapter, adapter->FreeRcvBufferCount,
3243 adapter->FreeRcvBlockCount, adapter->AllRcvBlockCount);
3244 adapter->Stats.NoMem++;
3248 * sxg_allocate_sgl_buffer_complete - Complete a SGL buffer allocation
3251 * adapter - A pointer to our adapter structure
3252 * SxgSgl - struct sxg_scatter_gather buffer
3253 * PhysicalAddress - Physical address
3254 * Length - Memory length
3259 static void sxg_allocate_sgl_buffer_complete(struct adapter_t *adapter,
3260 struct sxg_scatter_gather *SxgSgl,
3261 dma_addr_t PhysicalAddress,
3264 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlSglCmp",
3265 adapter, SxgSgl, Length, 0);
3266 spin_lock(&adapter->SglQLock);
3267 adapter->AllSglBufferCount++;
3268 memset(SxgSgl, 0, sizeof(struct sxg_scatter_gather));
3269 SxgSgl->PhysicalAddress = PhysicalAddress; /* *PhysicalAddress; */
3270 SxgSgl->adapter = adapter; /* Initialize backpointer once */
3271 InsertTailList(&adapter->AllSglBuffers, &SxgSgl->AllList);
3272 spin_unlock(&adapter->SglQLock);
3273 SxgSgl->State = SXG_BUFFER_BUSY;
3274 SXG_FREE_SGL_BUFFER(adapter, SxgSgl, NULL);
3275 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlSgl",
3276 adapter, SxgSgl, Length, 0);
3280 static void sxg_adapter_set_hwaddr(struct adapter_t *adapter)
3282 /* DBG_ERROR ("%s ENTER card->config_set[%x] port[%d] physport[%d] funct#[%d]\n", __func__, */
3283 /* card->config_set, adapter->port, adapter->physport, adapter->functionnumber); */
3285 /* sxg_dbg_macaddrs(adapter); */
3287 memcpy(adapter->macaddr, temp_mac_address, sizeof(struct sxg_config_mac));
3288 /* DBG_ERROR ("%s AFTER copying from config.macinfo into currmacaddr\n", __func__); */
3289 /* sxg_dbg_macaddrs(adapter); */
3290 if (!(adapter->currmacaddr[0] ||
3291 adapter->currmacaddr[1] ||
3292 adapter->currmacaddr[2] ||
3293 adapter->currmacaddr[3] ||
3294 adapter->currmacaddr[4] || adapter->currmacaddr[5])) {
3295 memcpy(adapter->currmacaddr, adapter->macaddr, 6);
3297 if (adapter->netdev) {
3298 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6);
3299 memcpy(adapter->netdev->perm_addr, adapter->currmacaddr, 6);
3301 /* DBG_ERROR ("%s EXIT port %d\n", __func__, adapter->port); */
3302 sxg_dbg_macaddrs(adapter);
3307 static int sxg_mac_set_address(struct net_device *dev, void *ptr)
3309 struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
3310 struct sockaddr *addr = ptr;
3312 DBG_ERROR("%s ENTER (%s)\n", __func__, adapter->netdev->name);
3314 if (netif_running(dev)) {
3320 DBG_ERROR("sxg: %s (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
3321 __func__, adapter->netdev->name, adapter->currmacaddr[0],
3322 adapter->currmacaddr[1], adapter->currmacaddr[2],
3323 adapter->currmacaddr[3], adapter->currmacaddr[4],
3324 adapter->currmacaddr[5]);
3325 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3326 memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
3327 DBG_ERROR("sxg: %s (%s) new %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
3328 __func__, adapter->netdev->name, adapter->currmacaddr[0],
3329 adapter->currmacaddr[1], adapter->currmacaddr[2],
3330 adapter->currmacaddr[3], adapter->currmacaddr[4],
3331 adapter->currmacaddr[5]);
3333 sxg_config_set(adapter, TRUE);
3338 /*****************************************************************************/
3339 /************* SXG DRIVER FUNCTIONS (below) ********************************/
3340 /*****************************************************************************/
3343 * sxg_initialize_adapter - Initialize adapter
3346 * adapter - A pointer to our adapter structure
3351 static int sxg_initialize_adapter(struct adapter_t *adapter)
3353 u32 RssIds, IsrCount;
3357 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitAdpt",
3360 RssIds = 1; /* XXXTODO SXG_RSS_CPU_COUNT(adapter); */
3361 IsrCount = adapter->MsiEnabled ? RssIds : 1;
3363 /* Sanity check SXG_UCODE_REGS structure definition to */
3364 /* make sure the length is correct */
3365 ASSERT(sizeof(struct sxg_ucode_regs) == SXG_REGISTER_SIZE_PER_CPU);
3367 /* Disable interrupts */
3368 SXG_DISABLE_ALL_INTERRUPTS(adapter);
3371 ASSERT((adapter->FrameSize == ETHERMAXFRAME) ||
3372 (adapter->FrameSize == JUMBOMAXFRAME));
3373 WRITE_REG(adapter->UcodeRegs[0].LinkMtu, adapter->FrameSize, TRUE);
3375 /* Set event ring base address and size */
3376 WRITE_REG64(adapter,
3377 adapter->UcodeRegs[0].EventBase, adapter->PEventRings, 0);
3378 WRITE_REG(adapter->UcodeRegs[0].EventSize, EVENT_RING_SIZE, TRUE);
3380 /* Per-ISR initialization */
3381 for (i = 0; i < IsrCount; i++) {
3383 /* Set interrupt status pointer */
3384 Addr = adapter->PIsr + (i * sizeof(u32));
3385 WRITE_REG64(adapter, adapter->UcodeRegs[i].Isp, Addr, i);
3388 /* XMT ring zero index */
3389 WRITE_REG64(adapter,
3390 adapter->UcodeRegs[0].SPSendIndex,
3391 adapter->PXmtRingZeroIndex, 0);
3393 /* Per-RSS initialization */
3394 for (i = 0; i < RssIds; i++) {
3395 /* Release all event ring entries to the Microcode */
3396 WRITE_REG(adapter->UcodeRegs[i].EventRelease, EVENT_RING_SIZE,
3400 /* Transmit ring base and size */
3401 WRITE_REG64(adapter,
3402 adapter->UcodeRegs[0].XmtBase, adapter->PXmtRings, 0);
3403 WRITE_REG(adapter->UcodeRegs[0].XmtSize, SXG_XMT_RING_SIZE, TRUE);
3405 /* Receive ring base and size */
3406 WRITE_REG64(adapter,
3407 adapter->UcodeRegs[0].RcvBase, adapter->PRcvRings, 0);
3408 WRITE_REG(adapter->UcodeRegs[0].RcvSize, SXG_RCV_RING_SIZE, TRUE);
3410 /* Populate the card with receive buffers */
3411 sxg_stock_rcv_buffers(adapter);
3413 /* Initialize checksum offload capabilities. At the moment */
3414 /* we always enable IP and TCP receive checksums on the card. */
3415 /* Depending on the checksum configuration specified by the */
3416 /* user, we can choose to report or ignore the checksum */
3417 /* information provided by the card. */
3418 WRITE_REG(adapter->UcodeRegs[0].ReceiveChecksum,
3419 SXG_RCV_TCP_CSUM_ENABLED | SXG_RCV_IP_CSUM_ENABLED, TRUE);
3421 /* Initialize the MAC, XAUI */
3422 DBG_ERROR("sxg: %s ENTER sxg_initialize_link\n", __func__);
3423 status = sxg_initialize_link(adapter);
3424 DBG_ERROR("sxg: %s EXIT sxg_initialize_link status[%x]\n", __func__,
3426 if (status != STATUS_SUCCESS) {
3429 /* Initialize Dead to FALSE. */
3430 /* SlicCheckForHang or SlicDumpThread will take it from here. */
3431 adapter->Dead = FALSE;
3432 adapter->PingOutstanding = FALSE;
3433 adapter->State = SXG_STATE_RUNNING;
3435 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInit",
3437 return (STATUS_SUCCESS);
3441 * sxg_fill_descriptor_block - Populate a descriptor block and give it to
3442 * the card. The caller should hold the RcvQLock
3445 * adapter - A pointer to our adapter structure
3446 * RcvDescriptorBlockHdr - Descriptor block to fill
3451 static int sxg_fill_descriptor_block(struct adapter_t *adapter,
3452 struct sxg_rcv_descriptor_block_hdr
3453 *RcvDescriptorBlockHdr)
3456 struct sxg_ring_info *RcvRingInfo = &adapter->RcvRingZeroInfo;
3457 struct sxg_rcv_data_buffer_hdr *RcvDataBufferHdr;
3458 struct sxg_rcv_descriptor_block *RcvDescriptorBlock;
3459 struct sxg_cmd *RingDescriptorCmd;
3460 struct sxg_rcv_ring *RingZero = &adapter->RcvRings[0];
3462 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FilBlk",
3463 adapter, adapter->RcvBuffersOnCard,
3464 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3466 ASSERT(RcvDescriptorBlockHdr);
3468 /* If we don't have the resources to fill the descriptor block, */
3469 /* return failure */
3470 if ((adapter->FreeRcvBufferCount < SXG_RCV_DESCRIPTORS_PER_BLOCK) ||
3471 SXG_RING_FULL(RcvRingInfo)) {
3472 adapter->Stats.NoMem++;
3473 return (STATUS_FAILURE);
3475 /* Get a ring descriptor command */
3476 SXG_GET_CMD(RingZero,
3477 RcvRingInfo, RingDescriptorCmd, RcvDescriptorBlockHdr);
3478 ASSERT(RingDescriptorCmd);
3479 RcvDescriptorBlockHdr->State = SXG_BUFFER_ONCARD;
3480 RcvDescriptorBlock =
3481 (struct sxg_rcv_descriptor_block *) RcvDescriptorBlockHdr->VirtualAddress;
3483 /* Fill in the descriptor block */
3484 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; i++) {
3485 SXG_GET_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
3486 ASSERT(RcvDataBufferHdr);
3487 ASSERT(RcvDataBufferHdr->SxgDumbRcvPacket);
3488 SXG_REINIATIALIZE_PACKET(RcvDataBufferHdr->SxgDumbRcvPacket);
3489 RcvDataBufferHdr->State = SXG_BUFFER_ONCARD;
3490 RcvDescriptorBlock->Descriptors[i].VirtualAddress =
3491 (void *)RcvDataBufferHdr;
3493 printk("ASK:sxg_fill_descriptor_block: first virt address %p\n", RcvDataBufferHdr);
3494 if (i == (SXG_RCV_DESCRIPTORS_PER_BLOCK - 1))
3495 printk("ASK:sxg_fill_descriptor_block: last virt address %p\n", RcvDataBufferHdr);
3497 RcvDescriptorBlock->Descriptors[i].PhysicalAddress =
3498 RcvDataBufferHdr->PhysicalAddress;
3500 /* Add the descriptor block to receive descriptor ring 0 */
3501 RingDescriptorCmd->Sgl = RcvDescriptorBlockHdr->PhysicalAddress;
3503 /* RcvBuffersOnCard is not protected via the receive lock (see */
3504 /* sxg_process_event_queue) We don't want to grap a lock every time a */
3505 /* buffer is returned to us, so we use atomic interlocked functions */
3507 adapter->RcvBuffersOnCard += SXG_RCV_DESCRIPTORS_PER_BLOCK;
3509 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DscBlk",
3510 RcvDescriptorBlockHdr,
3511 RingDescriptorCmd, RcvRingInfo->Head, RcvRingInfo->Tail);
3513 WRITE_REG(adapter->UcodeRegs[0].RcvCmd, 1, true);
3514 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlk",
3515 adapter, adapter->RcvBuffersOnCard,
3516 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3517 return (STATUS_SUCCESS);
3521 * sxg_stock_rcv_buffers - Stock the card with receive buffers
3524 * adapter - A pointer to our adapter structure
3529 static void sxg_stock_rcv_buffers(struct adapter_t *adapter)
3531 struct sxg_rcv_descriptor_block_hdr *RcvDescriptorBlockHdr;
3533 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "StockBuf",
3534 adapter, adapter->RcvBuffersOnCard,
3535 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3536 /* First, see if we've got less than our minimum threshold of */
3537 /* receive buffers, there isn't an allocation in progress, and */
3538 /* we haven't exceeded our maximum.. get another block of buffers */
3539 /* None of this needs to be SMP safe. It's round numbers. */
3540 if ((adapter->FreeRcvBufferCount < SXG_MIN_RCV_DATA_BUFFERS) &&
3541 (adapter->AllRcvBlockCount < SXG_MAX_RCV_BLOCKS) &&
3542 (adapter->AllocationsPending == 0)) {
3543 sxg_allocate_buffer_memory(adapter,
3544 SXG_RCV_BLOCK_SIZE(adapter->
3546 SXG_BUFFER_TYPE_RCV);
3548 printk("ASK:sxg_stock_rcv_buffers: RcvBuffersOnCard %d\n", adapter->RcvBuffersOnCard);
3549 /* Now grab the RcvQLock lock and proceed */
3550 spin_lock(&adapter->RcvQLock);
3551 while (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
3552 struct list_entry *_ple;
3554 /* Get a descriptor block */
3555 RcvDescriptorBlockHdr = NULL;
3556 if (adapter->FreeRcvBlockCount) {
3557 _ple = RemoveHeadList(&adapter->FreeRcvBlocks);
3558 RcvDescriptorBlockHdr =
3559 container_of(_ple, struct sxg_rcv_descriptor_block_hdr,
3561 adapter->FreeRcvBlockCount--;
3562 RcvDescriptorBlockHdr->State = SXG_BUFFER_BUSY;
3565 if (RcvDescriptorBlockHdr == NULL) {
3567 adapter->Stats.NoMem++;
3570 /* Fill in the descriptor block and give it to the card */
3571 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
3573 /* Free the descriptor block */
3574 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
3575 RcvDescriptorBlockHdr);
3579 spin_unlock(&adapter->RcvQLock);
3580 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlks",
3581 adapter, adapter->RcvBuffersOnCard,
3582 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3586 * sxg_complete_descriptor_blocks - Return descriptor blocks that have been
3587 * completed by the microcode
3590 * adapter - A pointer to our adapter structure
3591 * Index - Where the microcode is up to
3596 static void sxg_complete_descriptor_blocks(struct adapter_t *adapter,
3597 unsigned char Index)
3599 struct sxg_rcv_ring *RingZero = &adapter->RcvRings[0];
3600 struct sxg_ring_info *RcvRingInfo = &adapter->RcvRingZeroInfo;
3601 struct sxg_rcv_descriptor_block_hdr *RcvDescriptorBlockHdr;
3602 struct sxg_cmd *RingDescriptorCmd;
3604 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlks",
3605 adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
3607 /* Now grab the RcvQLock lock and proceed */
3608 spin_lock(&adapter->RcvQLock);
3609 ASSERT(Index != RcvRingInfo->Tail);
3610 while (RcvRingInfo->Tail != Index) {
3612 /* Locate the current Cmd (ring descriptor entry), and */
3613 /* associated receive descriptor block, and advance */
3616 SXG_RETURN_CMD(RingZero,
3618 RingDescriptorCmd, RcvDescriptorBlockHdr);
3619 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlk",
3620 RcvRingInfo->Head, RcvRingInfo->Tail,
3621 RingDescriptorCmd, RcvDescriptorBlockHdr);
3623 /* Clear the SGL field */
3624 RingDescriptorCmd->Sgl = 0;
3625 /* Attempt to refill it and hand it right back to the */
3626 /* card. If we fail to refill it, free the descriptor block */
3627 /* header. The card will be restocked later via the */
3628 /* RcvBuffersOnCard test */
3629 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
3631 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
3632 RcvDescriptorBlockHdr);
3635 spin_unlock(&adapter->RcvQLock);
3636 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XCRBlks",
3637 adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
3640 static struct pci_driver sxg_driver = {
3642 .id_table = sxg_pci_tbl,
3643 .probe = sxg_entry_probe,
3644 .remove = sxg_entry_remove,
3645 #if SXG_POWER_MANAGEMENT_ENABLED
3646 .suspend = sxgpm_suspend,
3647 .resume = sxgpm_resume,
3649 /* .shutdown = slic_shutdown, MOOK_INVESTIGATE */
3652 static int __init sxg_module_init(void)
3659 return pci_register_driver(&sxg_driver);
3662 static void __exit sxg_module_cleanup(void)
3664 pci_unregister_driver(&sxg_driver);
3667 module_init(sxg_module_init);
3668 module_exit(sxg_module_cleanup);