drivers/staging/sep/sep_driver_hw_defs.h

   1 /*
   2  *
   3  *  sep_driver_hw_defs.h - Security Processor Driver hardware definitions
   4  *
   5  *  Copyright(c) 2009,2010 Intel Corporation. All rights reserved.
   6  *  Contributions(c) 2009,2010 Discretix. All rights reserved.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the Free
  10  *  Software Foundation; version 2 of the License.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along with
  18  *  this program; if not, write to the Free Software Foundation, Inc., 59
  19  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  20  *
  21  *  CONTACTS:
  22  *
  23  *  Mark Allyn          mark.a.allyn@intel.com
  24  *  Jayant Mangalampalli jayant.mangalampalli@intel.com
  25  *
  26  *  CHANGES:
  27  *
  28  *  2010.09.20  Upgrade to Medfield
  29  *
  30  */
  31
  32 #ifndef SEP_DRIVER_HW_DEFS__H
  33 #define SEP_DRIVER_HW_DEFS__H
  34
  35 /* PCI ID's */
  36 #define MFLD_PCI_DEVICE_ID 0x0826
  37
  38 /*----------------------- */
  39 /* HW Registers Defines.  */
  40 /*                        */
  41 /*---------------------- -*/
  42
  43
  44 /* cf registers */
  45 #define         HW_R0B_ADDR_0_REG_ADDR                  0x0000UL
  46 #define         HW_R0B_ADDR_1_REG_ADDR                  0x0004UL
  47 #define         HW_R0B_ADDR_2_REG_ADDR                  0x0008UL
  48 #define         HW_R0B_ADDR_3_REG_ADDR                  0x000cUL
  49 #define         HW_R0B_ADDR_4_REG_ADDR                  0x0010UL
  50 #define         HW_R0B_ADDR_5_REG_ADDR                  0x0014UL
  51 #define         HW_R0B_ADDR_6_REG_ADDR                  0x0018UL
  52 #define         HW_R0B_ADDR_7_REG_ADDR                  0x001cUL
  53 #define         HW_R0B_ADDR_8_REG_ADDR                  0x0020UL
  54 #define         HW_R2B_ADDR_0_REG_ADDR                  0x0080UL
  55 #define         HW_R2B_ADDR_1_REG_ADDR                  0x0084UL
  56 #define         HW_R2B_ADDR_2_REG_ADDR                  0x0088UL
  57 #define         HW_R2B_ADDR_3_REG_ADDR                  0x008cUL
  58 #define         HW_R2B_ADDR_4_REG_ADDR                  0x0090UL
  59 #define         HW_R2B_ADDR_5_REG_ADDR                  0x0094UL
  60 #define         HW_R2B_ADDR_6_REG_ADDR                  0x0098UL
  61 #define         HW_R2B_ADDR_7_REG_ADDR                  0x009cUL
  62 #define         HW_R2B_ADDR_8_REG_ADDR                  0x00a0UL
  63 #define         HW_R3B_REG_ADDR                         0x00C0UL
  64 #define         HW_R4B_REG_ADDR                         0x0100UL
  65 #define         HW_CSA_ADDR_0_REG_ADDR                  0x0140UL
  66 #define         HW_CSA_ADDR_1_REG_ADDR                  0x0144UL
  67 #define         HW_CSA_ADDR_2_REG_ADDR                  0x0148UL
  68 #define         HW_CSA_ADDR_3_REG_ADDR                  0x014cUL
  69 #define         HW_CSA_ADDR_4_REG_ADDR                  0x0150UL
  70 #define         HW_CSA_ADDR_5_REG_ADDR                  0x0154UL
  71 #define         HW_CSA_ADDR_6_REG_ADDR                  0x0158UL
  72 #define         HW_CSA_ADDR_7_REG_ADDR                  0x015cUL
  73 #define         HW_CSA_ADDR_8_REG_ADDR                  0x0160UL
  74 #define         HW_CSA_REG_ADDR                         0x0140UL
  75 #define         HW_SINB_REG_ADDR                        0x0180UL
  76 #define         HW_SOUTB_REG_ADDR                       0x0184UL
  77 #define         HW_PKI_CONTROL_REG_ADDR                 0x01C0UL
  78 #define         HW_PKI_STATUS_REG_ADDR                  0x01C4UL
  79 #define         HW_PKI_BUSY_REG_ADDR                    0x01C8UL
  80 #define         HW_PKI_A_1025_REG_ADDR                  0x01CCUL
  81 #define         HW_PKI_SDMA_CTL_REG_ADDR                0x01D0UL
  82 #define         HW_PKI_SDMA_OFFSET_REG_ADDR             0x01D4UL
  83 #define         HW_PKI_SDMA_POINTERS_REG_ADDR           0x01D8UL
  84 #define         HW_PKI_SDMA_DLENG_REG_ADDR              0x01DCUL
  85 #define         HW_PKI_SDMA_EXP_POINTERS_REG_ADDR       0x01E0UL
  86 #define         HW_PKI_SDMA_RES_POINTERS_REG_ADDR       0x01E4UL
  87 #define         HW_PKI_CLR_REG_ADDR                     0x01E8UL
  88 #define         HW_PKI_SDMA_BUSY_REG_ADDR               0x01E8UL
  89 #define         HW_PKI_SDMA_FIRST_EXP_N_REG_ADDR        0x01ECUL
  90 #define         HW_PKI_SDMA_MUL_BY1_REG_ADDR            0x01F0UL
  91 #define         HW_PKI_SDMA_RMUL_SEL_REG_ADDR           0x01F4UL
  92 #define         HW_DES_KEY_0_REG_ADDR                   0x0208UL
  93 #define         HW_DES_KEY_1_REG_ADDR                   0x020CUL
  94 #define         HW_DES_KEY_2_REG_ADDR                   0x0210UL
  95 #define         HW_DES_KEY_3_REG_ADDR                   0x0214UL
  96 #define         HW_DES_KEY_4_REG_ADDR                   0x0218UL
  97 #define         HW_DES_KEY_5_REG_ADDR                   0x021CUL
  98 #define         HW_DES_CONTROL_0_REG_ADDR               0x0220UL
  99 #define         HW_DES_CONTROL_1_REG_ADDR               0x0224UL
 100 #define         HW_DES_IV_0_REG_ADDR                    0x0228UL
 101 #define         HW_DES_IV_1_REG_ADDR                    0x022CUL
 102 #define         HW_AES_KEY_0_ADDR_0_REG_ADDR            0x0400UL
 103 #define         HW_AES_KEY_0_ADDR_1_REG_ADDR            0x0404UL
 104 #define         HW_AES_KEY_0_ADDR_2_REG_ADDR            0x0408UL
 105 #define         HW_AES_KEY_0_ADDR_3_REG_ADDR            0x040cUL
 106 #define         HW_AES_KEY_0_ADDR_4_REG_ADDR            0x0410UL
 107 #define         HW_AES_KEY_0_ADDR_5_REG_ADDR            0x0414UL
 108 #define         HW_AES_KEY_0_ADDR_6_REG_ADDR            0x0418UL
 109 #define         HW_AES_KEY_0_ADDR_7_REG_ADDR            0x041cUL
 110 #define         HW_AES_KEY_0_REG_ADDR                   0x0400UL
 111 #define         HW_AES_IV_0_ADDR_0_REG_ADDR             0x0440UL
 112 #define         HW_AES_IV_0_ADDR_1_REG_ADDR             0x0444UL
 113 #define         HW_AES_IV_0_ADDR_2_REG_ADDR             0x0448UL
 114 #define         HW_AES_IV_0_ADDR_3_REG_ADDR             0x044cUL
 115 #define         HW_AES_IV_0_REG_ADDR                    0x0440UL
 116 #define         HW_AES_CTR1_ADDR_0_REG_ADDR             0x0460UL
 117 #define         HW_AES_CTR1_ADDR_1_REG_ADDR             0x0464UL
 118 #define         HW_AES_CTR1_ADDR_2_REG_ADDR             0x0468UL
 119 #define         HW_AES_CTR1_ADDR_3_REG_ADDR             0x046cUL
 120 #define         HW_AES_CTR1_REG_ADDR                    0x0460UL
 121 #define         HW_AES_SK_REG_ADDR                      0x0478UL
 122 #define         HW_AES_MAC_OK_REG_ADDR                  0x0480UL
 123 #define         HW_AES_PREV_IV_0_ADDR_0_REG_ADDR        0x0490UL
 124 #define         HW_AES_PREV_IV_0_ADDR_1_REG_ADDR        0x0494UL
 125 #define         HW_AES_PREV_IV_0_ADDR_2_REG_ADDR        0x0498UL
 126 #define         HW_AES_PREV_IV_0_ADDR_3_REG_ADDR        0x049cUL
 127 #define         HW_AES_PREV_IV_0_REG_ADDR               0x0490UL
 128 #define         HW_AES_CONTROL_REG_ADDR                 0x04C0UL
 129 #define         HW_HASH_H0_REG_ADDR                     0x0640UL
 130 #define         HW_HASH_H1_REG_ADDR                     0x0644UL
 131 #define         HW_HASH_H2_REG_ADDR                     0x0648UL
 132 #define         HW_HASH_H3_REG_ADDR                     0x064CUL
 133 #define         HW_HASH_H4_REG_ADDR                     0x0650UL
 134 #define         HW_HASH_H5_REG_ADDR                     0x0654UL
 135 #define         HW_HASH_H6_REG_ADDR                     0x0658UL
 136 #define         HW_HASH_H7_REG_ADDR                     0x065CUL
 137 #define         HW_HASH_H8_REG_ADDR                     0x0660UL
 138 #define         HW_HASH_H9_REG_ADDR                     0x0664UL
 139 #define         HW_HASH_H10_REG_ADDR                    0x0668UL
 140 #define         HW_HASH_H11_REG_ADDR                    0x066CUL
 141 #define         HW_HASH_H12_REG_ADDR                    0x0670UL
 142 #define         HW_HASH_H13_REG_ADDR                    0x0674UL
 143 #define         HW_HASH_H14_REG_ADDR                    0x0678UL
 144 #define         HW_HASH_H15_REG_ADDR                    0x067CUL
 145 #define         HW_HASH_CONTROL_REG_ADDR                0x07C0UL
 146 #define         HW_HASH_PAD_EN_REG_ADDR                 0x07C4UL
 147 #define         HW_HASH_PAD_CFG_REG_ADDR                0x07C8UL
 148 #define         HW_HASH_CUR_LEN_0_REG_ADDR              0x07CCUL
 149 #define         HW_HASH_CUR_LEN_1_REG_ADDR              0x07D0UL
 150 #define         HW_HASH_CUR_LEN_2_REG_ADDR              0x07D4UL
 151 #define         HW_HASH_CUR_LEN_3_REG_ADDR              0x07D8UL
 152 #define         HW_HASH_PARAM_REG_ADDR                  0x07DCUL
 153 #define         HW_HASH_INT_BUSY_REG_ADDR               0x07E0UL
 154 #define         HW_HASH_SW_RESET_REG_ADDR               0x07E4UL
 155 #define         HW_HASH_ENDIANESS_REG_ADDR              0x07E8UL
 156 #define         HW_HASH_DATA_REG_ADDR                   0x07ECUL
 157 #define         HW_DRNG_CONTROL_REG_ADDR                0x0800UL
 158 #define         HW_DRNG_VALID_REG_ADDR                  0x0804UL
 159 #define         HW_DRNG_DATA_REG_ADDR                   0x0808UL
 160 #define         HW_RND_SRC_EN_REG_ADDR                  0x080CUL
 161 #define         HW_AES_CLK_ENABLE_REG_ADDR              0x0810UL
 162 #define         HW_DES_CLK_ENABLE_REG_ADDR              0x0814UL
 163 #define         HW_HASH_CLK_ENABLE_REG_ADDR             0x0818UL
 164 #define         HW_PKI_CLK_ENABLE_REG_ADDR              0x081CUL
 165 #define         HW_CLK_STATUS_REG_ADDR                  0x0824UL
 166 #define         HW_CLK_ENABLE_REG_ADDR                  0x0828UL
 167 #define         HW_DRNG_SAMPLE_REG_ADDR                 0x0850UL
 168 #define         HW_RND_SRC_CTL_REG_ADDR                 0x0858UL
 169 #define         HW_CRYPTO_CTL_REG_ADDR                  0x0900UL
 170 #define         HW_CRYPTO_STATUS_REG_ADDR               0x090CUL
 171 #define         HW_CRYPTO_BUSY_REG_ADDR                 0x0910UL
 172 #define         HW_AES_BUSY_REG_ADDR                    0x0914UL
 173 #define         HW_DES_BUSY_REG_ADDR                    0x0918UL
 174 #define         HW_HASH_BUSY_REG_ADDR                   0x091CUL
 175 #define         HW_CONTENT_REG_ADDR                     0x0924UL
 176 #define         HW_VERSION_REG_ADDR                     0x0928UL
 177 #define         HW_CONTEXT_ID_REG_ADDR                  0x0930UL
 178 #define         HW_DIN_BUFFER_REG_ADDR                  0x0C00UL
 179 #define         HW_DIN_MEM_DMA_BUSY_REG_ADDR            0x0c20UL
 180 #define         HW_SRC_LLI_MEM_ADDR_REG_ADDR            0x0c24UL
 181 #define         HW_SRC_LLI_WORD0_REG_ADDR               0x0C28UL
 182 #define         HW_SRC_LLI_WORD1_REG_ADDR               0x0C2CUL
 183 #define         HW_SRAM_SRC_ADDR_REG_ADDR               0x0c30UL
 184 #define         HW_DIN_SRAM_BYTES_LEN_REG_ADDR          0x0c34UL
 185 #define         HW_DIN_SRAM_DMA_BUSY_REG_ADDR           0x0C38UL
 186 #define         HW_WRITE_ALIGN_REG_ADDR                 0x0C3CUL
 187 #define         HW_OLD_DATA_REG_ADDR                    0x0C48UL
 188 #define         HW_WRITE_ALIGN_LAST_REG_ADDR            0x0C4CUL
 189 #define         HW_DOUT_BUFFER_REG_ADDR                 0x0C00UL
 190 #define         HW_DST_LLI_WORD0_REG_ADDR               0x0D28UL
 191 #define         HW_DST_LLI_WORD1_REG_ADDR               0x0D2CUL
 192 #define         HW_DST_LLI_MEM_ADDR_REG_ADDR            0x0D24UL
 193 #define         HW_DOUT_MEM_DMA_BUSY_REG_ADDR           0x0D20UL
 194 #define         HW_SRAM_DEST_ADDR_REG_ADDR              0x0D30UL
 195 #define         HW_DOUT_SRAM_BYTES_LEN_REG_ADDR         0x0D34UL
 196 #define         HW_DOUT_SRAM_DMA_BUSY_REG_ADDR          0x0D38UL
 197 #define         HW_READ_ALIGN_REG_ADDR                  0x0D3CUL
 198 #define         HW_READ_LAST_DATA_REG_ADDR              0x0D44UL
 199 #define         HW_RC4_THRU_CPU_REG_ADDR                0x0D4CUL
 200 #define         HW_AHB_SINGLE_REG_ADDR                  0x0E00UL
 201 #define         HW_SRAM_DATA_REG_ADDR                   0x0F00UL
 202 #define         HW_SRAM_ADDR_REG_ADDR                   0x0F04UL
 203 #define         HW_SRAM_DATA_READY_REG_ADDR             0x0F08UL
 204 #define         HW_HOST_IRR_REG_ADDR                    0x0A00UL
 205 #define         HW_HOST_IMR_REG_ADDR                    0x0A04UL
 206 #define         HW_HOST_ICR_REG_ADDR                    0x0A08UL
 207 #define         HW_HOST_SEP_SRAM_THRESHOLD_REG_ADDR     0x0A10UL
 208 #define         HW_HOST_SEP_BUSY_REG_ADDR               0x0A14UL
 209 #define         HW_HOST_SEP_LCS_REG_ADDR                0x0A18UL
 210 #define         HW_HOST_CC_SW_RST_REG_ADDR              0x0A40UL
 211 #define         HW_HOST_SEP_SW_RST_REG_ADDR             0x0A44UL
 212 #define         HW_HOST_FLOW_DMA_SW_INT0_REG_ADDR       0x0A80UL
 213 #define         HW_HOST_FLOW_DMA_SW_INT1_REG_ADDR       0x0A84UL
 214 #define         HW_HOST_FLOW_DMA_SW_INT2_REG_ADDR       0x0A88UL
 215 #define         HW_HOST_FLOW_DMA_SW_INT3_REG_ADDR       0x0A8cUL
 216 #define         HW_HOST_FLOW_DMA_SW_INT4_REG_ADDR       0x0A90UL
 217 #define         HW_HOST_FLOW_DMA_SW_INT5_REG_ADDR       0x0A94UL
 218 #define         HW_HOST_FLOW_DMA_SW_INT6_REG_ADDR       0x0A98UL
 219 #define         HW_HOST_FLOW_DMA_SW_INT7_REG_ADDR       0x0A9cUL
 220 #define         HW_HOST_SEP_HOST_GPR0_REG_ADDR          0x0B00UL
 221 #define         HW_HOST_SEP_HOST_GPR1_REG_ADDR          0x0B04UL
 222 #define         HW_HOST_SEP_HOST_GPR2_REG_ADDR          0x0B08UL
 223 #define         HW_HOST_SEP_HOST_GPR3_REG_ADDR          0x0B0CUL
 224 #define         HW_HOST_HOST_SEP_GPR0_REG_ADDR          0x0B80UL
 225 #define         HW_HOST_HOST_SEP_GPR1_REG_ADDR          0x0B84UL
 226 #define         HW_HOST_HOST_SEP_GPR2_REG_ADDR          0x0B88UL
 227 #define         HW_HOST_HOST_SEP_GPR3_REG_ADDR          0x0B8CUL
 228 #define         HW_HOST_HOST_ENDIAN_REG_ADDR            0x0B90UL
 229 #define         HW_HOST_HOST_COMM_CLK_EN_REG_ADDR       0x0B94UL
 230 #define         HW_CLR_SRAM_BUSY_REG_REG_ADDR           0x0F0CUL
 231 #define         HW_CC_SRAM_BASE_ADDRESS                 0x5800UL
 232
 233 #endif          /* ifndef HW_DEFS */