1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
28 #include "rtsx_scsi.h"
29 #include "rtsx_transport.h"
30 #include "rtsx_chip.h"
31 #include "rtsx_card.h"
34 /***********************************************************************
35 * Scatter-gather transfer buffer access routines
36 ***********************************************************************/
38 /* Copy a buffer of length buflen to/from the srb's transfer buffer.
39 * (Note: for scatter-gather transfers (srb->use_sg > 0), srb->request_buffer
40 * points to a list of s-g entries and we ignore srb->request_bufflen.
41 * For non-scatter-gather transfers, srb->request_buffer points to the
42 * transfer buffer itself and srb->request_bufflen is the buffer's length.)
43 * Update the *index and *offset variables so that the next copy will
44 * pick up from where this one left off. */
46 unsigned int rtsx_stor_access_xfer_buf(unsigned char *buffer,
47 unsigned int buflen, struct scsi_cmnd *srb, unsigned int *index,
48 unsigned int *offset, enum xfer_buf_dir dir)
52 /* If not using scatter-gather, just transfer the data directly.
53 * Make certain it will fit in the available buffer space. */
54 if (scsi_sg_count(srb) == 0) {
55 if (*offset >= scsi_bufflen(srb))
57 cnt = min(buflen, scsi_bufflen(srb) - *offset);
58 if (dir == TO_XFER_BUF)
59 memcpy((unsigned char *) scsi_sglist(srb) + *offset,
62 memcpy(buffer, (unsigned char *) scsi_sglist(srb) +
66 /* Using scatter-gather. We have to go through the list one entry
67 * at a time. Each s-g entry contains some number of pages, and
68 * each page has to be kmap()'ed separately. If the page is already
69 * in kernel-addressable memory then kmap() will return its address.
70 * If the page is not directly accessible -- such as a user buffer
71 * located in high memory -- then kmap() will map it to a temporary
72 * position in the kernel's virtual address space. */
74 struct scatterlist *sg =
75 (struct scatterlist *) scsi_sglist(srb)
78 /* This loop handles a single s-g list entry, which may
79 * include multiple pages. Find the initial page structure
80 * and the starting offset within the page, and update
81 * the *offset and *index values for the next loop. */
83 while (cnt < buflen && *index < scsi_sg_count(srb)) {
84 struct page *page = sg_page(sg) +
85 ((sg->offset + *offset) >> PAGE_SHIFT);
87 (sg->offset + *offset) & (PAGE_SIZE-1);
88 unsigned int sglen = sg->length - *offset;
90 if (sglen > buflen - cnt) {
92 /* Transfer ends within this s-g entry */
97 /* Transfer continues to next s-g entry */
103 /* Transfer the data for all the pages in this
104 * s-g entry. For each page: call kmap(), do the
105 * transfer, and call kunmap() immediately after. */
107 unsigned int plen = min(sglen, (unsigned int)
109 unsigned char *ptr = kmap(page);
111 if (dir == TO_XFER_BUF)
112 memcpy(ptr + poff, buffer + cnt, plen);
114 memcpy(buffer + cnt, ptr + poff, plen);
117 /* Start at the beginning of the next page */
126 /* Return the amount actually transferred */
130 /* Store the contents of buffer into srb's transfer buffer and set the
132 void rtsx_stor_set_xfer_buf(unsigned char *buffer,
133 unsigned int buflen, struct scsi_cmnd *srb)
135 unsigned int index = 0, offset = 0;
137 rtsx_stor_access_xfer_buf(buffer, buflen, srb, &index, &offset,
139 if (buflen < scsi_bufflen(srb))
140 scsi_set_resid(srb, scsi_bufflen(srb) - buflen);
143 void rtsx_stor_get_xfer_buf(unsigned char *buffer,
144 unsigned int buflen, struct scsi_cmnd *srb)
146 unsigned int index = 0, offset = 0;
148 rtsx_stor_access_xfer_buf(buffer, buflen, srb, &index, &offset,
150 if (buflen < scsi_bufflen(srb))
151 scsi_set_resid(srb, scsi_bufflen(srb) - buflen);
155 /***********************************************************************
157 ***********************************************************************/
159 /* Invoke the transport and basic error-handling/recovery methods
161 * This is used to send the message to the device and receive the response.
163 void rtsx_invoke_transport(struct scsi_cmnd *srb, struct rtsx_chip *chip)
167 result = rtsx_scsi_handler(srb, chip);
169 /* if the command gets aborted by the higher layers, we need to
170 * short-circuit all other processing
172 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT)) {
173 RTSX_DEBUGP("-- command was aborted\n");
174 srb->result = DID_ABORT << 16;
178 /* if there is a transport error, reset and don't auto-sense */
179 if (result == TRANSPORT_ERROR) {
180 RTSX_DEBUGP("-- transport indicates error, resetting\n");
181 srb->result = DID_ERROR << 16;
185 srb->result = SAM_STAT_GOOD;
188 * If we have a failure, we're going to do a REQUEST_SENSE
189 * automatically. Note that we differentiate between a command
190 * "failure" and an "error" in the transport mechanism.
192 if (result == TRANSPORT_FAILED) {
193 /* set the result so the higher layers expect this data */
194 srb->result = SAM_STAT_CHECK_CONDITION;
195 memcpy(srb->sense_buffer,
196 (unsigned char *)&(chip->sense_buffer[SCSI_LUN(srb)]),
197 sizeof(struct sense_data_t));
202 /* Error and abort processing: try to resynchronize with the device
203 * by issuing a port reset. If that fails, try a class-specific
209 void rtsx_add_cmd(struct rtsx_chip *chip,
210 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
212 u32 *cb = (u32 *)(chip->host_cmds_ptr);
215 val |= (u32)(cmd_type & 0x03) << 30;
216 val |= (u32)(reg_addr & 0x3FFF) << 16;
217 val |= (u32)mask << 8;
220 spin_lock_irq(&chip->rtsx->reg_lock);
221 if (chip->ci < (HOST_CMDS_BUF_LEN / 4)) {
222 cb[(chip->ci)++] = cpu_to_le32(val);
224 spin_unlock_irq(&chip->rtsx->reg_lock);
227 void rtsx_send_cmd_no_wait(struct rtsx_chip *chip)
231 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
233 val |= (u32)(chip->ci * 4) & 0x00FFFFFF;
234 /* Hardware Auto Response */
236 rtsx_writel(chip, RTSX_HCBCTLR, val);
239 int rtsx_send_cmd(struct rtsx_chip *chip, u8 card, int timeout)
241 struct rtsx_dev *rtsx = chip->rtsx;
242 struct completion trans_done;
247 if (card == SD_CARD) {
248 rtsx->check_card_cd = SD_EXIST;
249 } else if (card == MS_CARD) {
250 rtsx->check_card_cd = MS_EXIST;
251 } else if (card == XD_CARD) {
252 rtsx->check_card_cd = XD_EXIST;
254 rtsx->check_card_cd = 0;
257 spin_lock_irq(&rtsx->reg_lock);
259 /* set up data structures for the wakeup system */
260 rtsx->done = &trans_done;
261 rtsx->trans_result = TRANS_NOT_READY;
262 init_completion(&trans_done);
263 rtsx->trans_state = STATE_TRANS_CMD;
265 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
267 val |= (u32)(chip->ci * 4) & 0x00FFFFFF;
268 /* Hardware Auto Response */
270 rtsx_writel(chip, RTSX_HCBCTLR, val);
272 spin_unlock_irq(&rtsx->reg_lock);
274 /* Wait for TRANS_OK_INT */
275 timeleft = wait_for_completion_interruptible_timeout(
276 &trans_done, timeout * HZ / 1000);
278 RTSX_DEBUGP("chip->int_reg = 0x%x\n", chip->int_reg);
280 TRACE_GOTO(chip, finish_send_cmd);
283 spin_lock_irq(&rtsx->reg_lock);
284 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
286 } else if (rtsx->trans_result == TRANS_RESULT_OK) {
289 spin_unlock_irq(&rtsx->reg_lock);
293 rtsx->trans_state = STATE_TRANS_NONE;
296 rtsx_stop_cmd(chip, card);
301 static inline void rtsx_add_sg_tbl(
302 struct rtsx_chip *chip, u32 addr, u32 len, u8 option)
304 u64 *sgb = (u64 *)(chip->host_sg_tbl_ptr);
312 temp_opt = option & (~SG_END);
317 val = ((u64)addr << 32) | ((u64)temp_len << 12) | temp_opt;
319 if (chip->sgi < (HOST_SG_TBL_BUF_LEN / 8))
320 sgb[(chip->sgi)++] = cpu_to_le64(val);
327 static int rtsx_transfer_sglist_adma_partial(struct rtsx_chip *chip, u8 card,
328 struct scatterlist *sg, int num_sg, unsigned int *index,
329 unsigned int *offset, int size,
330 enum dma_data_direction dma_dir, int timeout)
332 struct rtsx_dev *rtsx = chip->rtsx;
333 struct completion trans_done;
335 int sg_cnt, i, resid;
338 struct scatterlist *sg_ptr;
341 if ((sg == NULL) || (num_sg <= 0) || !offset || !index)
344 if (dma_dir == DMA_TO_DEVICE) {
345 dir = HOST_TO_DEVICE;
346 } else if (dma_dir == DMA_FROM_DEVICE) {
347 dir = DEVICE_TO_HOST;
352 if (card == SD_CARD) {
353 rtsx->check_card_cd = SD_EXIST;
354 } else if (card == MS_CARD) {
355 rtsx->check_card_cd = MS_EXIST;
356 } else if (card == XD_CARD) {
357 rtsx->check_card_cd = XD_EXIST;
359 rtsx->check_card_cd = 0;
362 spin_lock_irq(&rtsx->reg_lock);
364 /* set up data structures for the wakeup system */
365 rtsx->done = &trans_done;
367 rtsx->trans_state = STATE_TRANS_SG;
368 rtsx->trans_result = TRANS_NOT_READY;
370 spin_unlock_irq(&rtsx->reg_lock);
372 sg_cnt = dma_map_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
377 /* Usually the next entry will be @sg@ + 1, but if this sg element
378 * is part of a chained scatterlist, it could jump to the start of
379 * a new scatterlist array. So here we use sg_next to move to
382 for (i = 0; i < *index; i++)
383 sg_ptr = sg_next(sg_ptr);
384 for (i = *index; i < sg_cnt; i++) {
389 addr = sg_dma_address(sg_ptr);
390 len = sg_dma_len(sg_ptr);
392 RTSX_DEBUGP("DMA addr: 0x%x, Len: 0x%x\n",
393 (unsigned int)addr, len);
394 RTSX_DEBUGP("*index = %d, *offset = %d\n", *index, *offset);
398 if ((len - *offset) > resid) {
403 resid -= (len - *offset);
408 if ((i == (sg_cnt - 1)) || !resid) {
409 option = SG_VALID | SG_END | SG_TRANS_DATA;
411 option = SG_VALID | SG_TRANS_DATA;
414 rtsx_add_sg_tbl(chip, (u32)addr, (u32)len, option);
419 sg_ptr = sg_next(sg_ptr);
422 RTSX_DEBUGP("SG table count = %d\n", chip->sgi);
424 val |= (u32)(dir & 0x01) << 29;
427 spin_lock_irq(&rtsx->reg_lock);
429 init_completion(&trans_done);
431 rtsx_writel(chip, RTSX_HDBAR, chip->host_sg_tbl_addr);
432 rtsx_writel(chip, RTSX_HDBCTLR, val);
434 spin_unlock_irq(&rtsx->reg_lock);
436 timeleft = wait_for_completion_interruptible_timeout(
437 &trans_done, timeout * HZ / 1000);
439 RTSX_DEBUGP("Timeout (%s %d)\n", __func__, __LINE__);
440 RTSX_DEBUGP("chip->int_reg = 0x%x\n", chip->int_reg);
445 spin_lock_irq(&rtsx->reg_lock);
446 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
448 spin_unlock_irq(&rtsx->reg_lock);
451 spin_unlock_irq(&rtsx->reg_lock);
453 /* Wait for TRANS_OK_INT */
454 spin_lock_irq(&rtsx->reg_lock);
455 if (rtsx->trans_result == TRANS_NOT_READY) {
456 init_completion(&trans_done);
457 spin_unlock_irq(&rtsx->reg_lock);
458 timeleft = wait_for_completion_interruptible_timeout(
459 &trans_done, timeout * HZ / 1000);
461 RTSX_DEBUGP("Timeout (%s %d)\n", __func__, __LINE__);
462 RTSX_DEBUGP("chip->int_reg = 0x%x\n", chip->int_reg);
467 spin_unlock_irq(&rtsx->reg_lock);
470 spin_lock_irq(&rtsx->reg_lock);
471 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
473 } else if (rtsx->trans_result == TRANS_RESULT_OK) {
476 spin_unlock_irq(&rtsx->reg_lock);
480 rtsx->trans_state = STATE_TRANS_NONE;
481 dma_unmap_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
484 rtsx_stop_cmd(chip, card);
489 static int rtsx_transfer_sglist_adma(struct rtsx_chip *chip, u8 card,
490 struct scatterlist *sg, int num_sg,
491 enum dma_data_direction dma_dir, int timeout)
493 struct rtsx_dev *rtsx = chip->rtsx;
494 struct completion trans_done;
499 struct scatterlist *sg_ptr;
501 if ((sg == NULL) || (num_sg <= 0))
504 if (dma_dir == DMA_TO_DEVICE) {
505 dir = HOST_TO_DEVICE;
506 } else if (dma_dir == DMA_FROM_DEVICE) {
507 dir = DEVICE_TO_HOST;
512 if (card == SD_CARD) {
513 rtsx->check_card_cd = SD_EXIST;
514 } else if (card == MS_CARD) {
515 rtsx->check_card_cd = MS_EXIST;
516 } else if (card == XD_CARD) {
517 rtsx->check_card_cd = XD_EXIST;
519 rtsx->check_card_cd = 0;
522 spin_lock_irq(&rtsx->reg_lock);
524 /* set up data structures for the wakeup system */
525 rtsx->done = &trans_done;
527 rtsx->trans_state = STATE_TRANS_SG;
528 rtsx->trans_result = TRANS_NOT_READY;
530 spin_unlock_irq(&rtsx->reg_lock);
532 buf_cnt = dma_map_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
536 for (i = 0; i <= buf_cnt / (HOST_SG_TBL_BUF_LEN / 8); i++) {
540 if (i == buf_cnt / (HOST_SG_TBL_BUF_LEN / 8)) {
541 sg_cnt = buf_cnt % (HOST_SG_TBL_BUF_LEN / 8);
543 sg_cnt = (HOST_SG_TBL_BUF_LEN / 8);
547 for (j = 0; j < sg_cnt; j++) {
548 dma_addr_t addr = sg_dma_address(sg_ptr);
549 unsigned int len = sg_dma_len(sg_ptr);
552 RTSX_DEBUGP("DMA addr: 0x%x, Len: 0x%x\n",
553 (unsigned int)addr, len);
555 if (j == (sg_cnt - 1)) {
556 option = SG_VALID | SG_END | SG_TRANS_DATA;
558 option = SG_VALID | SG_TRANS_DATA;
561 rtsx_add_sg_tbl(chip, (u32)addr, (u32)len, option);
563 sg_ptr = sg_next(sg_ptr);
566 RTSX_DEBUGP("SG table count = %d\n", chip->sgi);
568 val |= (u32)(dir & 0x01) << 29;
571 spin_lock_irq(&rtsx->reg_lock);
573 init_completion(&trans_done);
575 rtsx_writel(chip, RTSX_HDBAR, chip->host_sg_tbl_addr);
576 rtsx_writel(chip, RTSX_HDBCTLR, val);
578 spin_unlock_irq(&rtsx->reg_lock);
580 timeleft = wait_for_completion_interruptible_timeout(
581 &trans_done, timeout * HZ / 1000);
583 RTSX_DEBUGP("Timeout (%s %d)\n", __func__, __LINE__);
584 RTSX_DEBUGP("chip->int_reg = 0x%x\n", chip->int_reg);
589 spin_lock_irq(&rtsx->reg_lock);
590 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
592 spin_unlock_irq(&rtsx->reg_lock);
595 spin_unlock_irq(&rtsx->reg_lock);
600 /* Wait for TRANS_OK_INT */
601 spin_lock_irq(&rtsx->reg_lock);
602 if (rtsx->trans_result == TRANS_NOT_READY) {
603 init_completion(&trans_done);
604 spin_unlock_irq(&rtsx->reg_lock);
605 timeleft = wait_for_completion_interruptible_timeout(
606 &trans_done, timeout * HZ / 1000);
608 RTSX_DEBUGP("Timeout (%s %d)\n", __func__, __LINE__);
609 RTSX_DEBUGP("chip->int_reg = 0x%x\n", chip->int_reg);
614 spin_unlock_irq(&rtsx->reg_lock);
617 spin_lock_irq(&rtsx->reg_lock);
618 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
620 } else if (rtsx->trans_result == TRANS_RESULT_OK) {
623 spin_unlock_irq(&rtsx->reg_lock);
627 rtsx->trans_state = STATE_TRANS_NONE;
628 dma_unmap_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
631 rtsx_stop_cmd(chip, card);
636 static int rtsx_transfer_buf(struct rtsx_chip *chip, u8 card, void *buf, size_t len,
637 enum dma_data_direction dma_dir, int timeout)
639 struct rtsx_dev *rtsx = chip->rtsx;
640 struct completion trans_done;
647 if ((buf == NULL) || (len <= 0))
650 if (dma_dir == DMA_TO_DEVICE) {
651 dir = HOST_TO_DEVICE;
652 } else if (dma_dir == DMA_FROM_DEVICE) {
653 dir = DEVICE_TO_HOST;
658 addr = dma_map_single(&(rtsx->pci->dev), buf, len, dma_dir);
662 if (card == SD_CARD) {
663 rtsx->check_card_cd = SD_EXIST;
664 } else if (card == MS_CARD) {
665 rtsx->check_card_cd = MS_EXIST;
666 } else if (card == XD_CARD) {
667 rtsx->check_card_cd = XD_EXIST;
669 rtsx->check_card_cd = 0;
672 val |= (u32)(dir & 0x01) << 29;
673 val |= (u32)(len & 0x00FFFFFF);
675 spin_lock_irq(&rtsx->reg_lock);
677 /* set up data structures for the wakeup system */
678 rtsx->done = &trans_done;
680 init_completion(&trans_done);
682 rtsx->trans_state = STATE_TRANS_BUF;
683 rtsx->trans_result = TRANS_NOT_READY;
685 rtsx_writel(chip, RTSX_HDBAR, addr);
686 rtsx_writel(chip, RTSX_HDBCTLR, val);
688 spin_unlock_irq(&rtsx->reg_lock);
690 /* Wait for TRANS_OK_INT */
691 timeleft = wait_for_completion_interruptible_timeout(
692 &trans_done, timeout * HZ / 1000);
694 RTSX_DEBUGP("Timeout (%s %d)\n", __func__, __LINE__);
695 RTSX_DEBUGP("chip->int_reg = 0x%x\n", chip->int_reg);
700 spin_lock_irq(&rtsx->reg_lock);
701 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
703 } else if (rtsx->trans_result == TRANS_RESULT_OK) {
706 spin_unlock_irq(&rtsx->reg_lock);
710 rtsx->trans_state = STATE_TRANS_NONE;
711 dma_unmap_single(&(rtsx->pci->dev), addr, len, dma_dir);
714 rtsx_stop_cmd(chip, card);
719 int rtsx_transfer_data_partial(struct rtsx_chip *chip, u8 card,
720 void *buf, size_t len, int use_sg, unsigned int *index,
721 unsigned int *offset, enum dma_data_direction dma_dir,
726 /* don't transfer data during abort processing */
727 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT))
731 err = rtsx_transfer_sglist_adma_partial(chip, card,
732 (struct scatterlist *)buf, use_sg,
733 index, offset, (int)len, dma_dir, timeout);
735 err = rtsx_transfer_buf(chip, card,
736 buf, len, dma_dir, timeout);
740 if (RTSX_TST_DELINK(chip)) {
741 RTSX_CLR_DELINK(chip);
742 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
743 rtsx_reinit_cards(chip, 1);
750 int rtsx_transfer_data(struct rtsx_chip *chip, u8 card, void *buf, size_t len,
751 int use_sg, enum dma_data_direction dma_dir, int timeout)
755 RTSX_DEBUGP("use_sg = %d\n", use_sg);
757 /* don't transfer data during abort processing */
758 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT))
762 err = rtsx_transfer_sglist_adma(chip, card,
763 (struct scatterlist *)buf,
764 use_sg, dma_dir, timeout);
766 err = rtsx_transfer_buf(chip, card, buf, len, dma_dir, timeout);
770 if (RTSX_TST_DELINK(chip)) {
771 RTSX_CLR_DELINK(chip);
772 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
773 rtsx_reinit_cards(chip, 1);