1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/workqueue.h>
27 #include <linux/kernel.h>
30 #include "rtsx_transport.h"
31 #include "rtsx_scsi.h"
32 #include "rtsx_card.h"
41 void do_remaining_work(struct rtsx_chip *chip)
43 struct sd_info *sd_card = &(chip->sd_card);
45 struct xd_info *xd_card = &(chip->xd_card);
47 struct ms_info *ms_card = &(chip->ms_card);
49 if (chip->card_ready & SD_CARD) {
50 if (sd_card->seq_mode) {
51 rtsx_set_stat(chip, RTSX_STAT_RUN);
52 sd_card->cleanup_counter++;
54 sd_card->cleanup_counter = 0;
59 if (chip->card_ready & XD_CARD) {
60 if (xd_card->delay_write.delay_write_flag) {
61 rtsx_set_stat(chip, RTSX_STAT_RUN);
62 xd_card->cleanup_counter++;
64 xd_card->cleanup_counter = 0;
69 if (chip->card_ready & MS_CARD) {
70 if (CHK_MSPRO(ms_card)) {
71 if (ms_card->seq_mode) {
72 rtsx_set_stat(chip, RTSX_STAT_RUN);
73 ms_card->cleanup_counter++;
75 ms_card->cleanup_counter = 0;
79 if (ms_card->delay_write.delay_write_flag) {
80 rtsx_set_stat(chip, RTSX_STAT_RUN);
81 ms_card->cleanup_counter++;
83 ms_card->cleanup_counter = 0;
89 if (sd_card->cleanup_counter > POLLING_WAIT_CNT)
90 sd_cleanup_work(chip);
92 if (xd_card->cleanup_counter > POLLING_WAIT_CNT)
93 xd_cleanup_work(chip);
95 if (ms_card->cleanup_counter > POLLING_WAIT_CNT)
96 ms_cleanup_work(chip);
99 void try_to_switch_sdio_ctrl(struct rtsx_chip *chip)
101 u8 reg1 = 0, reg2 = 0;
103 rtsx_read_register(chip, 0xFF34, ®1);
104 rtsx_read_register(chip, 0xFF38, ®2);
105 RTSX_DEBUGP("reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n", reg1, reg2);
106 if ((reg1 & 0xC0) && (reg2 & 0xC0)) {
108 rtsx_write_register(chip, SDIO_CTRL, 0xFF, SDIO_BUS_CTRL | SDIO_CD_CTRL);
109 rtsx_write_register(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
113 #ifdef SUPPORT_SDIO_ASPM
114 void dynamic_configure_sdio_aspm(struct rtsx_chip *chip)
119 for (i = 0; i < 12; i++)
120 rtsx_read_register(chip, 0xFF08 + i, &buf[i]);
121 rtsx_read_register(chip, 0xFF25, ®);
122 if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) {
123 chip->sdio_counter = 0;
126 if (!chip->sdio_idle) {
127 chip->sdio_counter++;
128 if (chip->sdio_counter >= SDIO_IDLE_COUNT) {
129 chip->sdio_counter = 0;
134 memcpy(chip->sdio_raw_data, buf, 12);
136 if (chip->sdio_idle) {
137 if (!chip->sdio_aspm) {
138 RTSX_DEBUGP("SDIO enter ASPM!\n");
139 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC,
140 0x30 | (chip->aspm_level[1] << 2));
144 if (chip->sdio_aspm) {
145 RTSX_DEBUGP("SDIO exit ASPM!\n");
146 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30);
153 void do_reset_sd_card(struct rtsx_chip *chip)
157 RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
158 chip->sd_reset_counter, chip->card2lun[SD_CARD]);
160 if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT) {
161 clear_bit(SD_NR, &(chip->need_reset));
162 chip->sd_reset_counter = 0;
163 chip->sd_show_cnt = 0;
167 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
169 rtsx_set_stat(chip, RTSX_STAT_RUN);
170 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
172 retval = reset_sd_card(chip);
173 if (chip->need_release & SD_CARD)
175 if (retval == STATUS_SUCCESS) {
176 clear_bit(SD_NR, &(chip->need_reset));
177 chip->sd_reset_counter = 0;
178 chip->sd_show_cnt = 0;
179 chip->card_ready |= SD_CARD;
180 chip->card_fail &= ~SD_CARD;
181 chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
183 if (chip->sd_io || (chip->sd_reset_counter >= MAX_RESET_CNT)) {
184 clear_bit(SD_NR, &(chip->need_reset));
185 chip->sd_reset_counter = 0;
186 chip->sd_show_cnt = 0;
188 chip->sd_reset_counter++;
190 chip->card_ready &= ~SD_CARD;
191 chip->card_fail |= SD_CARD;
192 chip->capacity[chip->card2lun[SD_CARD]] = 0;
193 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
195 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
196 if (!chip->ft2_fast_mode)
197 card_power_off(chip, SD_CARD);
200 try_to_switch_sdio_ctrl(chip);
202 disable_card_clock(chip, SD_CARD);
207 void do_reset_xd_card(struct rtsx_chip *chip)
211 RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
212 chip->xd_reset_counter, chip->card2lun[XD_CARD]);
214 if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT) {
215 clear_bit(XD_NR, &(chip->need_reset));
216 chip->xd_reset_counter = 0;
217 chip->xd_show_cnt = 0;
221 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
223 rtsx_set_stat(chip, RTSX_STAT_RUN);
224 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
226 retval = reset_xd_card(chip);
227 if (chip->need_release & XD_CARD)
229 if (retval == STATUS_SUCCESS) {
230 clear_bit(XD_NR, &(chip->need_reset));
231 chip->xd_reset_counter = 0;
232 chip->card_ready |= XD_CARD;
233 chip->card_fail &= ~XD_CARD;
234 chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
236 if (chip->xd_reset_counter >= MAX_RESET_CNT) {
237 clear_bit(XD_NR, &(chip->need_reset));
238 chip->xd_reset_counter = 0;
239 chip->xd_show_cnt = 0;
241 chip->xd_reset_counter++;
243 chip->card_ready &= ~XD_CARD;
244 chip->card_fail |= XD_CARD;
245 chip->capacity[chip->card2lun[XD_CARD]] = 0;
246 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
248 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
249 if (!chip->ft2_fast_mode)
250 card_power_off(chip, XD_CARD);
251 disable_card_clock(chip, XD_CARD);
255 void do_reset_ms_card(struct rtsx_chip *chip)
259 RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
260 chip->ms_reset_counter, chip->card2lun[MS_CARD]);
262 if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT) {
263 clear_bit(MS_NR, &(chip->need_reset));
264 chip->ms_reset_counter = 0;
265 chip->ms_show_cnt = 0;
269 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
271 rtsx_set_stat(chip, RTSX_STAT_RUN);
272 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
274 retval = reset_ms_card(chip);
275 if (chip->need_release & MS_CARD)
277 if (retval == STATUS_SUCCESS) {
278 clear_bit(MS_NR, &(chip->need_reset));
279 chip->ms_reset_counter = 0;
280 chip->card_ready |= MS_CARD;
281 chip->card_fail &= ~MS_CARD;
282 chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
284 if (chip->ms_reset_counter >= MAX_RESET_CNT) {
285 clear_bit(MS_NR, &(chip->need_reset));
286 chip->ms_reset_counter = 0;
287 chip->ms_show_cnt = 0;
289 chip->ms_reset_counter++;
291 chip->card_ready &= ~MS_CARD;
292 chip->card_fail |= MS_CARD;
293 chip->capacity[chip->card2lun[MS_CARD]] = 0;
294 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
296 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
297 if (!chip->ft2_fast_mode)
298 card_power_off(chip, MS_CARD);
299 disable_card_clock(chip, MS_CARD);
303 static void release_sdio(struct rtsx_chip *chip)
306 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
307 SD_STOP | SD_CLR_ERR);
309 if (chip->chip_insert_with_sdio) {
310 chip->chip_insert_with_sdio = 0;
312 if (CHECK_PID(chip, 0x5288)) {
313 rtsx_write_register(chip, 0xFE5A, 0x08, 0x00);
315 rtsx_write_register(chip, 0xFE70, 0x80, 0x00);
319 rtsx_write_register(chip, SDIO_CTRL, SDIO_CD_CTRL, 0);
324 void rtsx_power_off_card(struct rtsx_chip *chip)
326 if ((chip->card_ready & SD_CARD) || chip->sd_io) {
327 sd_cleanup_work(chip);
328 sd_power_off_card3v3(chip);
331 if (chip->card_ready & XD_CARD) {
332 xd_cleanup_work(chip);
333 xd_power_off_card3v3(chip);
336 if (chip->card_ready & MS_CARD) {
337 ms_cleanup_work(chip);
338 ms_power_off_card3v3(chip);
342 void rtsx_release_cards(struct rtsx_chip *chip)
344 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
346 if ((chip->card_ready & SD_CARD) || chip->sd_io) {
347 if (chip->int_reg & SD_EXIST)
348 sd_cleanup_work(chip);
349 release_sd_card(chip);
352 if (chip->card_ready & XD_CARD) {
353 if (chip->int_reg & XD_EXIST)
354 xd_cleanup_work(chip);
355 release_xd_card(chip);
358 if (chip->card_ready & MS_CARD) {
359 if (chip->int_reg & MS_EXIST)
360 ms_cleanup_work(chip);
361 release_ms_card(chip);
365 void rtsx_reset_cards(struct rtsx_chip *chip)
367 if (!chip->need_reset)
370 rtsx_set_stat(chip, RTSX_STAT_RUN);
372 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
374 rtsx_disable_aspm(chip);
376 if ((chip->need_reset & SD_CARD) && chip->chip_insert_with_sdio)
377 clear_bit(SD_NR, &(chip->need_reset));
379 if (chip->need_reset & XD_CARD) {
380 chip->card_exist |= XD_CARD;
382 if (chip->xd_show_cnt >= MAX_SHOW_CNT) {
383 do_reset_xd_card(chip);
388 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
389 if (chip->card_exist & XD_CARD) {
390 clear_bit(SD_NR, &(chip->need_reset));
391 clear_bit(MS_NR, &(chip->need_reset));
394 if (chip->need_reset & SD_CARD) {
395 chip->card_exist |= SD_CARD;
397 if (chip->sd_show_cnt >= MAX_SHOW_CNT) {
398 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
399 do_reset_sd_card(chip);
404 if (chip->need_reset & MS_CARD) {
405 chip->card_exist |= MS_CARD;
407 if (chip->ms_show_cnt >= MAX_SHOW_CNT) {
408 do_reset_ms_card(chip);
415 void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip)
417 rtsx_set_stat(chip, RTSX_STAT_RUN);
419 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
422 rtsx_reset_chip(chip);
424 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
426 if ((chip->int_reg & SD_EXIST) && (chip->need_reinit & SD_CARD)) {
428 release_sd_card(chip);
432 chip->card_exist |= SD_CARD;
433 do_reset_sd_card(chip);
436 if ((chip->int_reg & XD_EXIST) && (chip->need_reinit & XD_CARD)) {
437 release_xd_card(chip);
441 chip->card_exist |= XD_CARD;
442 do_reset_xd_card(chip);
445 if ((chip->int_reg & MS_EXIST) && (chip->need_reinit & MS_CARD)) {
446 release_ms_card(chip);
450 chip->card_exist |= MS_CARD;
451 do_reset_ms_card(chip);
454 chip->need_reinit = 0;
457 #ifdef DISABLE_CARD_INT
458 void card_cd_debounce(struct rtsx_chip *chip, unsigned long *need_reset, unsigned long *need_release)
460 u8 release_map = 0, reset_map = 0;
462 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
464 if (chip->card_exist) {
465 if (chip->card_exist & XD_CARD) {
466 if (!(chip->int_reg & XD_EXIST))
467 release_map |= XD_CARD;
468 } else if (chip->card_exist & SD_CARD) {
469 if (!(chip->int_reg & SD_EXIST))
470 release_map |= SD_CARD;
471 } else if (chip->card_exist & MS_CARD) {
472 if (!(chip->int_reg & MS_EXIST))
473 release_map |= MS_CARD;
476 if (chip->int_reg & XD_EXIST) {
477 reset_map |= XD_CARD;
478 } else if (chip->int_reg & SD_EXIST) {
479 reset_map |= SD_CARD;
480 } else if (chip->int_reg & MS_EXIST) {
481 reset_map |= MS_CARD;
486 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
489 for (i = 0; i < (DEBOUNCE_CNT); i++) {
490 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
492 if (chip->int_reg & XD_EXIST) {
497 if (chip->int_reg & SD_EXIST) {
502 if (chip->int_reg & MS_EXIST) {
511 if (!(chip->card_exist & XD_CARD) && (xd_cnt > (DEBOUNCE_CNT-1)))
512 reset_map |= XD_CARD;
513 if (!(chip->card_exist & SD_CARD) && (sd_cnt > (DEBOUNCE_CNT-1)))
514 reset_map |= SD_CARD;
515 if (!(chip->card_exist & MS_CARD) && (ms_cnt > (DEBOUNCE_CNT-1)))
516 reset_map |= MS_CARD;
519 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
520 rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00);
523 *need_reset = reset_map;
525 *need_release = release_map;
529 void rtsx_init_cards(struct rtsx_chip *chip)
531 if (RTSX_TST_DELINK(chip) && (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
532 RTSX_DEBUGP("Reset chip in polling thread!\n");
533 rtsx_reset_chip(chip);
534 RTSX_CLR_DELINK(chip);
537 #ifdef DISABLE_CARD_INT
538 card_cd_debounce(chip, &(chip->need_reset), &(chip->need_release));
541 if (chip->need_release) {
542 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
543 if (chip->int_reg & XD_EXIST) {
544 clear_bit(SD_NR, &(chip->need_release));
545 clear_bit(MS_NR, &(chip->need_release));
549 if (!(chip->card_exist & SD_CARD) && !chip->sd_io)
550 clear_bit(SD_NR, &(chip->need_release));
551 if (!(chip->card_exist & XD_CARD))
552 clear_bit(XD_NR, &(chip->need_release));
553 if (!(chip->card_exist & MS_CARD))
554 clear_bit(MS_NR, &(chip->need_release));
556 RTSX_DEBUGP("chip->need_release = 0x%x\n", (unsigned int)(chip->need_release));
559 if (chip->need_release) {
560 if (CHECK_PID(chip, 0x5209)) {
561 u8 mask = 0, val = 0;
562 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
563 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
564 mask |= MS_OCP_INT_CLR | MS_OC_CLR;
565 val |= MS_OCP_INT_CLR | MS_OC_CLR;
568 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
569 mask |= SD_OCP_INT_CLR | SD_OC_CLR;
570 val |= SD_OCP_INT_CLR | SD_OC_CLR;
573 rtsx_write_register(chip, OCPCTL, mask, val);
575 if (chip->ocp_stat & (CARD_OC_NOW | CARD_OC_EVER))
576 rtsx_write_register(chip, OCPCLR,
577 CARD_OC_INT_CLR | CARD_OC_CLR,
578 CARD_OC_INT_CLR | CARD_OC_CLR);
583 if (chip->need_release) {
584 rtsx_set_stat(chip, RTSX_STAT_RUN);
585 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
588 if (chip->need_release & SD_CARD) {
589 clear_bit(SD_NR, &(chip->need_release));
590 chip->card_exist &= ~SD_CARD;
591 chip->card_ejected &= ~SD_CARD;
592 chip->card_fail &= ~SD_CARD;
593 CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]);
594 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
595 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
598 release_sd_card(chip);
601 if (chip->need_release & XD_CARD) {
602 clear_bit(XD_NR, &(chip->need_release));
603 chip->card_exist &= ~XD_CARD;
604 chip->card_ejected &= ~XD_CARD;
605 chip->card_fail &= ~XD_CARD;
606 CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]);
607 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
609 release_xd_card(chip);
611 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
612 rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0xC0);
615 if (chip->need_release & MS_CARD) {
616 clear_bit(MS_NR, &(chip->need_release));
617 chip->card_exist &= ~MS_CARD;
618 chip->card_ejected &= ~MS_CARD;
619 chip->card_fail &= ~MS_CARD;
620 CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]);
621 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
623 release_ms_card(chip);
626 RTSX_DEBUGP("chip->card_exist = 0x%x\n", chip->card_exist);
628 if (!chip->card_exist)
629 turn_off_led(chip, LED_GPIO);
632 if (chip->need_reset) {
633 RTSX_DEBUGP("chip->need_reset = 0x%x\n", (unsigned int)(chip->need_reset));
635 rtsx_reset_cards(chip);
638 if (chip->need_reinit) {
639 RTSX_DEBUGP("chip->need_reinit = 0x%x\n", (unsigned int)(chip->need_reinit));
641 rtsx_reinit_cards(chip, 0);
645 static inline u8 double_depth(u8 depth)
647 return ((depth > 1) ? (depth - 1) : depth);
650 int switch_ssc_clock(struct rtsx_chip *chip, int clk)
652 struct sd_info *sd_card = &(chip->sd_card);
653 struct ms_info *ms_card = &(chip->ms_card);
655 u8 N = (u8)(clk - 2), min_N, max_N;
656 u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask;
657 int sd_vpclk_phase_reset = 0;
659 if (chip->cur_clk == clk)
660 return STATUS_SUCCESS;
662 if (CHECK_PID(chip, 0x5209)) {
672 if (CHECK_PID(chip, 0x5209) && (chip->cur_card == SD_CARD)) {
673 struct sd_info *sd_card = &(chip->sd_card);
674 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
675 sd_vpclk_phase_reset = 1;
678 RTSX_DEBUGP("Switch SSC clock to %dMHz (cur_clk = %d)\n", clk, chip->cur_clk);
680 if ((clk <= 2) || (N > max_N)) {
681 TRACE_RET(chip, STATUS_FAIL);
684 mcu_cnt = (u8)(125/clk + 3);
685 if (CHECK_PID(chip, 0x5209)) {
694 while ((N < min_N) && (div < max_div)) {
698 RTSX_DEBUGP("N = %d, div = %d\n", N, div);
701 if (CHECK_PID(chip, 0x5209)) {
702 if (chip->cur_card == SD_CARD) {
703 if (CHK_SD_SDR104(sd_card)) {
704 ssc_depth = chip->ssc_depth_sd_sdr104;
705 } else if (CHK_SD_SDR50(sd_card)) {
706 ssc_depth = chip->ssc_depth_sd_sdr50;
707 } else if (CHK_SD_DDR50(sd_card)) {
708 ssc_depth = double_depth(chip->ssc_depth_sd_ddr50);
709 } else if (CHK_SD_HS(sd_card)) {
710 ssc_depth = double_depth(chip->ssc_depth_sd_hs);
711 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
712 ssc_depth = double_depth(chip->ssc_depth_mmc_52m);
714 ssc_depth = double_depth(chip->ssc_depth_low_speed);
716 } else if (chip->cur_card == MS_CARD) {
717 if (CHK_MSPRO(ms_card)) {
718 if (CHK_HG8BIT(ms_card)) {
719 ssc_depth = double_depth(chip->ssc_depth_ms_hg);
721 ssc_depth = double_depth(chip->ssc_depth_ms_4bit);
724 if (CHK_MS4BIT(ms_card)) {
725 ssc_depth = double_depth(chip->ssc_depth_ms_4bit);
727 ssc_depth = double_depth(chip->ssc_depth_low_speed);
731 ssc_depth = double_depth(chip->ssc_depth_low_speed);
735 if (div == CLK_DIV_2) {
739 ssc_depth = SSC_DEPTH_4M;
741 } else if (div == CLK_DIV_4) {
745 ssc_depth = SSC_DEPTH_4M;
747 } else if (div == CLK_DIV_8) {
751 ssc_depth = SSC_DEPTH_4M;
763 if (CHECK_PID(chip, 0x5209)) {
764 ssc_depth_mask = SSC_DEPTH_MASK;
766 ssc_depth_mask = 0x03;
769 RTSX_DEBUGP("ssc_depth = %d\n", ssc_depth);
772 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
773 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
774 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
775 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth);
776 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
777 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
778 if (sd_vpclk_phase_reset) {
779 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
780 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
783 retval = rtsx_send_cmd(chip, 0, WAIT_TIME);
785 TRACE_RET(chip, STATUS_ERROR);
789 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
793 return STATUS_SUCCESS;
796 int switch_normal_clock(struct rtsx_chip *chip, int clk)
798 u8 sel, div, mcu_cnt;
799 int sd_vpclk_phase_reset = 0;
801 if (chip->cur_clk == clk)
802 return STATUS_SUCCESS;
804 if (CHECK_PID(chip, 0x5209) && (chip->cur_card == SD_CARD)) {
805 struct sd_info *sd_card = &(chip->sd_card);
806 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
807 sd_vpclk_phase_reset = 1;
812 RTSX_DEBUGP("Switch clock to 20MHz\n");
819 RTSX_DEBUGP("Switch clock to 30MHz\n");
826 RTSX_DEBUGP("Switch clock to 40MHz\n");
833 RTSX_DEBUGP("Switch clock to 50MHz\n");
840 RTSX_DEBUGP("Switch clock to 60MHz\n");
847 RTSX_DEBUGP("Switch clock to 80MHz\n");
854 RTSX_DEBUGP("Switch clock to 100MHz\n");
861 RTSX_DEBUGP("Switch clock to 120MHz\n");
868 RTSX_DEBUGP("Switch clock to 150MHz\n");
875 RTSX_DEBUGP("Switch clock to 200MHz\n");
882 RTSX_DEBUGP("Try to switch to an illegal clock (%d)\n", clk);
883 TRACE_RET(chip, STATUS_FAIL);
886 RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ);
887 if (sd_vpclk_phase_reset) {
888 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
889 RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, 0);
891 RTSX_WRITE_REG(chip, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
892 RTSX_WRITE_REG(chip, CLK_SEL, 0xFF, sel);
894 if (sd_vpclk_phase_reset) {
896 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
897 RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
900 RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, 0);
904 return STATUS_SUCCESS;
907 void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size)
909 if (pack_size > DMA_1024)
912 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT);
914 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24));
915 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(byte_cnt >> 16));
916 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(byte_cnt >> 8));
917 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC0, 0xFF, (u8)byte_cnt);
919 if (dir == DMA_FROM_DEVICE) {
920 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL, 0x03 | DMA_PACK_SIZE_MASK,
921 DMA_DIR_FROM_CARD | DMA_EN | pack_size);
923 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL, 0x03 | DMA_PACK_SIZE_MASK,
924 DMA_DIR_TO_CARD | DMA_EN | pack_size);
927 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
930 int enable_card_clock(struct rtsx_chip *chip, u8 card)
941 RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
943 return STATUS_SUCCESS;
946 int disable_card_clock(struct rtsx_chip *chip, u8 card)
957 RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, 0);
959 return STATUS_SUCCESS;
962 int card_power_on(struct rtsx_chip *chip, u8 card)
967 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
968 mask = MS_POWER_MASK;
969 val1 = MS_PARTIAL_POWER_ON;
972 mask = SD_POWER_MASK;
973 val1 = SD_PARTIAL_POWER_ON;
978 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1);
979 if (CHECK_PID(chip, 0x5209) && (card == SD_CARD)) {
980 rtsx_add_cmd(chip, WRITE_REG_CMD, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_SUSPEND);
982 retval = rtsx_send_cmd(chip, 0, 100);
983 if (retval != STATUS_SUCCESS) {
984 TRACE_RET(chip, STATUS_FAIL);
987 udelay(chip->pmos_pwr_on_interval);
990 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2);
991 if (CHECK_PID(chip, 0x5209) && (card == SD_CARD)) {
992 rtsx_add_cmd(chip, WRITE_REG_CMD, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
994 retval = rtsx_send_cmd(chip, 0, 100);
995 if (retval != STATUS_SUCCESS) {
996 TRACE_RET(chip, STATUS_FAIL);
999 return STATUS_SUCCESS;
1002 int card_power_off(struct rtsx_chip *chip, u8 card)
1006 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
1007 mask = MS_POWER_MASK;
1010 mask = SD_POWER_MASK;
1013 if (CHECK_PID(chip, 0x5209)) {
1014 mask |= PMOS_STRG_MASK;
1015 val |= PMOS_STRG_400mA;
1018 RTSX_WRITE_REG(chip, CARD_PWR_CTL, mask, val);
1019 if (CHECK_PID(chip, 0x5209) && (card == SD_CARD)) {
1020 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
1023 return STATUS_SUCCESS;
1026 int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 sec_addr, u16 sec_cnt)
1029 unsigned int lun = SCSI_LUN(srb);
1032 if (chip->rw_card[lun] == NULL) {
1033 TRACE_RET(chip, STATUS_FAIL);
1036 for (i = 0; i < 3; i++) {
1037 chip->rw_need_retry = 0;
1039 retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt);
1040 if (retval != STATUS_SUCCESS) {
1041 if (rtsx_check_chip_exist(chip) != STATUS_SUCCESS) {
1042 rtsx_release_chip(chip);
1043 TRACE_RET(chip, STATUS_FAIL);
1045 if (detect_card_cd(chip, chip->cur_card) != STATUS_SUCCESS) {
1046 TRACE_RET(chip, STATUS_FAIL);
1048 if (!chip->rw_need_retry) {
1049 RTSX_DEBUGP("RW fail, but no need to retry\n");
1053 chip->rw_need_retry = 0;
1057 RTSX_DEBUGP("Retry RW, (i = %d)\n", i);
1063 int card_share_mode(struct rtsx_chip *chip, int card)
1067 if (CHECK_PID(chip, 0x5209) || CHECK_PID(chip, 0x5208)) {
1068 mask = CARD_SHARE_MASK;
1069 if (card == SD_CARD) {
1070 value = CARD_SHARE_48_SD;
1071 } else if (card == MS_CARD) {
1072 value = CARD_SHARE_48_MS;
1073 } else if (card == XD_CARD) {
1074 value = CARD_SHARE_48_XD;
1076 TRACE_RET(chip, STATUS_FAIL);
1078 } else if (CHECK_PID(chip, 0x5288)) {
1080 if (card == SD_CARD) {
1081 value = CARD_SHARE_BAROSSA_SD;
1082 } else if (card == MS_CARD) {
1083 value = CARD_SHARE_BAROSSA_MS;
1084 } else if (card == XD_CARD) {
1085 value = CARD_SHARE_BAROSSA_XD;
1087 TRACE_RET(chip, STATUS_FAIL);
1090 TRACE_RET(chip, STATUS_FAIL);
1093 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, mask, value);
1095 return STATUS_SUCCESS;
1099 int select_card(struct rtsx_chip *chip, int card)
1103 if (chip->cur_card != card) {
1106 if (card == SD_CARD) {
1108 } else if (card == MS_CARD) {
1110 } else if (card == XD_CARD) {
1112 } else if (card == SPI_CARD) {
1115 TRACE_RET(chip, STATUS_FAIL);
1117 RTSX_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
1118 chip->cur_card = card;
1120 retval = card_share_mode(chip, card);
1121 if (retval != STATUS_SUCCESS) {
1122 TRACE_RET(chip, STATUS_FAIL);
1126 return STATUS_SUCCESS;
1129 void toggle_gpio(struct rtsx_chip *chip, u8 gpio)
1133 rtsx_read_register(chip, CARD_GPIO, &temp_reg);
1134 temp_reg ^= (0x01 << gpio);
1135 rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg);
1138 void turn_on_led(struct rtsx_chip *chip, u8 gpio)
1140 if (CHECK_PID(chip, 0x5288)) {
1141 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), (u8)(1 << gpio));
1143 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1147 void turn_off_led(struct rtsx_chip *chip, u8 gpio)
1149 if (CHECK_PID(chip, 0x5288)) {
1150 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1152 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), (u8)(1 << gpio));
1156 int detect_card_cd(struct rtsx_chip *chip, int card)
1158 u32 card_cd, status;
1160 if (card == SD_CARD) {
1162 } else if (card == MS_CARD) {
1164 } else if (card == XD_CARD) {
1167 RTSX_DEBUGP("Wrong card type: 0x%x\n", card);
1168 TRACE_RET(chip, STATUS_FAIL);
1171 status = rtsx_readl(chip, RTSX_BIPR);
1172 if (!(status & card_cd)) {
1173 TRACE_RET(chip, STATUS_FAIL);
1176 return STATUS_SUCCESS;
1179 int check_card_exist(struct rtsx_chip *chip, unsigned int lun)
1181 if (chip->card_exist & chip->lun2card[lun]) {
1188 int check_card_ready(struct rtsx_chip *chip, unsigned int lun)
1190 if (chip->card_ready & chip->lun2card[lun]) {
1197 int check_card_wp(struct rtsx_chip *chip, unsigned int lun)
1199 if (chip->card_wp & chip->lun2card[lun]) {
1206 int check_card_fail(struct rtsx_chip *chip, unsigned int lun)
1208 if (chip->card_fail & chip->lun2card[lun]) {
1215 int check_card_ejected(struct rtsx_chip *chip, unsigned int lun)
1217 if (chip->card_ejected & chip->lun2card[lun]) {
1224 u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun)
1226 if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
1228 } else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
1230 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
1237 void eject_card(struct rtsx_chip *chip, unsigned int lun)
1239 do_remaining_work(chip);
1241 if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
1242 release_sd_card(chip);
1243 chip->card_ejected |= SD_CARD;
1244 chip->card_ready &= ~SD_CARD;
1245 chip->capacity[lun] = 0;
1246 } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
1247 release_xd_card(chip);
1248 chip->card_ejected |= XD_CARD;
1249 chip->card_ready &= ~XD_CARD;
1250 chip->capacity[lun] = 0;
1251 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
1252 release_ms_card(chip);
1253 chip->card_ejected |= MS_CARD;
1254 chip->card_ready &= ~MS_CARD;
1255 chip->capacity[lun] = 0;