drivers/staging/rts5208/xd.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/vmalloc.h>
  27
  28 #include "rtsx.h"
  29 #include "rtsx_transport.h"
  30 #include "rtsx_scsi.h"
  31 #include "rtsx_card.h"
  32 #include "xd.h"
  33
  34 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no);
  35 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff,
  36                         u8 start_page, u8 end_page);
  37
  38 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
  39 {
  40         struct xd_info *xd_card = &(chip->xd_card);
  41
  42         xd_card->err_code = err_code;
  43 }
  44
  45 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
  46 {
  47         struct xd_info *xd_card = &(chip->xd_card);
  48
  49         return (xd_card->err_code == err_code);
  50 }
  51
  52 static int xd_set_init_para(struct rtsx_chip *chip)
  53 {
  54         struct xd_info *xd_card = &(chip->xd_card);
  55         int retval;
  56
  57         if (chip->asic_code)
  58                 xd_card->xd_clock = 47;
  59         else
  60                 xd_card->xd_clock = CLK_50;
  61
  62         retval = switch_clock(chip, xd_card->xd_clock);
  63         if (retval != STATUS_SUCCESS)
  64                 TRACE_RET(chip, STATUS_FAIL);
  65
  66         return STATUS_SUCCESS;
  67 }
  68
  69 static int xd_switch_clock(struct rtsx_chip *chip)
  70 {
  71         struct xd_info *xd_card = &(chip->xd_card);
  72         int retval;
  73
  74         retval = select_card(chip, XD_CARD);
  75         if (retval != STATUS_SUCCESS)
  76                 TRACE_RET(chip, STATUS_FAIL);
  77
  78         retval = switch_clock(chip, xd_card->xd_clock);
  79         if (retval != STATUS_SUCCESS)
  80                 TRACE_RET(chip, STATUS_FAIL);
  81
  82         return STATUS_SUCCESS;
  83 }
  84
  85 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len)
  86 {
  87         int retval, i;
  88         u8 *ptr;
  89
  90         rtsx_init_cmd(chip);
  91
  92         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
  93         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
  94                 XD_TRANSFER_START | XD_READ_ID);
  95         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
  96                 XD_TRANSFER_END);
  97
  98         for (i = 0; i < 4; i++)
  99                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
 100
 101         retval = rtsx_send_cmd(chip, XD_CARD, 20);
 102         if (retval < 0)
 103                 TRACE_RET(chip, STATUS_FAIL);
 104
 105         ptr = rtsx_get_cmd_data(chip) + 1;
 106         if (id_buf && buf_len) {
 107                 if (buf_len > 4)
 108                         buf_len = 4;
 109                 memcpy(id_buf, ptr, buf_len);
 110         }
 111
 112         return STATUS_SUCCESS;
 113 }
 114
 115 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode)
 116 {
 117         struct xd_info *xd_card = &(chip->xd_card);
 118
 119         switch (mode) {
 120         case XD_RW_ADDR:
 121                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
 122                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
 123                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
 124                         0xFF, (u8)(addr >> 8));
 125                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3,
 126                         0xFF, (u8)(addr >> 16));
 127                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 128                         xd_card->addr_cycle | XD_CALC_ECC | XD_BA_NO_TRANSFORM);
 129                 break;
 130
 131         case XD_ERASE_ADDR:
 132                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
 133                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1,
 134                         0xFF, (u8)(addr >> 8));
 135                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
 136                         0xFF, (u8)(addr >> 16));
 137                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 138                         (xd_card->addr_cycle - 1) | XD_CALC_ECC |
 139                         XD_BA_NO_TRANSFORM);
 140                 break;
 141
 142         default:
 143                 break;
 144         }
 145 }
 146
 147 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr,
 148                         u8 *buf, int buf_len)
 149 {
 150         int retval, i;
 151
 152         rtsx_init_cmd(chip);
 153
 154         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 155
 156         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
 157                 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT);
 158         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 159                 XD_TRANSFER_END, XD_TRANSFER_END);
 160
 161         for (i = 0; i < 6; i++)
 162                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i),
 163                         0, 0);
 164         for (i = 0; i < 4; i++)
 165                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i),
 166                         0, 0);
 167         rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
 168
 169         retval = rtsx_send_cmd(chip, XD_CARD, 500);
 170         if (retval < 0)
 171                 TRACE_RET(chip, STATUS_FAIL);
 172
 173         if (buf && buf_len) {
 174                 u8 *ptr = rtsx_get_cmd_data(chip) + 1;
 175
 176                 if (buf_len > 11)
 177                         buf_len = 11;
 178                 memcpy(buf, ptr, buf_len);
 179         }
 180
 181         return STATUS_SUCCESS;
 182 }
 183
 184 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset,
 185                                 u8 *buf, int buf_len)
 186 {
 187         int retval, i;
 188
 189         if (!buf || (buf_len < 0))
 190                 TRACE_RET(chip, STATUS_FAIL);
 191
 192         rtsx_init_cmd(chip);
 193
 194         for (i = 0; i < buf_len; i++)
 195                 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i,
 196                         0, 0);
 197
 198         retval = rtsx_send_cmd(chip, 0, 250);
 199         if (retval < 0) {
 200                 rtsx_clear_xd_error(chip);
 201                 TRACE_RET(chip, STATUS_FAIL);
 202         }
 203
 204         memcpy(buf, rtsx_get_cmd_data(chip), buf_len);
 205
 206         return STATUS_SUCCESS;
 207 }
 208
 209 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf,
 210                 int buf_len)
 211 {
 212         int retval;
 213         u8 reg;
 214
 215         if (!buf || (buf_len < 10))
 216                 TRACE_RET(chip, STATUS_FAIL);
 217
 218         rtsx_init_cmd(chip);
 219
 220         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 221
 222         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 223                 0x01, PINGPONG_BUFFER);
 224         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
 225         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
 226                 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
 227
 228         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 229                 XD_TRANSFER_START | XD_READ_PAGES);
 230         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
 231                 XD_TRANSFER_END);
 232
 233         retval = rtsx_send_cmd(chip, XD_CARD, 250);
 234         if (retval == -ETIMEDOUT) {
 235                 rtsx_clear_xd_error(chip);
 236                 TRACE_RET(chip, STATUS_FAIL);
 237         }
 238
 239         RTSX_READ_REG(chip, XD_PAGE_STATUS, &reg);
 240         if (reg != XD_GPG) {
 241                 rtsx_clear_xd_error(chip);
 242                 TRACE_RET(chip, STATUS_FAIL);
 243         }
 244
 245         RTSX_READ_REG(chip, XD_CTL, &reg);
 246         if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
 247                 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
 248                 if (retval != STATUS_SUCCESS)
 249                         TRACE_RET(chip, STATUS_FAIL);
 250                 if (reg & XD_ECC1_ERROR) {
 251                         u8 ecc_bit, ecc_byte;
 252
 253                         RTSX_READ_REG(chip, XD_ECC_BIT1, &ecc_bit);
 254                         RTSX_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte);
 255
 256                         dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
 257                                 ecc_bit, ecc_byte);
 258                         if (ecc_byte < buf_len) {
 259                                 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
 260                                         buf[ecc_byte]);
 261                                 buf[ecc_byte] ^= (1 << ecc_bit);
 262                                 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
 263                                         buf[ecc_byte]);
 264                         }
 265                 }
 266         } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
 267                 rtsx_clear_xd_error(chip);
 268
 269                 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
 270                 if (retval != STATUS_SUCCESS)
 271                         TRACE_RET(chip, STATUS_FAIL);
 272                 if (reg & XD_ECC2_ERROR) {
 273                         u8 ecc_bit, ecc_byte;
 274
 275                         RTSX_READ_REG(chip, XD_ECC_BIT2, &ecc_bit);
 276                         RTSX_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte);
 277
 278                         dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
 279                                 ecc_bit, ecc_byte);
 280                         if (ecc_byte < buf_len) {
 281                                 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
 282                                         buf[ecc_byte]);
 283                                 buf[ecc_byte] ^= (1 << ecc_bit);
 284                                 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
 285                                         buf[ecc_byte]);
 286                         }
 287                 }
 288         } else {
 289                 rtsx_clear_xd_error(chip);
 290                 TRACE_RET(chip, STATUS_FAIL);
 291         }
 292
 293         return STATUS_SUCCESS;
 294 }
 295
 296 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip)
 297 {
 298         if (CHECK_PID(chip, 0x5208)) {
 299                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
 300                         XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
 301                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
 302                         XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
 303                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
 304                         XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
 305                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
 306                         XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
 307                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
 308                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
 309                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
 310                         MS_D5_PD | MS_D4_PD);
 311         } else if (CHECK_PID(chip, 0x5288)) {
 312                 if (CHECK_BARO_PKG(chip, QFN)) {
 313                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
 314                                 0xFF, 0x55);
 315                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
 316                                 0xFF, 0x55);
 317                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
 318                                 0xFF, 0x4B);
 319                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
 320                                 0xFF, 0x69);
 321                 }
 322         }
 323 }
 324
 325 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip)
 326 {
 327         if (CHECK_BARO_PKG(chip, QFN)) {
 328                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
 329                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 330                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
 331                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 332         }
 333 }
 334
 335 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip)
 336 {
 337         if (CHECK_PID(chip, 0x5208)) {
 338                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
 339                         XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
 340                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
 341                         XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
 342                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
 343                         XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU);
 344                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
 345                         XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD);
 346                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
 347                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
 348                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
 349                         MS_D5_PD | MS_D4_PD);
 350         } else if (CHECK_PID(chip, 0x5288)) {
 351                 if (CHECK_BARO_PKG(chip, QFN)) {
 352                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
 353                                 0xFF, 0x55);
 354                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
 355                                 0xFF, 0x55);
 356                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
 357                                 0xFF, 0x53);
 358                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
 359                                 0xFF, 0xA9);
 360                 }
 361         }
 362 }
 363
 364 static int xd_pull_ctl_disable(struct rtsx_chip *chip)
 365 {
 366         if (CHECK_PID(chip, 0x5208)) {
 367                 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
 368                         XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
 369                 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
 370                         XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
 371                 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
 372                         XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
 373                 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
 374                         XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
 375                 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
 376                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
 377                 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
 378         } else if (CHECK_PID(chip, 0x5288)) {
 379                 if (CHECK_BARO_PKG(chip, QFN)) {
 380                         RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
 381                         RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
 382                         RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
 383                         RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
 384                 }
 385         }
 386
 387         return STATUS_SUCCESS;
 388 }
 389
 390 static int reset_xd(struct rtsx_chip *chip)
 391 {
 392         struct xd_info *xd_card = &(chip->xd_card);
 393         int retval, i, j;
 394         u8 *ptr, id_buf[4], redunt[11];
 395
 396         retval = select_card(chip, XD_CARD);
 397         if (retval != STATUS_SUCCESS)
 398                 TRACE_RET(chip, STATUS_FAIL);
 399
 400         rtsx_init_cmd(chip);
 401
 402         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
 403                 XD_PGSTS_NOT_FF);
 404         if (chip->asic_code) {
 405                 if (!CHECK_PID(chip, 0x5288))
 406                         xd_fill_pull_ctl_disable(chip);
 407                 else
 408                         xd_fill_pull_ctl_stage1_barossa(chip);
 409         } else {
 410                 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 411                         (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20);
 412         }
 413
 414         if (!chip->ft2_fast_mode)
 415                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT,
 416                         XD_NO_AUTO_PWR_OFF, 0);
 417
 418         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
 419
 420         retval = rtsx_send_cmd(chip, XD_CARD, 100);
 421         if (retval < 0)
 422                 TRACE_RET(chip, STATUS_FAIL);
 423
 424         if (!chip->ft2_fast_mode) {
 425                 retval = card_power_off(chip, XD_CARD);
 426                 if (retval != STATUS_SUCCESS)
 427                         TRACE_RET(chip, STATUS_FAIL);
 428
 429                 wait_timeout(250);
 430
 431                 rtsx_init_cmd(chip);
 432
 433                 if (chip->asic_code) {
 434                         xd_fill_pull_ctl_enable(chip);
 435                 } else {
 436                         rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 437                                 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) |
 438                                 0x20);
 439                 }
 440
 441                 retval = rtsx_send_cmd(chip, XD_CARD, 100);
 442                 if (retval < 0)
 443                         TRACE_RET(chip, STATUS_FAIL);
 444
 445                 retval = card_power_on(chip, XD_CARD);
 446                 if (retval != STATUS_SUCCESS)
 447                         TRACE_RET(chip, STATUS_FAIL);
 448
 449 #ifdef SUPPORT_OCP
 450                 wait_timeout(50);
 451                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
 452                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
 453                                 chip->ocp_stat);
 454                         TRACE_RET(chip, STATUS_FAIL);
 455                 }
 456 #endif
 457         }
 458
 459         rtsx_init_cmd(chip);
 460
 461         if (chip->ft2_fast_mode) {
 462                 if (chip->asic_code) {
 463                         xd_fill_pull_ctl_enable(chip);
 464                 } else {
 465                         rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 466                                 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) |
 467                                 0x20);
 468                 }
 469         }
 470
 471         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
 472         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
 473
 474         retval = rtsx_send_cmd(chip, XD_CARD, 100);
 475         if (retval < 0)
 476                 TRACE_RET(chip, STATUS_FAIL);
 477
 478         if (!chip->ft2_fast_mode)
 479                 wait_timeout(200);
 480
 481         retval = xd_set_init_para(chip);
 482         if (retval != STATUS_SUCCESS)
 483                 TRACE_RET(chip, STATUS_FAIL);
 484
 485         /* Read ID to check if the timing setting is right */
 486         for (i = 0; i < 4; i++) {
 487                 rtsx_init_cmd(chip);
 488
 489                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
 490                         XD_TIME_SETUP_STEP * 3 +
 491                         XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i);
 492                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
 493                         XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 + i) +
 494                         XD_TIME_RWN_STEP * (3 + i));
 495
 496                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 497                         XD_TRANSFER_START | XD_RESET);
 498                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 499                         XD_TRANSFER_END, XD_TRANSFER_END);
 500
 501                 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
 502                 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
 503
 504                 retval = rtsx_send_cmd(chip, XD_CARD, 100);
 505                 if (retval < 0)
 506                         TRACE_RET(chip, STATUS_FAIL);
 507
 508                 ptr = rtsx_get_cmd_data(chip) + 1;
 509
 510                 dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n",
 511                         ptr[0], ptr[1]);
 512
 513                 if (((ptr[0] & READY_FLAG) != READY_STATE) ||
 514                         !(ptr[1] & XD_RDY))
 515                         continue;
 516
 517                 retval = xd_read_id(chip, READ_ID, id_buf, 4);
 518                 if (retval != STATUS_SUCCESS)
 519                         TRACE_RET(chip, STATUS_FAIL);
 520
 521                 dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
 522                         id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 523
 524                 xd_card->device_code = id_buf[1];
 525
 526                 /* Check if the xD card is supported */
 527                 switch (xd_card->device_code) {
 528                 case XD_4M_X8_512_1:
 529                 case XD_4M_X8_512_2:
 530                         xd_card->block_shift = 4;
 531                         xd_card->page_off = 0x0F;
 532                         xd_card->addr_cycle = 3;
 533                         xd_card->zone_cnt = 1;
 534                         xd_card->capacity = 8000;
 535                         XD_SET_4MB(xd_card);
 536                         break;
 537                 case XD_8M_X8_512:
 538                         xd_card->block_shift = 4;
 539                         xd_card->page_off = 0x0F;
 540                         xd_card->addr_cycle = 3;
 541                         xd_card->zone_cnt = 1;
 542                         xd_card->capacity = 16000;
 543                         break;
 544                 case XD_16M_X8_512:
 545                         XD_PAGE_512(xd_card);
 546                         xd_card->addr_cycle = 3;
 547                         xd_card->zone_cnt = 1;
 548                         xd_card->capacity = 32000;
 549                         break;
 550                 case XD_32M_X8_512:
 551                         XD_PAGE_512(xd_card);
 552                         xd_card->addr_cycle = 3;
 553                         xd_card->zone_cnt = 2;
 554                         xd_card->capacity = 64000;
 555                         break;
 556                 case XD_64M_X8_512:
 557                         XD_PAGE_512(xd_card);
 558                         xd_card->addr_cycle = 4;
 559                         xd_card->zone_cnt = 4;
 560                         xd_card->capacity = 128000;
 561                         break;
 562                 case XD_128M_X8_512:
 563                         XD_PAGE_512(xd_card);
 564                         xd_card->addr_cycle = 4;
 565                         xd_card->zone_cnt = 8;
 566                         xd_card->capacity = 256000;
 567                         break;
 568                 case XD_256M_X8_512:
 569                         XD_PAGE_512(xd_card);
 570                         xd_card->addr_cycle = 4;
 571                         xd_card->zone_cnt = 16;
 572                         xd_card->capacity = 512000;
 573                         break;
 574                 case XD_512M_X8:
 575                         XD_PAGE_512(xd_card);
 576                         xd_card->addr_cycle = 4;
 577                         xd_card->zone_cnt = 32;
 578                         xd_card->capacity = 1024000;
 579                         break;
 580                 case xD_1G_X8_512:
 581                         XD_PAGE_512(xd_card);
 582                         xd_card->addr_cycle = 4;
 583                         xd_card->zone_cnt = 64;
 584                         xd_card->capacity = 2048000;
 585                         break;
 586                 case xD_2G_X8_512:
 587                         XD_PAGE_512(xd_card);
 588                         xd_card->addr_cycle = 4;
 589                         xd_card->zone_cnt = 128;
 590                         xd_card->capacity = 4096000;
 591                         break;
 592                 default:
 593                         continue;
 594                 }
 595
 596                 /* Confirm timing setting */
 597                 for (j = 0; j < 10; j++) {
 598                         retval = xd_read_id(chip, READ_ID, id_buf, 4);
 599                         if (retval != STATUS_SUCCESS)
 600                                 TRACE_RET(chip, STATUS_FAIL);
 601
 602                         if (id_buf[1] != xd_card->device_code)
 603                                 break;
 604                 }
 605
 606                 if (j == 10)
 607                         break;
 608         }
 609
 610         if (i == 4) {
 611                 xd_card->block_shift = 0;
 612                 xd_card->page_off = 0;
 613                 xd_card->addr_cycle = 0;
 614                 xd_card->capacity = 0;
 615
 616                 TRACE_RET(chip, STATUS_FAIL);
 617         }
 618
 619         retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
 620         if (retval != STATUS_SUCCESS)
 621                 TRACE_RET(chip, STATUS_FAIL);
 622         dev_dbg(rtsx_dev(chip), "READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
 623                 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 624         if (id_buf[2] != XD_ID_CODE)
 625                 TRACE_RET(chip, STATUS_FAIL);
 626
 627         /* Search CIS block */
 628         for (i = 0; i < 24; i++) {
 629                 u32 page_addr;
 630
 631                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS)
 632                         TRACE_RET(chip, STATUS_FAIL);
 633
 634                 page_addr = (u32)i << xd_card->block_shift;
 635
 636                 for (j = 0; j < 3; j++) {
 637                         retval = xd_read_redundant(chip, page_addr, redunt, 11);
 638                         if (retval == STATUS_SUCCESS)
 639                                 break;
 640                 }
 641                 if (j == 3)
 642                         continue;
 643
 644                 if (redunt[BLOCK_STATUS] != XD_GBLK)
 645                         continue;
 646
 647                 j = 0;
 648                 if (redunt[PAGE_STATUS] != XD_GPG) {
 649                         for (j = 1; j <= 8; j++) {
 650                                 retval = xd_read_redundant(chip, page_addr + j,
 651                                                         redunt, 11);
 652                                 if (retval == STATUS_SUCCESS) {
 653                                         if (redunt[PAGE_STATUS] == XD_GPG)
 654                                                 break;
 655                                 }
 656                         }
 657
 658                         if (j == 9)
 659                                 break;
 660                 }
 661
 662                 /* Check CIS data */
 663                 if ((redunt[BLOCK_STATUS] == XD_GBLK) &&
 664                         (redunt[PARITY] & XD_BA1_ALL0)) {
 665                         u8 buf[10];
 666
 667                         page_addr += j;
 668
 669                         retval = xd_read_cis(chip, page_addr, buf, 10);
 670                         if (retval != STATUS_SUCCESS)
 671                                 TRACE_RET(chip, STATUS_FAIL);
 672
 673                         if ((buf[0] == 0x01) && (buf[1] == 0x03) &&
 674                                 (buf[2] == 0xD9)
 675                                         && (buf[3] == 0x01) && (buf[4] == 0xFF)
 676                                         && (buf[5] == 0x18) && (buf[6] == 0x02)
 677                                         && (buf[7] == 0xDF) && (buf[8] == 0x01)
 678                                         && (buf[9] == 0x20)) {
 679                                 xd_card->cis_block = (u16)i;
 680                         }
 681                 }
 682
 683                 break;
 684         }
 685
 686         dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block);
 687         if (xd_card->cis_block == 0xFFFF)
 688                 TRACE_RET(chip, STATUS_FAIL);
 689
 690         chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
 691
 692         return STATUS_SUCCESS;
 693 }
 694
 695 static int xd_check_data_blank(u8 *redunt)
 696 {
 697         int i;
 698
 699         for (i = 0; i < 6; i++) {
 700                 if (redunt[PAGE_STATUS + i] != 0xFF)
 701                         return 0;
 702         }
 703
 704         if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1))
 705                 != (XD_ECC1_ALL1 | XD_ECC2_ALL1))
 706                 return 0;
 707
 708
 709         for (i = 0; i < 4; i++) {
 710                 if (redunt[RESERVED0 + i] != 0xFF)
 711                         return 0;
 712         }
 713
 714         return 1;
 715 }
 716
 717 static u16 xd_load_log_block_addr(u8 *redunt)
 718 {
 719         u16 addr = 0xFFFF;
 720
 721         if (redunt[PARITY] & XD_BA1_BA2_EQL)
 722                 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
 723                         redunt[BLOCK_ADDR1_L];
 724         else if (redunt[PARITY] & XD_BA1_VALID)
 725                 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
 726                         redunt[BLOCK_ADDR1_L];
 727         else if (redunt[PARITY] & XD_BA2_VALID)
 728                 addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) |
 729                         redunt[BLOCK_ADDR2_L];
 730
 731         return addr;
 732 }
 733
 734 static int xd_init_l2p_tbl(struct rtsx_chip *chip)
 735 {
 736         struct xd_info *xd_card = &(chip->xd_card);
 737         int size, i;
 738
 739         dev_dbg(rtsx_dev(chip), "xd_init_l2p_tbl: zone_cnt = %d\n",
 740                 xd_card->zone_cnt);
 741
 742         if (xd_card->zone_cnt < 1)
 743                 TRACE_RET(chip, STATUS_FAIL);
 744
 745         size = xd_card->zone_cnt * sizeof(struct zone_entry);
 746         dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size);
 747
 748         xd_card->zone = vmalloc(size);
 749         if (!xd_card->zone)
 750                 TRACE_RET(chip, STATUS_ERROR);
 751
 752         for (i = 0; i < xd_card->zone_cnt; i++) {
 753                 xd_card->zone[i].build_flag = 0;
 754                 xd_card->zone[i].l2p_table = NULL;
 755                 xd_card->zone[i].free_table = NULL;
 756                 xd_card->zone[i].get_index = 0;
 757                 xd_card->zone[i].set_index = 0;
 758                 xd_card->zone[i].unused_blk_cnt = 0;
 759         }
 760
 761         return STATUS_SUCCESS;
 762 }
 763
 764 static inline void free_zone(struct zone_entry *zone)
 765 {
 766         if (!zone)
 767                 return;
 768
 769         zone->build_flag = 0;
 770         zone->set_index = 0;
 771         zone->get_index = 0;
 772         zone->unused_blk_cnt = 0;
 773         if (zone->l2p_table) {
 774                 vfree(zone->l2p_table);
 775                 zone->l2p_table = NULL;
 776         }
 777         if (zone->free_table) {
 778                 vfree(zone->free_table);
 779                 zone->free_table = NULL;
 780         }
 781 }
 782
 783 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk)
 784 {
 785         struct xd_info *xd_card = &(chip->xd_card);
 786         struct zone_entry *zone;
 787         int zone_no;
 788
 789         zone_no = (int)phy_blk >> 10;
 790         if (zone_no >= xd_card->zone_cnt) {
 791                 dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n",
 792                         zone_no, xd_card->zone_cnt);
 793                 return;
 794         }
 795         zone = &(xd_card->zone[zone_no]);
 796
 797         if (zone->free_table == NULL) {
 798                 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
 799                         return;
 800         }
 801
 802         if ((zone->set_index >= XD_FREE_TABLE_CNT)
 803                         || (zone->set_index < 0)) {
 804                 free_zone(zone);
 805                 dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n");
 806                 return;
 807         }
 808
 809         dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n",
 810                 zone->set_index);
 811
 812         zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff);
 813         if (zone->set_index >= XD_FREE_TABLE_CNT)
 814                 zone->set_index = 0;
 815         zone->unused_blk_cnt++;
 816 }
 817
 818 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no)
 819 {
 820         struct xd_info *xd_card = &(chip->xd_card);
 821         struct zone_entry *zone;
 822         u32 phy_blk;
 823
 824         if (zone_no >= xd_card->zone_cnt) {
 825                 dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n",
 826                         zone_no, xd_card->zone_cnt);
 827                 return BLK_NOT_FOUND;
 828         }
 829         zone = &(xd_card->zone[zone_no]);
 830
 831         if ((zone->unused_blk_cnt == 0) ||
 832                 (zone->set_index == zone->get_index)) {
 833                 free_zone(zone);
 834                 dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n");
 835                 return BLK_NOT_FOUND;
 836         }
 837         if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
 838                 free_zone(zone);
 839                 dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n");
 840                 return BLK_NOT_FOUND;
 841         }
 842
 843         dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n",
 844                 zone->get_index);
 845
 846         phy_blk = zone->free_table[zone->get_index];
 847         zone->free_table[zone->get_index++] = 0xFFFF;
 848         if (zone->get_index >= XD_FREE_TABLE_CNT)
 849                 zone->get_index = 0;
 850         zone->unused_blk_cnt--;
 851
 852         phy_blk += ((u32)(zone_no) << 10);
 853         return phy_blk;
 854 }
 855
 856 static void xd_set_l2p_tbl(struct rtsx_chip *chip,
 857                         int zone_no, u16 log_off, u16 phy_off)
 858 {
 859         struct xd_info *xd_card = &(chip->xd_card);
 860         struct zone_entry *zone;
 861
 862         zone = &(xd_card->zone[zone_no]);
 863         zone->l2p_table[log_off] = phy_off;
 864 }
 865
 866 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off)
 867 {
 868         struct xd_info *xd_card = &(chip->xd_card);
 869         struct zone_entry *zone;
 870         int retval;
 871
 872         zone = &(xd_card->zone[zone_no]);
 873         if (zone->l2p_table[log_off] == 0xFFFF) {
 874                 u32 phy_blk = 0;
 875                 int i;
 876
 877 #ifdef XD_DELAY_WRITE
 878                 retval = xd_delay_write(chip);
 879                 if (retval != STATUS_SUCCESS) {
 880                         dev_dbg(rtsx_dev(chip), "In xd_get_l2p_tbl, delay write fail!\n");
 881                         return BLK_NOT_FOUND;
 882                 }
 883 #endif
 884
 885                 if (zone->unused_blk_cnt <= 0) {
 886                         dev_dbg(rtsx_dev(chip), "No unused block!\n");
 887                         return BLK_NOT_FOUND;
 888                 }
 889
 890                 for (i = 0; i < zone->unused_blk_cnt; i++) {
 891                         phy_blk = xd_get_unused_block(chip, zone_no);
 892                         if (phy_blk == BLK_NOT_FOUND) {
 893                                 dev_dbg(rtsx_dev(chip), "No unused block available!\n");
 894                                 return BLK_NOT_FOUND;
 895                         }
 896
 897                         retval = xd_init_page(chip, phy_blk, log_off,
 898                                         0, xd_card->page_off + 1);
 899                         if (retval == STATUS_SUCCESS)
 900                                 break;
 901                 }
 902                 if (i >= zone->unused_blk_cnt) {
 903                         dev_dbg(rtsx_dev(chip), "No good unused block available!\n");
 904                         return BLK_NOT_FOUND;
 905                 }
 906
 907                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF));
 908                 return phy_blk;
 909         }
 910
 911         return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10);
 912 }
 913
 914 int reset_xd_card(struct rtsx_chip *chip)
 915 {
 916         struct xd_info *xd_card = &(chip->xd_card);
 917         int retval;
 918
 919         memset(xd_card, 0, sizeof(struct xd_info));
 920
 921         xd_card->block_shift = 0;
 922         xd_card->page_off = 0;
 923         xd_card->addr_cycle = 0;
 924         xd_card->capacity = 0;
 925         xd_card->zone_cnt = 0;
 926         xd_card->cis_block = 0xFFFF;
 927         xd_card->delay_write.delay_write_flag = 0;
 928
 929         retval = enable_card_clock(chip, XD_CARD);
 930         if (retval != STATUS_SUCCESS)
 931                 TRACE_RET(chip, STATUS_FAIL);
 932
 933         retval = reset_xd(chip);
 934         if (retval != STATUS_SUCCESS)
 935                 TRACE_RET(chip, STATUS_FAIL);
 936
 937         retval = xd_init_l2p_tbl(chip);
 938         if (retval != STATUS_SUCCESS)
 939                 TRACE_RET(chip, STATUS_FAIL);
 940
 941         return STATUS_SUCCESS;
 942 }
 943
 944 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk)
 945 {
 946         struct xd_info *xd_card = &(chip->xd_card);
 947         int retval;
 948         u32 page_addr;
 949         u8 reg = 0;
 950
 951         dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk);
 952
 953         if (phy_blk == BLK_NOT_FOUND)
 954                 TRACE_RET(chip, STATUS_FAIL);
 955
 956         rtsx_init_cmd(chip);
 957
 958         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
 959         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
 960         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
 961         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
 962         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
 963         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
 964         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
 965         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
 966         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
 967         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
 968
 969         page_addr = phy_blk << xd_card->block_shift;
 970
 971         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 972
 973         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
 974                 xd_card->page_off + 1);
 975
 976         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 977                 XD_TRANSFER_START | XD_WRITE_REDUNDANT);
 978         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 979                 XD_TRANSFER_END, XD_TRANSFER_END);
 980
 981         retval = rtsx_send_cmd(chip, XD_CARD, 500);
 982         if (retval < 0) {
 983                 rtsx_clear_xd_error(chip);
 984                 rtsx_read_register(chip, XD_DAT, &reg);
 985                 if (reg & PROGRAM_ERROR)
 986                         xd_set_err_code(chip, XD_PRG_ERROR);
 987                 else
 988                         xd_set_err_code(chip, XD_TO_ERROR);
 989                 TRACE_RET(chip, STATUS_FAIL);
 990         }
 991
 992         return STATUS_SUCCESS;
 993 }
 994
 995 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk,
 996                         u16 logoff, u8 start_page, u8 end_page)
 997 {
 998         struct xd_info *xd_card = &(chip->xd_card);
 999         int retval;
1000         u32 page_addr;
1001         u8 reg = 0;
1002
1003         dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk);
1004
1005         if (start_page > end_page)
1006                 TRACE_RET(chip, STATUS_FAIL);
1007         if (phy_blk == BLK_NOT_FOUND)
1008                 TRACE_RET(chip, STATUS_FAIL);
1009
1010         rtsx_init_cmd(chip);
1011
1012         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1013         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1014         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1015                 0xFF, (u8)(logoff >> 8));
1016         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1017
1018         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1019
1020         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1021
1022         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG,
1023                 XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1024
1025         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT,
1026                 0xFF, (end_page - start_page));
1027
1028         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1029                 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1030         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1031                 XD_TRANSFER_END, XD_TRANSFER_END);
1032
1033         retval = rtsx_send_cmd(chip, XD_CARD, 500);
1034         if (retval < 0) {
1035                 rtsx_clear_xd_error(chip);
1036                 rtsx_read_register(chip, XD_DAT, &reg);
1037                 if (reg & PROGRAM_ERROR) {
1038                         xd_mark_bad_block(chip, phy_blk);
1039                         xd_set_err_code(chip, XD_PRG_ERROR);
1040                 } else {
1041                         xd_set_err_code(chip, XD_TO_ERROR);
1042                 }
1043                 TRACE_RET(chip, STATUS_FAIL);
1044         }
1045
1046         return STATUS_SUCCESS;
1047 }
1048
1049 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk,
1050                         u8 start_page, u8 end_page)
1051 {
1052         struct xd_info *xd_card = &(chip->xd_card);
1053         u32 old_page, new_page;
1054         u8 i, reg = 0;
1055         int retval;
1056
1057         dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n",
1058                 old_blk, new_blk);
1059
1060         if (start_page > end_page)
1061                 TRACE_RET(chip, STATUS_FAIL);
1062
1063         if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1064                 TRACE_RET(chip, STATUS_FAIL);
1065
1066         old_page = (old_blk << xd_card->block_shift) + start_page;
1067         new_page = (new_blk << xd_card->block_shift) + start_page;
1068
1069         XD_CLR_BAD_NEWBLK(xd_card);
1070
1071         RTSX_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
1072
1073         for (i = start_page; i < end_page; i++) {
1074                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1075                         rtsx_clear_xd_error(chip);
1076                         xd_set_err_code(chip, XD_NO_CARD);
1077                         TRACE_RET(chip, STATUS_FAIL);
1078                 }
1079
1080                 rtsx_init_cmd(chip);
1081
1082                 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1083
1084                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1085                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1086                         XD_AUTO_CHK_DATA_STATUS, 0);
1087                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1088                         XD_TRANSFER_START | XD_READ_PAGES);
1089                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1090                         XD_TRANSFER_END, XD_TRANSFER_END);
1091
1092                 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1093                 if (retval < 0) {
1094                         rtsx_clear_xd_error(chip);
1095                         reg = 0;
1096                         rtsx_read_register(chip, XD_CTL, &reg);
1097                         if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1098                                 wait_timeout(100);
1099
1100                                 if (detect_card_cd(chip,
1101                                         XD_CARD) != STATUS_SUCCESS) {
1102                                         xd_set_err_code(chip, XD_NO_CARD);
1103                                         TRACE_RET(chip, STATUS_FAIL);
1104                                 }
1105
1106                                 if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1107                                                 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1108                                         || ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1109                                                 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1110                                         rtsx_write_register(chip,
1111                                                         XD_PAGE_STATUS, 0xFF,
1112                                                         XD_BPG);
1113                                         rtsx_write_register(chip,
1114                                                         XD_BLOCK_STATUS, 0xFF,
1115                                                         XD_GBLK);
1116                                         XD_SET_BAD_OLDBLK(xd_card);
1117                                         dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n",
1118                                                 old_blk);
1119                                 }
1120                         } else {
1121                                 xd_set_err_code(chip, XD_TO_ERROR);
1122                                 TRACE_RET(chip, STATUS_FAIL);
1123                         }
1124                 }
1125
1126                 if (XD_CHK_BAD_OLDBLK(xd_card))
1127                         rtsx_clear_xd_error(chip);
1128
1129                 rtsx_init_cmd(chip);
1130
1131                 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1132                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1133                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1134                              XD_TRANSFER_START | XD_WRITE_PAGES);
1135                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1136                         XD_TRANSFER_END, XD_TRANSFER_END);
1137
1138                 retval = rtsx_send_cmd(chip, XD_CARD, 300);
1139                 if (retval < 0) {
1140                         rtsx_clear_xd_error(chip);
1141                         reg = 0;
1142                         rtsx_read_register(chip, XD_DAT, &reg);
1143                         if (reg & PROGRAM_ERROR) {
1144                                 xd_mark_bad_block(chip, new_blk);
1145                                 xd_set_err_code(chip, XD_PRG_ERROR);
1146                                 XD_SET_BAD_NEWBLK(xd_card);
1147                         } else {
1148                                 xd_set_err_code(chip, XD_TO_ERROR);
1149                         }
1150                         TRACE_RET(chip, STATUS_FAIL);
1151                 }
1152
1153                 old_page++;
1154                 new_page++;
1155         }
1156
1157         return STATUS_SUCCESS;
1158 }
1159
1160 static int xd_reset_cmd(struct rtsx_chip *chip)
1161 {
1162         int retval;
1163         u8 *ptr;
1164
1165         rtsx_init_cmd(chip);
1166
1167         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1168                 0xFF, XD_TRANSFER_START | XD_RESET);
1169         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1170                 XD_TRANSFER_END, XD_TRANSFER_END);
1171         rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1172         rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1173
1174         retval = rtsx_send_cmd(chip, XD_CARD, 100);
1175         if (retval < 0)
1176                 TRACE_RET(chip, STATUS_FAIL);
1177
1178         ptr = rtsx_get_cmd_data(chip) + 1;
1179         if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY))
1180                 return STATUS_SUCCESS;
1181
1182         TRACE_RET(chip, STATUS_FAIL);
1183 }
1184
1185 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk)
1186 {
1187         struct xd_info *xd_card = &(chip->xd_card);
1188         u32 page_addr;
1189         u8 reg = 0, *ptr;
1190         int i, retval;
1191
1192         if (phy_blk == BLK_NOT_FOUND)
1193                 TRACE_RET(chip, STATUS_FAIL);
1194
1195         page_addr = phy_blk << xd_card->block_shift;
1196
1197         for (i = 0; i < 3; i++) {
1198                 rtsx_init_cmd(chip);
1199
1200                 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1201
1202                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1203                         XD_TRANSFER_START | XD_ERASE);
1204                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1205                         XD_TRANSFER_END, XD_TRANSFER_END);
1206                 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1207
1208                 retval = rtsx_send_cmd(chip, XD_CARD, 250);
1209                 if (retval < 0) {
1210                         rtsx_clear_xd_error(chip);
1211                         rtsx_read_register(chip, XD_DAT, &reg);
1212                         if (reg & PROGRAM_ERROR) {
1213                                 xd_mark_bad_block(chip, phy_blk);
1214                                 xd_set_err_code(chip, XD_PRG_ERROR);
1215                                 TRACE_RET(chip, STATUS_FAIL);
1216                         } else {
1217                                 xd_set_err_code(chip, XD_ERASE_FAIL);
1218                         }
1219                         retval = xd_reset_cmd(chip);
1220                         if (retval != STATUS_SUCCESS)
1221                                 TRACE_RET(chip, STATUS_FAIL);
1222                         continue;
1223                 }
1224
1225                 ptr = rtsx_get_cmd_data(chip) + 1;
1226                 if (*ptr & PROGRAM_ERROR) {
1227                         xd_mark_bad_block(chip, phy_blk);
1228                         xd_set_err_code(chip, XD_PRG_ERROR);
1229                         TRACE_RET(chip, STATUS_FAIL);
1230                 }
1231
1232                 return STATUS_SUCCESS;
1233         }
1234
1235         xd_mark_bad_block(chip, phy_blk);
1236         xd_set_err_code(chip, XD_ERASE_FAIL);
1237         TRACE_RET(chip, STATUS_FAIL);
1238 }
1239
1240
1241 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)
1242 {
1243         struct xd_info *xd_card = &(chip->xd_card);
1244         struct zone_entry *zone;
1245         int retval;
1246         u32 start, end, i;
1247         u16 max_logoff, cur_fst_page_logoff;
1248         u16 cur_lst_page_logoff, ent_lst_page_logoff;
1249         u8 redunt[11];
1250
1251         dev_dbg(rtsx_dev(chip), "xd_build_l2p_tbl: %d\n", zone_no);
1252
1253         if (xd_card->zone == NULL) {
1254                 retval = xd_init_l2p_tbl(chip);
1255                 if (retval != STATUS_SUCCESS)
1256                         return retval;
1257         }
1258
1259         if (xd_card->zone[zone_no].build_flag) {
1260                 dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n",
1261                         zone_no);
1262                 return STATUS_SUCCESS;
1263         }
1264
1265         zone = &(xd_card->zone[zone_no]);
1266
1267         if (zone->l2p_table == NULL) {
1268                 zone->l2p_table = vmalloc(2000);
1269                 if (zone->l2p_table == NULL)
1270                         TRACE_GOTO(chip, Build_Fail);
1271         }
1272         memset((u8 *)(zone->l2p_table), 0xff, 2000);
1273
1274         if (zone->free_table == NULL) {
1275                 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1276                 if (zone->free_table == NULL)
1277                         TRACE_GOTO(chip, Build_Fail);
1278         }
1279         memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1280
1281         if (zone_no == 0) {
1282                 if (xd_card->cis_block == 0xFFFF)
1283                         start = 0;
1284                 else
1285                         start = xd_card->cis_block + 1;
1286                 if (XD_CHK_4MB(xd_card)) {
1287                         end = 0x200;
1288                         max_logoff = 499;
1289                 } else {
1290                         end = 0x400;
1291                         max_logoff = 999;
1292                 }
1293         } else {
1294                 start = (u32)(zone_no) << 10;
1295                 end = (u32)(zone_no + 1) << 10;
1296                 max_logoff = 999;
1297         }
1298
1299         dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n",
1300                 start, end);
1301
1302         zone->set_index = zone->get_index = 0;
1303         zone->unused_blk_cnt = 0;
1304
1305         for (i = start; i < end; i++) {
1306                 u32 page_addr = i << xd_card->block_shift;
1307                 u32 phy_block;
1308
1309                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1310                 if (retval != STATUS_SUCCESS)
1311                         continue;
1312
1313                 if (redunt[BLOCK_STATUS] != 0xFF) {
1314                         dev_dbg(rtsx_dev(chip), "bad block\n");
1315                         continue;
1316                 }
1317
1318                 if (xd_check_data_blank(redunt)) {
1319                         dev_dbg(rtsx_dev(chip), "blank block\n");
1320                         xd_set_unused_block(chip, i);
1321                         continue;
1322                 }
1323
1324                 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1325                 if ((cur_fst_page_logoff == 0xFFFF) ||
1326                         (cur_fst_page_logoff > max_logoff)) {
1327                         retval = xd_erase_block(chip, i);
1328                         if (retval == STATUS_SUCCESS)
1329                                 xd_set_unused_block(chip, i);
1330                         continue;
1331                 }
1332
1333                 if ((zone_no == 0) && (cur_fst_page_logoff == 0) &&
1334                         (redunt[PAGE_STATUS] != XD_GPG))
1335                         XD_SET_MBR_FAIL(xd_card);
1336
1337                 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1338                         zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1339                         continue;
1340                 }
1341
1342                 phy_block = zone->l2p_table[cur_fst_page_logoff] +
1343                         ((u32)((zone_no) << 10));
1344
1345                 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1346
1347                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1348                 if (retval != STATUS_SUCCESS)
1349                         continue;
1350
1351                 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1352                 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1353                         int m;
1354
1355                         page_addr = ((phy_block + 1) <<
1356                                 xd_card->block_shift) - 1;
1357
1358                         for (m = 0; m < 3; m++) {
1359                                 retval = xd_read_redundant(chip, page_addr,
1360                                                         redunt, 11);
1361                                 if (retval == STATUS_SUCCESS)
1362                                         break;
1363                         }
1364
1365                         if (m == 3) {
1366                                 zone->l2p_table[cur_fst_page_logoff] =
1367                                         (u16)(i & 0x3FF);
1368                                 retval = xd_erase_block(chip, phy_block);
1369                                 if (retval == STATUS_SUCCESS)
1370                                         xd_set_unused_block(chip, phy_block);
1371                                 continue;
1372                         }
1373
1374                         ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1375                         if (ent_lst_page_logoff != cur_fst_page_logoff) {
1376                                 zone->l2p_table[cur_fst_page_logoff] =
1377                                         (u16)(i & 0x3FF);
1378                                 retval = xd_erase_block(chip, phy_block);
1379                                 if (retval == STATUS_SUCCESS)
1380                                         xd_set_unused_block(chip, phy_block);
1381                                 continue;
1382                         } else {
1383                                 retval = xd_erase_block(chip, i);
1384                                 if (retval == STATUS_SUCCESS)
1385                                         xd_set_unused_block(chip, i);
1386                         }
1387                 } else {
1388                         retval = xd_erase_block(chip, i);
1389                         if (retval == STATUS_SUCCESS)
1390                                 xd_set_unused_block(chip, i);
1391                 }
1392         }
1393
1394         if (XD_CHK_4MB(xd_card))
1395                 end = 500;
1396         else
1397                 end = 1000;
1398
1399         i = 0;
1400         for (start = 0; start < end; start++) {
1401                 if (zone->l2p_table[start] == 0xFFFF)
1402                         i++;
1403         }
1404
1405         dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n",
1406                 end, i);
1407         dev_dbg(rtsx_dev(chip), "Total unused block: %d\n",
1408                 zone->unused_blk_cnt);
1409
1410         if ((zone->unused_blk_cnt - i) < 1)
1411                 chip->card_wp |= XD_CARD;
1412
1413         zone->build_flag = 1;
1414
1415         return STATUS_SUCCESS;
1416
1417 Build_Fail:
1418         if (zone->l2p_table) {
1419                 vfree(zone->l2p_table);
1420                 zone->l2p_table = NULL;
1421         }
1422         if (zone->free_table) {
1423                 vfree(zone->free_table);
1424                 zone->free_table = NULL;
1425         }
1426
1427         return STATUS_FAIL;
1428 }
1429
1430 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd)
1431 {
1432         int retval;
1433
1434         rtsx_init_cmd(chip);
1435
1436         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1437         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1438                 XD_TRANSFER_START | XD_SET_CMD);
1439         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1440                 XD_TRANSFER_END, XD_TRANSFER_END);
1441
1442         retval = rtsx_send_cmd(chip, XD_CARD, 200);
1443         if (retval < 0)
1444                 TRACE_RET(chip, STATUS_FAIL);
1445
1446         return STATUS_SUCCESS;
1447 }
1448
1449 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk,
1450                                 u32 log_blk, u8 start_page, u8 end_page,
1451                                 u8 *buf, unsigned int *index,
1452                                 unsigned int *offset)
1453 {
1454         struct xd_info *xd_card = &(chip->xd_card);
1455         u32 page_addr, new_blk;
1456         u16 log_off;
1457         u8 reg_val, page_cnt;
1458         int zone_no, retval, i;
1459
1460         if (start_page > end_page)
1461                 TRACE_RET(chip, STATUS_FAIL);
1462
1463         page_cnt = end_page - start_page;
1464         zone_no = (int)(log_blk / 1000);
1465         log_off = (u16)(log_blk % 1000);
1466
1467         if ((phy_blk & 0x3FF) == 0x3FF) {
1468                 for (i = 0; i < 256; i++) {
1469                         page_addr = ((u32)i) << xd_card->block_shift;
1470
1471                         retval = xd_read_redundant(chip, page_addr, NULL, 0);
1472                         if (retval == STATUS_SUCCESS)
1473                                 break;
1474
1475                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1476                                 xd_set_err_code(chip, XD_NO_CARD);
1477                                 TRACE_RET(chip, STATUS_FAIL);
1478                         }
1479                 }
1480         }
1481
1482         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1483
1484         rtsx_init_cmd(chip);
1485
1486         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1487         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1488         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1489         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1490         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1491                         XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1492
1493         trans_dma_enable(chip->srb->sc_data_direction, chip,
1494                         page_cnt * 512, DMA_512);
1495
1496         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1497                 XD_TRANSFER_START | XD_READ_PAGES);
1498         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1499                 XD_TRANSFER_END | XD_PPB_EMPTY, XD_TRANSFER_END | XD_PPB_EMPTY);
1500
1501         rtsx_send_cmd_no_wait(chip);
1502
1503         retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1504                                         scsi_sg_count(chip->srb),
1505                                         index, offset, DMA_FROM_DEVICE,
1506                                         chip->xd_timeout);
1507         if (retval < 0) {
1508                 rtsx_clear_xd_error(chip);
1509
1510                 if (retval == -ETIMEDOUT) {
1511                         xd_set_err_code(chip, XD_TO_ERROR);
1512                         TRACE_RET(chip, STATUS_FAIL);
1513                 } else {
1514                         TRACE_GOTO(chip, Fail);
1515                 }
1516         }
1517
1518         return STATUS_SUCCESS;
1519
1520 Fail:
1521         RTSX_READ_REG(chip, XD_PAGE_STATUS, &reg_val);
1522
1523         if (reg_val !=  XD_GPG)
1524                 xd_set_err_code(chip, XD_PRG_ERROR);
1525
1526         RTSX_READ_REG(chip, XD_CTL, &reg_val);
1527
1528         if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1529                                 == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1530                 || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))
1531                         == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1532                 wait_timeout(100);
1533
1534                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1535                         xd_set_err_code(chip, XD_NO_CARD);
1536                         TRACE_RET(chip, STATUS_FAIL);
1537                 }
1538
1539                 xd_set_err_code(chip, XD_ECC_ERROR);
1540
1541                 new_blk = xd_get_unused_block(chip, zone_no);
1542                 if (new_blk == NO_NEW_BLK) {
1543                         XD_CLR_BAD_OLDBLK(xd_card);
1544                         TRACE_RET(chip, STATUS_FAIL);
1545                 }
1546
1547                 retval = xd_copy_page(chip, phy_blk, new_blk, 0,
1548                                 xd_card->page_off + 1);
1549                 if (retval != STATUS_SUCCESS) {
1550                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1551                                 retval = xd_erase_block(chip, new_blk);
1552                                 if (retval == STATUS_SUCCESS)
1553                                         xd_set_unused_block(chip, new_blk);
1554                         } else {
1555                                 XD_CLR_BAD_NEWBLK(xd_card);
1556                         }
1557                         XD_CLR_BAD_OLDBLK(xd_card);
1558                         TRACE_RET(chip, STATUS_FAIL);
1559                 }
1560                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1561                 xd_erase_block(chip, phy_blk);
1562                 xd_mark_bad_block(chip, phy_blk);
1563                 XD_CLR_BAD_OLDBLK(xd_card);
1564         }
1565
1566         TRACE_RET(chip, STATUS_FAIL);
1567 }
1568
1569 static int xd_finish_write(struct rtsx_chip *chip,
1570                 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1571 {
1572         struct xd_info *xd_card = &(chip->xd_card);
1573         int retval, zone_no;
1574         u16 log_off;
1575
1576         dev_dbg(rtsx_dev(chip), "xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1577                 old_blk, new_blk, log_blk);
1578
1579         if (page_off > xd_card->page_off)
1580                 TRACE_RET(chip, STATUS_FAIL);
1581
1582         zone_no = (int)(log_blk / 1000);
1583         log_off = (u16)(log_blk % 1000);
1584
1585         if (old_blk == BLK_NOT_FOUND) {
1586                 retval = xd_init_page(chip, new_blk, log_off,
1587                                 page_off, xd_card->page_off + 1);
1588                 if (retval != STATUS_SUCCESS) {
1589                         retval = xd_erase_block(chip, new_blk);
1590                         if (retval == STATUS_SUCCESS)
1591                                 xd_set_unused_block(chip, new_blk);
1592                         TRACE_RET(chip, STATUS_FAIL);
1593                 }
1594         } else {
1595                 retval = xd_copy_page(chip, old_blk, new_blk,
1596                                 page_off, xd_card->page_off + 1);
1597                 if (retval != STATUS_SUCCESS) {
1598                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1599                                 retval = xd_erase_block(chip, new_blk);
1600                                 if (retval == STATUS_SUCCESS)
1601                                         xd_set_unused_block(chip, new_blk);
1602                         }
1603                         XD_CLR_BAD_NEWBLK(xd_card);
1604                         TRACE_RET(chip, STATUS_FAIL);
1605                 }
1606
1607                 retval = xd_erase_block(chip, old_blk);
1608                 if (retval == STATUS_SUCCESS) {
1609                         if (XD_CHK_BAD_OLDBLK(xd_card)) {
1610                                 xd_mark_bad_block(chip, old_blk);
1611                                 XD_CLR_BAD_OLDBLK(xd_card);
1612                         } else {
1613                                 xd_set_unused_block(chip, old_blk);
1614                         }
1615                 } else {
1616                         xd_set_err_code(chip, XD_NO_ERROR);
1617                         XD_CLR_BAD_OLDBLK(xd_card);
1618                 }
1619         }
1620
1621         xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1622
1623         return STATUS_SUCCESS;
1624 }
1625
1626 static int xd_prepare_write(struct rtsx_chip *chip,
1627                 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1628 {
1629         int retval;
1630
1631         dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n",
1632                 __func__, old_blk, new_blk, log_blk, (int)page_off);
1633
1634         if (page_off) {
1635                 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1636                 if (retval != STATUS_SUCCESS)
1637                         TRACE_RET(chip, STATUS_FAIL);
1638         }
1639
1640         return STATUS_SUCCESS;
1641 }
1642
1643
1644 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk,
1645                                 u32 new_blk, u32 log_blk, u8 start_page,
1646                                 u8 end_page, u8 *buf, unsigned int *index,
1647                                 unsigned int *offset)
1648 {
1649         struct xd_info *xd_card = &(chip->xd_card);
1650         u32 page_addr;
1651         int zone_no, retval;
1652         u16 log_off;
1653         u8 page_cnt, reg_val;
1654
1655         dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1656                 __func__, old_blk, new_blk, log_blk);
1657
1658         if (start_page > end_page)
1659                 TRACE_RET(chip, STATUS_FAIL);
1660
1661         page_cnt = end_page - start_page;
1662         zone_no = (int)(log_blk / 1000);
1663         log_off = (u16)(log_blk % 1000);
1664
1665         page_addr = (new_blk << xd_card->block_shift) + start_page;
1666
1667         retval = xd_send_cmd(chip, READ1_1);
1668         if (retval != STATUS_SUCCESS)
1669                 TRACE_RET(chip, STATUS_FAIL);
1670
1671         rtsx_init_cmd(chip);
1672
1673         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1674                 0xFF, (u8)(log_off >> 8));
1675         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1676         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1677         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1678
1679         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1680
1681         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1682                 XD_BA_TRANSFORM);
1683         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1684         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1685
1686         trans_dma_enable(chip->srb->sc_data_direction, chip,
1687                         page_cnt * 512, DMA_512);
1688
1689         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1690                 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES);
1691         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1692                 XD_TRANSFER_END, XD_TRANSFER_END);
1693
1694         rtsx_send_cmd_no_wait(chip);
1695
1696         retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1697                                         scsi_sg_count(chip->srb),
1698                         index, offset, DMA_TO_DEVICE, chip->xd_timeout);
1699         if (retval < 0) {
1700                 rtsx_clear_xd_error(chip);
1701
1702                 if (retval == -ETIMEDOUT) {
1703                         xd_set_err_code(chip, XD_TO_ERROR);
1704                         TRACE_RET(chip, STATUS_FAIL);
1705                 } else {
1706                         TRACE_GOTO(chip, Fail);
1707                 }
1708         }
1709
1710         if (end_page == (xd_card->page_off + 1)) {
1711                 xd_card->delay_write.delay_write_flag = 0;
1712
1713                 if (old_blk != BLK_NOT_FOUND) {
1714                         retval = xd_erase_block(chip, old_blk);
1715                         if (retval == STATUS_SUCCESS) {
1716                                 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1717                                         xd_mark_bad_block(chip, old_blk);
1718                                         XD_CLR_BAD_OLDBLK(xd_card);
1719                                 } else {
1720                                         xd_set_unused_block(chip, old_blk);
1721                                 }
1722                         } else {
1723                                 xd_set_err_code(chip, XD_NO_ERROR);
1724                                 XD_CLR_BAD_OLDBLK(xd_card);
1725                         }
1726                 }
1727                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1728         }
1729
1730         return STATUS_SUCCESS;
1731
1732 Fail:
1733         RTSX_READ_REG(chip, XD_DAT, &reg_val);
1734         if (reg_val & PROGRAM_ERROR) {
1735                 xd_set_err_code(chip, XD_PRG_ERROR);
1736                 xd_mark_bad_block(chip, new_blk);
1737         }
1738
1739         TRACE_RET(chip, STATUS_FAIL);
1740 }
1741
1742 #ifdef XD_DELAY_WRITE
1743 int xd_delay_write(struct rtsx_chip *chip)
1744 {
1745         struct xd_info *xd_card = &(chip->xd_card);
1746         struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1747         int retval;
1748
1749         if (delay_write->delay_write_flag) {
1750                 dev_dbg(rtsx_dev(chip), "xd_delay_write\n");
1751                 retval = xd_switch_clock(chip);
1752                 if (retval != STATUS_SUCCESS)
1753                         TRACE_RET(chip, STATUS_FAIL);
1754
1755                 delay_write->delay_write_flag = 0;
1756                 retval = xd_finish_write(chip,
1757                                 delay_write->old_phyblock,
1758                                         delay_write->new_phyblock,
1759                                 delay_write->logblock, delay_write->pageoff);
1760                 if (retval != STATUS_SUCCESS)
1761                         TRACE_RET(chip, STATUS_FAIL);
1762         }
1763
1764         return STATUS_SUCCESS;
1765 }
1766 #endif
1767
1768 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
1769         u32 start_sector, u16 sector_cnt)
1770 {
1771         struct xd_info *xd_card = &(chip->xd_card);
1772         unsigned int lun = SCSI_LUN(srb);
1773 #ifdef XD_DELAY_WRITE
1774         struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1775 #endif
1776         int retval, zone_no;
1777         unsigned int index = 0, offset = 0;
1778         u32 log_blk, old_blk = 0, new_blk = 0;
1779         u16 log_off, total_sec_cnt = sector_cnt;
1780         u8 start_page, end_page = 0, page_cnt;
1781         u8 *ptr;
1782
1783         xd_set_err_code(chip, XD_NO_ERROR);
1784
1785         xd_card->cleanup_counter = 0;
1786
1787         dev_dbg(rtsx_dev(chip), "xd_rw: scsi_sg_count = %d\n",
1788                 scsi_sg_count(srb));
1789
1790         ptr = (u8 *)scsi_sglist(srb);
1791
1792         retval = xd_switch_clock(chip);
1793         if (retval != STATUS_SUCCESS)
1794                 TRACE_RET(chip, STATUS_FAIL);
1795
1796
1797         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1798                 chip->card_fail |= XD_CARD;
1799                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1800                 TRACE_RET(chip, STATUS_FAIL);
1801         }
1802
1803         log_blk = start_sector >> xd_card->block_shift;
1804         start_page = (u8)start_sector & xd_card->page_off;
1805         zone_no = (int)(log_blk / 1000);
1806         log_off = (u16)(log_blk % 1000);
1807
1808         if (xd_card->zone[zone_no].build_flag == 0) {
1809                 retval = xd_build_l2p_tbl(chip, zone_no);
1810                 if (retval != STATUS_SUCCESS) {
1811                         chip->card_fail |= XD_CARD;
1812                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1813                         TRACE_RET(chip, STATUS_FAIL);
1814                 }
1815         }
1816
1817         if (srb->sc_data_direction == DMA_TO_DEVICE) {
1818 #ifdef XD_DELAY_WRITE
1819                 if (delay_write->delay_write_flag &&
1820                                 (delay_write->logblock == log_blk) &&
1821                                 (start_page > delay_write->pageoff)) {
1822                         delay_write->delay_write_flag = 0;
1823                         if (delay_write->old_phyblock != BLK_NOT_FOUND) {
1824                                 retval = xd_copy_page(chip,
1825                                         delay_write->old_phyblock,
1826                                         delay_write->new_phyblock,
1827                                         delay_write->pageoff, start_page);
1828                                 if (retval != STATUS_SUCCESS) {
1829                                         set_sense_type(chip, lun,
1830                                                 SENSE_TYPE_MEDIA_WRITE_ERR);
1831                                         TRACE_RET(chip, STATUS_FAIL);
1832                                 }
1833                         }
1834                         old_blk = delay_write->old_phyblock;
1835                         new_blk = delay_write->new_phyblock;
1836                 } else if (delay_write->delay_write_flag &&
1837                                 (delay_write->logblock == log_blk) &&
1838                                 (start_page == delay_write->pageoff)) {
1839                         delay_write->delay_write_flag = 0;
1840                         old_blk = delay_write->old_phyblock;
1841                         new_blk = delay_write->new_phyblock;
1842                 } else {
1843                         retval = xd_delay_write(chip);
1844                         if (retval != STATUS_SUCCESS) {
1845                                 set_sense_type(chip, lun,
1846                                         SENSE_TYPE_MEDIA_WRITE_ERR);
1847                                 TRACE_RET(chip, STATUS_FAIL);
1848                         }
1849 #endif
1850                         old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1851                         new_blk  = xd_get_unused_block(chip, zone_no);
1852                         if ((old_blk == BLK_NOT_FOUND) ||
1853                                 (new_blk == BLK_NOT_FOUND)) {
1854                                 set_sense_type(chip, lun,
1855                                         SENSE_TYPE_MEDIA_WRITE_ERR);
1856                                 TRACE_RET(chip, STATUS_FAIL);
1857                         }
1858
1859                         retval = xd_prepare_write(chip, old_blk, new_blk,
1860                                                 log_blk, start_page);
1861                         if (retval != STATUS_SUCCESS) {
1862                                 if (detect_card_cd(chip, XD_CARD) !=
1863                                         STATUS_SUCCESS) {
1864                                         set_sense_type(chip, lun,
1865                                                 SENSE_TYPE_MEDIA_NOT_PRESENT);
1866                                         TRACE_RET(chip, STATUS_FAIL);
1867                                 }
1868                                 set_sense_type(chip, lun,
1869                                         SENSE_TYPE_MEDIA_WRITE_ERR);
1870                                 TRACE_RET(chip, STATUS_FAIL);
1871                         }
1872 #ifdef XD_DELAY_WRITE
1873                 }
1874 #endif
1875         } else {
1876 #ifdef XD_DELAY_WRITE
1877                 retval = xd_delay_write(chip);
1878                 if (retval != STATUS_SUCCESS) {
1879                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1880                                 set_sense_type(chip, lun,
1881                                         SENSE_TYPE_MEDIA_NOT_PRESENT);
1882                                 TRACE_RET(chip, STATUS_FAIL);
1883                         }
1884                         set_sense_type(chip, lun,
1885                                 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1886                         TRACE_RET(chip, STATUS_FAIL);
1887                 }
1888 #endif
1889
1890                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1891                 if (old_blk == BLK_NOT_FOUND) {
1892                         set_sense_type(chip, lun,
1893                                 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1894                         TRACE_RET(chip, STATUS_FAIL);
1895                 }
1896         }
1897
1898         dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk);
1899
1900         while (total_sec_cnt) {
1901                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1902                         chip->card_fail |= XD_CARD;
1903                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1904                         TRACE_RET(chip, STATUS_FAIL);
1905                 }
1906
1907                 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
1908                         end_page = xd_card->page_off + 1;
1909                 else
1910                         end_page = start_page + (u8)total_sec_cnt;
1911
1912                 page_cnt = end_page - start_page;
1913                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
1914                         retval = xd_read_multiple_pages(chip, old_blk, log_blk,
1915                                         start_page, end_page, ptr,
1916                                                         &index, &offset);
1917                         if (retval != STATUS_SUCCESS) {
1918                                 set_sense_type(chip, lun,
1919                                         SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1920                                 TRACE_RET(chip, STATUS_FAIL);
1921                         }
1922                 } else {
1923                         retval = xd_write_multiple_pages(chip, old_blk,
1924                                                         new_blk, log_blk,
1925                                         start_page, end_page, ptr,
1926                                                         &index, &offset);
1927                         if (retval != STATUS_SUCCESS) {
1928                                 set_sense_type(chip, lun,
1929                                         SENSE_TYPE_MEDIA_WRITE_ERR);
1930                                 TRACE_RET(chip, STATUS_FAIL);
1931                         }
1932                 }
1933
1934                 total_sec_cnt -= page_cnt;
1935                 if (scsi_sg_count(srb) == 0)
1936                         ptr += page_cnt * 512;
1937
1938                 if (total_sec_cnt == 0)
1939                         break;
1940
1941                 log_blk++;
1942                 zone_no = (int)(log_blk / 1000);
1943                 log_off = (u16)(log_blk % 1000);
1944
1945                 if (xd_card->zone[zone_no].build_flag == 0) {
1946                         retval = xd_build_l2p_tbl(chip, zone_no);
1947                         if (retval != STATUS_SUCCESS) {
1948                                 chip->card_fail |= XD_CARD;
1949                                 set_sense_type(chip, lun,
1950                                         SENSE_TYPE_MEDIA_NOT_PRESENT);
1951                                 TRACE_RET(chip, STATUS_FAIL);
1952                         }
1953                 }
1954
1955                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1956                 if (old_blk == BLK_NOT_FOUND) {
1957                         if (srb->sc_data_direction == DMA_FROM_DEVICE)
1958                                 set_sense_type(chip, lun,
1959                                         SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1960                         else
1961                                 set_sense_type(chip, lun,
1962                                         SENSE_TYPE_MEDIA_WRITE_ERR);
1963
1964                         TRACE_RET(chip, STATUS_FAIL);
1965                 }
1966
1967                 if (srb->sc_data_direction == DMA_TO_DEVICE) {
1968                         new_blk = xd_get_unused_block(chip, zone_no);
1969                         if (new_blk == BLK_NOT_FOUND) {
1970                                 set_sense_type(chip, lun,
1971                                         SENSE_TYPE_MEDIA_WRITE_ERR);
1972                                 TRACE_RET(chip, STATUS_FAIL);
1973                         }
1974                 }
1975
1976                 start_page = 0;
1977         }
1978
1979         if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
1980                         (end_page != (xd_card->page_off + 1))) {
1981 #ifdef XD_DELAY_WRITE
1982                 delay_write->delay_write_flag = 1;
1983                 delay_write->old_phyblock = old_blk;
1984                 delay_write->new_phyblock = new_blk;
1985                 delay_write->logblock = log_blk;
1986                 delay_write->pageoff = end_page;
1987 #else
1988                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1989                         chip->card_fail |= XD_CARD;
1990                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1991                         TRACE_RET(chip, STATUS_FAIL);
1992                 }
1993
1994                 retval = xd_finish_write(chip, old_blk, new_blk,
1995                                         log_blk, end_page);
1996                 if (retval != STATUS_SUCCESS) {
1997                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1998                                 set_sense_type(chip, lun,
1999                                         SENSE_TYPE_MEDIA_NOT_PRESENT);
2000                                 TRACE_RET(chip, STATUS_FAIL);
2001                         }
2002                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
2003                         TRACE_RET(chip, STATUS_FAIL);
2004                 }
2005 #endif
2006         }
2007
2008         scsi_set_resid(srb, 0);
2009
2010         return STATUS_SUCCESS;
2011 }
2012
2013 void xd_free_l2p_tbl(struct rtsx_chip *chip)
2014 {
2015         struct xd_info *xd_card = &(chip->xd_card);
2016         int i = 0;
2017
2018         if (xd_card->zone != NULL) {
2019                 for (i = 0; i < xd_card->zone_cnt; i++) {
2020                         if (xd_card->zone[i].l2p_table != NULL) {
2021                                 vfree(xd_card->zone[i].l2p_table);
2022                                 xd_card->zone[i].l2p_table = NULL;
2023                         }
2024                         if (xd_card->zone[i].free_table != NULL) {
2025                                 vfree(xd_card->zone[i].free_table);
2026                                 xd_card->zone[i].free_table = NULL;
2027                         }
2028                 }
2029                 vfree(xd_card->zone);
2030                 xd_card->zone = NULL;
2031         }
2032 }
2033
2034 void xd_cleanup_work(struct rtsx_chip *chip)
2035 {
2036 #ifdef XD_DELAY_WRITE
2037         struct xd_info *xd_card = &(chip->xd_card);
2038
2039         if (xd_card->delay_write.delay_write_flag) {
2040                 dev_dbg(rtsx_dev(chip), "xD: delay write\n");
2041                 xd_delay_write(chip);
2042                 xd_card->cleanup_counter = 0;
2043         }
2044 #endif
2045 }
2046
2047 int xd_power_off_card3v3(struct rtsx_chip *chip)
2048 {
2049         int retval;
2050
2051         retval = disable_card_clock(chip, XD_CARD);
2052         if (retval != STATUS_SUCCESS)
2053                 TRACE_RET(chip, STATUS_FAIL);
2054
2055         RTSX_WRITE_REG(chip, CARD_OE, XD_OUTPUT_EN, 0);
2056
2057         if (!chip->ft2_fast_mode) {
2058                 retval = card_power_off(chip, XD_CARD);
2059                 if (retval != STATUS_SUCCESS)
2060                         TRACE_RET(chip, STATUS_FAIL);
2061
2062                 wait_timeout(50);
2063         }
2064
2065         if (chip->asic_code) {
2066                 retval = xd_pull_ctl_disable(chip);
2067                 if (retval != STATUS_SUCCESS)
2068                         TRACE_RET(chip, STATUS_FAIL);
2069         } else {
2070                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, 0xDF);
2071         }
2072
2073         return STATUS_SUCCESS;
2074 }
2075
2076 int release_xd_card(struct rtsx_chip *chip)
2077 {
2078         struct xd_info *xd_card = &(chip->xd_card);
2079         int retval;
2080
2081         chip->card_ready &= ~XD_CARD;
2082         chip->card_fail &= ~XD_CARD;
2083         chip->card_wp &= ~XD_CARD;
2084
2085         xd_card->delay_write.delay_write_flag = 0;
2086
2087         xd_free_l2p_tbl(chip);
2088
2089         retval = xd_power_off_card3v3(chip);
2090         if (retval != STATUS_SUCCESS)
2091                 TRACE_RET(chip, STATUS_FAIL);
2092
2093         return STATUS_SUCCESS;
2094 }