drivers/staging/rts5208/rtsx_chip.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/vmalloc.h>
  28
  29 #include "rtsx.h"
  30 #include "rtsx_transport.h"
  31 #include "rtsx_scsi.h"
  32 #include "rtsx_card.h"
  33 #include "rtsx_chip.h"
  34 #include "rtsx_sys.h"
  35 #include "general.h"
  36
  37 #include "sd.h"
  38 #include "xd.h"
  39 #include "ms.h"
  40
  41 static void rtsx_calibration(struct rtsx_chip *chip)
  42 {
  43         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  44         wait_timeout(10);
  45         rtsx_write_phy_register(chip, 0x00, 0x0280);
  46         rtsx_write_phy_register(chip, 0x01, 0x7112);
  47         rtsx_write_phy_register(chip, 0x01, 0x7110);
  48         rtsx_write_phy_register(chip, 0x01, 0x7112);
  49         rtsx_write_phy_register(chip, 0x01, 0x7113);
  50         rtsx_write_phy_register(chip, 0x00, 0x0288);
  51 }
  52
  53 void rtsx_disable_card_int(struct rtsx_chip *chip)
  54 {
  55         u32 reg = rtsx_readl(chip, RTSX_BIER);
  56
  57         reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
  58         rtsx_writel(chip, RTSX_BIER, reg);
  59 }
  60
  61 void rtsx_enable_card_int(struct rtsx_chip *chip)
  62 {
  63         u32 reg = rtsx_readl(chip, RTSX_BIER);
  64         int i;
  65
  66         for (i = 0; i <= chip->max_lun; i++) {
  67                 if (chip->lun2card[i] & XD_CARD)
  68                         reg |= XD_INT_EN;
  69                 if (chip->lun2card[i] & SD_CARD)
  70                         reg |= SD_INT_EN;
  71                 if (chip->lun2card[i] & MS_CARD)
  72                         reg |= MS_INT_EN;
  73         }
  74         if (chip->hw_bypass_sd)
  75                 reg &= ~((u32)SD_INT_EN);
  76
  77         rtsx_writel(chip, RTSX_BIER, reg);
  78 }
  79
  80 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  81 {
  82         u32 reg = 0;
  83 #ifndef DISABLE_CARD_INT
  84         int i;
  85 #endif
  86
  87         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  88
  89 #ifndef DISABLE_CARD_INT
  90         for (i = 0; i <= chip->max_lun; i++) {
  91                 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
  92                         i, chip->lun2card[i]);
  93
  94                 if (chip->lun2card[i] & XD_CARD)
  95                         reg |= XD_INT_EN;
  96                 if (chip->lun2card[i] & SD_CARD)
  97                         reg |= SD_INT_EN;
  98                 if (chip->lun2card[i] & MS_CARD)
  99                         reg |= MS_INT_EN;
 100         }
 101         if (chip->hw_bypass_sd)
 102                 reg &= ~((u32)SD_INT_EN);
 103 #endif
 104
 105         if (chip->ic_version >= IC_VER_C)
 106                 reg |= DELINK_INT_EN;
 107 #ifdef SUPPORT_OCP
 108         reg |= OC_INT_EN;
 109 #endif
 110         if (!chip->adma_mode)
 111                 reg |= DATA_DONE_INT_EN;
 112
 113         /* Enable Bus Interrupt */
 114         rtsx_writel(chip, RTSX_BIER, reg);
 115
 116         dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
 117 }
 118
 119 void rtsx_disable_bus_int(struct rtsx_chip *chip)
 120 {
 121         rtsx_writel(chip, RTSX_BIER, 0);
 122 }
 123
 124 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
 125 {
 126         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 127                 if (chip->asic_code) {
 128                         RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
 129                                 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
 130                 } else {
 131                         RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF,
 132                                 FPGA_SD_PULL_CTL_EN);
 133                 }
 134                 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD);
 135
 136                 /* Enable SDIO internal clock */
 137                 RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01);
 138
 139                 RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF,
 140                         SDIO_BUS_CTRL | SDIO_CD_CTRL);
 141
 142                 chip->sd_int = 1;
 143                 chip->sd_io = 1;
 144         } else {
 145                 chip->need_reset |= SD_CARD;
 146         }
 147
 148         return STATUS_SUCCESS;
 149 }
 150
 151 #ifdef HW_AUTO_SWITCH_SD_BUS
 152 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 153 {
 154         u8 tmp;
 155         int sw_bypass_sd = 0;
 156         int retval;
 157
 158         if (chip->driver_first_load) {
 159                 if (CHECK_PID(chip, 0x5288)) {
 160                         RTSX_READ_REG(chip, 0xFE5A, &tmp);
 161                         if (tmp & 0x08)
 162                                 sw_bypass_sd = 1;
 163                 } else if (CHECK_PID(chip, 0x5208)) {
 164                         RTSX_READ_REG(chip, 0xFE70, &tmp);
 165                         if (tmp & 0x80)
 166                                 sw_bypass_sd = 1;
 167                 }
 168         } else {
 169                 if (chip->sdio_in_charge)
 170                         sw_bypass_sd = 1;
 171         }
 172         dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
 173                 chip->sdio_in_charge);
 174         dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
 175                 chip->driver_first_load);
 176         dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
 177                 sw_bypass_sd);
 178
 179         if (sw_bypass_sd) {
 180                 u8 cd_toggle_mask = 0;
 181
 182                 RTSX_READ_REG(chip, TLPTISTAT, &tmp);
 183                 cd_toggle_mask = 0x08;
 184
 185                 if (tmp & cd_toggle_mask) {
 186                         /* Disable sdio_bus_auto_switch */
 187                         if (CHECK_PID(chip, 0x5288))
 188                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00);
 189                         else if (CHECK_PID(chip, 0x5208))
 190                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00);
 191
 192                         RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp);
 193
 194                         chip->need_reset |= SD_CARD;
 195                 } else {
 196                         dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
 197
 198                         if (chip->asic_code) {
 199                                 retval = sd_pull_ctl_enable(chip);
 200                                 if (retval != STATUS_SUCCESS)
 201                                         TRACE_RET(chip, STATUS_FAIL);
 202                         } else {
 203                                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
 204                                         FPGA_SD_PULL_CTL_BIT | 0x20, 0);
 205                         }
 206                         retval = card_share_mode(chip, SD_CARD);
 207                         if (retval != STATUS_SUCCESS)
 208                                 TRACE_RET(chip, STATUS_FAIL);
 209
 210                         /* Enable sdio_bus_auto_switch */
 211                         if (CHECK_PID(chip, 0x5288))
 212                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08);
 213                         else if (CHECK_PID(chip, 0x5208))
 214                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80);
 215
 216                         chip->chip_insert_with_sdio = 1;
 217                         chip->sd_io = 1;
 218                 }
 219         } else {
 220                 RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08);
 221
 222                 chip->need_reset |= SD_CARD;
 223         }
 224
 225         return STATUS_SUCCESS;
 226 }
 227 #endif
 228
 229 int rtsx_reset_chip(struct rtsx_chip *chip)
 230 {
 231         int retval;
 232
 233         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 234
 235         rtsx_disable_aspm(chip);
 236
 237         RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 238
 239         /* Disable card clock */
 240         RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0);
 241
 242 #ifdef SUPPORT_OCP
 243         /* SSC power on, OCD power on */
 244         if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
 245                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0);
 246         else
 247                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN);
 248
 249         RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800);
 250         RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946);
 251         RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN);
 252 #else
 253         /* OC power down */
 254         RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN);
 255 #endif
 256
 257         if (!CHECK_PID(chip, 0x5288))
 258                 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 259
 260         /* Turn off LED */
 261         RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03);
 262
 263         /* Reset delink mode */
 264         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0);
 265
 266         /* Card driving select */
 267         RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel);
 268
 269 #ifdef LED_AUTO_BLINK
 270         RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF,
 271                         LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 272 #endif
 273
 274         if (chip->asic_code) {
 275                 /* Enable SSC Clock */
 276                 RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M);
 277                 RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12);
 278         }
 279
 280         /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 281               0xFE5B
 282               bit[1]    u_cd_rst_core_en        rst_value = 0
 283               bit[2]    u_force_rst_core_en     rst_value = 0
 284               bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 285               bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 286         */
 287         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 288
 289         /* Enable ASPM */
 290         if (chip->aspm_l0s_l1_en) {
 291                 if (chip->dynamic_aspm) {
 292                         if (CHK_SDIO_EXIST(chip)) {
 293                                 if (CHECK_PID(chip, 0x5288)) {
 294                                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 295                                         if (retval != STATUS_SUCCESS)
 296                                                 TRACE_RET(chip, STATUS_FAIL);
 297                                 }
 298                         }
 299                 } else {
 300                         if (CHECK_PID(chip, 0x5208))
 301                                 RTSX_WRITE_REG(chip, ASPM_FORCE_CTL,
 302                                         0xFF, 0x3F);
 303
 304                         retval = rtsx_write_config_byte(chip, LCTLR,
 305                                                         chip->aspm_l0s_l1_en);
 306                         if (retval != STATUS_SUCCESS)
 307                                 TRACE_RET(chip, STATUS_FAIL);
 308
 309                         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 310                         if (CHK_SDIO_EXIST(chip)) {
 311                                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 312                                 if (CHECK_PID(chip, 0x5288))
 313                                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 314                                 else
 315                                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 316
 317                                 if (retval != STATUS_SUCCESS)
 318                                         TRACE_RET(chip, STATUS_FAIL);
 319
 320                         }
 321
 322                         chip->aspm_enabled = 1;
 323                 }
 324         } else {
 325                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 326                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 327                         if (retval != STATUS_SUCCESS)
 328                                 TRACE_RET(chip, STATUS_FAIL);
 329                 }
 330                 retval = rtsx_write_config_byte(chip, LCTLR,
 331                                                 chip->aspm_l0s_l1_en);
 332                 if (retval != STATUS_SUCCESS)
 333                         TRACE_RET(chip, STATUS_FAIL);
 334         }
 335
 336         retval = rtsx_write_config_byte(chip, 0x81, 1);
 337         if (retval != STATUS_SUCCESS)
 338                 TRACE_RET(chip, STATUS_FAIL);
 339
 340         if (CHK_SDIO_EXIST(chip)) {
 341                 if (CHECK_PID(chip, 0x5288))
 342                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0,
 343                                                 0xFF00, 0x0100);
 344                 else
 345                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0,
 346                                                 0xFF00, 0x0100);
 347
 348                 if (retval != STATUS_SUCCESS)
 349                         TRACE_RET(chip, STATUS_FAIL);
 350
 351         }
 352
 353         if (CHECK_PID(chip, 0x5288)) {
 354                 if (!CHK_SDIO_EXIST(chip)) {
 355                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF,
 356                                                 0x0103);
 357                         if (retval != STATUS_SUCCESS)
 358                                 TRACE_RET(chip, STATUS_FAIL);
 359
 360                         retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 361                         if (retval != STATUS_SUCCESS)
 362                                 TRACE_RET(chip, STATUS_FAIL);
 363
 364                 }
 365         }
 366
 367         RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
 368
 369         RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 370
 371         /* Enable PCIE interrupt */
 372         if (chip->asic_code) {
 373                 if (CHECK_PID(chip, 0x5208)) {
 374                         if (chip->phy_debug_mode) {
 375                                 RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0);
 376                                 rtsx_disable_bus_int(chip);
 377                         } else {
 378                                 rtsx_enable_bus_int(chip);
 379                         }
 380
 381                         if (chip->ic_version >= IC_VER_D) {
 382                                 u16 reg;
 383
 384                                 retval = rtsx_read_phy_register(chip, 0x00,
 385                                                                 &reg);
 386                                 if (retval != STATUS_SUCCESS)
 387                                         TRACE_RET(chip, STATUS_FAIL);
 388
 389                                 reg &= 0xFE7F;
 390                                 reg |= 0x80;
 391                                 retval = rtsx_write_phy_register(chip, 0x00,
 392                                                                 reg);
 393                                 if (retval != STATUS_SUCCESS)
 394                                         TRACE_RET(chip, STATUS_FAIL);
 395
 396                                 retval = rtsx_read_phy_register(chip, 0x1C,
 397                                                                 &reg);
 398                                 if (retval != STATUS_SUCCESS)
 399                                         TRACE_RET(chip, STATUS_FAIL);
 400
 401                                 reg &= 0xFFF7;
 402                                 retval = rtsx_write_phy_register(chip, 0x1C,
 403                                                                 reg);
 404                                 if (retval != STATUS_SUCCESS)
 405                                         TRACE_RET(chip, STATUS_FAIL);
 406
 407                         }
 408
 409                         if (chip->driver_first_load &&
 410                                 (chip->ic_version < IC_VER_C))
 411                                 rtsx_calibration(chip);
 412
 413                 } else {
 414                         rtsx_enable_bus_int(chip);
 415                 }
 416         } else {
 417                 rtsx_enable_bus_int(chip);
 418         }
 419
 420         chip->need_reset = 0;
 421
 422         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 423
 424         if (chip->hw_bypass_sd)
 425                 goto NextCard;
 426         dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
 427                 chip->int_reg);
 428         if (chip->int_reg & SD_EXIST) {
 429 #ifdef HW_AUTO_SWITCH_SD_BUS
 430                 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
 431                         retval = rtsx_pre_handle_sdio_old(chip);
 432                 else
 433                         retval = rtsx_pre_handle_sdio_new(chip);
 434
 435                 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
 436                         (unsigned int)(chip->need_reset));
 437 #else  /* HW_AUTO_SWITCH_SD_BUS */
 438                 retval = rtsx_pre_handle_sdio_old(chip);
 439 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 440                 if (retval != STATUS_SUCCESS)
 441                         TRACE_RET(chip, STATUS_FAIL);
 442
 443         } else {
 444                 chip->sd_io = 0;
 445                 RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL,
 446                         0);
 447         }
 448
 449 NextCard:
 450         if (chip->int_reg & XD_EXIST)
 451                 chip->need_reset |= XD_CARD;
 452         if (chip->int_reg & MS_EXIST)
 453                 chip->need_reset |= MS_CARD;
 454         if (chip->int_reg & CARD_EXIST)
 455                 RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 456
 457         dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
 458                 (unsigned int)(chip->need_reset));
 459
 460         RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00);
 461
 462         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 463                 /* Turn off main power when entering S3/S4 state */
 464                 RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03);
 465         }
 466
 467         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 468                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07);
 469                 if (chip->aux_pwr_exist)
 470                         RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33);
 471         } else {
 472                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04);
 473                 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30);
 474         }
 475
 476         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D))
 477                 RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14);
 478
 479         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 480                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 481                 if (retval != STATUS_SUCCESS)
 482                         TRACE_RET(chip, STATUS_FAIL);
 483         }
 484
 485         if (chip->ft2_fast_mode) {
 486                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF,
 487                         MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
 488                 udelay(chip->pmos_pwr_on_interval);
 489                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF,
 490                         MS_POWER_ON | SD_POWER_ON);
 491
 492                 wait_timeout(200);
 493         }
 494
 495         /* Reset card */
 496         rtsx_reset_detected_cards(chip, 0);
 497
 498         chip->driver_first_load = 0;
 499
 500         return STATUS_SUCCESS;
 501 }
 502
 503 static inline int check_sd_speed_prior(u32 sd_speed_prior)
 504 {
 505         int i, fake_para = 0;
 506
 507         for (i = 0; i < 4; i++) {
 508                 u8 tmp = (u8)(sd_speed_prior >> (i*8));
 509
 510                 if ((tmp < 0x01) || (tmp > 0x04)) {
 511                         fake_para = 1;
 512                         break;
 513                 }
 514         }
 515
 516         return !fake_para;
 517 }
 518
 519 static inline int check_sd_current_prior(u32 sd_current_prior)
 520 {
 521         int i, fake_para = 0;
 522
 523         for (i = 0; i < 4; i++) {
 524                 u8 tmp = (u8)(sd_current_prior >> (i*8));
 525
 526                 if (tmp > 0x03) {
 527                         fake_para = 1;
 528                         break;
 529                 }
 530         }
 531
 532         return !fake_para;
 533 }
 534
 535 static int rts5208_init(struct rtsx_chip *chip)
 536 {
 537         int retval;
 538         u16 reg = 0;
 539         u8 val = 0;
 540
 541         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 542         RTSX_READ_REG(chip, CLK_SEL, &val);
 543         if (val == 0)
 544                 chip->asic_code = 1;
 545         else
 546                 chip->asic_code = 0;
 547
 548         if (chip->asic_code) {
 549                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 550                 if (retval != STATUS_SUCCESS)
 551                         TRACE_RET(chip, STATUS_FAIL);
 552
 553                 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
 554                         reg);
 555                 chip->ic_version = (reg >> 4) & 0x07;
 556                 if (reg & PHY_DEBUG_MODE)
 557                         chip->phy_debug_mode = 1;
 558                 else
 559                         chip->phy_debug_mode = 0;
 560
 561         } else {
 562                 RTSX_READ_REG(chip, 0xFE80, &val);
 563                 chip->ic_version = val;
 564                 chip->phy_debug_mode = 0;
 565         }
 566
 567         RTSX_READ_REG(chip, PDINFO, &val);
 568         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 569         if (val & AUX_PWR_DETECTED)
 570                 chip->aux_pwr_exist = 1;
 571         else
 572                 chip->aux_pwr_exist = 0;
 573
 574         RTSX_READ_REG(chip, 0xFE50, &val);
 575         if (val & 0x01)
 576                 chip->hw_bypass_sd = 1;
 577         else
 578                 chip->hw_bypass_sd = 0;
 579
 580         rtsx_read_config_byte(chip, 0x0E, &val);
 581         if (val & 0x80)
 582                 SET_SDIO_EXIST(chip);
 583         else
 584                 CLR_SDIO_EXIST(chip);
 585
 586         if (chip->use_hw_setting) {
 587                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 588                 if (val & 0x80)
 589                         chip->auto_delink_en = 1;
 590                 else
 591                         chip->auto_delink_en = 0;
 592         }
 593
 594         return STATUS_SUCCESS;
 595 }
 596
 597 static int rts5288_init(struct rtsx_chip *chip)
 598 {
 599         int retval;
 600         u8 val = 0, max_func;
 601         u32 lval = 0;
 602
 603         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 604         RTSX_READ_REG(chip, CLK_SEL, &val);
 605         if (val == 0)
 606                 chip->asic_code = 1;
 607         else
 608                 chip->asic_code = 0;
 609
 610         chip->ic_version = 0;
 611         chip->phy_debug_mode = 0;
 612
 613         RTSX_READ_REG(chip, PDINFO, &val);
 614         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 615         if (val & AUX_PWR_DETECTED)
 616                 chip->aux_pwr_exist = 1;
 617         else
 618                 chip->aux_pwr_exist = 0;
 619
 620         RTSX_READ_REG(chip, CARD_SHARE_MODE, &val);
 621         dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
 622         if (val & 0x04)
 623                 chip->baro_pkg = QFN;
 624         else
 625                 chip->baro_pkg = LQFP;
 626
 627         RTSX_READ_REG(chip, 0xFE5A, &val);
 628         if (val & 0x10)
 629                 chip->hw_bypass_sd = 1;
 630         else
 631                 chip->hw_bypass_sd = 0;
 632
 633         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 634         if (retval != STATUS_SUCCESS)
 635                 TRACE_RET(chip, STATUS_FAIL);
 636
 637         max_func = (u8)((lval >> 29) & 0x07);
 638         dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
 639         if (max_func == 0x02)
 640                 SET_SDIO_EXIST(chip);
 641         else
 642                 CLR_SDIO_EXIST(chip);
 643
 644         if (chip->use_hw_setting) {
 645                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 646                 if (val & 0x80)
 647                         chip->auto_delink_en = 1;
 648                 else
 649                         chip->auto_delink_en = 0;
 650
 651                 if (CHECK_BARO_PKG(chip, LQFP))
 652                         chip->lun_mode = SD_MS_1LUN;
 653                 else
 654                         chip->lun_mode = DEFAULT_SINGLE;
 655
 656         }
 657
 658         return STATUS_SUCCESS;
 659 }
 660
 661 int rtsx_init_chip(struct rtsx_chip *chip)
 662 {
 663         struct sd_info *sd_card = &(chip->sd_card);
 664         struct xd_info *xd_card = &(chip->xd_card);
 665         struct ms_info *ms_card = &(chip->ms_card);
 666         int retval;
 667         unsigned int i;
 668
 669         dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 670                 chip->vendor_id, chip->product_id);
 671
 672         chip->ic_version = 0;
 673
 674 #ifdef _MSG_TRACE
 675         chip->msg_idx = 0;
 676 #endif
 677
 678         memset(xd_card, 0, sizeof(struct xd_info));
 679         memset(sd_card, 0, sizeof(struct sd_info));
 680         memset(ms_card, 0, sizeof(struct ms_info));
 681
 682         chip->xd_reset_counter = 0;
 683         chip->sd_reset_counter = 0;
 684         chip->ms_reset_counter = 0;
 685
 686         chip->xd_show_cnt = MAX_SHOW_CNT;
 687         chip->sd_show_cnt = MAX_SHOW_CNT;
 688         chip->ms_show_cnt = MAX_SHOW_CNT;
 689
 690         chip->sd_io = 0;
 691         chip->auto_delink_cnt = 0;
 692         chip->auto_delink_allowed = 1;
 693         rtsx_set_stat(chip, RTSX_STAT_INIT);
 694
 695         chip->aspm_enabled = 0;
 696         chip->chip_insert_with_sdio = 0;
 697         chip->sdio_aspm = 0;
 698         chip->sdio_idle = 0;
 699         chip->sdio_counter = 0;
 700         chip->cur_card = 0;
 701         chip->phy_debug_mode = 0;
 702         chip->sdio_func_exist = 0;
 703         memset(chip->sdio_raw_data, 0, 12);
 704
 705         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 706                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 707                 chip->rw_fail_cnt[i] = 0;
 708         }
 709
 710         if (!check_sd_speed_prior(chip->sd_speed_prior))
 711                 chip->sd_speed_prior = 0x01040203;
 712
 713         dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
 714                 chip->sd_speed_prior);
 715
 716         if (!check_sd_current_prior(chip->sd_current_prior))
 717                 chip->sd_current_prior = 0x00010203;
 718
 719         dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
 720                 chip->sd_current_prior);
 721
 722         if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
 723                 chip->sd_ddr_tx_phase = 0;
 724
 725         if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
 726                 chip->mmc_ddr_tx_phase = 0;
 727
 728         RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0);
 729         wait_timeout(200);
 730         RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07);
 731         dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
 732                 chip->use_hw_setting);
 733
 734         if (CHECK_PID(chip, 0x5208)) {
 735                 retval = rts5208_init(chip);
 736                 if (retval != STATUS_SUCCESS)
 737                         TRACE_RET(chip, STATUS_FAIL);
 738
 739         } else if (CHECK_PID(chip, 0x5288)) {
 740                 retval = rts5288_init(chip);
 741                 if (retval != STATUS_SUCCESS)
 742                         TRACE_RET(chip, STATUS_FAIL);
 743
 744         }
 745
 746         if (chip->ss_en == 2)
 747                 chip->ss_en = 0;
 748
 749         dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
 750         dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
 751         dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
 752                 chip->phy_debug_mode);
 753         dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
 754                 chip->aux_pwr_exist);
 755         dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
 756                 chip->sdio_func_exist);
 757         dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
 758                 chip->hw_bypass_sd);
 759         dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
 760                 chip->aspm_l0s_l1_en);
 761         dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
 762         dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
 763                 chip->auto_delink_en);
 764         dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
 765         dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
 766
 767         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 768                 chip->card2lun[SD_CARD] = 0;
 769                 chip->card2lun[MS_CARD] = 1;
 770                 chip->card2lun[XD_CARD] = 0xFF;
 771                 chip->lun2card[0] = SD_CARD;
 772                 chip->lun2card[1] = MS_CARD;
 773                 chip->max_lun = 1;
 774                 SET_SDIO_IGNORED(chip);
 775         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
 776                 chip->card2lun[SD_CARD] = 0;
 777                 chip->card2lun[MS_CARD] = 0;
 778                 chip->card2lun[XD_CARD] = 0xFF;
 779                 chip->lun2card[0] = SD_CARD | MS_CARD;
 780                 chip->max_lun = 0;
 781         } else {
 782                 chip->card2lun[XD_CARD] = 0;
 783                 chip->card2lun[SD_CARD] = 0;
 784                 chip->card2lun[MS_CARD] = 0;
 785                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
 786                 chip->max_lun = 0;
 787         }
 788
 789         retval = rtsx_reset_chip(chip);
 790         if (retval != STATUS_SUCCESS)
 791                 TRACE_RET(chip, STATUS_FAIL);
 792
 793         return STATUS_SUCCESS;
 794 }
 795
 796 void rtsx_release_chip(struct rtsx_chip *chip)
 797 {
 798         xd_free_l2p_tbl(chip);
 799         ms_free_l2p_tbl(chip);
 800         chip->card_exist = 0;
 801         chip->card_ready = 0;
 802 }
 803
 804 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 805 static inline void rtsx_blink_led(struct rtsx_chip *chip)
 806 {
 807         if (chip->card_exist && chip->blink_led) {
 808                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
 809                         chip->led_toggle_counter++;
 810                 } else {
 811                         chip->led_toggle_counter = 0;
 812                         toggle_gpio(chip, LED_GPIO);
 813                 }
 814         }
 815 }
 816 #endif
 817
 818 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
 819 {
 820         int maybe_support_aspm, reg_changed;
 821         u32 tmp = 0;
 822         u8 reg0 = 0, reg1 = 0;
 823
 824         maybe_support_aspm = 0;
 825         reg_changed = 0;
 826         rtsx_read_config_byte(chip, LCTLR, &reg0);
 827         if (chip->aspm_level[0] != reg0) {
 828                 reg_changed = 1;
 829                 chip->aspm_level[0] = reg0;
 830         }
 831         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
 832                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
 833                 reg1 = (u8)tmp;
 834                 if (chip->aspm_level[1] != reg1) {
 835                         reg_changed = 1;
 836                         chip->aspm_level[1] = reg1;
 837                 }
 838
 839                 if ((reg0 & 0x03) && (reg1 & 0x03))
 840                         maybe_support_aspm = 1;
 841
 842         } else {
 843                 if (reg0 & 0x03)
 844                         maybe_support_aspm = 1;
 845
 846         }
 847
 848         if (reg_changed) {
 849                 if (maybe_support_aspm)
 850                         chip->aspm_l0s_l1_en = 0x03;
 851
 852                 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
 853                         chip->aspm_level[0], chip->aspm_level[1]);
 854
 855                 if (chip->aspm_l0s_l1_en) {
 856                         chip->aspm_enabled = 1;
 857                 } else {
 858                         chip->aspm_enabled = 0;
 859                         chip->sdio_aspm = 0;
 860                 }
 861                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
 862                                 0x30 | chip->aspm_level[0] |
 863                                 (chip->aspm_level[1] << 2));
 864         }
 865 }
 866
 867 void rtsx_polling_func(struct rtsx_chip *chip)
 868 {
 869 #ifdef SUPPORT_SD_LOCK
 870         struct sd_info *sd_card = &(chip->sd_card);
 871 #endif
 872         int ss_allowed;
 873
 874         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
 875                 return;
 876
 877         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
 878                 goto Delink_Stage;
 879
 880         if (chip->polling_config) {
 881                 u8 val;
 882
 883                 rtsx_read_config_byte(chip, 0, &val);
 884         }
 885
 886         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
 887                 return;
 888
 889 #ifdef SUPPORT_OCP
 890         if (chip->ocp_int) {
 891                 rtsx_read_register(chip, OCPSTAT, &(chip->ocp_stat));
 892
 893                 if (chip->card_exist & SD_CARD)
 894                         sd_power_off_card3v3(chip);
 895                 else if (chip->card_exist & MS_CARD)
 896                         ms_power_off_card3v3(chip);
 897                 else if (chip->card_exist & XD_CARD)
 898                         xd_power_off_card3v3(chip);
 899
 900                 chip->ocp_int = 0;
 901         }
 902 #endif
 903
 904 #ifdef SUPPORT_SD_LOCK
 905         if (sd_card->sd_erase_status) {
 906                 if (chip->card_exist & SD_CARD) {
 907                         u8 val;
 908
 909                         rtsx_read_register(chip, 0xFD30, &val);
 910                         if (val & 0x02) {
 911                                 sd_card->sd_erase_status = SD_NOT_ERASE;
 912                                 sd_card->sd_lock_notify = 1;
 913                                 chip->need_reinit |= SD_CARD;
 914                         }
 915                 } else {
 916                         sd_card->sd_erase_status = SD_NOT_ERASE;
 917                 }
 918         }
 919 #endif
 920
 921         rtsx_init_cards(chip);
 922
 923         if (chip->ss_en) {
 924                 ss_allowed = 1;
 925
 926                 if (CHECK_PID(chip, 0x5288)) {
 927                         ss_allowed = 0;
 928                 } else {
 929                         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
 930                                 u32 val;
 931
 932                                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
 933                                 if (val & 0x07)
 934                                         ss_allowed = 0;
 935
 936                         }
 937                 }
 938         } else {
 939                 ss_allowed = 0;
 940         }
 941
 942         if (ss_allowed && !chip->sd_io) {
 943                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
 944                         chip->ss_counter = 0;
 945                 } else {
 946                         if (chip->ss_counter <
 947                                 (chip->ss_idle_period / POLLING_INTERVAL)) {
 948                                 chip->ss_counter++;
 949                         } else {
 950                                 rtsx_exclusive_enter_ss(chip);
 951                                 return;
 952                         }
 953                 }
 954         }
 955
 956         if (CHECK_PID(chip, 0x5208)) {
 957                 rtsx_monitor_aspm_config(chip);
 958
 959 #ifdef SUPPORT_SDIO_ASPM
 960                 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) &&
 961                                 chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
 962                         if (chip->sd_io) {
 963                                 dynamic_configure_sdio_aspm(chip);
 964                         } else {
 965                                 if (!chip->sdio_aspm) {
 966                                         dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
 967                                         rtsx_write_register(chip,
 968                                                 ASPM_FORCE_CTL, 0xFC,
 969                                                 0x30 | (chip->aspm_level[1] << 2));
 970                                         chip->sdio_aspm = 1;
 971                                 }
 972                         }
 973                 }
 974 #endif
 975         }
 976
 977         if (chip->idle_counter < IDLE_MAX_COUNT) {
 978                 chip->idle_counter++;
 979         } else {
 980                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
 981                         dev_dbg(rtsx_dev(chip), "Idle state!\n");
 982                         rtsx_set_stat(chip, RTSX_STAT_IDLE);
 983
 984 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 985                         chip->led_toggle_counter = 0;
 986 #endif
 987                         rtsx_force_power_on(chip, SSC_PDCTL);
 988
 989                         turn_off_led(chip, LED_GPIO);
 990
 991                         if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
 992                                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
 993
 994                 }
 995         }
 996
 997         switch (rtsx_get_stat(chip)) {
 998         case RTSX_STAT_RUN:
 999 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1000                 rtsx_blink_led(chip);
1001 #endif
1002                 do_remaining_work(chip);
1003                 break;
1004
1005         case RTSX_STAT_IDLE:
1006                 if (chip->sd_io && !chip->sd_int)
1007                         try_to_switch_sdio_ctrl(chip);
1008
1009                 rtsx_enable_aspm(chip);
1010                 break;
1011
1012         default:
1013                 break;
1014         }
1015
1016
1017 #ifdef SUPPORT_OCP
1018         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1019                 if (chip->ocp_stat &
1020                         (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER))
1021                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1022                                 chip->ocp_stat);
1023
1024                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1025                         if (chip->card_exist & SD_CARD) {
1026                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
1027                                                 0);
1028                                 card_power_off(chip, SD_CARD);
1029                                 chip->card_fail |= SD_CARD;
1030                         }
1031                 }
1032                 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
1033                         if (chip->card_exist & MS_CARD) {
1034                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
1035                                                 0);
1036                                 card_power_off(chip, MS_CARD);
1037                                 chip->card_fail |= MS_CARD;
1038                         }
1039                 }
1040         } else {
1041                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1042                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1043                                 chip->ocp_stat);
1044                         if (chip->card_exist & SD_CARD) {
1045                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
1046                                                 0);
1047                                 chip->card_fail |= SD_CARD;
1048                         } else if (chip->card_exist & MS_CARD) {
1049                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
1050                                                 0);
1051                                 chip->card_fail |= MS_CARD;
1052                         } else if (chip->card_exist & XD_CARD) {
1053                                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN,
1054                                                 0);
1055                                 chip->card_fail |= XD_CARD;
1056                         }
1057                         card_power_off(chip, SD_CARD);
1058                 }
1059         }
1060 #endif
1061
1062 Delink_Stage:
1063         if (chip->auto_delink_en && chip->auto_delink_allowed &&
1064                 !chip->card_ready && !chip->card_ejected && !chip->sd_io) {
1065                 int enter_L1 = chip->auto_delink_in_L1 && (
1066                         chip->aspm_l0s_l1_en || chip->ss_en);
1067                 int delink_stage1_cnt = chip->delink_stage1_step;
1068                 int delink_stage2_cnt = delink_stage1_cnt +
1069                         chip->delink_stage2_step;
1070                 int delink_stage3_cnt = delink_stage2_cnt +
1071                         chip->delink_stage3_step;
1072
1073                 if (chip->auto_delink_cnt <= delink_stage3_cnt) {
1074                         if (chip->auto_delink_cnt == delink_stage1_cnt) {
1075                                 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1076
1077                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1078                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1079
1080                                 if (chip->card_exist) {
1081                                         dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1082
1083                                         if (enter_L1)
1084                                                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1085
1086                                         rtsx_write_register(chip,
1087                                                         CHANGE_LINK_STATE, 0x0A,
1088                                                         0x0A);
1089
1090                                         if (enter_L1)
1091                                                 rtsx_enter_L1(chip);
1092
1093                                         chip->auto_delink_cnt = delink_stage3_cnt + 1;
1094                                 } else {
1095                                         dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1096
1097                                         if (enter_L1)
1098                                                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1099
1100                                         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0x02);
1101
1102                                         if (enter_L1)
1103                                                 rtsx_enter_L1(chip);
1104
1105                                 }
1106                         }
1107
1108                         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1109                                 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1110
1111                                 if (enter_L1)
1112                                         rtsx_exit_L1(chip);
1113
1114                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1115                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1116
1117                                 rtsx_write_register(chip, CHANGE_LINK_STATE,
1118                                                 0x0A, 0x0A);
1119                         }
1120
1121                         chip->auto_delink_cnt++;
1122                 }
1123         } else {
1124                 chip->auto_delink_cnt = 0;
1125         }
1126 }
1127
1128 void rtsx_undo_delink(struct rtsx_chip *chip)
1129 {
1130         chip->auto_delink_allowed = 0;
1131         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1132 }
1133
1134 /**
1135  * rtsx_stop_cmd - stop command transfer and DMA transfer
1136  * @chip: Realtek's card reader chip
1137  * @card: flash card type
1138  *
1139  * Stop command transfer and DMA transfer.
1140  * This function is called in error handler.
1141  */
1142 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1143 {
1144         int i;
1145
1146         for (i = 0; i <= 8; i++) {
1147                 int addr = RTSX_HCBAR + i * 4;
1148                 u32 reg;
1149
1150                 reg = rtsx_readl(chip, addr);
1151                 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1152         }
1153         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1154         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1155
1156         for (i = 0; i < 16; i++) {
1157                 u16 addr = 0xFE20 + (u16)i;
1158                 u8 val;
1159
1160                 rtsx_read_register(chip, addr, &val);
1161                 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1162         }
1163
1164         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1165         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1166 }
1167
1168 #define MAX_RW_REG_CNT          1024
1169
1170 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1171 {
1172         int i;
1173         u32 val = 3 << 30;
1174
1175         val |= (u32)(addr & 0x3FFF) << 16;
1176         val |= (u32)mask << 8;
1177         val |= (u32)data;
1178
1179         rtsx_writel(chip, RTSX_HAIMR, val);
1180
1181         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1182                 val = rtsx_readl(chip, RTSX_HAIMR);
1183                 if ((val & (1 << 31)) == 0) {
1184                         if (data != (u8)val)
1185                                 TRACE_RET(chip, STATUS_FAIL);
1186
1187                         return STATUS_SUCCESS;
1188                 }
1189         }
1190
1191         TRACE_RET(chip, STATUS_TIMEDOUT);
1192 }
1193
1194 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1195 {
1196         u32 val = 2 << 30;
1197         int i;
1198
1199         if (data)
1200                 *data = 0;
1201
1202         val |= (u32)(addr & 0x3FFF) << 16;
1203
1204         rtsx_writel(chip, RTSX_HAIMR, val);
1205
1206         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1207                 val = rtsx_readl(chip, RTSX_HAIMR);
1208                 if ((val & (1 << 31)) == 0)
1209                         break;
1210         }
1211
1212         if (i >= MAX_RW_REG_CNT)
1213                 TRACE_RET(chip, STATUS_TIMEDOUT);
1214
1215         if (data)
1216                 *data = (u8)(val & 0xFF);
1217
1218         return STATUS_SUCCESS;
1219 }
1220
1221 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1222                 u32 val)
1223 {
1224         u8 mode = 0, tmp;
1225         int i;
1226
1227         for (i = 0; i < 4; i++) {
1228                 if (mask & 0xFF) {
1229                         RTSX_WRITE_REG(chip, CFGDATA0 + i,
1230                                        0xFF, (u8)(val & mask & 0xFF));
1231                         mode |= (1 << i);
1232                 }
1233                 mask >>= 8;
1234                 val >>= 8;
1235         }
1236
1237         if (mode) {
1238                 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1239                 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1240
1241                 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF,
1242                                0x80 | mode | ((func_no & 0x03) << 4));
1243
1244                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1245                         RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1246                         if ((tmp & 0x80) == 0)
1247                                 break;
1248                 }
1249         }
1250
1251         return STATUS_SUCCESS;
1252 }
1253
1254 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1255 {
1256         int i;
1257         u8 tmp;
1258         u32 data = 0;
1259
1260         RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1261         RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1262         RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4));
1263
1264         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1265                 RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1266                 if ((tmp & 0x80) == 0)
1267                         break;
1268         }
1269
1270         for (i = 0; i < 4; i++) {
1271                 RTSX_READ_REG(chip, CFGDATA0 + i, &tmp);
1272                 data |= (u32)tmp << (i * 8);
1273         }
1274
1275         if (val)
1276                 *val = data;
1277
1278         return STATUS_SUCCESS;
1279 }
1280
1281 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1282                 int len)
1283 {
1284         u32 *data, *mask;
1285         u16 offset = addr % 4;
1286         u16 aligned_addr = addr - offset;
1287         int dw_len, i, j;
1288         int retval;
1289
1290         if (!buf)
1291                 TRACE_RET(chip, STATUS_NOMEM);
1292
1293         if ((len + offset) % 4)
1294                 dw_len = (len + offset) / 4 + 1;
1295         else
1296                 dw_len = (len + offset) / 4;
1297
1298         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1299
1300         data = vzalloc(dw_len * 4);
1301         if (!data)
1302                 TRACE_RET(chip, STATUS_NOMEM);
1303
1304         mask = vzalloc(dw_len * 4);
1305         if (!mask) {
1306                 vfree(data);
1307                 TRACE_RET(chip, STATUS_NOMEM);
1308         }
1309
1310         j = 0;
1311         for (i = 0; i < len; i++) {
1312                 mask[j] |= 0xFF << (offset * 8);
1313                 data[j] |= buf[i] << (offset * 8);
1314                 if (++offset == 4) {
1315                         j++;
1316                         offset = 0;
1317                 }
1318         }
1319
1320         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1321                              dw_len * 4);
1322         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1323                              dw_len * 4);
1324
1325         for (i = 0; i < dw_len; i++) {
1326                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1327                                         mask[i], data[i]);
1328                 if (retval != STATUS_SUCCESS) {
1329                         vfree(data);
1330                         vfree(mask);
1331                         TRACE_RET(chip, STATUS_FAIL);
1332                 }
1333         }
1334
1335         vfree(data);
1336         vfree(mask);
1337
1338         return STATUS_SUCCESS;
1339 }
1340
1341 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1342                 int len)
1343 {
1344         u32 *data;
1345         u16 offset = addr % 4;
1346         u16 aligned_addr = addr - offset;
1347         int dw_len, i, j;
1348         int retval;
1349
1350         if ((len + offset) % 4)
1351                 dw_len = (len + offset) / 4 + 1;
1352         else
1353                 dw_len = (len + offset) / 4;
1354
1355         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1356
1357         data = vmalloc(dw_len * 4);
1358         if (!data)
1359                 TRACE_RET(chip, STATUS_NOMEM);
1360
1361         for (i = 0; i < dw_len; i++) {
1362                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1363                                         data + i);
1364                 if (retval != STATUS_SUCCESS) {
1365                         vfree(data);
1366                         TRACE_RET(chip, STATUS_FAIL);
1367                 }
1368         }
1369
1370         if (buf) {
1371                 j = 0;
1372
1373                 for (i = 0; i < len; i++) {
1374                         buf[i] = (u8)(data[j] >> (offset * 8));
1375                         if (++offset == 4) {
1376                                 j++;
1377                                 offset = 0;
1378                         }
1379                 }
1380         }
1381
1382         vfree(data);
1383
1384         return STATUS_SUCCESS;
1385 }
1386
1387 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1388 {
1389         int i, finished = 0;
1390         u8 tmp;
1391
1392         RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val);
1393         RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1394         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1395         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81);
1396
1397         for (i = 0; i < 100000; i++) {
1398                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1399                 if (!(tmp & 0x80)) {
1400                         finished = 1;
1401                         break;
1402                 }
1403         }
1404
1405         if (!finished)
1406                 TRACE_RET(chip, STATUS_FAIL);
1407
1408         return STATUS_SUCCESS;
1409 }
1410
1411 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1412 {
1413         int i, finished = 0;
1414         u16 data = 0;
1415         u8 tmp;
1416
1417         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1418         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80);
1419
1420         for (i = 0; i < 100000; i++) {
1421                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1422                 if (!(tmp & 0x80)) {
1423                         finished = 1;
1424                         break;
1425                 }
1426         }
1427
1428         if (!finished)
1429                 TRACE_RET(chip, STATUS_FAIL);
1430
1431         RTSX_READ_REG(chip, PHYDATA0, &tmp);
1432         data = tmp;
1433         RTSX_READ_REG(chip, PHYDATA1, &tmp);
1434         data |= (u16)tmp << 8;
1435
1436         if (val)
1437                 *val = data;
1438
1439         return STATUS_SUCCESS;
1440 }
1441
1442 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1443 {
1444         int i;
1445         u8 data = 0;
1446
1447         RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr);
1448
1449         for (i = 0; i < 100; i++) {
1450                 RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1451                 if (!(data & 0x80))
1452                         break;
1453                 udelay(1);
1454         }
1455
1456         if (data & 0x80)
1457                 TRACE_RET(chip, STATUS_TIMEDOUT);
1458
1459         RTSX_READ_REG(chip, EFUSE_DATA, &data);
1460         if (val)
1461                 *val = data;
1462
1463         return STATUS_SUCCESS;
1464 }
1465
1466 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1467 {
1468         int i, j;
1469         u8 data = 0, tmp = 0xFF;
1470
1471         for (i = 0; i < 8; i++) {
1472                 if (val & (u8)(1 << i))
1473                         continue;
1474
1475                 tmp &= (~(u8)(1 << i));
1476                 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1477
1478                 RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp);
1479                 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr);
1480
1481                 for (j = 0; j < 100; j++) {
1482                         RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1483                         if (!(data & 0x80))
1484                                 break;
1485                         wait_timeout(3);
1486                 }
1487
1488                 if (data & 0x80)
1489                         TRACE_RET(chip, STATUS_TIMEDOUT);
1490
1491                 wait_timeout(5);
1492         }
1493
1494         return STATUS_SUCCESS;
1495 }
1496
1497 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1498 {
1499         int retval;
1500         u16 value;
1501
1502         retval = rtsx_read_phy_register(chip, reg, &value);
1503         if (retval != STATUS_SUCCESS)
1504                 TRACE_RET(chip, STATUS_FAIL);
1505
1506         if (value & (1 << bit)) {
1507                 value &= ~(1 << bit);
1508                 retval = rtsx_write_phy_register(chip, reg, value);
1509                 if (retval != STATUS_SUCCESS)
1510                         TRACE_RET(chip, STATUS_FAIL);
1511         }
1512
1513         return STATUS_SUCCESS;
1514 }
1515
1516 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1517 {
1518         int retval;
1519         u16 value;
1520
1521         retval = rtsx_read_phy_register(chip, reg, &value);
1522         if (retval != STATUS_SUCCESS)
1523                 TRACE_RET(chip, STATUS_FAIL);
1524
1525         if (0 == (value & (1 << bit))) {
1526                 value |= (1 << bit);
1527                 retval = rtsx_write_phy_register(chip, reg, value);
1528                 if (retval != STATUS_SUCCESS)
1529                         TRACE_RET(chip, STATUS_FAIL);
1530         }
1531
1532         return STATUS_SUCCESS;
1533 }
1534
1535 int rtsx_check_link_ready(struct rtsx_chip *chip)
1536 {
1537         u8 val;
1538
1539         RTSX_READ_REG(chip, IRQSTAT0, &val);
1540
1541         dev_dbg(rtsx_dev(chip), "IRQSTAT0: 0x%x\n", val);
1542         if (val & LINK_RDY_INT) {
1543                 dev_dbg(rtsx_dev(chip), "Delinked!\n");
1544                 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1545                 return STATUS_FAIL;
1546         }
1547
1548         return STATUS_SUCCESS;
1549 }
1550
1551 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1552 {
1553         u32 ultmp;
1554
1555         dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1556                 chip->product_id, dstate);
1557
1558         if (CHK_SDIO_EXIST(chip)) {
1559                 u8 func_no;
1560
1561                 if (CHECK_PID(chip, 0x5288))
1562                         func_no = 2;
1563                 else
1564                         func_no = 1;
1565
1566                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
1567                 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
1568                         (int)func_no, ultmp);
1569                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
1570         }
1571
1572         rtsx_write_config_byte(chip, 0x44, dstate);
1573         rtsx_write_config_byte(chip, 0x45, 0);
1574 }
1575
1576 void rtsx_enter_L1(struct rtsx_chip *chip)
1577 {
1578         rtsx_handle_pm_dstate(chip, 2);
1579 }
1580
1581 void rtsx_exit_L1(struct rtsx_chip *chip)
1582 {
1583         rtsx_write_config_byte(chip, 0x44, 0);
1584         rtsx_write_config_byte(chip, 0x45, 0);
1585 }
1586
1587 void rtsx_enter_ss(struct rtsx_chip *chip)
1588 {
1589         dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
1590
1591         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1592
1593         if (chip->power_down_in_ss) {
1594                 rtsx_power_off_card(chip);
1595                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1596         }
1597
1598         if (CHK_SDIO_EXIST(chip)) {
1599                 if (CHECK_PID(chip, 0x5288))
1600                         rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100);
1601                 else
1602                         rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100);
1603         }
1604
1605         if (chip->auto_delink_en) {
1606                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
1607         } else {
1608                 if (!chip->phy_debug_mode) {
1609                         u32 tmp;
1610
1611                         tmp = rtsx_readl(chip, RTSX_BIER);
1612                         tmp |= CARD_INT;
1613                         rtsx_writel(chip, RTSX_BIER, tmp);
1614                 }
1615
1616                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
1617         }
1618
1619         rtsx_enter_L1(chip);
1620
1621         RTSX_CLR_DELINK(chip);
1622         rtsx_set_stat(chip, RTSX_STAT_SS);
1623 }
1624
1625 void rtsx_exit_ss(struct rtsx_chip *chip)
1626 {
1627         dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
1628
1629         rtsx_exit_L1(chip);
1630
1631         if (chip->power_down_in_ss) {
1632                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
1633                 udelay(1000);
1634         }
1635
1636         if (RTSX_TST_DELINK(chip)) {
1637                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1638                 rtsx_reinit_cards(chip, 1);
1639                 RTSX_CLR_DELINK(chip);
1640         } else if (chip->power_down_in_ss) {
1641                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1642                 rtsx_reinit_cards(chip, 0);
1643         }
1644 }
1645
1646 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
1647 {
1648         u32 status, int_enable;
1649         int exit_ss = 0;
1650 #ifdef SUPPORT_OCP
1651         u32 ocp_int = 0;
1652
1653         ocp_int = OC_INT;
1654 #endif
1655
1656         if (chip->ss_en) {
1657                 chip->ss_counter = 0;
1658                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
1659                         exit_ss = 1;
1660                         rtsx_exit_L1(chip);
1661                         rtsx_set_stat(chip, RTSX_STAT_RUN);
1662                 }
1663         }
1664
1665         int_enable = rtsx_readl(chip, RTSX_BIER);
1666         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
1667
1668         if (((chip->int_reg & int_enable) == 0) ||
1669                 (chip->int_reg == 0xFFFFFFFF))
1670                 return STATUS_FAIL;
1671
1672         status = chip->int_reg &= (int_enable | 0x7FFFFF);
1673
1674         if (status & CARD_INT) {
1675                 chip->auto_delink_cnt = 0;
1676
1677                 if (status & SD_INT) {
1678                         if (status & SD_EXIST) {
1679                                 set_bit(SD_NR, &(chip->need_reset));
1680                         } else {
1681                                 set_bit(SD_NR, &(chip->need_release));
1682                                 chip->sd_reset_counter = 0;
1683                                 chip->sd_show_cnt = 0;
1684                                 clear_bit(SD_NR, &(chip->need_reset));
1685                         }
1686                 } else {
1687                         /* If multi-luns, it's possible that
1688                            when plugging/unplugging one card
1689                            there is another card which still
1690                            exists in the slot. In this case,
1691                            all existed cards should be reset.
1692                         */
1693                         if (exit_ss && (status & SD_EXIST))
1694                                 set_bit(SD_NR, &(chip->need_reinit));
1695                 }
1696                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
1697                         if (status & XD_INT) {
1698                                 if (status & XD_EXIST) {
1699                                         set_bit(XD_NR, &(chip->need_reset));
1700                                 } else {
1701                                         set_bit(XD_NR, &(chip->need_release));
1702                                         chip->xd_reset_counter = 0;
1703                                         chip->xd_show_cnt = 0;
1704                                         clear_bit(XD_NR, &(chip->need_reset));
1705                                 }
1706                         } else {
1707                                 if (exit_ss && (status & XD_EXIST))
1708                                         set_bit(XD_NR, &(chip->need_reinit));
1709                         }
1710                 }
1711                 if (status & MS_INT) {
1712                         if (status & MS_EXIST) {
1713                                 set_bit(MS_NR, &(chip->need_reset));
1714                         } else {
1715                                 set_bit(MS_NR, &(chip->need_release));
1716                                 chip->ms_reset_counter = 0;
1717                                 chip->ms_show_cnt = 0;
1718                                 clear_bit(MS_NR, &(chip->need_reset));
1719                         }
1720                 } else {
1721                         if (exit_ss && (status & MS_EXIST))
1722                                 set_bit(MS_NR, &(chip->need_reinit));
1723                 }
1724         }
1725
1726 #ifdef SUPPORT_OCP
1727         chip->ocp_int = ocp_int & status;
1728 #endif
1729
1730         if (chip->sd_io) {
1731                 if (chip->int_reg & DATA_DONE_INT)
1732                         chip->int_reg &= ~(u32)DATA_DONE_INT;
1733         }
1734
1735         return STATUS_SUCCESS;
1736 }
1737
1738 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
1739 {
1740         int retval;
1741
1742         dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
1743
1744         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
1745
1746         retval = rtsx_force_power_on(chip, SSC_PDCTL);
1747         if (retval != STATUS_SUCCESS)
1748                 return;
1749
1750         rtsx_release_cards(chip);
1751         rtsx_disable_bus_int(chip);
1752         turn_off_led(chip, LED_GPIO);
1753
1754 #ifdef HW_AUTO_SWITCH_SD_BUS
1755         if (chip->sd_io) {
1756                 chip->sdio_in_charge = 1;
1757                 if (CHECK_PID(chip, 0x5208)) {
1758                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
1759                         /* Enable sdio_bus_auto_switch */
1760                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
1761                 } else if (CHECK_PID(chip, 0x5288)) {
1762                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
1763                         /* Enable sdio_bus_auto_switch */
1764                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
1765                 }
1766         }
1767 #endif
1768
1769         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
1770                 /* u_force_clkreq_0 */
1771                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
1772         }
1773
1774         if (pm_stat == PM_S1) {
1775                 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
1776                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
1777                                 HOST_ENTER_S1);
1778         } else if (pm_stat == PM_S3) {
1779                 if (chip->s3_pwr_off_delay > 0)
1780                         wait_timeout(chip->s3_pwr_off_delay);
1781
1782                 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
1783                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
1784                                 HOST_ENTER_S3);
1785         }
1786
1787         if (chip->do_delink_before_power_down && chip->auto_delink_en)
1788                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
1789
1790         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1791
1792         chip->cur_clk = 0;
1793         chip->cur_card = 0;
1794         chip->card_exist = 0;
1795 }
1796
1797 void rtsx_enable_aspm(struct rtsx_chip *chip)
1798 {
1799         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
1800                 if (!chip->aspm_enabled) {
1801                         dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
1802                         chip->aspm_enabled = 1;
1803
1804                         if (chip->asic_code && CHECK_PID(chip, 0x5208))
1805                                 rtsx_write_phy_register(chip, 0x07, 0);
1806                         if (CHECK_PID(chip, 0x5208)) {
1807                                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
1808                                         0x30 | chip->aspm_level[0]);
1809                         } else {
1810                                 rtsx_write_config_byte(chip, LCTLR,
1811                                                 chip->aspm_l0s_l1_en);
1812                         }
1813
1814                         if (CHK_SDIO_EXIST(chip)) {
1815                                 u16 val = chip->aspm_l0s_l1_en | 0x0100;
1816
1817                                 if (CHECK_PID(chip, 0x5288))
1818                                         rtsx_write_cfg_dw(chip, 2, 0xC0,
1819                                                         0xFFFF, val);
1820                                 else
1821                                         rtsx_write_cfg_dw(chip, 1, 0xC0,
1822                                                         0xFFFF, val);
1823                         }
1824                 }
1825         }
1826 }
1827
1828 void rtsx_disable_aspm(struct rtsx_chip *chip)
1829 {
1830         if (CHECK_PID(chip, 0x5208))
1831                 rtsx_monitor_aspm_config(chip);
1832
1833         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
1834                 if (chip->aspm_enabled) {
1835                         dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
1836                         chip->aspm_enabled = 0;
1837
1838                         if (chip->asic_code && CHECK_PID(chip, 0x5208))
1839                                 rtsx_write_phy_register(chip, 0x07, 0x0129);
1840                         if (CHECK_PID(chip, 0x5208))
1841                                 rtsx_write_register(chip, ASPM_FORCE_CTL,
1842                                                 0xF3, 0x30);
1843                         else
1844                                 rtsx_write_config_byte(chip, LCTLR, 0x00);
1845
1846                         wait_timeout(1);
1847                 }
1848         }
1849 }
1850
1851 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
1852 {
1853         int retval;
1854         int i, j;
1855         u16 reg_addr;
1856         u8 *ptr;
1857
1858         if (!buf)
1859                 TRACE_RET(chip, STATUS_ERROR);
1860
1861         ptr = buf;
1862         reg_addr = PPBUF_BASE2;
1863         for (i = 0; i < buf_len/256; i++) {
1864                 rtsx_init_cmd(chip);
1865
1866                 for (j = 0; j < 256; j++)
1867                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
1868
1869                 retval = rtsx_send_cmd(chip, 0, 250);
1870                 if (retval < 0)
1871                         TRACE_RET(chip, STATUS_FAIL);
1872
1873                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
1874                 ptr += 256;
1875         }
1876
1877         if (buf_len%256) {
1878                 rtsx_init_cmd(chip);
1879
1880                 for (j = 0; j < buf_len%256; j++)
1881                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
1882
1883                 retval = rtsx_send_cmd(chip, 0, 250);
1884                 if (retval < 0)
1885                         TRACE_RET(chip, STATUS_FAIL);
1886         }
1887
1888         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
1889
1890         return STATUS_SUCCESS;
1891 }
1892
1893 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
1894 {
1895         int retval;
1896         int i, j;
1897         u16 reg_addr;
1898         u8 *ptr;
1899
1900         if (!buf)
1901                 TRACE_RET(chip, STATUS_ERROR);
1902
1903         ptr = buf;
1904         reg_addr = PPBUF_BASE2;
1905         for (i = 0; i < buf_len/256; i++) {
1906                 rtsx_init_cmd(chip);
1907
1908                 for (j = 0; j < 256; j++) {
1909                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
1910                                 *ptr);
1911                         ptr++;
1912                 }
1913
1914                 retval = rtsx_send_cmd(chip, 0, 250);
1915                 if (retval < 0)
1916                         TRACE_RET(chip, STATUS_FAIL);
1917         }
1918
1919         if (buf_len%256) {
1920                 rtsx_init_cmd(chip);
1921
1922                 for (j = 0; j < buf_len%256; j++) {
1923                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
1924                                 *ptr);
1925                         ptr++;
1926                 }
1927
1928                 retval = rtsx_send_cmd(chip, 0, 250);
1929                 if (retval < 0)
1930                         TRACE_RET(chip, STATUS_FAIL);
1931         }
1932
1933         return STATUS_SUCCESS;
1934 }
1935
1936 int rtsx_check_chip_exist(struct rtsx_chip *chip)
1937 {
1938         if (rtsx_readl(chip, 0) == 0xFFFFFFFF)
1939                 TRACE_RET(chip, STATUS_FAIL);
1940
1941         return STATUS_SUCCESS;
1942 }
1943
1944 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
1945 {
1946         int retval;
1947         u8 mask = 0;
1948
1949         if (ctl & SSC_PDCTL)
1950                 mask |= SSC_POWER_DOWN;
1951
1952 #ifdef SUPPORT_OCP
1953         if (ctl & OC_PDCTL) {
1954                 mask |= SD_OC_POWER_DOWN;
1955                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1956                         mask |= MS_OC_POWER_DOWN;
1957         }
1958 #endif
1959
1960         if (mask) {
1961                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
1962                 if (retval != STATUS_SUCCESS)
1963                         TRACE_RET(chip, STATUS_FAIL);
1964
1965                 if (CHECK_PID(chip, 0x5288))
1966                         wait_timeout(200);
1967         }
1968
1969         return STATUS_SUCCESS;
1970 }
1971
1972 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
1973 {
1974         int retval;
1975         u8 mask = 0, val = 0;
1976
1977         if (ctl & SSC_PDCTL)
1978                 mask |= SSC_POWER_DOWN;
1979
1980 #ifdef SUPPORT_OCP
1981         if (ctl & OC_PDCTL) {
1982                 mask |= SD_OC_POWER_DOWN;
1983                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1984                         mask |= MS_OC_POWER_DOWN;
1985         }
1986 #endif
1987
1988         if (mask) {
1989                 val = mask;
1990                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
1991                 if (retval != STATUS_SUCCESS)
1992                         TRACE_RET(chip, STATUS_FAIL);
1993         }
1994
1995         return STATUS_SUCCESS;
1996 }