drivers/staging/rts5139/xd.c

   1 /* Driver for Realtek RTS51xx USB card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  * Maintainer:
  22  *   Edwin Rong (edwin_rong@realsil.com.cn)
  23  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  24  */
  25
  26 #include <linux/blkdev.h>
  27 #include <linux/kthread.h>
  28 #include <linux/sched.h>
  29 #include <linux/vmalloc.h>
  30
  31 #include "debug.h"
  32 #include "trace.h"
  33 #include "rts51x.h"
  34 #include "rts51x_transport.h"
  35 #include "rts51x_scsi.h"
  36 #include "rts51x_card.h"
  37 #include "xd.h"
  38
  39 static int xd_build_l2p_tbl(struct rts51x_chip *chip, int zone_no);
  40 static int xd_init_page(struct rts51x_chip *chip, u32 phy_blk, u16 logoff,
  41                         u8 start_page, u8 end_page);
  42
  43 static inline void xd_set_err_code(struct rts51x_chip *chip, u8 err_code)
  44 {
  45         struct xd_info *xd_card = &(chip->xd_card);
  46
  47         xd_card->err_code = err_code;
  48 }
  49
  50 static inline int xd_check_err_code(struct rts51x_chip *chip, u8 err_code)
  51 {
  52         struct xd_info *xd_card = &(chip->xd_card);
  53
  54         return (xd_card->err_code == err_code);
  55 }
  56
  57 static int xd_set_init_para(struct rts51x_chip *chip)
  58 {
  59         struct xd_info *xd_card = &(chip->xd_card);
  60         int retval;
  61
  62         if (chip->asic_code)
  63                 xd_card->xd_clock = 47;
  64         else
  65                 xd_card->xd_clock = CLK_50;
  66
  67         retval = switch_clock(chip, xd_card->xd_clock);
  68         if (retval != STATUS_SUCCESS)
  69                 TRACE_RET(chip, retval);
  70
  71         return STATUS_SUCCESS;
  72 }
  73
  74 static int xd_switch_clock(struct rts51x_chip *chip)
  75 {
  76         struct xd_info *xd_card = &(chip->xd_card);
  77         int retval;
  78
  79         retval = rts51x_select_card(chip, XD_CARD);
  80         if (retval != STATUS_SUCCESS)
  81                 TRACE_RET(chip, retval);
  82
  83         retval = switch_clock(chip, xd_card->xd_clock);
  84         if (retval != STATUS_SUCCESS)
  85                 TRACE_RET(chip, retval);
  86
  87         return STATUS_SUCCESS;
  88 }
  89
  90 static int xd_read_id(struct rts51x_chip *chip, u8 id_cmd, u8 *id_buf,
  91                       u8 buf_len)
  92 {
  93         int retval, i;
  94
  95         rts51x_init_cmd(chip);
  96
  97         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
  98         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
  99                        XD_TRANSFER_START | XD_READ_ID);
 100         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
 101                        XD_TRANSFER_END);
 102
 103         for (i = 0; i < 4; i++) {
 104                 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_ADDRESS1 + i), 0,
 105                                0);
 106         }
 107
 108         retval = rts51x_send_cmd(chip, MODE_CR, 20);
 109         if (retval != STATUS_SUCCESS)
 110                 TRACE_RET(chip, retval);
 111
 112         retval = rts51x_get_rsp(chip, 5, 20);
 113
 114         if (retval != STATUS_SUCCESS) {
 115                 rts51x_clear_xd_error(chip);
 116                 TRACE_RET(chip, retval);
 117         }
 118
 119         if (id_buf && buf_len) {
 120                 if (buf_len > 4)
 121                         buf_len = 4;
 122                 rts51x_read_rsp_buf(chip, 1, id_buf, buf_len);
 123         }
 124
 125         return STATUS_SUCCESS;
 126 }
 127
 128 static void xd_assign_phy_addr(struct rts51x_chip *chip, u32 addr, u8 mode)
 129 {
 130         struct xd_info *xd_card = &(chip->xd_card);
 131
 132         switch (mode) {
 133         case XD_RW_ADDR:
 134                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
 135                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF,
 136                                (u8) addr);
 137                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF,
 138                                (u8) (addr >> 8));
 139                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF,
 140                                (u8) (addr >> 16));
 141                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 142                                xd_card->addr_cycle | XD_CALC_ECC |
 143                                XD_BA_NO_TRANSFORM);
 144                 break;
 145
 146         case XD_ERASE_ADDR:
 147                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF,
 148                                (u8) addr);
 149                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF,
 150                                (u8) (addr >> 8));
 151                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF,
 152                                (u8) (addr >> 16));
 153                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 154                                (xd_card->addr_cycle - 1) |
 155                                XD_CALC_ECC | XD_BA_NO_TRANSFORM);
 156                 break;
 157
 158         default:
 159                 break;
 160         }
 161 }
 162
 163 static int xd_read_redundant(struct rts51x_chip *chip, u32 page_addr, u8 *buf,
 164                              int buf_len)
 165 {
 166         int retval, i;
 167
 168         rts51x_init_cmd(chip);
 169
 170         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 171
 172         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 173                        XD_TRANSFER_START | XD_READ_REDUNDANT);
 174         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
 175                        XD_TRANSFER_END);
 176
 177         for (i = 0; i < 6; i++) {
 178                 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_PAGE_STATUS + i),
 179                                0, 0);
 180         }
 181         for (i = 0; i < 4; i++) {
 182                 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_RESERVED0 + i), 0,
 183                                0);
 184         }
 185         rts51x_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
 186
 187         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 188         if (retval != STATUS_SUCCESS)
 189                 TRACE_RET(chip, retval);
 190
 191         retval = rts51x_get_rsp(chip, 11, 500);
 192
 193         if (retval != STATUS_SUCCESS) {
 194                 rts51x_clear_xd_error(chip);
 195                 TRACE_RET(chip, retval);
 196         }
 197
 198         if (buf && buf_len) {
 199                 if (buf_len > 11)
 200                         buf_len = 11;
 201                 rts51x_read_rsp_buf(chip, 1, buf, buf_len);
 202         }
 203
 204         return STATUS_SUCCESS;
 205 }
 206
 207 static int xd_read_data_from_ppb(struct rts51x_chip *chip, int offset, u8 *buf,
 208                                  int buf_len)
 209 {
 210         int retval, i;
 211
 212         if (!buf || (buf_len <= 0))
 213                 TRACE_RET(chip, STATUS_FAIL);
 214
 215         rts51x_init_cmd(chip);
 216
 217         for (i = 0; i < buf_len; i++) {
 218                 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0,
 219                                0);
 220         }
 221
 222         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 223         if (retval != STATUS_SUCCESS)
 224                 TRACE_RET(chip, retval);
 225
 226         retval = rts51x_get_rsp(chip, buf_len, 200);
 227         if (retval != STATUS_SUCCESS)
 228                 TRACE_RET(chip, retval);
 229
 230         rts51x_read_rsp_buf(chip, 0, buf, buf_len);
 231
 232         return STATUS_SUCCESS;
 233 }
 234
 235 static int xd_read_cis(struct rts51x_chip *chip, u32 page_addr, u8 *buf,
 236                        int buf_len)
 237 {
 238         int retval;
 239         u8 reg;
 240
 241         if (!buf || (buf_len < 10))
 242                 TRACE_RET(chip, STATUS_FAIL);
 243
 244         rts51x_init_cmd(chip);
 245
 246         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 247
 248         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 249                        PINGPONG_BUFFER);
 250         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
 251         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
 252                        XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
 253
 254         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 255                        XD_TRANSFER_START | XD_READ_PAGES);
 256         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 257                        XD_TRANSFER_END | XD_PPB_EMPTY,
 258                        XD_TRANSFER_END | XD_PPB_EMPTY);
 259
 260         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 261         if (retval != STATUS_SUCCESS)
 262                 TRACE_RET(chip, retval);
 263
 264         retval = rts51x_get_rsp(chip, 1, 500);
 265         if (retval == STATUS_TIMEDOUT) {
 266                 rts51x_clear_xd_error(chip);
 267                 TRACE_RET(chip, retval);
 268         }
 269
 270         RTS51X_READ_REG(chip, XD_PAGE_STATUS, &reg);
 271         if (reg != XD_GPG) {
 272                 rts51x_clear_xd_error(chip);
 273                 TRACE_RET(chip, STATUS_FAIL);
 274         }
 275
 276         RTS51X_READ_REG(chip, XD_CTL, &reg);
 277
 278         if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
 279                 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
 280                 if (retval != STATUS_SUCCESS)
 281                         TRACE_RET(chip, retval);
 282                 if (reg & XD_ECC1_ERROR) {      /* correctable error */
 283                         u8 ecc_bit, ecc_byte;
 284
 285                         RTS51X_READ_REG(chip, XD_ECC_BIT1, &ecc_bit);
 286                         RTS51X_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte);
 287
 288                         RTS51X_DEBUGP("ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
 289                                        ecc_bit, ecc_byte);
 290                         if (ecc_byte < buf_len) {
 291                                 RTS51X_DEBUGP("Before correct: 0x%x\n",
 292                                                buf[ecc_byte]);
 293                                 buf[ecc_byte] ^= (1 << ecc_bit);
 294                                 RTS51X_DEBUGP("After correct: 0x%x\n",
 295                                                buf[ecc_byte]);
 296                         }
 297                 }
 298         } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
 299                 RTS51X_WRITE_REG(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
 300                                  XD_STOP | XD_CLR_ERR);
 301
 302                 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
 303                 if (retval != STATUS_SUCCESS)
 304                         TRACE_RET(chip, retval);
 305                 if (reg & XD_ECC2_ERROR) {
 306                         u8 ecc_bit, ecc_byte;
 307
 308                         RTS51X_READ_REG(chip, XD_ECC_BIT2, &ecc_bit);
 309                         RTS51X_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte);
 310
 311                         RTS51X_DEBUGP("ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
 312                                        ecc_bit, ecc_byte);
 313                         if (ecc_byte < buf_len) {
 314                                 RTS51X_DEBUGP("Before correct: 0x%x\n",
 315                                                buf[ecc_byte]);
 316                                 buf[ecc_byte] ^= (1 << ecc_bit);
 317                                 RTS51X_DEBUGP("After correct: 0x%x\n",
 318                                                buf[ecc_byte]);
 319                         }
 320                 }
 321         } else {
 322                 rts51x_clear_xd_error(chip);
 323                 TRACE_RET(chip, STATUS_FAIL);
 324         }
 325
 326         return STATUS_SUCCESS;
 327 }
 328
 329 static void xd_pull_ctl_disable(struct rts51x_chip *chip)
 330 {
 331         if (CHECK_PKG(chip, LQFP48)) {
 332                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
 333                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 334                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
 335                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 336                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
 337                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
 338         } else {
 339                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
 340                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 341                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
 342                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 343                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
 344                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
 345         }
 346 }
 347
 348 static void xd_pull_ctl_enable(struct rts51x_chip *chip)
 349 {
 350         if (CHECK_PKG(chip, LQFP48)) {
 351                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
 352                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 353                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
 354                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 355                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
 356                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
 357         } else {
 358                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA5);
 359                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x59);
 360                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
 361                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 362                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
 363                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
 364         }
 365 }
 366
 367 static int reset_xd(struct rts51x_chip *chip)
 368 {
 369         struct xd_info *xd_card = &(chip->xd_card);
 370         int retval, i, j;
 371         u8 id_buf[4], redunt[11];
 372
 373         retval = rts51x_select_card(chip, XD_CARD);
 374         if (retval != STATUS_SUCCESS)
 375                 TRACE_RET(chip, STATUS_FAIL);
 376
 377         rts51x_init_cmd(chip);
 378
 379         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
 380                        XD_PGSTS_NOT_FF);
 381         if (chip->asic_code)
 382                 xd_pull_ctl_disable(chip);
 383         else
 384                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 385                                (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3));
 386
 387         if (!chip->option.FT2_fast_mode) {
 388                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF,
 389                                0);
 390                 if (CHECK_PKG(chip, LQFP48) ||
 391                                 chip->option.rts5129_D3318_off_enable) {
 392                         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
 393                                        DV3318_AUTO_PWR_OFF,
 394                                        DV3318_AUTO_PWR_OFF);
 395                 }
 396         }
 397         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
 398         if (!chip->option.FT2_fast_mode) {
 399                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
 400                                POWER_OFF);
 401         }
 402
 403         retval = rts51x_send_cmd(chip, MODE_C, 100);
 404         if (retval != STATUS_SUCCESS)
 405                 TRACE_RET(chip, retval);
 406         if (!chip->option.FT2_fast_mode) {
 407 #ifdef SD_XD_IO_FOLLOW_PWR
 408                 if (CHECK_PKG(chip, LQFP48)
 409                     || chip->option.rts5129_D3318_off_enable) {
 410                         rts51x_write_register(chip, CARD_PWR_CTL,
 411                                         LDO_OFF, LDO_OFF);
 412                 }
 413 #endif
 414
 415                 wait_timeout(250);
 416
 417 #ifdef SD_XD_IO_FOLLOW_PWR
 418                 if (CHECK_PKG(chip, LQFP48)
 419                     || chip->option.rts5129_D3318_off_enable) {
 420                         rts51x_init_cmd(chip);
 421                         if (chip->asic_code) {
 422                                 xd_pull_ctl_enable(chip);
 423                         } else {
 424                                 rts51x_add_cmd(chip, WRITE_REG_CMD,
 425                                         FPGA_PULL_CTL, 0xFF,
 426                                         (FPGA_XD_PULL_CTL_EN1 &
 427                                                 FPGA_XD_PULL_CTL_EN2));
 428                         }
 429                         retval = rts51x_send_cmd(chip, MODE_C, 100);
 430                         if (retval != STATUS_SUCCESS)
 431                                 TRACE_RET(chip, STATUS_FAIL);
 432                 }
 433 #endif
 434
 435                 retval = card_power_on(chip, XD_CARD);
 436                 if (retval != STATUS_SUCCESS)
 437                         TRACE_RET(chip, retval);
 438 #ifdef SUPPORT_OCP
 439                 wait_timeout(50);
 440                 rts51x_get_card_status(chip, &(chip->card_status));
 441                 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
 442
 443                 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
 444                         RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
 445                                        chip->ocp_stat);
 446                         TRACE_RET(chip, STATUS_FAIL);
 447                 }
 448 #endif
 449         }
 450
 451         rts51x_init_cmd(chip);
 452
 453         if (chip->asic_code)
 454                 xd_pull_ctl_enable(chip);
 455         else
 456                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 457                                (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2));
 458         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN,
 459                        XD_OUTPUT_EN);
 460         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
 461
 462         retval = rts51x_send_cmd(chip, MODE_C, 100);
 463         if (retval != STATUS_SUCCESS)
 464                 TRACE_RET(chip, STATUS_FAIL);
 465
 466         if (!chip->option.FT2_fast_mode)
 467                 wait_timeout(200);
 468
 469         retval = xd_set_init_para(chip);
 470         if (retval != STATUS_SUCCESS)
 471                 TRACE_RET(chip, STATUS_FAIL);
 472         /* Read ID to check if the timing setting is right */
 473         for (i = 0; i < 4; i++) {
 474                 u8 xd_dat, xd_ctl;
 475
 476                 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST)
 477                         TRACE_RET(chip, STATUS_FAIL);
 478
 479                 rts51x_init_cmd(chip);
 480                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
 481                         XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP *
 482                         (2 + i + chip->option.xd_rw_step)
 483                         + XD_TIME_RWN_STEP * (i + chip->option.xd_rwn_step));
 484                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
 485                         XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 +
 486                         i) + XD_TIME_RWN_STEP * (3 + i));
 487
 488                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 489                                XD_TRANSFER_START | XD_RESET);
 490                 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 491                                XD_TRANSFER_END, XD_TRANSFER_END);
 492
 493                 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
 494                 rts51x_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
 495
 496                 retval = rts51x_send_cmd(chip, MODE_CR, 100);
 497                 if (retval != STATUS_SUCCESS) {
 498                         rts51x_clear_xd_error(chip);
 499                         TRACE_RET(chip, retval);
 500                 }
 501
 502                 retval = rts51x_get_rsp(chip, 3, 100);
 503                 if (retval != STATUS_SUCCESS) {
 504                         rts51x_clear_xd_error(chip);
 505                         TRACE_RET(chip, retval);
 506                 }
 507
 508                 xd_dat = chip->rsp_buf[1];
 509                 xd_ctl = chip->rsp_buf[2];
 510                 RTS51X_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", xd_dat, xd_ctl);
 511
 512                 if (((xd_dat & READY_FLAG) != READY_STATE)
 513                     || !(xd_ctl & XD_RDY))
 514                         continue;
 515
 516                 retval = xd_read_id(chip, READ_ID, id_buf, 4);
 517                 if (retval != STATUS_SUCCESS)
 518                         TRACE_RET(chip, retval);
 519
 520                 RTS51X_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
 521                                id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 522
 523                 xd_card->device_code = id_buf[1];
 524
 525                 switch (xd_card->device_code) {
 526                 case XD_4M_X8_512_1:
 527                 case XD_4M_X8_512_2:
 528                         xd_card->block_shift = 4;       /* 16 pages per block */
 529                         xd_card->page_off = 0x0F;
 530                         xd_card->addr_cycle = 3;
 531                         xd_card->zone_cnt = 1;
 532                         xd_card->capacity = 8000;       /* 500 * 2 ^ 4 */
 533                         XD_SET_4MB(xd_card);
 534                         break;
 535                 case XD_8M_X8_512:
 536                         xd_card->block_shift = 4;
 537                         xd_card->page_off = 0x0F;
 538                         xd_card->addr_cycle = 3;
 539                         xd_card->zone_cnt = 1;
 540                         xd_card->capacity = 16000;      /* 1000 * 2 ^ 4 */
 541                         break;
 542                 case XD_16M_X8_512:
 543                         XD_PAGE_512(xd_card);   /* 32 pages per block */
 544                         xd_card->addr_cycle = 3;
 545                         xd_card->zone_cnt = 1;
 546                         xd_card->capacity = 32000;      /* 1000 * 2 ^ 5 */
 547                         break;
 548                 case XD_32M_X8_512:
 549                         XD_PAGE_512(xd_card);
 550                         xd_card->addr_cycle = 3;
 551                         xd_card->zone_cnt = 2;
 552                         xd_card->capacity = 64000;      /* 2000 * 2 ^ 5 */
 553                         break;
 554                 case XD_64M_X8_512:
 555                         XD_PAGE_512(xd_card);
 556                         xd_card->addr_cycle = 4;
 557                         xd_card->zone_cnt = 4;
 558                         xd_card->capacity = 128000;     /* 4000 * 2 ^ 5 */
 559                         break;
 560                 case XD_128M_X8_512:
 561                         XD_PAGE_512(xd_card);
 562                         xd_card->addr_cycle = 4;
 563                         xd_card->zone_cnt = 8;
 564                         xd_card->capacity = 256000;     /* 8000 * 2 ^ 5 */
 565                         break;
 566                 case XD_256M_X8_512:
 567                         XD_PAGE_512(xd_card);
 568                         xd_card->addr_cycle = 4;
 569                         xd_card->zone_cnt = 16;
 570                         xd_card->capacity = 512000;     /* 16000 * 2 ^ 5 */
 571                         break;
 572                 case XD_512M_X8:
 573                         XD_PAGE_512(xd_card);
 574                         xd_card->addr_cycle = 4;
 575                         xd_card->zone_cnt = 32;
 576                         xd_card->capacity = 1024000;    /* 32000 * 2 ^ 5 */
 577                         break;
 578                 case xD_1G_X8_512:
 579                         XD_PAGE_512(xd_card);
 580                         xd_card->addr_cycle = 4;
 581                         xd_card->zone_cnt = 64;
 582                         xd_card->capacity = 2048000;    /* 64000 * 2 ^ 5 */
 583                         break;
 584                 case xD_2G_X8_512:
 585                         XD_PAGE_512(xd_card);
 586                         xd_card->addr_cycle = 4;
 587                         xd_card->zone_cnt = 128;
 588                         xd_card->capacity = 4096000;    /* 128000 * 2 ^ 5 */
 589                         break;
 590                 default:
 591                         continue;
 592                 }
 593
 594                 /* Confirm timing setting */
 595                 for (j = 0; j < 10; j++) {
 596                         retval = xd_read_id(chip, READ_ID, id_buf, 4);
 597                         if (retval != STATUS_SUCCESS)
 598                                 TRACE_RET(chip, retval);
 599
 600                         if (id_buf[1] != xd_card->device_code)
 601                                 break;
 602                 }
 603
 604                 /* Current timing pass */
 605                 if (j == 10)
 606                         break;
 607         }
 608
 609         if (i == 4) {
 610                 xd_card->block_shift = 0;
 611                 xd_card->page_off = 0;
 612                 xd_card->addr_cycle = 0;
 613                 xd_card->capacity = 0;
 614
 615                 TRACE_RET(chip, STATUS_FAIL);
 616         }
 617
 618         retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
 619         if (retval != STATUS_SUCCESS)
 620                 TRACE_RET(chip, retval);
 621         RTS51X_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
 622                        id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 623         if (id_buf[2] != XD_ID_CODE)
 624                 TRACE_RET(chip, STATUS_FAIL);
 625
 626         /* Search CIS block */
 627         for (i = 0; i < 24; i++) {
 628                 u32 page_addr;
 629
 630                 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST)
 631                         TRACE_RET(chip, STATUS_FAIL);
 632
 633                 page_addr = (u32) i << xd_card->block_shift;
 634
 635                 for (j = 0; j < 3; j++) {
 636                         retval = xd_read_redundant(chip, page_addr, redunt, 11);
 637                         if (retval == STATUS_SUCCESS)
 638                                 break;
 639                 }
 640                 if (j == 3)
 641                         continue;
 642
 643                 if (redunt[BLOCK_STATUS] != XD_GBLK)
 644                         continue;
 645
 646                 j = 0;
 647                 /* Check page status */
 648                 if (redunt[PAGE_STATUS] != XD_GPG) {
 649                         for (j = 1; j <= 8; j++) {
 650                                 retval =
 651                                     xd_read_redundant(chip, page_addr + j,
 652                                                       redunt, 11);
 653                                 if (retval == STATUS_SUCCESS) {
 654                                         if (redunt[PAGE_STATUS] == XD_GPG)
 655                                                 break;
 656                                 }
 657                         }
 658
 659                         if (j == 9)
 660                                 break;
 661                 }
 662
 663                 if ((redunt[BLOCK_STATUS] == XD_GBLK)
 664                     && (redunt[PARITY] & XD_BA1_ALL0)) {
 665                         u8 buf[10];
 666
 667                         page_addr += j;
 668
 669                         retval = xd_read_cis(chip, page_addr, buf, 10);
 670                         if (retval != STATUS_SUCCESS)
 671                                 TRACE_RET(chip, retval);
 672
 673                         if ((buf[0] == 0x01) && (buf[1] == 0x03)
 674                             && (buf[2] == 0xD9)
 675                             && (buf[3] == 0x01) && (buf[4] == 0xFF)
 676                             && (buf[5] == 0x18) && (buf[6] == 0x02)
 677                             && (buf[7] == 0xDF) && (buf[8] == 0x01)
 678                             && (buf[9] == 0x20)) {
 679                                 xd_card->cis_block = (u16) i;
 680                         }
 681                 }
 682
 683                 break;
 684         }
 685
 686         RTS51X_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block);
 687         if (xd_card->cis_block == 0xFFFF)
 688                 TRACE_RET(chip, STATUS_FAIL);
 689
 690         chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
 691
 692         return STATUS_SUCCESS;
 693 }
 694
 695 static int xd_check_data_blank(u8 *redunt)
 696 {
 697         int i;
 698
 699         for (i = 0; i < 6; i++) {
 700                 if (redunt[PAGE_STATUS + i] != 0xFF)
 701                         return 0;
 702         }
 703
 704         if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) !=
 705             (XD_ECC1_ALL1 | XD_ECC2_ALL1))
 706                 return 0;
 707
 708         for (i = 0; i < 4; i++) {
 709                 if (redunt[RESERVED0 + i] != 0xFF)
 710                         return 0;
 711         }
 712
 713         return 1;
 714 }
 715
 716 static u16 xd_load_log_block_addr(u8 *redunt)
 717 {
 718         u16 addr = 0xFFFF;
 719
 720         if (redunt[PARITY] & XD_BA1_BA2_EQL)
 721                 addr =
 722                     ((u16) redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
 723         else if (redunt[PARITY] & XD_BA1_VALID)
 724                 addr =
 725                     ((u16) redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
 726         else if (redunt[PARITY] & XD_BA2_VALID)
 727                 addr =
 728                     ((u16) redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L];
 729
 730         return addr;
 731 }
 732
 733 static int xd_init_l2p_tbl(struct rts51x_chip *chip)
 734 {
 735         struct xd_info *xd_card = &(chip->xd_card);
 736         int size, i;
 737
 738         RTS51X_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt);
 739
 740         if (xd_card->zone_cnt < 1)
 741                 TRACE_RET(chip, STATUS_FAIL);
 742
 743         size = xd_card->zone_cnt * sizeof(struct zone_entry);
 744         RTS51X_DEBUGP("Buffer size for l2p table is %d\n", size);
 745
 746         xd_card->zone = vmalloc(size);
 747         if (!xd_card->zone)
 748                 TRACE_RET(chip, STATUS_NOMEM);
 749
 750         for (i = 0; i < xd_card->zone_cnt; i++) {
 751                 xd_card->zone[i].build_flag = 0;
 752                 xd_card->zone[i].l2p_table = NULL;
 753                 xd_card->zone[i].free_table = NULL;
 754                 xd_card->zone[i].get_index = 0;
 755                 xd_card->zone[i].set_index = 0;
 756                 xd_card->zone[i].unused_blk_cnt = 0;
 757         }
 758
 759         return STATUS_SUCCESS;
 760 }
 761
 762 static inline void free_zone(struct zone_entry *zone)
 763 {
 764         RTS51X_DEBUGP("free_zone\n");
 765         if (!zone)
 766                 return;
 767         zone->build_flag = 0;
 768         zone->set_index = 0;
 769         zone->get_index = 0;
 770         zone->unused_blk_cnt = 0;
 771         if (zone->l2p_table) {
 772                 vfree(zone->l2p_table);
 773                 zone->l2p_table = NULL;
 774         }
 775         if (zone->free_table) {
 776                 vfree(zone->free_table);
 777                 zone->free_table = NULL;
 778         }
 779 }
 780
 781 static void xd_set_unused_block(struct rts51x_chip *chip, u32 phy_blk)
 782 {
 783         struct xd_info *xd_card = &(chip->xd_card);
 784         struct zone_entry *zone;
 785         int zone_no;
 786
 787         zone_no = (int)phy_blk >> 10;
 788         if (zone_no >= xd_card->zone_cnt) {
 789                 RTS51X_DEBUGP("Set unused block to invalid zone"
 790                                         "(zone_no = %d, zone_cnt = %d)\n",
 791                                         zone_no, xd_card->zone_cnt);
 792                 return;
 793         }
 794         zone = &(xd_card->zone[zone_no]);
 795
 796         if (zone->free_table == NULL) {
 797                 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
 798                         return;
 799         }
 800
 801         if ((zone->set_index >= XD_FREE_TABLE_CNT)
 802             || (zone->set_index < 0)) {
 803                 free_zone(zone);
 804                 RTS51X_DEBUGP("Set unused block fail, invalid set_index\n");
 805                 return;
 806         }
 807
 808         RTS51X_DEBUGP("Set unused block to index %d\n", zone->set_index);
 809
 810         zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff);
 811         if (zone->set_index >= XD_FREE_TABLE_CNT)
 812                 zone->set_index = 0;
 813         zone->unused_blk_cnt++;
 814 }
 815
 816 static u32 xd_get_unused_block(struct rts51x_chip *chip, int zone_no)
 817 {
 818         struct xd_info *xd_card = &(chip->xd_card);
 819         struct zone_entry *zone;
 820         u32 phy_blk;
 821
 822         if (zone_no >= xd_card->zone_cnt) {
 823                 RTS51X_DEBUGP("Get unused block from invalid zone"
 824                                         "(zone_no = %d, zone_cnt = %d)\n",
 825                                         zone_no, xd_card->zone_cnt);
 826                 TRACE_RET(chip, BLK_NOT_FOUND);
 827         }
 828         zone = &(xd_card->zone[zone_no]);
 829
 830         if ((zone->unused_blk_cnt == 0) ||
 831                         (zone->set_index == zone->get_index)) {
 832                 free_zone(zone);
 833                 RTS51X_DEBUGP("Get unused block fail,"
 834                                         "no unused block available\n");
 835                 TRACE_RET(chip, BLK_NOT_FOUND);
 836         }
 837         if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
 838                 free_zone(zone);
 839                 RTS51X_DEBUGP("Get unused block fail, invalid get_index\n");
 840                 TRACE_RET(chip, BLK_NOT_FOUND);
 841         }
 842
 843         RTS51X_DEBUGP("Get unused block from index %d\n", zone->get_index);
 844
 845         phy_blk = zone->free_table[zone->get_index];
 846         zone->free_table[zone->get_index++] = 0xFFFF;
 847         if (zone->get_index >= XD_FREE_TABLE_CNT)
 848                 zone->get_index = 0;
 849         zone->unused_blk_cnt--;
 850
 851         phy_blk += ((u32) (zone_no) << 10);
 852         return phy_blk;
 853 }
 854
 855 static void xd_set_l2p_tbl(struct rts51x_chip *chip, int zone_no, u16 log_off,
 856                            u16 phy_off)
 857 {
 858         struct xd_info *xd_card = &(chip->xd_card);
 859         struct zone_entry *zone;
 860
 861         zone = &(xd_card->zone[zone_no]);
 862         zone->l2p_table[log_off] = phy_off;
 863 }
 864
 865 static u32 xd_get_l2p_tbl(struct rts51x_chip *chip, int zone_no, u16 log_off)
 866 {
 867         struct xd_info *xd_card = &(chip->xd_card);
 868         struct zone_entry *zone;
 869         int retval;
 870
 871         zone = &(xd_card->zone[zone_no]);
 872         if (zone->l2p_table[log_off] == 0xFFFF) {
 873                 u32 phy_blk = 0;
 874                 int i;
 875
 876                 retval = xd_delay_write(chip);
 877                 if (retval != STATUS_SUCCESS) {
 878                         RTS51X_DEBUGP("In xd_get_l2p_tbl,"
 879                                                 "delay write fail!\n");
 880                         TRACE_RET(chip, BLK_NOT_FOUND);
 881                 }
 882
 883                 if (zone->unused_blk_cnt <= 0) {
 884                         RTS51X_DEBUGP("No unused block!\n");
 885                         TRACE_RET(chip, BLK_NOT_FOUND);
 886                 }
 887
 888                 for (i = 0; i < zone->unused_blk_cnt; i++) {
 889                         phy_blk = xd_get_unused_block(chip, zone_no);
 890                         if (phy_blk == BLK_NOT_FOUND) {
 891                                 RTS51X_DEBUGP("No unused block available!\n");
 892                                 TRACE_RET(chip, BLK_NOT_FOUND);
 893                         }
 894
 895                         retval =
 896                             xd_init_page(chip, phy_blk, log_off, 0,
 897                                          xd_card->page_off + 1);
 898                         if (retval == STATUS_SUCCESS)
 899                                 break;
 900                 }
 901                 if (i >= zone->unused_blk_cnt) {
 902                         RTS51X_DEBUGP("No good unused block available!\n");
 903                         TRACE_RET(chip, BLK_NOT_FOUND);
 904                 }
 905
 906                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (phy_blk & 0x3FF));
 907                 return phy_blk;
 908         }
 909
 910         return (u32) zone->l2p_table[log_off] + ((u32) (zone_no) << 10);
 911 }
 912
 913 int reset_xd_card(struct rts51x_chip *chip)
 914 {
 915         struct xd_info *xd_card = &(chip->xd_card);
 916         int retval;
 917
 918         memset(xd_card, 0, sizeof(struct xd_info));
 919
 920         xd_card->block_shift = 0;
 921         xd_card->page_off = 0;
 922         xd_card->addr_cycle = 0;
 923         xd_card->capacity = 0;
 924         xd_card->zone_cnt = 0;
 925         xd_card->cis_block = 0xFFFF;
 926         xd_card->delay_write.delay_write_flag = 0;
 927
 928         enable_card_clock(chip, XD_CARD);
 929
 930         retval = reset_xd(chip);
 931         if (retval != STATUS_SUCCESS) {
 932                 if (chip->option.reset_or_rw_fail_set_pad_drive) {
 933                         rts51x_write_register(chip, CARD_DRIVE_SEL,
 934                                               SD20_DRIVE_MASK, DRIVE_8mA);
 935                 }
 936                 TRACE_RET(chip, retval);
 937         }
 938
 939         retval = xd_init_l2p_tbl(chip);
 940         if (retval != STATUS_SUCCESS)
 941                 TRACE_RET(chip, retval);
 942
 943         return STATUS_SUCCESS;
 944 }
 945
 946 static int xd_mark_bad_block(struct rts51x_chip *chip, u32 phy_blk)
 947 {
 948         struct xd_info *xd_card = &(chip->xd_card);
 949         int retval;
 950         u32 page_addr;
 951         u8 reg = 0;
 952
 953         RTS51X_DEBUGP("mark block 0x%x as bad block\n", phy_blk);
 954
 955         if (phy_blk == BLK_NOT_FOUND)
 956                 TRACE_RET(chip, STATUS_FAIL);
 957
 958         rts51x_init_cmd(chip);
 959
 960         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
 961         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF,
 962                        XD_LATER_BBLK);
 963         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
 964         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
 965         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
 966         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
 967         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
 968         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
 969         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
 970         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
 971
 972         page_addr = phy_blk << xd_card->block_shift;
 973
 974         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 975
 976         /* Specify page count */
 977         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
 978                        xd_card->page_off + 1);
 979
 980         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 981                        XD_TRANSFER_START | XD_WRITE_REDUNDANT);
 982         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
 983                        XD_TRANSFER_END);
 984
 985         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 986         if (retval != STATUS_SUCCESS)
 987                 TRACE_RET(chip, STATUS_FAIL);
 988
 989         retval = rts51x_get_rsp(chip, 1, 100);
 990
 991         if (retval != STATUS_SUCCESS) {
 992                 rts51x_clear_xd_error(chip);
 993                 rts51x_ep0_read_register(chip, XD_DAT, &reg);
 994                 if (reg & PROGRAM_ERROR)
 995                         xd_set_err_code(chip, XD_PRG_ERROR);
 996                 else
 997                         xd_set_err_code(chip, XD_TO_ERROR);
 998                 TRACE_RET(chip, STATUS_FAIL);
 999         }
1000
1001         return STATUS_SUCCESS;
1002 }
1003
1004 static int xd_init_page(struct rts51x_chip *chip, u32 phy_blk, u16 logoff,
1005                         u8 start_page, u8 end_page)
1006 {
1007         struct xd_info *xd_card = &(chip->xd_card);
1008         int retval;
1009         u32 page_addr;
1010         u8 reg = 0;
1011
1012         RTS51X_DEBUGP("Init block 0x%x\n", phy_blk);
1013
1014         if (start_page > end_page)
1015                 TRACE_RET(chip, STATUS_FAIL);
1016         if (phy_blk == BLK_NOT_FOUND)
1017                 TRACE_RET(chip, STATUS_FAIL);
1018
1019         rts51x_init_cmd(chip);
1020
1021         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1022         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1023         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF,
1024                        (u8) (logoff >> 8));
1025         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF,
1026                        (u8) logoff);
1027
1028         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1029
1030         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1031
1032         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1033                        XD_BA_TRANSFORM);
1034
1035         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1036                        (end_page - start_page));
1037
1038         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1039                        XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1040         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1041                        XD_TRANSFER_END);
1042
1043         retval = rts51x_send_cmd(chip, MODE_CR, 100);
1044         if (retval != STATUS_SUCCESS)
1045                 TRACE_RET(chip, STATUS_FAIL);
1046
1047         retval = rts51x_get_rsp(chip, 1, 500);
1048
1049         if (retval != STATUS_SUCCESS) {
1050                 rts51x_clear_xd_error(chip);
1051                 rts51x_ep0_read_register(chip, XD_DAT, &reg);
1052                 if (reg & PROGRAM_ERROR) {
1053                         xd_mark_bad_block(chip, phy_blk);
1054                         xd_set_err_code(chip, XD_PRG_ERROR);
1055                 } else {
1056                         xd_set_err_code(chip, XD_TO_ERROR);
1057                 }
1058                 TRACE_RET(chip, STATUS_FAIL);
1059         }
1060
1061         return STATUS_SUCCESS;
1062 }
1063
1064 static int xd_copy_page(struct rts51x_chip *chip,
1065                         u32 old_blk, u32 new_blk, u8 start_page, u8 end_page)
1066 {
1067         struct xd_info *xd_card = &(chip->xd_card);
1068         u32 old_page, new_page;
1069         u8 i, reg = 0;
1070         int retval;
1071
1072         RTS51X_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk,
1073                        new_blk);
1074
1075         if (start_page > end_page)
1076                 TRACE_RET(chip, STATUS_FAIL);
1077
1078         if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1079                 TRACE_RET(chip, STATUS_FAIL);
1080
1081         old_page = (old_blk << xd_card->block_shift) + start_page;
1082         new_page = (new_blk << xd_card->block_shift) + start_page;
1083
1084         XD_CLR_BAD_NEWBLK(xd_card);
1085
1086         RTS51X_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
1087
1088         for (i = start_page; i < end_page; i++) {
1089                 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1090                         RTS51X_WRITE_REG(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
1091                                          XD_STOP | XD_CLR_ERR);
1092                         xd_set_err_code(chip, XD_NO_CARD);
1093                         TRACE_RET(chip, STATUS_FAIL);
1094                 }
1095
1096                 rts51x_init_cmd(chip);
1097
1098                 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1099
1100                 /* Single page read */
1101                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1102                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1103                                XD_AUTO_CHK_DATA_STATUS, 0);
1104                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1105                                XD_TRANSFER_START | XD_READ_PAGES);
1106                 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1107                                XD_TRANSFER_END, XD_TRANSFER_END);
1108
1109                 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_XD_STATUS, 100);
1110                 if (retval != STATUS_SUCCESS)
1111                         TRACE_RET(chip, retval);
1112
1113                 retval = rts51x_get_rsp(chip, 4, 500);
1114                 if ((retval != STATUS_SUCCESS) ||
1115                     (chip->rsp_buf[2] & (XD_ECC1_ERROR | XD_ECC2_ERROR))) {
1116                         rts51x_clear_xd_error(chip);
1117                         reg = 0;
1118                         rts51x_ep0_read_register(chip, XD_CTL, &reg);
1119                         if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1120                                 wait_timeout(100);
1121
1122                                 if (monitor_card_cd(chip, XD_CARD) ==
1123                                     CD_NOT_EXIST) {
1124                                         xd_set_err_code(chip, XD_NO_CARD);
1125                                         TRACE_RET(chip, STATUS_FAIL);
1126                                 }
1127
1128                                 if (((reg &
1129                                       (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1130                                      == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1131                                     || ((reg & (XD_ECC2_ERROR |
1132                                         XD_ECC2_UNCORRECTABLE)) ==
1133                                      (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1134                                         RTS51X_WRITE_REG(chip, XD_PAGE_STATUS,
1135                                                          0xFF, XD_BPG);
1136                                         RTS51X_WRITE_REG(chip, XD_BLOCK_STATUS,
1137                                                          0xFF, XD_GBLK);
1138                                         XD_SET_BAD_OLDBLK(xd_card);
1139                                         RTS51X_DEBUGP("old block 0x%x"
1140                                                 "ecc error\n", old_blk);
1141                                 }
1142                         } else {
1143                                 xd_set_err_code(chip, XD_TO_ERROR);
1144                                 TRACE_RET(chip, STATUS_FAIL);
1145                         }
1146                 }
1147                 if (XD_CHK_BAD_OLDBLK(xd_card))
1148                         rts51x_clear_xd_error(chip);
1149
1150                 rts51x_init_cmd(chip);
1151
1152                 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1153                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1154                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1155                                XD_TRANSFER_START | XD_WRITE_PAGES);
1156                 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1157                                XD_TRANSFER_END, XD_TRANSFER_END);
1158
1159                 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1160                 if (retval != STATUS_SUCCESS)
1161                         TRACE_RET(chip, retval);
1162
1163                 retval = rts51x_get_rsp(chip, 1, 300);
1164                 if (retval != STATUS_SUCCESS) {
1165                         rts51x_clear_xd_error(chip);
1166                         reg = 0;
1167                         rts51x_ep0_read_register(chip, XD_DAT, &reg);
1168                         if (reg & PROGRAM_ERROR) {
1169                                 xd_mark_bad_block(chip, new_blk);
1170                                 xd_set_err_code(chip, XD_PRG_ERROR);
1171                                 XD_SET_BAD_NEWBLK(xd_card);
1172                         } else {
1173                                 xd_set_err_code(chip, XD_TO_ERROR);
1174                         }
1175                         TRACE_RET(chip, retval);
1176                 }
1177
1178                 old_page++;
1179                 new_page++;
1180         }
1181
1182         return STATUS_SUCCESS;
1183 }
1184
1185 #ifdef XD_SPEEDUP
1186 static int xd_auto_copy_page(struct rts51x_chip *chip,
1187                              u32 old_blk, u32 new_blk,
1188                              u8 start_page, u8 end_page)
1189 {
1190         struct xd_info *xd_card = &(chip->xd_card);
1191         u32 old_page, new_page;
1192         int retval;
1193         u8 page_count;
1194
1195         RTS51X_DEBUGP("Auto copy page from block 0x%x to block 0x%x\n",
1196                        old_blk, new_blk);
1197
1198         if (start_page > end_page)
1199                 TRACE_RET(chip, STATUS_FAIL);
1200
1201         page_count = end_page - start_page;
1202
1203         if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1204                 TRACE_RET(chip, STATUS_FAIL);
1205
1206         old_page = (old_blk << xd_card->block_shift) + start_page;
1207         new_page = (new_blk << xd_card->block_shift) + start_page;
1208
1209         XD_CLR_BAD_NEWBLK(xd_card);
1210
1211         rts51x_init_cmd(chip);
1212
1213         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WAITTIME, 0x03, WAIT_FF);
1214         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_PAGELEN, 0xFF, page_count);
1215
1216         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR0, 0xFF, 0);
1217         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR1, 0xFF,
1218                        (u8) old_page);
1219         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR2, 0xFF,
1220                        (u8) (old_page >> 8));
1221         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR3, 0xFF,
1222                        (u8) (old_page >> 16));
1223         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_READADDR4, 0xFF, 0);
1224
1225         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR0, 0xFF, 0);
1226         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR1, 0xFF,
1227                        (u8) new_page);
1228         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR2, 0xFF,
1229                        (u8) (new_page >> 8));
1230         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR3, 0xFF,
1231                        (u8) (new_page >> 16));
1232         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CP_WRITEADDR4, 0xFF, 0);
1233
1234         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1235                        PINGPONG_BUFFER);
1236
1237         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG,
1238                        XD_BA_TRANSFORM | XD_ADDR_MASK, 0 | xd_card->addr_cycle);
1239
1240         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1241                        XD_AUTO_CHK_DATA_STATUS, 0);
1242         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1243                        XD_TRANSFER_START | XD_COPY_PAGES);
1244         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1245                        XD_TRANSFER_END);
1246
1247         retval = rts51x_send_cmd(chip, MODE_CR, 100);
1248         if (retval != STATUS_SUCCESS) {
1249                 rts51x_clear_xd_error(chip);
1250                 TRACE_GOTO(chip, Copy_Fail);
1251         }
1252
1253         retval = rts51x_get_rsp(chip, 1, 800);
1254         if (retval != STATUS_SUCCESS) {
1255                 rts51x_clear_xd_error(chip);
1256                 TRACE_GOTO(chip, Copy_Fail);
1257         }
1258
1259         return STATUS_SUCCESS;
1260
1261 Copy_Fail:
1262         retval = xd_copy_page(chip, old_blk, new_blk, start_page, end_page);
1263         if (retval != STATUS_SUCCESS)
1264                 TRACE_RET(chip, retval);
1265
1266         return STATUS_SUCCESS;
1267 }
1268 #endif
1269
1270 static int xd_reset_cmd(struct rts51x_chip *chip)
1271 {
1272         int retval;
1273         u8 xd_dat, xd_ctl;
1274
1275         rts51x_init_cmd(chip);
1276
1277         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1278                        XD_TRANSFER_START | XD_RESET);
1279         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1280                        XD_TRANSFER_END);
1281         rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1282         rts51x_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1283
1284         retval = rts51x_send_cmd(chip, MODE_CR, 100);
1285         if (retval != STATUS_SUCCESS)
1286                 TRACE_RET(chip, retval);
1287
1288         retval = rts51x_get_rsp(chip, 3, 100);
1289         if (retval != STATUS_SUCCESS) {
1290                 rts51x_clear_xd_error(chip);
1291                 TRACE_RET(chip, retval);
1292         }
1293
1294         xd_dat = chip->rsp_buf[1];
1295         xd_ctl = chip->rsp_buf[2];
1296         if (((xd_dat & READY_FLAG) == READY_STATE) && (xd_ctl & XD_RDY))
1297                 return STATUS_SUCCESS;
1298
1299         TRACE_RET(chip, STATUS_FAIL);
1300 }
1301
1302 static int xd_erase_block(struct rts51x_chip *chip, u32 phy_blk)
1303 {
1304         struct xd_info *xd_card = &(chip->xd_card);
1305         u32 page_addr;
1306         u8 reg = 0, xd_dat;
1307         int i, retval;
1308
1309         if (phy_blk == BLK_NOT_FOUND)
1310                 TRACE_RET(chip, STATUS_FAIL);
1311
1312         page_addr = phy_blk << xd_card->block_shift;
1313
1314         for (i = 0; i < 3; i++) {
1315                 rts51x_init_cmd(chip);
1316
1317                 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1318
1319                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1320                                XD_TRANSFER_START | XD_ERASE);
1321                 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1322                                XD_TRANSFER_END, XD_TRANSFER_END);
1323                 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1324
1325                 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1326                 if (retval != STATUS_SUCCESS)
1327                         TRACE_RET(chip, retval);
1328
1329                 retval = rts51x_get_rsp(chip, 2, 300);
1330                 if (retval != STATUS_SUCCESS) {
1331                         rts51x_clear_xd_error(chip);
1332                         rts51x_ep0_read_register(chip, XD_DAT, &reg);
1333                         if (reg & PROGRAM_ERROR) {
1334                                 xd_mark_bad_block(chip, phy_blk);
1335                                 xd_set_err_code(chip, XD_PRG_ERROR);
1336                                 TRACE_RET(chip, STATUS_FAIL);
1337                         } else {
1338                                 xd_set_err_code(chip, XD_ERASE_FAIL);
1339                         }
1340                         retval = xd_reset_cmd(chip);
1341                         if (retval != STATUS_SUCCESS)
1342                                 TRACE_RET(chip, retval);
1343                         continue;
1344                 }
1345                 xd_dat = chip->rsp_buf[1];
1346                 if (xd_dat & PROGRAM_ERROR) {
1347                         xd_mark_bad_block(chip, phy_blk);
1348                         xd_set_err_code(chip, XD_PRG_ERROR);
1349                         TRACE_RET(chip, STATUS_FAIL);
1350                 }
1351
1352                 return STATUS_SUCCESS;
1353         }
1354
1355         xd_mark_bad_block(chip, phy_blk);
1356         xd_set_err_code(chip, XD_ERASE_FAIL);
1357         TRACE_RET(chip, STATUS_FAIL);
1358 }
1359
1360 static int xd_build_l2p_tbl(struct rts51x_chip *chip, int zone_no)
1361 {
1362         struct xd_info *xd_card = &(chip->xd_card);
1363         struct zone_entry *zone;
1364         int retval;
1365         u32 start, end, i;
1366         u16 max_logoff, cur_fst_page_logoff, cur_lst_page_logoff,
1367             ent_lst_page_logoff;
1368         u8 redunt[11];
1369
1370         RTS51X_DEBUGP("xd_build_l2p_tbl: %d\n", zone_no);
1371
1372         if (xd_card->zone == NULL) {
1373                 retval = xd_init_l2p_tbl(chip);
1374                 if (retval != STATUS_SUCCESS)
1375                         TRACE_RET(chip, retval);
1376         }
1377
1378         if (xd_card->zone[zone_no].build_flag) {
1379                 RTS51X_DEBUGP("l2p table of zone %d has been built\n",
1380                                zone_no);
1381                 return STATUS_SUCCESS;
1382         }
1383
1384         zone = &(xd_card->zone[zone_no]);
1385
1386         if (zone->l2p_table == NULL) {
1387                 zone->l2p_table = vmalloc(2000);
1388                 if (zone->l2p_table == NULL)
1389                         TRACE_GOTO(chip, Build_Fail);
1390         }
1391         memset((u8 *) (zone->l2p_table), 0xff, 2000);
1392
1393         if (zone->free_table == NULL) {
1394                 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1395                 if (zone->free_table == NULL)
1396                         TRACE_GOTO(chip, Build_Fail);
1397         }
1398         memset((u8 *) (zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1399
1400         if (zone_no == 0) {
1401                 if (xd_card->cis_block == 0xFFFF)
1402                         start = 0;
1403                 else
1404                         start = xd_card->cis_block + 1;
1405                 if (XD_CHK_4MB(xd_card)) {
1406                         end = 0x200;
1407                         max_logoff = 499;
1408                 } else {
1409                         end = 0x400;
1410                         max_logoff = 999;
1411                 }
1412         } else {
1413                 start = (u32) (zone_no) << 10;
1414                 end = (u32) (zone_no + 1) << 10;
1415                 max_logoff = 999;
1416         }
1417
1418         RTS51X_DEBUGP("start block 0x%x, end block 0x%x\n", start, end);
1419
1420         zone->set_index = zone->get_index = 0;
1421         zone->unused_blk_cnt = 0;
1422
1423         for (i = start; i < end; i++) {
1424                 u32 page_addr = i << xd_card->block_shift;
1425                 u32 phy_block;
1426
1427                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1428                 if (retval != STATUS_SUCCESS)
1429                         continue;
1430
1431                 if (redunt[BLOCK_STATUS] != 0xFF) {
1432                         RTS51X_DEBUGP("bad block\n");
1433                         continue;
1434                 }
1435
1436                 if (xd_check_data_blank(redunt)) {
1437                         RTS51X_DEBUGP("blank block\n");
1438                         xd_set_unused_block(chip, i);
1439                         continue;
1440                 }
1441
1442                 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1443                 if ((cur_fst_page_logoff == 0xFFFF)
1444                     || (cur_fst_page_logoff > max_logoff)) {
1445                         retval = xd_erase_block(chip, i);
1446                         if (retval == STATUS_SUCCESS)
1447                                 xd_set_unused_block(chip, i);
1448                         continue;
1449                 }
1450                 if ((zone_no == 0) && (cur_fst_page_logoff == 0)
1451                     && (redunt[PAGE_STATUS] != XD_GPG))
1452                         XD_SET_MBR_FAIL(xd_card);
1453
1454                 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1455                         zone->l2p_table[cur_fst_page_logoff] =
1456                             (u16) (i & 0x3FF);
1457                         continue;
1458                 }
1459
1460                 phy_block =
1461                     zone->l2p_table[cur_fst_page_logoff] +
1462                     ((u32) ((zone_no) << 10));
1463
1464                 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1465
1466                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1467                 if (retval != STATUS_SUCCESS)
1468                         continue;
1469
1470                 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1471                 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1472                         int m;
1473
1474                         page_addr =
1475                             ((phy_block + 1) << xd_card->block_shift) - 1;
1476
1477                         for (m = 0; m < 3; m++) {
1478                                 retval =
1479                                     xd_read_redundant(chip, page_addr, redunt,
1480                                                       11);
1481                                 if (retval == STATUS_SUCCESS)
1482                                         break;
1483                         }
1484
1485                         if (m == 3) {
1486                                 zone->l2p_table[cur_fst_page_logoff] =
1487                                     (u16) (i & 0x3FF);
1488                                 retval = xd_erase_block(chip, phy_block);
1489                                 if (retval == STATUS_SUCCESS)
1490                                         xd_set_unused_block(chip, phy_block);
1491                                 continue;
1492                         }
1493
1494                         ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1495                         if (ent_lst_page_logoff != cur_fst_page_logoff) {
1496                                 zone->l2p_table[cur_fst_page_logoff] =
1497                                     (u16) (i & 0x3FF);
1498                                 retval = xd_erase_block(chip, phy_block);
1499                                 if (retval == STATUS_SUCCESS)
1500                                         xd_set_unused_block(chip, phy_block);
1501                                 continue;
1502                         } else {
1503                                 retval = xd_erase_block(chip, i);
1504                                 if (retval == STATUS_SUCCESS)
1505                                         xd_set_unused_block(chip, i);
1506                         }
1507                 } else {
1508                         retval = xd_erase_block(chip, i);
1509                         if (retval == STATUS_SUCCESS)
1510                                 xd_set_unused_block(chip, i);
1511                 }
1512         }
1513
1514         if (XD_CHK_4MB(xd_card))
1515                 end = 500;
1516         else
1517                 end = 1000;
1518
1519         i = 0;
1520         for (start = 0; start < end; start++) {
1521                 if (zone->l2p_table[start] == 0xFFFF)
1522                         i++;
1523         }
1524
1525         RTS51X_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i);
1526         RTS51X_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt);
1527
1528         if ((zone->unused_blk_cnt - i) < 1)
1529                 chip->card_wp |= XD_CARD;
1530
1531         zone->build_flag = 1;
1532
1533         return STATUS_SUCCESS;
1534
1535 Build_Fail:
1536         if (zone->l2p_table) {
1537                 vfree(zone->l2p_table);
1538                 zone->l2p_table = NULL;
1539         }
1540         if (zone->free_table) {
1541                 vfree(zone->free_table);
1542                 zone->free_table = NULL;
1543         }
1544
1545         return STATUS_FAIL;
1546 }
1547
1548 static int xd_send_cmd(struct rts51x_chip *chip, u8 cmd)
1549 {
1550         int retval;
1551
1552         rts51x_init_cmd(chip);
1553
1554         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1555         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1556                        XD_TRANSFER_START | XD_SET_CMD);
1557         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1558                        XD_TRANSFER_END);
1559
1560         retval = rts51x_send_cmd(chip, MODE_CR, 100);
1561         if (retval != STATUS_SUCCESS)
1562                 TRACE_RET(chip, retval);
1563
1564         retval = rts51x_get_rsp(chip, 1, 200);
1565         if (retval != STATUS_SUCCESS) {
1566                 rts51x_clear_xd_error(chip);
1567                 TRACE_RET(chip, retval);
1568         }
1569
1570         return STATUS_SUCCESS;
1571 }
1572
1573 static int xd_read_multiple_pages(struct rts51x_chip *chip, u32 phy_blk,
1574                                   u32 log_blk, u8 start_page, u8 end_page,
1575                                   u8 *buf, void **ptr, unsigned int *offset)
1576 {
1577         struct xd_info *xd_card = &(chip->xd_card);
1578         u32 page_addr, new_blk;
1579         u16 log_off;
1580         u8 reg_val, page_cnt;
1581         int zone_no, retval, i;
1582
1583         if (start_page > end_page)
1584                 TRACE_RET(chip, STATUS_FAIL);
1585
1586         page_cnt = end_page - start_page;
1587         zone_no = (int)(log_blk / 1000);
1588         log_off = (u16) (log_blk % 1000);
1589
1590         if ((phy_blk & 0x3FF) == 0x3FF) {
1591                 for (i = 0; i < 256; i++) {
1592                         page_addr = ((u32) i) << xd_card->block_shift;
1593
1594                         retval = xd_read_redundant(chip, page_addr, NULL, 0);
1595                         if (retval == STATUS_SUCCESS)
1596                                 break;
1597
1598                         if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1599                                 xd_set_err_code(chip, XD_NO_CARD);
1600                                 TRACE_RET(chip, STATUS_FAIL);
1601                         }
1602                 }
1603         }
1604
1605         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1606
1607         rts51x_init_cmd(chip);
1608
1609         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1610
1611         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE,
1612                        XD_PPB_TO_SIE);
1613         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1614                        RING_BUFFER);
1615         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1616         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1617                        XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1618
1619         trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512,
1620                          DMA_512);
1621
1622         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1623                        XD_TRANSFER_START | XD_READ_PAGES);
1624         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1625                        XD_TRANSFER_END | XD_PPB_EMPTY,
1626                        XD_TRANSFER_END | XD_PPB_EMPTY);
1627
1628         retval = rts51x_send_cmd(chip, MODE_CDIR, 100);
1629         if (retval != STATUS_SUCCESS)
1630                 TRACE_RET(chip, retval);
1631
1632         retval =
1633             rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip), (void *)buf,
1634                                          ptr, offset, page_cnt * 512,
1635                                          scsi_sg_count(chip->srb), NULL, 2000);
1636         if (retval != STATUS_SUCCESS) {
1637                 rts51x_clear_xd_error(chip);
1638
1639                 if (retval == STATUS_TIMEDOUT) {
1640                         xd_set_err_code(chip, XD_TO_ERROR);
1641                         TRACE_RET(chip, retval);
1642                 } else {
1643                         TRACE_GOTO(chip, Fail);
1644                 }
1645         }
1646         retval = rts51x_get_rsp(chip, 1, 200);
1647         if (retval != STATUS_SUCCESS) {
1648                 rts51x_clear_xd_error(chip);
1649
1650                 if (retval == STATUS_TIMEDOUT) {
1651                         xd_set_err_code(chip, XD_TO_ERROR);
1652                         TRACE_RET(chip, retval);
1653                 } else {
1654                         TRACE_GOTO(chip, Fail);
1655                 }
1656         }
1657
1658         return STATUS_SUCCESS;
1659
1660 Fail:
1661         rts51x_ep0_read_register(chip, XD_PAGE_STATUS, &reg_val);
1662         RTS51X_DEBUGP("XD_PAGE_STATUS: 0x%x\n", reg_val);
1663
1664         if (reg_val != XD_GPG)
1665                 xd_set_err_code(chip, XD_PRG_ERROR);
1666
1667         rts51x_ep0_read_register(chip, XD_CTL, &reg_val);
1668         RTS51X_DEBUGP("XD_CTL: 0x%x\n", reg_val);
1669
1670         /* Handle uncorrectable ECC error */
1671         if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1672              == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1673             || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))
1674                 == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1675                 wait_timeout(100);
1676
1677                 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1678                         xd_set_err_code(chip, XD_NO_CARD);
1679                         TRACE_RET(chip, STATUS_FAIL);
1680                 }
1681
1682                 xd_set_err_code(chip, XD_ECC_ERROR);
1683
1684                 new_blk = xd_get_unused_block(chip, zone_no);
1685                 if (new_blk == NO_NEW_BLK) {
1686                         XD_CLR_BAD_OLDBLK(xd_card);
1687                         TRACE_RET(chip, STATUS_FAIL);
1688                 }
1689 #ifdef XD_SPEEDUP
1690                 retval =
1691                     xd_auto_copy_page(chip, phy_blk, new_blk, 0,
1692                                       xd_card->page_off + 1);
1693 #else
1694                 retval =
1695                     xd_copy_page(chip, phy_blk, new_blk, 0,
1696                                  xd_card->page_off + 1);
1697 #endif
1698                 if (retval != STATUS_SUCCESS) {
1699                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1700                                 retval = xd_erase_block(chip, new_blk);
1701                                 if (retval == STATUS_SUCCESS)
1702                                         xd_set_unused_block(chip, new_blk);
1703                         } else {
1704                                 XD_CLR_BAD_NEWBLK(xd_card);
1705                         }
1706                         XD_CLR_BAD_OLDBLK(xd_card);
1707                         TRACE_RET(chip, STATUS_FAIL);
1708                 }
1709                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1710                 xd_erase_block(chip, phy_blk);
1711                 xd_mark_bad_block(chip, phy_blk);
1712                 XD_CLR_BAD_OLDBLK(xd_card);
1713         }
1714
1715         TRACE_RET(chip, STATUS_FAIL);
1716 }
1717
1718 static int xd_finish_write(struct rts51x_chip *chip,
1719                            u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1720 {
1721         struct xd_info *xd_card = &(chip->xd_card);
1722         int retval, zone_no;
1723         u16 log_off;
1724
1725         RTS51X_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x,"
1726                                 "log_blk = 0x%x\n", old_blk, new_blk, log_blk);
1727
1728         if (page_off > xd_card->page_off)
1729                 TRACE_RET(chip, STATUS_FAIL);
1730
1731         zone_no = (int)(log_blk / 1000);
1732         log_off = (u16) (log_blk % 1000);
1733
1734         if (old_blk == BLK_NOT_FOUND) {
1735                 retval = xd_init_page(chip, new_blk, log_off,
1736                                       page_off, xd_card->page_off + 1);
1737                 if (retval != STATUS_SUCCESS) {
1738                         retval = xd_erase_block(chip, new_blk);
1739                         if (retval == STATUS_SUCCESS)
1740                                 xd_set_unused_block(chip, new_blk);
1741                         TRACE_RET(chip, STATUS_FAIL);
1742                 }
1743         } else {
1744 #ifdef XD_SPEEDUP
1745                 retval = xd_auto_copy_page(chip, old_blk, new_blk,
1746                                            page_off, xd_card->page_off + 1);
1747 #else
1748                 retval = xd_copy_page(chip, old_blk, new_blk,
1749                                       page_off, xd_card->page_off + 1);
1750 #endif
1751                 if (retval != STATUS_SUCCESS) {
1752                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1753                                 retval = xd_erase_block(chip, new_blk);
1754                                 if (retval == STATUS_SUCCESS)
1755                                         xd_set_unused_block(chip, new_blk);
1756                         }
1757                         XD_CLR_BAD_NEWBLK(xd_card);
1758                         TRACE_RET(chip, STATUS_FAIL);
1759                 }
1760
1761                 retval = xd_erase_block(chip, old_blk);
1762                 if (retval == STATUS_SUCCESS) {
1763                         if (XD_CHK_BAD_OLDBLK(xd_card)) {
1764                                 xd_mark_bad_block(chip, old_blk);
1765                                 XD_CLR_BAD_OLDBLK(xd_card);
1766                         } else {
1767                                 /* Add source block to unused block */
1768                                 xd_set_unused_block(chip, old_blk);
1769                         }
1770                 } else {
1771                         xd_set_err_code(chip, XD_NO_ERROR);
1772                         XD_CLR_BAD_OLDBLK(xd_card);
1773                 }
1774         }
1775
1776         /* Add target block to L2P table */
1777         xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1778
1779         return STATUS_SUCCESS;
1780 }
1781
1782 static int xd_prepare_write(struct rts51x_chip *chip,
1783                             u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1784 {
1785         int retval;
1786
1787         RTS51X_DEBUGP("xd_prepare_write, old_blk = 0x%x, new_blk = 0x%x,"
1788                                 "log_blk = 0x%x, page_off = %d\n",
1789                                 old_blk, new_blk, log_blk, (int)page_off);
1790
1791         if (page_off) {
1792 #ifdef XD_SPEEDUP
1793                 retval = xd_auto_copy_page(chip, old_blk, new_blk, 0, page_off);
1794 #else
1795                 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1796 #endif
1797                 if (retval != STATUS_SUCCESS)
1798                         TRACE_RET(chip, retval);
1799         }
1800
1801         return STATUS_SUCCESS;
1802 }
1803
1804 static int xd_write_multiple_pages(struct rts51x_chip *chip, u32 old_blk,
1805                                    u32 new_blk, u32 log_blk, u8 start_page,
1806                                    u8 end_page, u8 *buf, void **ptr,
1807                                    unsigned int *offset)
1808 {
1809         struct xd_info *xd_card = &(chip->xd_card);
1810         u32 page_addr;
1811         int zone_no, retval;
1812         u16 log_off;
1813         u8 page_cnt, reg_val;
1814
1815         RTS51X_DEBUGP("xd_write_multiple_pages, old_blk = 0x%x,"
1816                                 "new_blk = 0x%x, log_blk = 0x%x\n",
1817                                 old_blk, new_blk, log_blk);
1818
1819         if (start_page > end_page)
1820                 TRACE_RET(chip, STATUS_FAIL);
1821
1822         page_cnt = end_page - start_page;
1823         zone_no = (int)(log_blk / 1000);
1824         log_off = (u16) (log_blk % 1000);
1825
1826         page_addr = (new_blk << xd_card->block_shift) + start_page;
1827
1828         /* Send index command */
1829         retval = xd_send_cmd(chip, READ1_1);
1830         if (retval != STATUS_SUCCESS)
1831                 TRACE_RET(chip, retval);
1832
1833         rts51x_init_cmd(chip);
1834
1835         /* Prepare redundant field */
1836         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF,
1837                        (u8) (log_off >> 8));
1838         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF,
1839                        (u8) log_off);
1840         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1841         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1842
1843         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1844
1845         /* Transform the block address by hardware */
1846         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1847                        XD_BA_TRANSFORM);
1848
1849         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1850         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1851                        RING_BUFFER);
1852
1853         trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512,
1854                          DMA_512);
1855
1856         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1857                        XD_TRANSFER_START | XD_WRITE_PAGES);
1858         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1859                        XD_TRANSFER_END);
1860
1861         retval = rts51x_send_cmd(chip, MODE_CDOR, 100);
1862         if (retval != STATUS_SUCCESS)
1863                 TRACE_RET(chip, retval);
1864
1865         retval =
1866             rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip), (void *)buf,
1867                                          ptr, offset, page_cnt * 512,
1868                                          scsi_sg_count(chip->srb), NULL, 2000);
1869         if (retval != STATUS_SUCCESS) {
1870                 rts51x_clear_xd_error(chip);
1871
1872                 if (retval == STATUS_TIMEDOUT) {
1873                         xd_set_err_code(chip, XD_TO_ERROR);
1874                         TRACE_RET(chip, retval);
1875                 } else {
1876                         TRACE_GOTO(chip, Fail);
1877                 }
1878         }
1879         retval = rts51x_get_rsp(chip, 1, 200);
1880         if (retval != STATUS_SUCCESS) {
1881                 rts51x_clear_xd_error(chip);
1882
1883                 if (retval == STATUS_TIMEDOUT) {
1884                         xd_set_err_code(chip, XD_TO_ERROR);
1885                         TRACE_RET(chip, retval);
1886                 } else {
1887                         TRACE_GOTO(chip, Fail);
1888                 }
1889         }
1890
1891         if (end_page == (xd_card->page_off + 1)) {
1892                 xd_card->delay_write.delay_write_flag = 0;
1893
1894                 if (old_blk != BLK_NOT_FOUND) {
1895                         retval = xd_erase_block(chip, old_blk);
1896                         if (retval == STATUS_SUCCESS) {
1897                                 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1898                                         xd_mark_bad_block(chip, old_blk);
1899                                         XD_CLR_BAD_OLDBLK(xd_card);
1900                                 } else {
1901                                         xd_set_unused_block(chip, old_blk);
1902                                 }
1903                         } else {
1904                                 xd_set_err_code(chip, XD_NO_ERROR);
1905                                 XD_CLR_BAD_OLDBLK(xd_card);
1906                         }
1907                 }
1908                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1909         }
1910
1911         return STATUS_SUCCESS;
1912
1913 Fail:
1914         rts51x_ep0_read_register(chip, XD_DAT, &reg_val);
1915         RTS51X_DEBUGP("XD_DAT: 0x%x\n", reg_val);
1916
1917         if (reg_val & PROGRAM_ERROR) {
1918                 xd_set_err_code(chip, XD_PRG_ERROR);
1919                 xd_mark_bad_block(chip, new_blk);
1920         }
1921
1922         TRACE_RET(chip, STATUS_FAIL);
1923 }
1924
1925 int xd_delay_write(struct rts51x_chip *chip)
1926 {
1927         struct xd_info *xd_card = &(chip->xd_card);
1928         struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1929         int retval;
1930
1931         if (delay_write->delay_write_flag) {
1932                 RTS51X_DEBUGP("xd_delay_write\n");
1933                 retval = xd_switch_clock(chip);
1934                 if (retval != STATUS_SUCCESS)
1935                         TRACE_RET(chip, retval);
1936
1937                 delay_write->delay_write_flag = 0;
1938                 retval = xd_finish_write(chip,
1939                                          delay_write->old_phyblock,
1940                                          delay_write->new_phyblock,
1941                                          delay_write->logblock,
1942                                          delay_write->pageoff);
1943                 if (retval != STATUS_SUCCESS)
1944                         TRACE_RET(chip, retval);
1945         }
1946
1947         return STATUS_SUCCESS;
1948 }
1949
1950 int xd_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector,
1951           u16 sector_cnt)
1952 {
1953         struct xd_info *xd_card = &(chip->xd_card);
1954         unsigned int lun = SCSI_LUN(srb);
1955         struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1956         int retval, zone_no;
1957         u32 log_blk, old_blk = 0, new_blk = 0;
1958         u16 log_off, total_sec_cnt = sector_cnt;
1959         u8 start_page, end_page = 0, page_cnt;
1960         u8 *buf;
1961         void *ptr = NULL;
1962         unsigned int offset = 0;
1963
1964         xd_set_err_code(chip, XD_NO_ERROR);
1965
1966         xd_card->counter = 0;
1967
1968         RTS51X_DEBUGP("xd_rw: scsi_bufflen = %d, scsi_sg_count = %d\n",
1969                        scsi_bufflen(srb), scsi_sg_count(srb));
1970         RTS51X_DEBUGP("Data direction: %s\n",
1971                        (srb->sc_data_direction ==
1972                         DMA_TO_DEVICE) ? "write" : "read");
1973
1974         buf = (u8 *) scsi_sglist(srb);
1975
1976         retval = xd_switch_clock(chip);
1977         if (retval != STATUS_SUCCESS)
1978                 TRACE_RET(chip, retval);
1979
1980         log_blk = start_sector >> xd_card->block_shift;
1981         start_page = (u8) start_sector & xd_card->page_off;
1982         zone_no = (int)(log_blk / 1000);
1983         log_off = (u16) (log_blk % 1000);
1984
1985         RTS51X_DEBUGP("log_blk = 0x%x\n", log_blk);
1986
1987         if (xd_card->zone[zone_no].build_flag == 0) {
1988                 retval = xd_build_l2p_tbl(chip, zone_no);
1989                 if (retval != STATUS_SUCCESS) {
1990                         chip->card_fail |= XD_CARD;
1991                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1992                         TRACE_RET(chip, retval);
1993                 }
1994         }
1995
1996         if (srb->sc_data_direction == DMA_TO_DEVICE) {
1997                 if (delay_write->delay_write_flag &&
1998                     (delay_write->logblock == log_blk) &&
1999                     (start_page > delay_write->pageoff)) {
2000                         delay_write->delay_write_flag = 0;
2001                         if (delay_write->old_phyblock != BLK_NOT_FOUND) {
2002 #ifdef XD_SPEEDUP
2003                                 retval = xd_auto_copy_page(chip,
2004                                         delay_write->old_phyblock,
2005                                         delay_write->new_phyblock,
2006                                         delay_write->pageoff, start_page);
2007 #else
2008                                 retval = xd_copy_page(chip,
2009                                                       delay_write->old_phyblock,
2010                                                       delay_write->new_phyblock,
2011                                                       delay_write->pageoff,
2012                                                       start_page);
2013 #endif
2014                                 if (retval != STATUS_SUCCESS) {
2015                                         set_sense_type(chip, lun,
2016                                                 SENSE_TYPE_MEDIA_WRITE_ERR);
2017                                         TRACE_RET(chip, retval);
2018                                 }
2019                         }
2020                         old_blk = delay_write->old_phyblock;
2021                         new_blk = delay_write->new_phyblock;
2022                 } else if (delay_write->delay_write_flag &&
2023                            (delay_write->logblock == log_blk) &&
2024                            (start_page == delay_write->pageoff)) {
2025                         delay_write->delay_write_flag = 0;
2026                         old_blk = delay_write->old_phyblock;
2027                         new_blk = delay_write->new_phyblock;
2028                 } else {
2029                         retval = xd_delay_write(chip);
2030                         if (retval != STATUS_SUCCESS) {
2031                                 set_sense_type(chip, lun,
2032                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2033                                 TRACE_RET(chip, retval);
2034                         }
2035                         old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2036                         new_blk = xd_get_unused_block(chip, zone_no);
2037                         if ((old_blk == BLK_NOT_FOUND)
2038                             || (new_blk == BLK_NOT_FOUND)) {
2039                                 set_sense_type(chip, lun,
2040                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2041                                 TRACE_RET(chip, retval);
2042                         }
2043
2044                         retval =
2045                             xd_prepare_write(chip, old_blk, new_blk, log_blk,
2046                                              start_page);
2047                         if (retval != STATUS_SUCCESS) {
2048                                 if (monitor_card_cd(chip, XD_CARD) ==
2049                                     CD_NOT_EXIST) {
2050                                         set_sense_type(chip, lun,
2051                                                 SENSE_TYPE_MEDIA_NOT_PRESENT);
2052                                         TRACE_RET(chip, STATUS_FAIL);
2053                                 }
2054                                 set_sense_type(chip, lun,
2055                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2056                                 TRACE_RET(chip, retval);
2057                         }
2058                 }
2059         } else {
2060                 retval = xd_delay_write(chip);
2061                 if (retval != STATUS_SUCCESS) {
2062                         if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
2063                                 set_sense_type(chip, lun,
2064                                                SENSE_TYPE_MEDIA_NOT_PRESENT);
2065                                 TRACE_RET(chip, STATUS_FAIL);
2066                         }
2067                         set_sense_type(chip, lun,
2068                                        SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2069                         TRACE_RET(chip, retval);
2070                 }
2071
2072                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2073                 if (old_blk == BLK_NOT_FOUND) {
2074                         set_sense_type(chip, lun,
2075                                        SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2076                         TRACE_RET(chip, STATUS_FAIL);
2077                 }
2078         }
2079
2080         RTS51X_DEBUGP("old_blk = 0x%x\n", old_blk);
2081         if (srb->sc_data_direction == DMA_TO_DEVICE)
2082                 RTS51X_DEBUGP("new_blk = 0x%x\n", new_blk);
2083
2084         while (total_sec_cnt) {
2085                 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
2086                         end_page = xd_card->page_off + 1;
2087                 else
2088                         end_page = start_page + (u8) total_sec_cnt;
2089                 page_cnt = end_page - start_page;
2090                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2091                         retval = xd_read_multiple_pages(chip, old_blk, log_blk,
2092                                                         start_page, end_page,
2093                                                         buf, &ptr, &offset);
2094                         if (retval != STATUS_SUCCESS) {
2095                                 set_sense_type(chip, lun,
2096                                         SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2097                                 TRACE_RET(chip, STATUS_FAIL);
2098                         }
2099                 } else {
2100                         retval =
2101                             xd_write_multiple_pages(chip, old_blk, new_blk,
2102                                                     log_blk, start_page,
2103                                                     end_page, buf, &ptr,
2104                                                     &offset);
2105                         if (retval != STATUS_SUCCESS) {
2106                                 set_sense_type(chip, lun,
2107                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2108                                 TRACE_RET(chip, STATUS_FAIL);
2109                         }
2110                 }
2111
2112                 total_sec_cnt -= page_cnt;
2113
2114                 if (total_sec_cnt == 0)
2115                         break;
2116
2117                 log_blk++;
2118                 zone_no = (int)(log_blk / 1000);
2119                 log_off = (u16) (log_blk % 1000);
2120
2121                 if (xd_card->zone[zone_no].build_flag == 0) {
2122                         retval = xd_build_l2p_tbl(chip, zone_no);
2123                         if (retval != STATUS_SUCCESS) {
2124                                 chip->card_fail |= XD_CARD;
2125                                 set_sense_type(chip, lun,
2126                                                SENSE_TYPE_MEDIA_NOT_PRESENT);
2127                                 TRACE_RET(chip, retval);
2128                         }
2129                 }
2130
2131                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2132                 if (old_blk == BLK_NOT_FOUND) {
2133                         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2134                                 set_sense_type(chip, lun,
2135                                         SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2136                         } else {
2137                                 set_sense_type(chip, lun,
2138                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2139                         }
2140                         TRACE_RET(chip, STATUS_FAIL);
2141                 }
2142
2143                 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2144                         new_blk = xd_get_unused_block(chip, zone_no);
2145                         if (new_blk == BLK_NOT_FOUND) {
2146                                 set_sense_type(chip, lun,
2147                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2148                                 TRACE_RET(chip, STATUS_FAIL);
2149                         }
2150                 }
2151
2152                 start_page = 0;
2153         }
2154
2155         if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
2156             (end_page != (xd_card->page_off + 1))) {
2157                 delay_write->delay_write_flag = 1;
2158                 delay_write->old_phyblock = old_blk;
2159                 delay_write->new_phyblock = new_blk;
2160                 delay_write->logblock = log_blk;
2161                 delay_write->pageoff = end_page;
2162         }
2163
2164         scsi_set_resid(srb, 0);
2165
2166         return STATUS_SUCCESS;
2167 }
2168
2169 void xd_free_l2p_tbl(struct rts51x_chip *chip)
2170 {
2171         struct xd_info *xd_card = &(chip->xd_card);
2172         int i = 0;
2173
2174         if (xd_card->zone != NULL) {
2175                 for (i = 0; i < xd_card->zone_cnt; i++) {
2176                         if (xd_card->zone[i].l2p_table != NULL) {
2177                                 vfree(xd_card->zone[i].l2p_table);
2178                                 xd_card->zone[i].l2p_table = NULL;
2179                         }
2180                         if (xd_card->zone[i].free_table != NULL) {
2181                                 vfree(xd_card->zone[i].free_table);
2182                                 xd_card->zone[i].free_table = NULL;
2183                         }
2184                 }
2185                 vfree(xd_card->zone);
2186                 xd_card->zone = NULL;
2187         }
2188 }
2189
2190 void xd_cleanup_work(struct rts51x_chip *chip)
2191 {
2192         struct xd_info *xd_card = &(chip->xd_card);
2193
2194         if (xd_card->delay_write.delay_write_flag) {
2195                 RTS51X_DEBUGP("xD: delay write\n");
2196                 xd_delay_write(chip);
2197                 xd_card->counter = 0;
2198         }
2199 }
2200
2201 int xd_power_off_card3v3(struct rts51x_chip *chip)
2202 {
2203         int retval;
2204
2205         rts51x_init_cmd(chip);
2206
2207         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
2208
2209         if (chip->asic_code)
2210                 xd_pull_ctl_disable(chip);
2211         else
2212                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 0xDF);
2213         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
2214         if (!chip->option.FT2_fast_mode) {
2215                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
2216                                POWER_OFF);
2217                 if (CHECK_PKG(chip, LQFP48)
2218                     || chip->option.rts5129_D3318_off_enable)
2219                         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
2220                                        DV3318_AUTO_PWR_OFF, 0);
2221         }
2222
2223         retval = rts51x_send_cmd(chip, MODE_C, 100);
2224         if (retval != STATUS_SUCCESS)
2225                 TRACE_RET(chip, retval);
2226
2227         return STATUS_SUCCESS;
2228 }
2229
2230 int release_xd_card(struct rts51x_chip *chip)
2231 {
2232         struct xd_info *xd_card = &(chip->xd_card);
2233         int retval;
2234
2235         RTS51X_DEBUGP("elease_xd_card\n");
2236
2237         chip->card_ready &= ~XD_CARD;
2238         chip->card_fail &= ~XD_CARD;
2239         chip->card_wp &= ~XD_CARD;
2240
2241         xd_card->delay_write.delay_write_flag = 0;
2242
2243         xd_free_l2p_tbl(chip);
2244
2245         rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);
2246
2247         retval = xd_power_off_card3v3(chip);
2248         if (retval != STATUS_SUCCESS)
2249                 TRACE_RET(chip, retval);
2250
2251         if (chip->asic_code && CHECK_PKG(chip, QFN24))
2252                 wait_timeout(20);
2253
2254         return STATUS_SUCCESS;
2255 }