drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h

   1 #ifndef __RTL8712_EDCASETTING_BITDEF_H__
   2 #define __RTL8712_EDCASETTING_BITDEF_H__
   3
   4 /*EDCAPARAM*/
   5 #define _TXOPLIMIT_MSK          0xFFFF0000
   6 #define _TXOPLIMIT_SHT          16
   7 #define _ECWIN_MSK              0x0000FF00
   8 #define _ECWIN_SHT              8
   9 #define _AIFS_MSK               0x000000FF
  10 #define _AIFS_SHT               0
  11
  12 /*BCNTCFG*/
  13 #define _BCNECW_MSK             0xFF00
  14 #define _BCNECW_SHT             8
  15 #define _BCNIFS_MSK             0x00FF
  16 #define _BCNIFS_SHT             0
  17
  18 /*CWRR*/
  19 #define _CWRR_MSK               0x03FF
  20
  21 /*ACMAVG*/
  22 #define _AVG_TIME_UP            BIT(3)
  23 #define _AVGPERIOD_MSK          0x03
  24
  25 /*ACMHWCTRL*/
  26 #define _VOQ_ACM_STATUS         BIT(6)
  27 #define _VIQ_ACM_STATUS         BIT(5)
  28 #define _BEQ_ACM_STATUS         BIT(4)
  29 #define _VOQ_ACM_EN             BIT(3)
  30 #define _VIQ_ACM_EN             BIT(2)
  31 #define _BEQ_ACM_EN             BIT(1)
  32 #define _ACMHWEN                BIT(0)
  33
  34 /*VO_ADMTIME*/
  35 #define _VO_ACM_RUT             BIT(18)
  36 #define _VO_ADMTIME_MSK         0x0003FFF
  37
  38 /*VI_ADMTIME*/
  39 #define _VI_ACM_RUT             BIT(18)
  40 #define _VI_ADMTIME_MSK         0x0003FFF
  41
  42 /*BE_ADMTIME*/
  43 #define _BE_ACM_RUT             BIT(18)
  44 #define _BE_ADMTIME_MSK         0x0003FFF
  45
  46 /*Retry limit reg*/
  47 #define _SRL_MSK                0xFF00
  48 #define _SRL_SHT                8
  49 #define _LRL_MSK                0x00FF
  50 #define _LRL_SHT                0
  51
  52 #endif /* __RTL8712_EDCASETTING_BITDEF_H__*/