1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 * Linux device driver for RTL8192U
5 * Based on the r8187 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
23 * Contact Information:
24 * wlanfae <wlanfae@realtek.com>
25 ******************************************************************************/
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/ioport.h>
34 #include <linux/sched.h>
35 #include <linux/types.h>
36 #include <linux/slab.h>
37 #include <linux/netdevice.h>
38 #include <linux/usb.h>
39 #include <linux/etherdevice.h>
40 #include <linux/delay.h>
41 #include <linux/rtnetlink.h> //for rtnl_lock()
42 #include <linux/wireless.h>
43 #include <linux/timer.h>
44 #include <linux/proc_fs.h> // Necessary because we use the proc fs
45 #include <linux/if_arp.h>
46 #include <linux/random.h>
47 #include <linux/version.h>
50 #include "ieee80211/ieee80211.h"
52 #include "r8192S_firmware.h"
53 #include "r8192SU_led.h"
55 /* EEPROM defs for use with linux/eeprom_93cx6.h */
56 #define RTL819X_EEPROM_CMD_READ (1 << 0)
57 #define RTL819X_EEPROM_CMD_WRITE (1 << 1)
58 #define RTL819X_EEPROM_CMD_CK (1 << 2)
59 #define RTL819X_EEPROM_CMD_CS (1 << 3)
61 #define RTL819xU_MODULE_NAME "rtl819xU"
64 #define MAX_KEY_LEN 61
65 #define KEY_BUF_SIZE 5
67 #define BIT0 0x00000001
68 #define BIT1 0x00000002
69 #define BIT2 0x00000004
70 #define BIT3 0x00000008
71 #define BIT4 0x00000010
72 #define BIT5 0x00000020
73 #define BIT6 0x00000040
74 #define BIT7 0x00000080
75 #define BIT8 0x00000100
76 #define BIT9 0x00000200
77 #define BIT10 0x00000400
78 #define BIT11 0x00000800
79 #define BIT12 0x00001000
80 #define BIT13 0x00002000
81 #define BIT14 0x00004000
82 #define BIT15 0x00008000
83 #define BIT16 0x00010000
84 #define BIT17 0x00020000
85 #define BIT18 0x00040000
86 #define BIT19 0x00080000
87 #define BIT20 0x00100000
88 #define BIT21 0x00200000
89 #define BIT22 0x00400000
90 #define BIT23 0x00800000
91 #define BIT24 0x01000000
92 #define BIT25 0x02000000
93 #define BIT26 0x04000000
94 #define BIT27 0x08000000
95 #define BIT28 0x10000000
96 #define BIT29 0x20000000
97 #define BIT30 0x40000000
98 #define BIT31 0x80000000
101 #define Rx_Smooth_Factor 20
102 #define DMESG(x,a...)
103 #define DMESGW(x,a...)
104 #define DMESGE(x,a...)
105 extern u32 rt_global_debug_component;
106 #define RT_TRACE(component, x, args...) \
107 do { if(rt_global_debug_component & component) \
108 printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
111 //----------------------------------------------------------------------
112 //// Get 8192SU Rx descriptor. Added by Roger, 2008.04.15.
113 ////----------------------------------------------------------------------
114 #define RX_DESC_SIZE 24
115 #define RX_DRV_INFO_SIZE_UNIT 8
117 #define IS_UNDER_11N_AES_MODE(_ieee) ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\
118 (_ieee->pairwise_key_type==KEY_TYPE_CCMP))
120 #define COMP_TRACE BIT0 // For function call tracing.
121 #define COMP_DBG BIT1 // Only for temporary debug message.
122 #define COMP_MLME BIT1
123 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
126 #define COMP_RECV BIT3 // Reveive part data path.
127 #define COMP_SEND BIT4 // Send part path.
128 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
129 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
130 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
131 #define COMP_SWBW BIT8 // For bandwidth switch.
132 #define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING
133 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
134 #define COMP_QOS BIT11 // For QoS.
135 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
136 #define COMP_LPS BIT13 // For Radio Measurement.
137 #define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
138 #define COMP_PHY BIT15
139 #define COMP_CH BIT16 //channel setting debug
140 #define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
141 #define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
142 #define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko.
143 #define COMP_SEC BIT20 // Event handling
144 #define COMP_LED BIT21 // For LED.
145 #define COMP_RF BIT22 // For RF.
146 #define COMP_RXDESC BIT23
148 #define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
150 #define COMP_FIRMWARE BIT24 //for firmware downloading
151 #define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11
152 #define COMP_AMSDU BIT26 // For A-MSDU Debugging
153 #define COMP_PS BIT26
155 #define COMP_SCAN BIT27
156 #define COMP_CMD BIT28
157 #define COMP_DOWN BIT29 //for rm driver module
158 #define COMP_RESET BIT30 //for silent reset
159 #define COMP_ERR BIT31 //for error out, always on
161 #define RTL819x_DEBUG
163 #define assert(expr) \
165 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
166 #expr,__FILE__,__FUNCTION__,__LINE__); \
169 #define RT_DEBUG_DATA(level, data, datalen) \
170 do{ if ((rt_global_debug_component & (level)) == (level)) \
173 u8* pdata = (u8*) data; \
174 printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \
175 for(i=0; i<(int)(datalen); i++) \
177 printk("%2x ", pdata[i]); \
178 if ((i+1)%16 == 0) printk("\n"); \
184 #define assert(expr) do {} while (0)
185 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
186 #endif /* RTL8169_DEBUG */
188 //2TODO: We should define 8192S firmware related macro settings here!!
189 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
190 #define RTL819X_TOTAL_RF_PATH 2
192 #define Rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
193 #define Rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
194 #define Rtl819XPHY_REGArray Rtl8192UsbPHY_REGArray
195 #define Rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
196 #define Rtl819XRadioC_Array Rtl8192UsbRadioC_Array
197 #define Rtl819XRadioD_Array Rtl8192UsbRadioD_Array
199 #define Rtl819XFwImageArray Rtl8192SUFwImgArray
200 #define Rtl819XMAC_Array Rtl8192SUMAC_2T_Array
201 #define Rtl819XAGCTAB_Array Rtl8192SUAGCTAB_Array
202 #define Rtl819XPHY_REG_Array Rtl8192SUPHY_REG_2T2RArray
203 #define Rtl819XPHY_REG_to1T1R_Array Rtl8192SUPHY_ChangeTo_1T1RArray
204 #define Rtl819XPHY_REG_to1T2R_Array Rtl8192SUPHY_ChangeTo_1T2RArray
205 #define Rtl819XPHY_REG_to2T2R_Array Rtl8192SUPHY_ChangeTo_2T2RArray
206 #define Rtl819XPHY_REG_Array_PG Rtl8192SUPHY_REG_Array_PG
207 #define Rtl819XRadioA_Array Rtl8192SURadioA_1T_Array
208 #define Rtl819XRadioB_Array Rtl8192SURadioB_Array
209 #define Rtl819XRadioB_GM_Array Rtl8192SURadioB_GM_Array
210 #define Rtl819XRadioA_to1T_Array Rtl8192SURadioA_to1T_Array
211 #define Rtl819XRadioA_to2T_Array Rtl8192SURadioA_to2T_Array
213 // Queue Select Value in TxDesc
219 #define QSLT_BEACON 0x10
220 #define QSLT_HIGH 0x11
221 #define QSLT_MGNT 0x12
222 #define QSLT_CMD 0x13
224 #define DESC90_RATE1M 0x00
225 #define DESC90_RATE2M 0x01
226 #define DESC90_RATE5_5M 0x02
227 #define DESC90_RATE11M 0x03
228 #define DESC90_RATE6M 0x04
229 #define DESC90_RATE9M 0x05
230 #define DESC90_RATE12M 0x06
231 #define DESC90_RATE18M 0x07
232 #define DESC90_RATE24M 0x08
233 #define DESC90_RATE36M 0x09
234 #define DESC90_RATE48M 0x0a
235 #define DESC90_RATE54M 0x0b
236 #define DESC90_RATEMCS0 0x00
237 #define DESC90_RATEMCS1 0x01
238 #define DESC90_RATEMCS2 0x02
239 #define DESC90_RATEMCS3 0x03
240 #define DESC90_RATEMCS4 0x04
241 #define DESC90_RATEMCS5 0x05
242 #define DESC90_RATEMCS6 0x06
243 #define DESC90_RATEMCS7 0x07
244 #define DESC90_RATEMCS8 0x08
245 #define DESC90_RATEMCS9 0x09
246 #define DESC90_RATEMCS10 0x0a
247 #define DESC90_RATEMCS11 0x0b
248 #define DESC90_RATEMCS12 0x0c
249 #define DESC90_RATEMCS13 0x0d
250 #define DESC90_RATEMCS14 0x0e
251 #define DESC90_RATEMCS15 0x0f
252 #define DESC90_RATEMCS32 0x20
254 // CCK Rates, TxHT = 0
255 #define DESC92S_RATE1M 0x00
256 #define DESC92S_RATE2M 0x01
257 #define DESC92S_RATE5_5M 0x02
258 #define DESC92S_RATE11M 0x03
260 // OFDM Rates, TxHT = 0
261 #define DESC92S_RATE6M 0x04
262 #define DESC92S_RATE9M 0x05
263 #define DESC92S_RATE12M 0x06
264 #define DESC92S_RATE18M 0x07
265 #define DESC92S_RATE24M 0x08
266 #define DESC92S_RATE36M 0x09
267 #define DESC92S_RATE48M 0x0a
268 #define DESC92S_RATE54M 0x0b
270 // MCS Rates, TxHT = 1
271 #define DESC92S_RATEMCS0 0x0c
272 #define DESC92S_RATEMCS1 0x0d
273 #define DESC92S_RATEMCS2 0x0e
274 #define DESC92S_RATEMCS3 0x0f
275 #define DESC92S_RATEMCS4 0x10
276 #define DESC92S_RATEMCS5 0x11
277 #define DESC92S_RATEMCS6 0x12
278 #define DESC92S_RATEMCS7 0x13
279 #define DESC92S_RATEMCS8 0x14
280 #define DESC92S_RATEMCS9 0x15
281 #define DESC92S_RATEMCS10 0x16
282 #define DESC92S_RATEMCS11 0x17
283 #define DESC92S_RATEMCS12 0x18
284 #define DESC92S_RATEMCS13 0x19
285 #define DESC92S_RATEMCS14 0x1a
286 #define DESC92S_RATEMCS15 0x1b
287 #define DESC92S_RATEMCS15_SG 0x1c
288 #define DESC92S_RATEMCS32 0x20
290 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
292 #define IEEE80211_WATCH_DOG_TIME 2000
293 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
294 //for txpowertracking
295 #define OFDM_Table_Length 19
296 #define CCK_Table_length 12
299 //Tx Descriptor for RLT8192SU(Normal mode)
301 typedef struct _tx_desc_819x_usb {
305 u8 Type:2; // Reserved for MAC header Frame Type subfield.
329 u8 PktOffset:5; //padding_len (hw)
336 u32 RTSRC:6; // Reserved for HW RTS Retry Count.
337 u32 DATARC:6; // Reserved for HW DATA Retry Count.
339 u32 AllowAggregation:1;
340 u32 BK:1; //Aggregation break.
344 u8 NextHeadPage;//:8;
355 u32 RaBRSRID:3; //Rate adaptive BRSR ID.
357 u32 TxShort:1;//for data
380 //u16 TxBuffSize;//:16;//pcie
385 }tx_desc_819x_usb, *ptx_desc_819x_usb;
386 typedef struct _tx_status_desc_8192s_usb{
414 }tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb;
419 //Tx Descriptor for RLT8192SU(Load FW mode)
421 typedef struct _tx_desc_cmd_819x_usb{
430 // DWORD 1, 2, 3, 4, 5, 6 are all reserved.
439 u16 TxBuffSize;//pcie
441 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
443 //H2C Command for RLT8192SU(Host TxCmd)
445 typedef struct _tx_h2c_desc_cmd_8192s_usb{
470 }tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb;
473 typedef struct _tx_h2c_cmd_hdr_8192s_usb{
481 }tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb;
483 typedef struct _tx_fwinfo_819x_usb{
490 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
491 u8 TxBandwidth:1; // This is used for HT MCS rate only.
492 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
494 u8 AllowAggregation:1;
495 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
496 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
497 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
498 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
500 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
506 u32 TxAGCOffSet:4;//TxAGCOffset:4;
510 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
512 typedef struct rtl8192_rx_info {
514 struct net_device *dev;
518 typedef struct rx_desc_819x_usb{
577 }rx_desc_819x_usb, *prx_desc_819x_usb;
581 // Driver info are written to the begining of the RxBuffer
583 typedef struct rx_drvinfo_819x_usb{
612 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
614 #define HWSET_MAX_SIZE_92S 128
615 #define MAX_802_11_HEADER_LENGTH 40
616 #define MAX_PKT_AGG_NUM 256
617 #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN
619 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
620 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
621 #define ENCRYPTION_MAX_OVERHEAD 128
622 #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
623 #define MAX_FRAGMENT_COUNT 8
625 #define MAX_TRANSMIT_BUFFER_SIZE 8000
627 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
629 #define scrclng 4 // octets for crc32 (FCS, ICV)
631 #define HAL_DM_DIG_DISABLE BIT0
632 #define HAL_DM_HIPWR_DISABLE BIT1
634 typedef enum rf_optype
636 RF_OP_By_SW_3wire = 0,
642 typedef enum _RT_STATUS{
643 RT_STATUS_SUCCESS = 0,
644 RT_STATUS_FAILURE = 1,
645 RT_STATUS_PENDING = 2,
646 RT_STATUS_RESOURCE = 3
647 }RT_STATUS,*PRT_STATUS;
649 typedef enum _RTL8192SUSB_LOOPBACK{
650 RTL8192SU_NO_LOOPBACK = 0,
651 RTL8192SU_MAC_LOOPBACK = 1,
652 RTL8192SU_DMA_LOOPBACK = 2,
653 RTL8192SU_CCK_LOOPBACK = 3,
654 }RTL8192SUSB_LOOPBACK_E;
656 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
659 /* Firmware Queue Layout */
660 #define NUM_OF_FIRMWARE_QUEUE 10
661 #define NUM_OF_PAGES_IN_FW 0x100
664 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
665 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
666 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
667 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
668 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
669 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
670 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
671 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
672 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
673 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
676 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
677 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
678 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
679 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
680 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
681 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
682 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
683 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
684 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
686 #define DEFAULT_FRAG_THRESHOLD 2342U
687 #define MIN_FRAG_THRESHOLD 256U
688 #define DEFAULT_BEACONINTERVAL 0x64U
689 #define DEFAULT_BEACON_ESSID "Rtl819xU"
691 #define DEFAULT_SSID ""
692 #define DEFAULT_RETRY_RTS 7
693 #define DEFAULT_RETRY_DATA 7
694 #define PRISM_HDR_SIZE 64
696 #define PHY_RSSI_SLID_WIN_MAX 100
699 typedef enum _WIRELESS_MODE {
700 WIRELESS_MODE_UNKNOWN = 0x00,
701 WIRELESS_MODE_A = 0x01,
702 WIRELESS_MODE_B = 0x02,
703 WIRELESS_MODE_G = 0x04,
704 WIRELESS_MODE_AUTO = 0x08,
705 WIRELESS_MODE_N_24G = 0x10,
706 WIRELESS_MODE_N_5G = 0x20
710 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
712 typedef struct buffer
719 typedef struct rtl_reg_debug{
725 unsigned char length;
727 unsigned char buf[0xff];
730 typedef struct _rt_9x_tx_rate_history {
734 }rt_tx_rahis_t, *prt_tx_rahis_t;
735 typedef struct _RT_SMOOTH_DATA_4RF {
736 char elements[4][100];//array to store values
737 u32 index; //index to current array to store
738 u32 TotalNum; //num of valid elements
739 u32 TotalVal[4]; //sum of valid elements
740 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
742 #define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size
743 //stats seems messed up, clean it ASAP
748 unsigned long rxframgment;
749 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
750 unsigned long rxurberr;
751 unsigned long rxstaterr;
752 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
753 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
754 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
755 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
756 unsigned long numpacket_matchbssid; // debug use only.
757 unsigned long numpacket_toself; // debug use only.
758 unsigned long num_process_phyinfo; // debug use only.
759 unsigned long numqry_phystatus;
760 unsigned long numqry_phystatusCCK;
761 unsigned long numqry_phystatusHT;
762 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
763 unsigned long txnperr;
764 unsigned long txnpdrop;
765 unsigned long txresumed;
766 unsigned long txnpokint;
767 unsigned long txoverflow;
768 unsigned long txlpokint;
769 unsigned long txlpdrop;
770 unsigned long txlperr;
771 unsigned long txbeokint;
772 unsigned long txbedrop;
773 unsigned long txbeerr;
774 unsigned long txbkokint;
775 unsigned long txbkdrop;
776 unsigned long txbkerr;
777 unsigned long txviokint;
778 unsigned long txvidrop;
779 unsigned long txvierr;
780 unsigned long txvookint;
781 unsigned long txvodrop;
782 unsigned long txvoerr;
783 unsigned long txbeaconokint;
784 unsigned long txbeacondrop;
785 unsigned long txbeaconerr;
786 unsigned long txmanageokint;
787 unsigned long txmanagedrop;
788 unsigned long txmanageerr;
789 unsigned long txdatapkt;
790 unsigned long txfeedback;
791 unsigned long txfeedbackok;
793 unsigned long txoktotal;
794 unsigned long txokbytestotal;
795 unsigned long txokinperiod;
796 unsigned long txmulticast;
797 unsigned long txbytesmulticast;
798 unsigned long txbroadcast;
799 unsigned long txbytesbroadcast;
800 unsigned long txunicast;
801 unsigned long txbytesunicast;
803 unsigned long rxoktotal;
804 unsigned long rxbytesunicast;
805 unsigned long txfeedbackfail;
806 unsigned long txerrtotal;
807 unsigned long txerrbytestotal;
808 unsigned long txerrmulticast;
809 unsigned long txerrbroadcast;
810 unsigned long txerrunicast;
811 unsigned long txretrycount;
812 unsigned long txfeedbackretry;
814 unsigned long slide_signal_strength[100];
815 unsigned long slide_evm[100];
816 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
817 unsigned long slide_evm_total; // For recording sliding window's EVM value
818 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
820 long last_signal_strength_inpercent;
821 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
822 u8 rx_rssi_percentage[4];
823 u8 rx_evm_percentage[2];
825 rt_tx_rahis_t txrate;
826 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
827 u32 Slide_Beacon_Total; //cosa add for beacon rssi
828 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
830 u32 CurrentShowTxate;
834 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
835 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
836 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
838 typedef struct ChnlAccessSetting {
845 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
847 typedef struct _BB_REGISTER_DEFINITION{
848 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
849 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
850 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
851 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
852 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
853 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
854 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
855 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
856 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
857 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
858 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
859 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
860 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
861 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
862 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
863 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
864 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
865 u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
866 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
868 typedef enum _RT_RF_TYPE_819xU{
873 RF_6052=4, // 4 11b/g/n RF
875 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
877 typedef enum _RF_POWER_STATE{
882 }RF_POWER_STATE, *PRF_POWER_STATE;
884 typedef struct _rate_adaptive
886 u8 rate_adaptive_disabled;
890 u32 high_rssi_thresh_for_ra;
891 u32 high2low_rssi_thresh_for_ra;
892 u8 low2high_rssi_thresh_for_ra40M;
893 u32 low_rssi_thresh_for_ra40M;
894 u8 low2high_rssi_thresh_for_ra20M;
895 u32 low_rssi_thresh_for_ra20M;
896 u32 upper_rssi_threshold_ratr;
897 u32 middle_rssi_threshold_ratr;
898 u32 low_rssi_threshold_ratr;
899 u32 low_rssi_threshold_ratr_40M;
900 u32 low_rssi_threshold_ratr_20M;
901 u8 ping_rssi_enable; //cosa add for test
902 u32 ping_rssi_ratr; //cosa add for test
903 u32 ping_rssi_thresh_for_ra;//cosa add for test
906 } rate_adaptive, *prate_adaptive;
908 #define TxBBGainTableLength 37
909 #define CCKTxBBGainTableLength 23
911 typedef struct _txbbgain_struct
913 long txbb_iq_amplifygain;
915 } txbbgain_struct, *ptxbbgain_struct;
917 typedef struct _ccktxbbgain_struct
919 //The Value is from a22 to a29 one Byte one time is much Safer
920 u8 ccktxbb_valuearray[8];
921 } ccktxbbgain_struct,*pccktxbbgain_struct;
924 typedef struct _init_gain
932 } init_gain, *pinit_gain;
934 typedef struct _phy_ofdm_rx_status_report_819xusb
949 }phy_sts_ofdm_819xusb_t;
951 typedef struct _phy_cck_rx_status_report_819xusb
953 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
954 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
958 }phy_sts_cck_819xusb_t;
961 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
966 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
968 typedef enum _RT_CUSTOMER_ID
971 RT_CID_8187_ALPHA0 = 1,
972 RT_CID_8187_SERCOMM_PS = 2,
973 RT_CID_8187_HW_LED = 3,
974 RT_CID_8187_NETGEAR = 4,
976 RT_CID_819x_CAMEO = 6,
977 RT_CID_819x_RUNTOP = 7,
978 RT_CID_819x_Senao = 8,
979 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
980 RT_CID_819x_Netcore = 10,
981 RT_CID_Nettronix = 11,
985 RT_CID_819x_ALPHA = 15,
986 RT_CID_819x_Sitecom = 16,
988 RT_CID_819x_Lenovo = 18,
989 RT_CID_819x_QMI = 19,
990 RT_CID_819x_Edimax_Belkin = 20,
991 RT_CID_819x_Sercomm_Belkin = 21,
992 RT_CID_819x_CAMEO1 = 22,
993 RT_CID_819x_MSI = 23,
994 RT_CID_819x_Acer = 24,
995 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
997 typedef enum _RT_OP_MODE{
999 RT_OP_MODE_INFRASTRUCTURE,
1002 }RT_OP_MODE, *PRT_OP_MODE;
1004 typedef enum _RESET_TYPE {
1005 RESET_TYPE_NORESET = 0x00,
1006 RESET_TYPE_NORMAL = 0x01,
1007 RESET_TYPE_SILENT = 0x02
1010 /* The simple tx command OP code. */
1011 typedef enum _tag_TxCmd_Config_Index{
1012 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
1013 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
1014 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
1015 TXCMD_SET_TX_DURATION = 0xFF900003,
1016 TXCMD_SET_RX_RSSI = 0xFF900004,
1017 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
1031 void (* rtl819x_read_eeprom_info)(struct net_device *dev);
1032 short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb);
1033 short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb);
1034 void (* rtl819x_rx_nomal)(struct sk_buff* skb);
1035 void (* rtl819x_rx_cmd)(struct sk_buff *skb);
1036 bool (* rtl819x_adapter_start)(struct net_device *dev);
1037 void (* rtl819x_link_change)(struct net_device *dev);
1038 void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation);
1039 void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
1042 typedef struct r8192_priv
1044 struct rtl819x_ops* ops;
1045 struct usb_device *udev;
1046 /* added for maintain info from eeprom */
1050 u8 eeprom_CustomerID;
1051 u8 eeprom_SubCustomerID;
1052 u16 eeprom_ChannelPlan;
1053 RT_CUSTOMER_ID CustomerID;
1054 LED_STRATEGY_819xUsb LedStrategy;
1055 u8 txqueue_to_outpipemap[9];
1062 struct ieee80211_device *ieee80211;
1067 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1068 u32 card_8192_version; /* if TCR reports card V B/C this discriminates */
1070 enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
1072 short plcp_preamble_mode;
1074 spinlock_t irq_lock;
1079 spinlock_t rf_lock; //used to lock rf write operation added by wb
1080 spinlock_t rf_ps_lock;
1088 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1089 bool bSurpriseRemoved;
1091 struct semaphore wx_sem;
1092 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1094 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1095 RT_RF_TYPE_819xU rf_chip;
1097 short (*rf_set_sens)(struct net_device *dev,short sens);
1098 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1099 void (*rf_close)(struct net_device *dev);
1100 void (*rf_init)(struct net_device *dev);
1105 struct iw_statistics wstats;
1106 struct proc_dir_entry *dir_dev;
1109 struct urb **rx_urb;
1110 struct urb **rx_cmd_urb;
1112 /* for Rx process */
1113 struct sk_buff_head rx_queue;
1114 struct sk_buff_head skb_queue;
1116 struct work_struct qos_activate;
1119 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1122 struct tasklet_struct irq_rx_tasklet;
1123 struct tasklet_struct irq_tx_tasklet;
1124 struct urb *rxurb_task;
1126 //2 Tx Related variables
1127 u16 ShortRetryLimit;
1130 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1132 u32 LastRxDescTSFHigh;
1133 u32 LastRxDescTSFLow;
1136 //2 Rx Related variables
1137 u16 EarlyRxThreshold;
1147 struct ChnlAccessSetting ChannelAccessSetting;
1149 struct work_struct reset_wq;
1150 struct work_struct mcast_wq;
1152 /**********************************************************/
1158 bool bCurrentRxAggrEnable;
1159 u8 Rf_Mode; //add for Firmware RF -R/W switch
1161 prt_firmware pFirmware;
1162 RTL8192SUSB_LOOPBACK_E LoopbackMode;
1165 u16 EEPROMTxPowerDiff;
1166 u8 EEPROMThermalMeter;
1168 u8 EEPROMCrystalCap;
1169 u8 EEPROMBluetoothCoexist;
1171 u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1172 u8 EEPROMTxPowerLevelCCK_V1[3];
1173 u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1174 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1178 bool bForcedShowRxRate;
1180 u32 RfRegChnlVal[2];
1182 bool bDmDisableProtect;
1183 bool bIgnoreDiffRateTxPowerOffset;
1185 // For EEPROM TX Power Index like 8190 series
1186 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1187 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1188 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1189 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1191 // F92S new definition
1192 //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14]
1193 u8 RfCckChnlAreaTxPwr[2][3];
1194 u8 RfOfdmChnlAreaTxPwr1T[2][3];
1195 u8 RfOfdmChnlAreaTxPwr2T[2][3];
1197 // Add For EEPROM Efuse switch and Efuse Shadow map Setting
1199 bool bBootFromEfuse; // system boot form EFUSE
1200 u8 EfuseMap[2][HWSET_MAX_SIZE_92S];
1202 u8 EfuseUsedPercentage;
1206 u8 EEPROMUsbPhyParam[5];
1209 bool bBootFromEEPROM; // system boot from EEPROM
1212 u8 EEPROMHT2T_TxPwr[6]; // For channel 1, 7 and 13 on path A/B.
1213 u8 EEPROMTxPwrTkMode;
1215 u8 bTXPowerDataReadFromEEPORM;
1216 u8 EEPROMRegulatory;
1217 u8 EEPROMPwrGroup[2][3];
1220 u8 EEPROMUsbEndPointNumber;
1222 bool AutoloadFailFlag;
1223 u8 RfTxPwrLevelCck[2][14];
1224 u8 RfTxPwrLevelOfdm1T[2][14];
1225 u8 RfTxPwrLevelOfdm2T[2][14];
1226 // new EEPROM format.
1227 u8 TxPwrHt20Diff[2][14]; // HT 20<->40 Pwr diff
1228 u8 TxPwrLegacyHtDiff[2][14]; // For HT<->legacy pwr diff
1229 u8 TxPwrbandEdgeHt40[2][2]; // Band edge for HY 40MHZlow/up channel
1230 u8 TxPwrbandEdgeHt20[2][2]; // Band edge for HY 40MHZ low/up channel
1231 u8 TxPwrbandEdgeLegacyOfdm[2][2]; // Band edge for legacy ofdm low/up channel
1232 u8 TxPwrbandEdgeFlag; // Band edge enable flag
1234 // L1 and L2 high power threshold.
1235 u8 MidHighPwrTHR_L1;
1236 u8 MidHighPwrTHR_L2;
1237 u8 TxPwrSafetyFlag; // for Tx power safety spec
1240 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1241 // Read/write are allow for following hardware information variables
1242 u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM
1243 u32 CCKTxPowerLevelOriginalOffset;
1244 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1245 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1246 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1249 u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1250 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1252 u8 CrystalCap; // CrystalCap.
1253 u8 BluetoothCoexist;
1257 // Use to calculate PWBD.
1259 long undecorated_smoothed_pwdb;
1262 u8 SwChnlInProgress;
1265 u8 SetBWModeInProgress;
1266 HT_CHANNEL_WIDTH CurrentChannelBW;
1267 bool bChnlPlanFromHW;
1273 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1277 bool brfpath_rxenable[4];
1279 bool SetRFPowerStateInProgress;
1281 struct timer_list watch_dog_timer;
1283 bool bdynamic_txpower; //bDynamicTxPower
1284 bool bDynamicTxHighPower; // Tx high power state
1285 bool bDynamicTxLowPower; // Tx low power state
1286 bool bLastDTPFlag_High;
1287 bool bLastDTPFlag_Low;
1289 bool bstore_last_dtpflag;
1290 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1292 rate_adaptive rate_adaptive;
1293 // TX power tracking
1294 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1295 u8 EEPROMTxPowerTrackEnable;
1296 u8 txpower_count;//For 6 sec do tracking again
1297 bool btxpower_trackingInit;
1300 u8 Record_CCK_20Mindex;
1301 u8 Record_CCK_40Mindex;
1302 // CCK TX Power Tracking
1303 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1304 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1305 u8 rfa_txpowertrackingindex;
1306 u8 rfa_txpowertrackingindex_real;
1307 u8 rfa_txpowertracking_default;
1308 u8 rfc_txpowertrackingindex;
1309 u8 rfc_txpowertrackingindex_real;
1311 s8 cck_present_attentuation;
1312 u8 cck_present_attentuation_20Mdefault;
1313 u8 cck_present_attentuation_40Mdefault;
1314 char cck_present_attentuation_difference;
1315 bool btxpower_tracking;
1317 bool btxpowerdata_readfromEEPORM;
1319 u8 CCKPresentAttentuation_20Mdefault;
1320 u8 CCKPresentAttentuation_40Mdefault;
1321 char CCKPresentAttentuation_difference;
1322 char CCKPresentAttentuation;
1323 bool bDMInitialGainEnable;
1324 //For Backup Initial Gain
1325 init_gain initgain_backup;
1326 u8 DefaultInitialGain[4];
1327 // For EDCA Turbo mode
1328 bool bis_any_nonbepkts;
1329 bool bcurrent_turbo_EDCA;
1330 bool bis_cur_rdlstate;
1331 struct timer_list fsync_timer;
1332 bool bfsync_processing; // 500ms Fsync timer is active or not
1334 u32 rateCountDiffRecord;
1335 u32 ContiuneDiffCount;
1340 u8 framesyncMonitor;
1343 u8 nrxAMPDU_aggr_num;
1349 bool bInPowerSaveMode;
1351 bool RFChangeInProgress;
1358 u32 txpower_checkcnt;
1359 u32 txpower_tracking_callback_cnt;
1360 u8 thermal_read_val[40];
1361 u8 thermal_readback_index;
1362 u32 ccktxpower_adjustcnt_not_ch14;
1363 u32 ccktxpower_adjustcnt_ch14;
1364 u8 tx_fwinfo_force_subcarriermode;
1365 u8 tx_fwinfo_force_subcarrierval;
1367 RESET_TYPE ResetProgress;
1368 bool bForcedSilentReset;
1369 bool bDisableNormalResetCheck;
1372 int IrpPendingCount;
1373 bool bResetInProgress;
1376 u8 InitialGainOperateType;
1380 struct delayed_work update_beacon_wq;
1381 struct delayed_work watch_dog_wq;
1382 struct delayed_work txpower_tracking_wq;
1383 struct delayed_work rfpath_check_wq;
1384 struct delayed_work gpio_change_rf_wq;
1385 struct delayed_work initialgain_operate_wq;
1387 struct workqueue_struct *priv_wq;
1390 // RF and BB access related synchronization flags.
1391 bool bChangeBBInProgress; // BaseBand RW is still in progress.
1392 bool bChangeRFInProgress; // RF RW is still in progress.
1394 u32 CCKTxPowerAdjustCntCh14; //debug only
1395 u32 CCKTxPowerAdjustCntNotCh14; //debug only
1396 u32 TXPowerTrackingCallbackCnt; //debug only
1397 u32 TxPowerCheckCnt; //debug only
1398 u32 RFWritePageCnt[3]; //debug only
1399 u32 RFReadPageCnt[3]; //debug only
1400 u8 ThermalReadBackIndex; //debug only
1401 u8 ThermalReadVal[40]; //debug only
1403 // not realize true, just define it, set it 0 default, because some func use it
1406 // The current Tx Power Level
1407 u8 CurrentCckTxPwrIdx;
1408 u8 CurrentOfdm24GTxPwrIdx;
1410 // For pass 92S common phycfg.c compiler
1411 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1412 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1413 u8 TxPowerLevelCCK_C[14]; // RF-C, CCK channel 1~14
1414 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1415 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1416 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1418 bool bRFSiOrPi;//0=si, 1=pi.
1420 bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only
1427 /* added for led control */
1432 struct work_struct BlinkWorkItem;
1433 /* added for led control */
1445 BULK_PRIORITY = 0x01,
1456 BEACON_PRIORITY, //0x0A
1461 UART_PRIORITY //0x0F
1465 struct ssid_thread {
1466 struct net_device *dev;
1467 u8 name[IW_ESSID_MAX_SIZE + 1];
1471 void LedControl8192SUsb(struct net_device *dev, LED_CTL_MODE LedAction);
1472 void InitSwLeds(struct net_device *dev);
1473 void DeInitSwLeds(struct net_device *dev);
1474 short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1475 short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
1476 bool FirmwareDownload92S(struct net_device *dev);
1478 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1479 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1481 u32 read_cam(struct net_device *dev, u8 addr);
1482 void write_cam(struct net_device *dev, u8 addr, u32 data);
1484 u8 read_nic_byte(struct net_device *dev, int x);
1485 u8 read_nic_byte_E(struct net_device *dev, int x);
1486 u32 read_nic_dword(struct net_device *dev, int x);
1487 u16 read_nic_word(struct net_device *dev, int x) ;
1488 void write_nic_byte(struct net_device *dev, int x,u8 y);
1489 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1490 void write_nic_word(struct net_device *dev, int x,u16 y);
1491 void write_nic_dword(struct net_device *dev, int x,u32 y);
1492 void force_pci_posting(struct net_device *dev);
1494 void rtl8192_rtx_disable(struct net_device *);
1495 void rtl8192_rx_enable(struct net_device *);
1496 void rtl8192_tx_enable(struct net_device *);
1498 void rtl8192_disassociate(struct net_device *dev);
1499 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1501 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1502 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1503 void rtl8192_update_msr(struct net_device *dev);
1504 int rtl8192_down(struct net_device *dev);
1505 int rtl8192_up(struct net_device *dev);
1506 void rtl8192_commit(struct net_device *dev);
1507 void rtl8192_set_chan(struct net_device *dev,short ch);
1508 void write_phy(struct net_device *dev, u8 adr, u8 data);
1509 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1510 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1511 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1512 void rtl8192_set_rxconf(struct net_device *dev);
1513 extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate);
1514 void CamResetAllEntry(struct net_device* dev);
1515 void EnableHWSecurityConfig8192(struct net_device *dev);
1516 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1517 short rtl8192_is_tx_queue_empty(struct net_device *dev);