1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
20 #include "r8192U_dm.h"
21 #include "r8192S_rtl6052.h"
23 #include "r8192S_hw.h"
24 #include "r8192S_phy.h"
25 #include "r8192S_phyreg.h"
26 #include "r8192SU_HWImg.h"
28 #include "ieee80211/dot11d.h"
30 /* Channel switch:The size of command tables for switch channel*/
31 #define MAX_PRECMD_CNT 16
32 #define MAX_RFDEPENDCMD_CNT 16
33 #define MAX_POSTCMD_CNT 16
34 #define MAX_DOZE_WAITING_TIMES_9x 64
37 phy_CalculateBitShift(u32 BitMask);
39 phy_ConfigMACWithHeaderFile(struct net_device* dev);
41 phy_InitBBRFRegisterDefinition(struct net_device* dev);
43 phy_BB8192S_Config_ParaFile(struct net_device* dev);
45 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
47 phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
49 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
51 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
53 SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
55 phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
58 struct net_device* dev,
65 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
66 static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx);
67 static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
68 void phy_SetFwCmdIOCallback(struct net_device* dev);
72 // Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
75 // - Only use on RTL8192S USB interface.
79 u32 phy_QueryUsbBBReg(struct net_device* dev, u32 RegAddr)
81 struct r8192_priv *priv = ieee80211_priv(dev);
82 u32 ReturnValue = 0xffffffff;
88 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
89 // We have to make sure that previous BB I/O has been done.
92 while(priv->bChangeBBInProgress)
95 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
98 // Wait too long, return FALSE to avoid to be stuck here.
99 if((BBWaitCounter > 100) )
101 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
106 priv->bChangeBBInProgress = true;
108 read_nic_dword(dev, RegAddr);
111 {// Make sure that access could be done.
112 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
114 }while( --PollingCnt );
118 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
122 // Data FW read back.
123 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
124 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
127 priv->bChangeBBInProgress = false;
136 // Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
139 // - Only use on RTL8192S USB interface.
143 phy_SetUsbBBReg(struct net_device* dev,u32 RegAddr,u32 Data)
145 struct r8192_priv *priv = ieee80211_priv(dev);
146 u8 BBWaitCounter = 0;
148 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
151 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
152 // We have to make sure that previous BB I/O has been done.
155 while(priv->bChangeBBInProgress)
158 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
161 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
163 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
168 priv->bChangeBBInProgress = true;
169 write_nic_dword(dev, RegAddr, Data);
171 priv->bChangeBBInProgress = false;
178 // RF read by 4181 to make sure that operation could be done in unlimited cycle.
181 // - Only use on RTL8192S USB interface.
183 // - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
185 // Created by Roger, 2008.09.06.
188 u32 phy_QueryUsbRFReg( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
191 struct r8192_priv *priv = ieee80211_priv(dev);
194 u8 RFWaitCounter = 0;
198 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
199 // We have to make sure that previous RF I/O has been done.
202 while(priv->bChangeRFInProgress)
207 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
210 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
212 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
220 priv->bChangeRFInProgress = true;
221 Offset &= 0x3f; //RF_Offset= 0x00~0x3F
223 write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
224 (Offset<<8)| //RF_Offset= 0x00~0x3F
225 (eRFPath<<16)); //RF_Path = 0(A) or 1(B)
228 {// Make sure that access could be done.
229 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
231 }while( --PollingCnt );
233 // Data FW read back.
234 ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
237 priv->bChangeRFInProgress = false;
239 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
248 // RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
251 // - Only use on RTL8192S USB interface.
253 // - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
255 // Created by Roger, 2008.09.06.
258 void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAddr,u32 Data)
261 struct r8192_priv *priv = ieee80211_priv(dev);
263 u8 RFWaitCounter = 0;
267 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
268 // We have to make sure that previous BB I/O has been done.
271 while(priv->bChangeRFInProgress)
276 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
279 if((RFWaitCounter > 100))
281 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
289 priv->bChangeRFInProgress = true;
292 RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
294 write_nic_dword(dev, RF_BB_CMD_DATA, Data);
295 write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
296 (RegAddr<<8)| //RF_Offset= 0x00~0x3F
297 (eRFPath<<16)); //RF_Path = 0(A) or 1(B)
300 {// Make sure that access could be done.
301 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
303 }while( --PollingCnt );
307 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
311 priv->bChangeRFInProgress = false;
316 // 1. BB register R/W API
319 * Function: PHY_QueryBBReg
321 * OverView: Read "sepcific bits" from BB register
325 * u32 RegAddr, //The target address to be readback
326 * u32 BitMask //The target bit position in the target address
329 * Return: u32 Data //The readback register value
330 * Note: This function is equal to "GetRegSetting" in PHY programming guide
332 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
335 u32 ReturnValue = 0, OriginalValue, BitShift;
338 RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
341 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
342 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
346 if(IS_BB_REG_OFFSET_92S(RegAddr))
349 if((RegAddr & 0x03) != 0)
351 printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
355 OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
359 OriginalValue = read_nic_dword(dev, RegAddr);
362 BitShift = phy_CalculateBitShift(BitMask);
363 ReturnValue = (OriginalValue & BitMask) >> BitShift;
366 RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
367 return (ReturnValue);
371 * Function: PHY_SetBBReg
373 * OverView: Write "Specific bits" to BB register (page 8~)
377 * u32 RegAddr, //The target address to be modified
378 * u32 BitMask //The target bit position in the target address
380 * u32 Data //The new register value in the target bit position
381 * //of the target address
385 * Note: This function is equal to "PutRegSetting" in PHY programming guide
387 void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
389 u32 OriginalValue, BitShift, NewValue;
392 RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
395 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
396 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
400 if(IS_BB_REG_OFFSET_92S(RegAddr))
402 if((RegAddr & 0x03) != 0)
404 printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
408 if(BitMask!= bMaskDWord)
409 {//if not "double word" write
410 OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
411 BitShift = phy_CalculateBitShift(BitMask);
412 NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
413 phy_SetUsbBBReg(dev, RegAddr, NewValue);
415 phy_SetUsbBBReg(dev, RegAddr, Data);
419 if(BitMask!= bMaskDWord)
420 {//if not "double word" write
421 OriginalValue = read_nic_dword(dev, RegAddr);
422 BitShift = phy_CalculateBitShift(BitMask);
423 NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
424 write_nic_dword(dev, RegAddr, NewValue);
426 write_nic_dword(dev, RegAddr, Data);
435 // 2. RF register R/W API
438 * Function: PHY_QueryRFReg
440 * OverView: Query "Specific bits" to RF register (page 8~)
444 * RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
445 * u32 RegAddr, //The target address to be read
446 * u32 BitMask //The target bit position in the target address
450 * Return: u32 Readback value
451 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
453 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
455 u32 Original_Value, Readback_Value, BitShift;//, flags;
456 struct r8192_priv *priv = ieee80211_priv(dev);
459 RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
461 if (!((priv->rf_pathmap >> eRFPath) & 0x1))
463 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
467 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
469 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
475 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
476 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
480 Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
482 BitShift = phy_CalculateBitShift(BitMask);
483 Readback_Value = (Original_Value & BitMask) >> BitShift;
486 return (Readback_Value);
490 * Function: PHY_SetRFReg
492 * OverView: Write "Specific bits" to RF register (page 8~)
496 * RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
497 * u32 RegAddr, //The target address to be modified
498 * u32 BitMask //The target bit position in the target address
500 * u32 Data //The new register Data in the target bit position
501 * //of the target address
505 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
507 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
510 struct r8192_priv *priv = ieee80211_priv(dev);
511 u32 Original_Value, BitShift, New_Value;//, flags;
513 RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
514 RegAddr, BitMask, Data, eRFPath);
516 if (!((priv->rf_pathmap >> eRFPath) & 0x1))
518 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
521 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
523 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
529 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
530 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
533 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
535 Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
536 BitShift = phy_CalculateBitShift(BitMask);
537 New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
538 phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
541 phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
543 RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
544 RegAddr, BitMask, Data, eRFPath);
549 * Function: phy_CalculateBitShift
551 * OverView: Get shifted position of the BitMask
557 * Return: u32 Return the shift bit bit position of the mask
560 static u32 phy_CalculateBitShift(u32 BitMask)
566 if ( ((BitMask>>i) & 0x1 ) == 1)
575 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
577 /*-----------------------------------------------------------------------------
578 * Function: PHY_MACConfig8192S
580 * Overview: Condig MAC by header file or parameter file.
590 * 08/12/2008 MHC Create Version 0.
592 *---------------------------------------------------------------------------*/
594 extern bool PHY_MACConfig8192S(struct net_device* dev)
596 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
601 rtStatus = phy_ConfigMACWithHeaderFile(dev);
602 return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
608 PHY_BBConfig8192S(struct net_device* dev)
610 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
612 u8 PathMap = 0, index = 0, rf_num = 0;
613 struct r8192_priv *priv = ieee80211_priv(dev);
614 phy_InitBBRFRegisterDefinition(dev);
617 rtStatus = phy_BB8192S_Config_ParaFile(dev);
619 PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
620 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
621 priv->rf_pathmap = PathMap;
622 for(index = 0; index<4; index++)
624 if((PathMap>>index)&0x1)
628 if((priv->rf_type==RF_1T1R && rf_num!=1) ||
629 (priv->rf_type==RF_1T2R && rf_num!=2) ||
630 (priv->rf_type==RF_2T2R && rf_num!=2) ||
631 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
632 (priv->rf_type==RF_2T4R && rf_num!=4))
634 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
636 return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
641 PHY_RFConfig8192S(struct net_device* dev)
643 struct r8192_priv *priv = ieee80211_priv(dev);
644 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
646 //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
648 //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
649 priv->rf_chip = RF_6052;
654 switch(priv->rf_chip)
658 rtStatus = PHY_RF6052_Config(dev);
662 //rtStatus = PHY_RF8256_Config(dev);
669 //rtStatus = PHY_RF8225_Config(dev);
675 return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
681 phy_BB8190_Config_HardCode(struct net_device* dev)
683 return RT_STATUS_SUCCESS;
687 /*-----------------------------------------------------------------------------
688 * Function: phy_SetBBtoDiffRFWithHeaderFile()
690 * Overview: This function
693 * Input: PADAPTER Adapter
694 * u1Byte ConfigType 0 => PHY_CONFIG
698 * Return: RT_STATUS_SUCCESS: configuration file exist
702 *---------------------------------------------------------------------------*/
704 phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
707 struct r8192_priv *priv = ieee80211_priv(dev);
708 u32* Rtl819XPHY_REGArraytoXTXR_Table;
709 u16 PHY_REGArraytoXTXRLen;
712 if(priv->rf_type == RF_1T1R)
714 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
715 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
717 else if(priv->rf_type == RF_1T2R)
719 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
720 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
724 return RT_STATUS_FAILURE;
727 if(ConfigType == BaseBand_Config_PHY_REG)
729 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
731 if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
733 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
735 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
737 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
739 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
741 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
743 rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
747 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
749 return RT_STATUS_SUCCESS;
755 phy_BB8192S_Config_ParaFile(struct net_device* dev)
757 struct r8192_priv *priv = ieee80211_priv(dev);
758 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
760 RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
763 // 1. Read PHY_REG.TXT BB INIT!!
764 // We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R
766 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
767 priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
769 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
770 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
771 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
772 //so we should reconfig BB reg with the right PHY parameters.
773 rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
776 rtStatus = RT_STATUS_FAILURE;
778 if(rtStatus != RT_STATUS_SUCCESS){
779 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
780 goto phy_BB8190_Config_ParaFile_Fail;
784 // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
786 if (priv->AutoloadFailFlag == false)
788 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
790 if(rtStatus != RT_STATUS_SUCCESS){
791 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
792 goto phy_BB8190_Config_ParaFile_Fail;
796 // 3. BB AGC table Initialization
798 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
800 if(rtStatus != RT_STATUS_SUCCESS){
801 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
802 goto phy_BB8190_Config_ParaFile_Fail;
806 // Check if the CCK HighPower is turned ON.
807 // This is used to calculate PWDB.
808 priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
811 phy_BB8190_Config_ParaFile_Fail:
815 /*-----------------------------------------------------------------------------
816 * Function: phy_ConfigMACWithHeaderFile()
818 * Overview: This function read BB parameters from Header file we gen, and do register
821 * Input: PADAPTER Adapter
826 * Return: RT_STATUS_SUCCESS: configuration file exist
828 * Note: The format of MACPHY_REG.txt is different from PHY and RF.
829 * [Register][Mask][Value]
830 *---------------------------------------------------------------------------*/
833 phy_ConfigMACWithHeaderFile(struct net_device* dev)
839 { //2008.11.06 Modified by tynli.
840 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
841 ArrayLength = MAC_2T_ArrayLength;
842 ptrArray = Rtl819XMAC_Array;
845 for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
846 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
848 return RT_STATUS_SUCCESS;
851 /*-----------------------------------------------------------------------------
852 * Function: phy_ConfigBBWithHeaderFile()
854 * Overview: This function read BB parameters from general file format, and do register
857 * Input: PADAPTER Adapter
858 * u8 ConfigType 0 => PHY_CONFIG
863 * Return: RT_STATUS_SUCCESS: configuration file exist
865 *---------------------------------------------------------------------------*/
868 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
871 u32* Rtl819XPHY_REGArray_Table;
872 u32* Rtl819XAGCTAB_Array_Table;
873 u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
875 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
876 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
877 PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
878 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
880 if(ConfigType == BaseBand_Config_PHY_REG)
882 for(i=0;i<PHY_REGArrayLen;i=i+2)
884 if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
886 else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
888 else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
890 else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
892 else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
894 else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
896 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
900 else if(ConfigType == BaseBand_Config_AGC_TAB){
901 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
903 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
906 return RT_STATUS_SUCCESS;
909 /*-----------------------------------------------------------------------------
910 * Function: phy_ConfigBBWithPgHeaderFile
912 * Overview: Config PHY_REG_PG array
922 * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!!
923 * 11/10/2008 tynli Modify to mew files.
925 *---------------------------------------------------------------------------*/
927 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
930 u32* Rtl819XPHY_REGArray_Table_PG;
931 u16 PHY_REGArrayPGLen;
933 PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
934 Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
936 if(ConfigType == BaseBand_Config_PHY_REG)
938 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
940 if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
942 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
944 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
946 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
948 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
950 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
952 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
955 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
957 return RT_STATUS_SUCCESS;
961 /*-----------------------------------------------------------------------------
962 * Function: PHY_ConfigRFWithHeaderFile()
964 * Overview: This function read RF parameters from general file format, and do RF 3-wire
966 * Input: PADAPTER Adapter
968 * RF90_RADIO_PATH_E eRFPath
972 * Return: RT_STATUS_SUCCESS: configuration file exist
974 * Note: Delay may be required for RF configuration
975 *---------------------------------------------------------------------------*/
976 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
979 struct r8192_priv *priv = ieee80211_priv(dev);
981 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
982 u32 *Rtl819XRadioA_Array_Table;
983 u32 *Rtl819XRadioB_Array_Table;
984 u16 RadioA_ArrayLen,RadioB_ArrayLen;
986 { //2008.11.06 Modified by tynli
987 RadioA_ArrayLen = RadioA_1T_ArrayLength;
988 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
989 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
990 RadioB_ArrayLen = RadioB_ArrayLength;
993 if( priv->rf_type == RF_2T2R_GREEN )
995 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
996 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1000 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1001 RadioB_ArrayLen = RadioB_ArrayLength;
1004 rtStatus = RT_STATUS_SUCCESS;
1009 for(i = 0;i<RadioA_ArrayLen; i=i+2){
1010 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1011 { // Deay specific ms. Only RF configuration require delay.
1014 else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1016 else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1018 else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1020 else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1022 else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1026 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1031 for(i = 0;i<RadioB_ArrayLen; i=i+2){
1032 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1033 { // Deay specific ms. Only RF configuration require delay.
1036 else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1038 else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1040 else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1042 else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1044 else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1048 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1064 /*-----------------------------------------------------------------------------
1065 * Function: PHY_CheckBBAndRFOK()
1067 * Overview: This function is write register and then readback to make sure whether
1068 * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
1070 * Input: PADAPTER Adapter
1071 * HW90_BLOCK_E CheckBlock
1072 * RF90_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF
1076 * Return: RT_STATUS_SUCCESS: PHY is OK
1078 * Note: This function may be removed in the ASIC
1079 *---------------------------------------------------------------------------*/
1080 //in 8256 phy_RF8256_Config_HardCode
1081 //but we don't use it temp
1084 struct net_device* dev,
1085 HW90_BLOCK_E CheckBlock,
1086 RF90_RADIO_PATH_E eRFPath
1089 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1090 u32 i, CheckTimes = 4,ulRegRead = 0;
1092 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1094 // Initialize register address offset to be checked
1095 WriteAddr[HW90_BLOCK_MAC] = 0x100;
1096 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1097 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1098 WriteAddr[HW90_BLOCK_RF] = 0x3;
1100 for(i=0 ; i < CheckTimes ; i++)
1104 // Write Data to register and readback
1108 case HW90_BLOCK_MAC:
1109 RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1112 case HW90_BLOCK_PHY0:
1113 case HW90_BLOCK_PHY1:
1114 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
1115 ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
1119 WriteData[i] &= 0xfff;
1120 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
1121 // TODO: we should not delay for such a long time. Ask SD3
1123 ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1128 rtStatus = RT_STATUS_FAILURE;
1134 // Check whether readback data is correct
1136 if(ulRegRead != WriteData[i])
1138 RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
1139 rtStatus = RT_STATUS_FAILURE;
1149 PHY_SetRFPowerState8192SUsb(
1150 struct net_device* dev,
1151 RF_POWER_STATE RFPowerState
1154 struct r8192_priv *priv = ieee80211_priv(dev);
1155 bool WaitShutDown = FALSE;
1158 BB_REGISTER_DEFINITION_T *pPhyReg;
1160 if(priv->SetRFPowerStateInProgress == TRUE)
1163 priv->SetRFPowerStateInProgress = TRUE;
1166 if(RFPowerState==RF_SHUT_DOWN)
1168 RFPowerState=RF_OFF;
1173 priv->RFPowerState = RFPowerState;
1174 switch( priv->rf_chip )
1178 switch( RFPowerState )
1192 switch( RFPowerState )
1201 for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
1203 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1206 pPhyReg = &priv->PHYRegDef[eRFPath];
1207 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
1208 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
1218 priv->SetRFPowerStateInProgress = FALSE;
1224 PHY_UpdateInitialGain(
1225 struct net_device* dev
1228 struct r8192_priv *priv = ieee80211_priv(dev);
1231 switch(priv->rf_chip)
1244 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
1250 void PHY_GetHWRegOriginalValue(struct net_device* dev)
1252 struct r8192_priv *priv = ieee80211_priv(dev);
1254 // read tx power offset
1256 priv->MCSTxPowerLevelOriginalOffset[0] =
1257 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
1258 priv->MCSTxPowerLevelOriginalOffset[1] =
1259 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
1260 priv->MCSTxPowerLevelOriginalOffset[2] =
1261 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
1262 priv->MCSTxPowerLevelOriginalOffset[3] =
1263 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
1264 priv->MCSTxPowerLevelOriginalOffset[4] =
1265 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
1266 priv->MCSTxPowerLevelOriginalOffset[5] =
1267 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
1270 priv->MCSTxPowerLevelOriginalOffset[6] =
1271 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
1272 RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
1273 priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
1274 priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
1275 priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
1277 // read rx initial gain
1278 priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
1279 priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
1280 priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
1281 priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
1282 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
1283 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1284 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1287 priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
1288 priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
1289 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
1290 rOFDM0_RxDetector3, priv->framesync);
1292 //YJ,modified,090107,end
1297 * Function: phy_InitBBRFRegisterDefinition
1299 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
1306 * Note: The initialization value is constant and it should never be changes
1309 static void phy_InitBBRFRegisterDefinition( struct net_device* dev)
1311 struct r8192_priv *priv = ieee80211_priv(dev);
1313 // RF Interface Sowrtware Control
1314 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1315 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1316 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1317 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1319 // RF Interface Readback Value
1320 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1321 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1322 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1323 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1325 // RF Interface Output (and Enable)
1326 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1327 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1328 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1329 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1331 // RF Interface (Output and) Enable
1332 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1333 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1334 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1335 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1337 //Addr of LSSI. Wirte RF register by driver
1338 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1339 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1340 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1341 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1344 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
1345 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1346 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1347 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1349 // Tx AGC Gain Stage (same for all path. Should we remove this?)
1350 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1351 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1352 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1353 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1355 // Tranceiver A~D HSSI Parameter-1
1356 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
1357 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
1358 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
1359 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
1361 // Tranceiver A~D HSSI Parameter-2
1362 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
1363 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
1364 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
1365 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
1367 // RF switch Control
1368 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1369 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1370 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1371 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1374 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1375 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1376 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1377 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1380 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1381 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1382 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1383 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1386 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1387 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1388 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1389 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1392 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1393 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1394 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1395 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1398 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1399 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1400 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1401 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1404 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1405 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1406 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1407 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1409 // Tranceiver LSSI Readback SI mode
1410 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1411 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1412 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1413 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1415 // Tranceiver LSSI Readback PI mode
1416 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
1417 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
1423 // Description: Change RF power state.
1425 // Assumption: This function must be executed in re-schdulable context,
1426 // ie. PASSIVE_LEVEL.
1429 bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
1431 struct r8192_priv *priv = ieee80211_priv(dev);
1432 bool bResult = FALSE;
1434 RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1436 if(eRFPowerState == priv->ieee80211->eRFPowerState)
1438 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
1442 bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
1444 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
1450 static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
1452 struct r8192_priv *priv = ieee80211_priv(dev);
1453 bool bResult = TRUE;
1456 if(priv->SetRFPowerStateInProgress == TRUE)
1459 priv->SetRFPowerStateInProgress = TRUE;
1461 switch(priv->rf_chip )
1464 switch( eRFPowerState )
1467 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
1468 write_nic_word(dev, CMDR, 0x37FC);
1469 write_nic_byte(dev, PHY_CCA, 0x3);
1470 write_nic_byte(dev, TXPAUSE, 0x00);
1471 write_nic_byte(dev, SPS1_CTRL, 0x64);
1475 // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
1476 // By Bruce, 2008-01-16.
1480 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
1483 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
1484 // (0) Disable FW BB reset checking
1485 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
1487 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
1488 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
1490 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
1492 write_nic_byte(dev, SPS1_CTRL, 0x0);
1493 write_nic_byte(dev, TXPAUSE, 0xFF);
1495 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
1496 write_nic_word(dev, CMDR, 0x77FC);
1497 write_nic_byte(dev, PHY_CCA, 0x0);
1500 write_nic_word(dev, CMDR, 0x37FC);
1503 write_nic_word(dev, CMDR, 0x77FC);
1506 // (3) Reset BB TRX blocks
1507 write_nic_word(dev, CMDR, 0x57FC);
1517 priv->ieee80211->eRFPowerState = eRFPowerState;
1521 // Update current RF state variable.
1522 priv->ieee80211->eRFPowerState = eRFPowerState;
1524 switch(priv->rf_chip )
1527 switch(priv->ieee80211->eRFPowerState)
1531 //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1533 if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
1535 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
1539 // Turn off LED if RF is not ON.
1540 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
1545 // Turn on RF we are still linked, which might happen when
1546 // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1547 if( pMgntInfo->bMediaConnect == TRUE )
1549 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
1553 // Turn off LED if RF is not ON.
1554 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
1566 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
1571 priv->SetRFPowerStateInProgress = FALSE;
1576 /*-----------------------------------------------------------------------------
1577 * Function: GetTxPowerLevel8190()
1579 * Overview: This function is export to "common" moudule
1581 * Input: PADAPTER Adapter
1582 * psByte Power Level
1588 *---------------------------------------------------------------------------*/
1591 PHY_GetTxPowerLevel8192S(
1592 struct net_device* dev,
1596 struct r8192_priv *priv = ieee80211_priv(dev);
1600 // Because the Tx power indexes are different, we report the maximum of them to
1601 // meet the CCX TPC request. By Bruce, 2008-01-31.
1605 TxPwrLevel = priv->CurrentCckTxPwrIdx;
1606 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
1609 TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
1611 // Compare with Legacy OFDM Tx power.
1612 if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
1613 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
1616 TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
1618 // Compare with HT OFDM Tx power.
1619 if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
1620 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
1622 *powerlevel = TxPwrDbm;
1625 /*-----------------------------------------------------------------------------
1626 * Function: SetTxPowerLevel8190()
1628 * Overview: This function is export to "HalCommon" moudule
1630 * Input: PADAPTER Adapter
1636 * 2008/11/04 MHC We remove EEPROM_93C56.
1637 * We need to move CCX relative code to independet file.
1638 * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
1639 *---------------------------------------------------------------------------*/
1640 void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8 channel)
1642 struct r8192_priv *priv = ieee80211_priv(dev);
1643 u8 powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
1644 s8 ant_pwr_diff = 0;
1646 u8 index = (channel -1);
1647 // 2009/01/22 MH Add for new EEPROM format from SD3
1648 u8 pwrdiff[2] = {0};
1649 u8 ht20pwr[2] = {0}, ht40pwr[2] = {0};
1650 u8 rfpath = 0, rfpathnum = 2;
1652 if(priv->bTXPowerDataReadFromEEPORM == FALSE)
1656 * Read predefined TX power index in EEPROM
1660 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
1661 // Power must be calculated by the antenna diff.
1662 // So we have to rewrite Antenna gain offset register here.
1663 // Please refer to BB register 0x80c
1665 // 2. For OFDM 1T or 2T
1669 powerlevel = priv->RfTxPwrLevelCck[0][index];
1671 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
1673 // Read HT 40 OFDM TX power
1674 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
1675 // RF B HT OFDM pwr-RFA HT OFDM pwr
1676 // Only one RF we need not to decide B <-> A pwr diff
1678 // Legacy<->HT pwr diff, we only care about path A.
1680 // We only assume 1T as RF path A
1682 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
1684 else if (priv->rf_type == RF_2T2R)
1686 // Read HT 40 OFDM TX power
1687 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
1688 // RF B HT OFDM pwr-RFA HT OFDM pwr
1689 ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] -
1690 priv->RfTxPwrLevelOfdm2T[0][index];
1692 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
1693 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
1697 // 2009/01/21 MH Support new EEPROM format from SD3 requirement
1698 // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
1700 if (priv->EEPROMVersion == 2) // Defined by SD1 Jong
1702 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1704 for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1706 // HT 20<->40 pwr diff
1707 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
1709 // Calculate Antenna pwr diff
1710 if (pwrdiff[rfpath] < 8) // 0~+7
1712 ht20pwr[rfpath] += pwrdiff[rfpath];
1714 else // index8-15=-8~-1
1716 ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
1720 // RF B HT OFDM pwr-RFA HT OFDM pwr
1721 if (priv->rf_type == RF_2T2R)
1722 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
1725 // Band Edge scheme is enabled for FCC mode
1726 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
1728 for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1730 pwrdiff[rfpath] = 0;
1731 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
1734 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
1735 else if (channel >= 9)
1736 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
1738 pwrdiff[rfpath] = 0;
1740 ht40pwr[rfpath] -= pwrdiff[rfpath];
1742 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1745 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
1746 else if (channel >= 11)
1747 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
1749 pwrdiff[rfpath] = 0;
1751 ht20pwr[rfpath] -= pwrdiff[rfpath];
1755 if (priv->rf_type == RF_2T2R)
1757 // HT 20/40 must decide if they need to minus BD pwr offset
1758 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
1759 ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
1761 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
1763 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1765 if (channel <= 1 || channel >= 11)
1771 if (channel <= 3 || channel >= 9)
1778 //Cosa added for protection, the reg rFPGA0_TxGainStage
1779 // range is from 7~-8, index = 0x0~0xf
1780 if(ant_pwr_diff > 7)
1782 if(ant_pwr_diff < -8)
1785 ant_pwr_diff &= 0xf;
1787 // Antenna TX power difference
1788 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
1789 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
1790 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); // RF-B
1792 // Antenna gain offset from B/C/D to A
1793 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
1794 priv->AntennaTxPwDiff[1]<<4 |
1795 priv->AntennaTxPwDiff[0] );
1797 // Notify Tx power difference for B/C/D to A!!!
1798 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1802 // CCX 2 S31, AP control of client transmit power:
1803 // 1. We shall not exceed Cell Power Limit as possible as we can.
1804 // 2. Tolerance is +/- 5dB.
1805 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
1808 // 1. 802.11h power contraint
1811 #ifdef TODO //WB, 11h has not implemented now.
1812 if( priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
1813 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
1815 u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
1816 u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
1817 u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
1819 RT_TRACE(COMP_TXAGC,
1820 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1821 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
1822 RT_TRACE(COMP_TXAGC,
1823 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1824 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1827 if(powerlevel > CckCellPwrIdx)
1828 powerlevel = CckCellPwrIdx;
1829 // Legacy OFDM, HT OFDM
1830 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
1832 if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
1834 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
1838 powerlevelOFDM24G = 0;
1842 RT_TRACE(COMP_TXAGC,
1843 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1844 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1848 priv->CurrentCckTxPwrIdx = powerlevel;
1849 priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
1851 switch(priv->rf_chip)
1860 PHY_RF6052SetCckTxPower(dev, powerlevel);
1861 PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
1874 // Update transmit power level of all channel supported.
1878 bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
1880 struct r8192_priv *priv = ieee80211_priv(dev);
1884 // TODO: A mode Tx power.
1885 u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
1886 u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
1888 if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
1889 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
1893 for(idx = 0; idx < 14; idx++)
1895 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
1896 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
1897 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
1898 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
1899 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
1900 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
1902 for (rf_path = 0; rf_path < 2; rf_path++)
1904 priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
1905 priv->RfTxPwrLevelOfdm1T[rf_path][idx] = \
1906 priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
1910 PHY_SetTxPowerLevel8192S(dev, priv->chan);
1917 When beacon interval is changed, the values of the
1918 hw registers should be modified.
1921 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
1925 NewBeaconNum = BeaconInterval *32 - 64;
1926 write_nic_dword(dev, WFM3+4, NewBeaconNum);
1927 write_nic_dword(dev, WFM3, 0xB026007C);
1932 // Map dBm into Tx power index according to
1933 // current HW model, for example, RF and PA, and
1934 // current wireless mode.
1936 static u8 phy_DbmToTxPwrIdx(
1937 struct net_device* dev,
1938 WIRELESS_MODE WirelessMode,
1947 // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
1948 // 3dbm, and OFDM HT equals to 0dbm repectively.
1950 // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
1952 switch(WirelessMode)
1954 case WIRELESS_MODE_B:
1958 case WIRELESS_MODE_G:
1959 case WIRELESS_MODE_N_24G:
1966 if((PowerInDbm - Offset) > 0)
1968 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
1975 // Tx Power Index is too large.
1976 if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
1977 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
1983 // Map Tx power index into dBm according to
1984 // current HW model, for example, RF and PA, and
1985 // current wireless mode.
1987 static long phy_TxPwrIdxToDbm(
1988 struct net_device* dev,
1989 WIRELESS_MODE WirelessMode,
1993 //struct r8192_priv *priv = ieee80211_priv(dev);
1998 // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
1999 // 3dbm, and OFDM HT equals to 0dbm repectively.
2001 // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2003 switch(WirelessMode)
2005 case WIRELESS_MODE_B:
2009 case WIRELESS_MODE_G:
2010 case WIRELESS_MODE_N_24G:
2017 PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
2024 PHY_ScanOperationBackup8192S(
2025 IN PADAPTER Adapter,
2030 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2031 PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
2033 u1Byte initial_gain;
2039 if(!Adapter->bDriverStopped)
2043 case SCAN_OPT_BACKUP:
2045 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
2046 // and resume both two DMs while scan complete.
2049 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
2052 case SCAN_OPT_RESTORE:
2054 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
2055 // recover earlier DIG settings.
2058 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
2062 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
2070 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation )
2075 /*-----------------------------------------------------------------------------
2076 * Function: SetBWModeCallback8190Pci()
2078 * Overview: Timer callback function for SetSetBWMode
2080 * Input: PRT_TIMER pTimer
2086 * Note: (1) We do not take j mode into consideration now
2087 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
2089 *---------------------------------------------------------------------------*/
2090 // use in phy only (in win it's timer)
2091 void PHY_SetBWModeCallback8192S(struct net_device *dev)
2093 struct r8192_priv *priv = ieee80211_priv(dev);
2098 RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \
2099 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
2101 if(priv->rf_chip == RF_PSEUDO_11N)
2103 priv->SetBWModeInProgress= FALSE;
2112 //3//<1>Set MAC register
2114 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
2115 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
2117 switch(priv->CurrentChannelBW)
2119 case HT_CHANNEL_WIDTH_20:
2121 regBwOpMode |= BW_OPMODE_20MHZ;
2122 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2123 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2126 case HT_CHANNEL_WIDTH_20_40:
2128 regBwOpMode &= ~BW_OPMODE_20MHZ;
2129 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2130 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2131 regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
2132 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
2136 RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n",
2137 priv->CurrentChannelBW);
2142 //3//<2>Set PHY related register
2144 switch(priv->CurrentChannelBW)
2147 case HT_CHANNEL_WIDTH_20:
2148 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
2149 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
2151 if (priv->card_8192_version >= VERSION_8192S_BCUT)
2152 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2158 case HT_CHANNEL_WIDTH_20_40:
2159 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
2160 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
2163 // Set Control channel to upper or lower. These settings are required only for 40MHz
2164 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2165 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2167 if (priv->card_8192_version >= VERSION_8192S_BCUT)
2168 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2173 RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
2174 ,priv->CurrentChannelBW);
2178 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2181 //3<3>Set RF related register
2182 switch( priv->rf_chip )
2185 //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
2189 // Please implement this function in Hal8190PciPhy8256.c
2190 //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
2194 // Please implement this function in Hal8190PciPhy8258.c
2195 // PHY_SetRF8258Bandwidth();
2203 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
2206 printk("Unknown rf_chip: %d\n", priv->rf_chip);
2210 priv->SetBWModeInProgress= FALSE;
2212 RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
2216 /*-----------------------------------------------------------------------------
2217 * Function: SetBWMode8190Pci()
2219 * Overview: This function is export to "HalCommon" moudule
2221 * Input: PADAPTER Adapter
2222 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
2228 * Note: We do not take j mode into consideration now
2229 *---------------------------------------------------------------------------*/
2230 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2232 struct r8192_priv *priv = ieee80211_priv(dev);
2233 HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
2235 if(priv->SetBWModeInProgress)
2238 priv->SetBWModeInProgress= TRUE;
2240 priv->CurrentChannelBW = Bandwidth;
2242 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2243 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2244 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2245 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2247 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2251 SetBWModeCallback8192SUsbWorkItem(dev);
2255 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
2256 priv->SetBWModeInProgress= FALSE;
2257 priv->CurrentChannelBW = tmpBW;
2261 // use in phy only (in win it's timer)
2262 void PHY_SwChnlCallback8192S(struct net_device *dev)
2265 struct r8192_priv *priv = ieee80211_priv(dev);
2268 RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
2273 if(priv->rf_chip == RF_PSEUDO_11N)
2275 priv->SwChnlInProgress=FALSE;
2276 return; //return immediately if it is peudo-phy
2280 if(!priv->SwChnlInProgress)
2283 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
2294 priv->SwChnlInProgress=FALSE;
2300 // Call after initialization
2301 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2303 struct r8192_priv *priv = ieee80211_priv(dev);
2308 if(priv->SwChnlInProgress)
2311 if(priv->SetBWModeInProgress)
2314 switch(priv->ieee80211->mode)
2316 case WIRELESS_MODE_A:
2317 case WIRELESS_MODE_N_5G:
2319 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2324 case WIRELESS_MODE_B:
2326 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2331 case WIRELESS_MODE_G:
2332 case WIRELESS_MODE_N_24G:
2334 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2344 priv->SwChnlInProgress = TRUE;
2350 priv->SwChnlStage=0;
2355 SwChnlCallback8192SUsbWorkItem(dev);
2359 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
2363 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
2364 priv->SwChnlInProgress = false;
2365 priv->CurrentChannel = tmpchannel;
2371 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
2372 priv->SwChnlInProgress = false;
2380 // Switch channel synchronously. Called by SwChnlByDelayHandler.
2382 // Implemented by Bruce, 2008-02-14.
2383 // The following procedure is operted according to SwChanlCallback8190Pci().
2384 // However, this procedure is performed synchronously which should be running under
2387 void PHY_SwChnlPhy8192S( // Only called during initialize
2388 struct net_device* dev,
2392 struct r8192_priv *priv = ieee80211_priv(dev);
2394 RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
2398 if(RT_CANNOT_IO(dev))
2402 // Channel Switching is in progress.
2403 if(priv->SwChnlInProgress)
2406 //return immediately if it is peudo-phy
2407 if(priv->rf_chip == RF_PSEUDO_11N)
2409 priv->SwChnlInProgress=FALSE;
2413 priv->SwChnlInProgress = TRUE;
2419 priv->SwChnlStage = 0;
2420 priv->SwChnlStep = 0;
2422 phy_FinishSwChnlNow(dev,channel);
2424 priv->SwChnlInProgress = FALSE;
2429 phy_SetSwChnlCmdArray(
2430 SwChnlCmd* CmdTable,
2441 if(CmdTable == NULL)
2445 if(CmdTableIdx >= CmdTableSz)
2450 pCmd = CmdTable + CmdTableIdx;
2451 pCmd->CmdID = CmdID;
2452 pCmd->Para1 = Para1;
2453 pCmd->Para2 = Para2;
2454 pCmd->msDelay = msDelay;
2461 phy_SwChnlStepByStep(
2462 struct net_device* dev,
2469 struct r8192_priv *priv = ieee80211_priv(dev);
2470 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
2471 u32 PreCommonCmdCnt;
2472 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
2473 u32 PostCommonCmdCnt;
2474 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
2476 SwChnlCmd *CurrentCmd = NULL;
2479 RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2480 if (!IsLegalChannel(priv->ieee80211, channel))
2482 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2483 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2486 // <1> Fill up pre common command.
2487 PreCommonCmdCnt = 0;
2488 phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2489 CmdID_SetTxPowerLevel, 0, 0, 0);
2490 phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2491 CmdID_End, 0, 0, 0);
2493 // <2> Fill up post common command.
2494 PostCommonCmdCnt = 0;
2496 phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2497 CmdID_End, 0, 0, 0);
2499 // <3> Fill up RF dependent command.
2501 switch( priv->rf_chip )
2504 if (channel < 1 || channel > 14)
2505 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2507 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2508 CmdID_RF_WriteReg, rRfChannel, channel, 10);
2509 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2510 CmdID_End, 0, 0, 0);
2514 if (channel < 1 || channel > 14)
2515 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2516 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2517 CmdID_RF_WriteReg, rRfChannel, channel, 10);
2518 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2519 CmdID_End, 0, 0, 0);
2523 if (channel < 1 || channel > 14)
2524 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2525 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2526 CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
2527 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2528 CmdID_End, 0, 0, 0);
2544 CurrentCmd=&PreCommonCmd[*step];
2547 CurrentCmd=&RfDependCmd[*step];
2550 CurrentCmd=&PostCommonCmd[*step];
2554 if(CurrentCmd->CmdID==CmdID_End)
2568 switch(CurrentCmd->CmdID)
2570 case CmdID_SetTxPowerLevel:
2571 PHY_SetTxPowerLevel8192S(dev,channel);
2573 case CmdID_WritePortUlong:
2574 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2576 case CmdID_WritePortUshort:
2577 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2579 case CmdID_WritePortUchar:
2580 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2582 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
2583 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2585 // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
2586 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
2596 (*delay)=CurrentCmd->msDelay;
2598 RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2602 //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
2605 phy_FinishSwChnlNow( // We should not call this function directly
2606 struct net_device* dev,
2610 struct r8192_priv *priv = ieee80211_priv(dev);
2613 while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2623 /*-----------------------------------------------------------------------------
2624 * Function: PHYCheckIsLegalRfPath8190Pci()
2626 * Overview: Check different RF type to execute legal judgement. If RF Path is illegal
2627 * We will return false.
2637 * 11/15/2007 MHC Create Version 0.
2639 *---------------------------------------------------------------------------*/
2640 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
2642 bool rtValue = TRUE;
2644 // NOt check RF Path now.!
2647 } /* PHY_CheckIsLegalRfPath8192S */
2651 /*-----------------------------------------------------------------------------
2652 * Function: PHY_IQCalibrate8192S()
2654 * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration
2655 * to improve RF EVM!!?
2657 * Input: IN PADAPTER pAdapter
2665 * 10/07/2008 MHC Create. Document from SD3 RFSI Jenyu.
2667 *---------------------------------------------------------------------------*/
2668 //called by InitializeAdapter8192SE
2670 PHY_IQCalibrate( struct net_device* dev)
2677 // 1. Check QFN68 or 64 92S (Read from EEPROM)
2682 // For 1T2R IQK only now !!!
2683 for (i = 0; i < 10; i++)
2686 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
2688 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
2690 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
2692 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
2694 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
2696 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
2698 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
2700 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
2702 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
2704 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
2706 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
2708 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
2710 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
2712 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
2715 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
2717 // Readback IQK value and rewrite
2718 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
2720 old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
2722 // Calibrate init gain for A path for TX0
2723 X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
2724 TXA[RF90_PATH_A] = (X * old_value)/0x100;
2725 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
2726 reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
2727 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
2730 // Calibrate init gain for C path for TX0
2731 Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
2732 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
2733 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
2734 reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
2735 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
2736 reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
2737 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
2738 rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
2741 // Calibrate RX A and B for RX0
2742 reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
2743 X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
2744 reg = (reg & 0xFFFFFC00) |X;
2745 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
2746 Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
2747 reg = (reg & 0xFFFF03FF) |Y<<10;
2748 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
2750 old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
2752 // Calibrate init gain for A path for TX1 !!!!!!
2753 X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
2754 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
2755 TXA[RF90_PATH_A] = (X * old_value) / 0x100;
2756 reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
2757 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
2760 // Calibrate init gain for C path for TX1
2761 Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
2762 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
2763 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
2764 reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
2765 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
2766 reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
2767 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
2768 rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
2771 // Calibrate RX A and B for RX1
2772 reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
2773 X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
2774 reg = (reg & 0xFFFFFC00) |X;
2775 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
2777 Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
2778 reg = (reg & 0xFFFF03FF) |Y<<10;
2779 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
2782 RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
2790 // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
2796 /*-----------------------------------------------------------------------------
2797 * Function: PHY_IQCalibrateBcut()
2799 * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration
2800 * to improve RF EVM!!?
2802 * Input: IN PADAPTER pAdapter
2810 * 11/18/2008 MHC Create. Document from SD3 RFSI Jenyu.
2811 * 92S B-cut QFN 68 pin IQ calibration procedure.doc
2813 *---------------------------------------------------------------------------*/
2814 extern void PHY_IQCalibrateBcut(struct net_device* dev)
2820 u32 calibrate_set[13] = {0};
2824 // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
2827 // 1. Save e70~ee0 register setting, and load calibration setting
2829 calibrate_set [0] = 0xee0;
2830 calibrate_set [1] = 0xedc;
2831 calibrate_set [2] = 0xe70;
2832 calibrate_set [3] = 0xe74;
2833 calibrate_set [4] = 0xe78;
2834 calibrate_set [5] = 0xe7c;
2835 calibrate_set [6] = 0xe80;
2836 calibrate_set [7] = 0xe84;
2837 calibrate_set [8] = 0xe88;
2838 calibrate_set [9] = 0xe8c;
2839 calibrate_set [10] = 0xed0;
2840 calibrate_set [11] = 0xed4;
2841 calibrate_set [12] = 0xed8;
2842 for (i = 0; i < 13; i++)
2844 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
2845 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
2849 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
2854 // For 1T2R IQK only now !!!
2855 for (i = 0; i < 10; i++)
2857 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
2858 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
2859 if (!RfPiEnable) //if original is SI mode, then switch to PI mode.
2861 rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
2862 rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
2866 // 2. IQ calibration & LO leakage calibration
2867 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
2869 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
2871 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
2873 //path-A IQ K and LO K gain setting
2874 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
2876 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
2878 //set LO calibration
2879 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
2881 //path-B IQ K and LO K gain setting
2882 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
2884 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
2887 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
2889 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
2896 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
2899 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
2901 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
2906 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
2908 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
2910 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
2912 if (!RfPiEnable) //if original is SI mode, then switch to PI mode.
2914 rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
2915 rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
2919 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
2921 // 3. check fail bit, and fill BB IQ matrix
2922 // Readback IQK value and rewrite
2923 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
2925 old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
2927 // Calibrate init gain for A path for TX0
2928 X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
2929 TXA[RF90_PATH_A] = (X * old_value)/0x100;
2930 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
2931 reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
2932 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
2935 // Calibrate init gain for C path for TX0
2936 Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
2937 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
2938 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
2939 reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
2940 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
2941 reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
2942 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
2943 rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
2946 // Calibrate RX A and B for RX0
2947 reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
2948 X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
2949 reg = (reg & 0xFFFFFC00) |X;
2950 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
2951 Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
2952 reg = (reg & 0xFFFF03FF) |Y<<10;
2953 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
2955 old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
2957 // Calibrate init gain for A path for TX1 !!!!!!
2958 X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
2959 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
2960 TXA[RF90_PATH_A] = (X * old_value) / 0x100;
2961 reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
2962 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
2965 // Calibrate init gain for C path for TX1
2966 Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
2967 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
2968 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
2969 reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
2970 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
2971 reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
2972 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
2973 rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
2976 // Calibrate RX A and B for RX1
2977 reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
2978 X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
2979 reg = (reg & 0xFFFFFC00) |X;
2980 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
2982 Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
2983 reg = (reg & 0xFFFF03FF) |Y<<10;
2984 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
2987 RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
2994 // 4. Reload e70~ee0 register setting.
2996 for (i = 0; i < 13; i++)
2997 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
3001 // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3010 // Move from phycfg.c to gen.c to be code independent later
3013 // use in phy only (in win it's timer)
3014 void SwChnlCallback8192SUsb(struct net_device *dev)
3017 struct r8192_priv *priv = ieee80211_priv(dev);
3020 RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel %d\n",
3027 if(priv->rf_chip == RF_PSEUDO_11N)
3029 priv->SwChnlInProgress=FALSE;
3030 return; //return immediately if it is peudo-phy
3034 if(!priv->SwChnlInProgress)
3037 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3048 priv->SwChnlInProgress=FALSE;
3056 // Callback routine of the work item for switch channel.
3058 // use in phy only (in win it's work)
3059 void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
3061 struct r8192_priv *priv = ieee80211_priv(dev);
3063 RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
3065 if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
3067 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
3069 pHalData->SwChnlInProgress = FALSE;
3073 phy_FinishSwChnlNow(dev, priv->chan);
3074 priv->SwChnlInProgress = FALSE;
3076 RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
3080 /*-----------------------------------------------------------------------------
3081 * Function: SetBWModeCallback8192SUsb()
3083 * Overview: Timer callback function for SetSetBWMode
3085 * Input: PRT_TIMER pTimer
3091 * Note: (1) We do not take j mode into consideration now
3092 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3094 *---------------------------------------------------------------------------*/
3096 void SetBWModeCallback8192SUsb(struct net_device *dev)
3098 struct r8192_priv *priv = ieee80211_priv(dev);
3103 RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \
3104 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3106 if(priv->rf_chip == RF_PSEUDO_11N)
3108 priv->SetBWModeInProgress= FALSE;
3116 //3<1>Set MAC register
3117 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3118 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3120 switch(priv->CurrentChannelBW)
3122 case HT_CHANNEL_WIDTH_20:
3123 regBwOpMode |= BW_OPMODE_20MHZ;
3124 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3127 case HT_CHANNEL_WIDTH_20_40:
3128 regBwOpMode &= ~BW_OPMODE_20MHZ;
3129 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3131 regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3132 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3136 RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n",
3137 priv->CurrentChannelBW);
3141 //3 <2>Set PHY related register
3142 switch(priv->CurrentChannelBW)
3144 case HT_CHANNEL_WIDTH_20:
3145 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3146 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3148 if (priv->card_8192_version >= VERSION_8192S_BCUT)
3149 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3152 case HT_CHANNEL_WIDTH_20_40:
3153 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3154 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3155 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3156 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3158 if (priv->card_8192_version >= VERSION_8192S_BCUT)
3159 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3163 RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
3164 ,priv->CurrentChannelBW);
3168 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3171 //3<3>Set RF related register
3172 switch( priv->rf_chip )
3175 PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3179 // Please implement this function in Hal8190PciPhy8256.c
3180 //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3184 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3188 // Please implement this function in Hal8190PciPhy8258.c
3189 // PHY_SetRF8258Bandwidth();
3200 priv->SetBWModeInProgress= FALSE;
3202 RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
3206 * Callback routine of the work item for set bandwidth mode.
3208 * use in phy only (in win it's work)
3210 void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
3212 struct r8192_priv *priv = ieee80211_priv(dev);
3216 RT_TRACE(COMP_SCAN, "%s(): Switch to %s bandwidth", __func__,
3217 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? "20MHz" : "40MHz");
3219 if (priv->rf_chip == RF_PSEUDO_11N) {
3220 priv->SetBWModeInProgress= FALSE;
3225 /* Set MAC register */
3226 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3227 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3228 switch (priv->CurrentChannelBW) {
3229 case HT_CHANNEL_WIDTH_20:
3230 regBwOpMode |= BW_OPMODE_20MHZ;
3231 /* we have not verified whether this register works */
3232 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3234 case HT_CHANNEL_WIDTH_20_40:
3235 regBwOpMode &= ~BW_OPMODE_20MHZ;
3236 /* we have not verified whether this register works */
3237 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3238 regRRSR_RSC = (regRRSR_RSC&0x90) | (priv->nCur40MhzPrimeSC<<5);
3239 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3242 RT_TRACE(COMP_DBG, "%s(): unknown Bandwidth: %#X", __func__,
3243 priv->CurrentChannelBW);
3246 /* Set PHY related register */
3247 switch (priv->CurrentChannelBW) {
3248 case HT_CHANNEL_WIDTH_20:
3249 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3250 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3251 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3253 case HT_CHANNEL_WIDTH_20_40:
3254 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3255 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3257 * Set Control channel to upper or lower.
3258 * These settings are required only for 40MHz
3260 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
3261 (priv->nCur40MhzPrimeSC>>1));
3262 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
3263 priv->nCur40MhzPrimeSC);
3264 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3267 RT_TRACE(COMP_DBG, "%s(): unknown Bandwidth: %#X", __func__,
3268 priv->CurrentChannelBW);
3273 * Skip over setting of J-mode in BB register here.
3274 * Default value is "None J mode".
3277 /* Set RF related register */
3278 switch (priv->rf_chip) {
3280 PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3283 /* Please implement this function in Hal8190PciPhy8256.c */
3284 /* PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); */
3287 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3290 /* Please implement this function in Hal8190PciPhy8258.c */
3291 /* PHY_SetRF8258Bandwidth(); */
3297 RT_TRACE(COMP_DBG, "%s(): unknown rf_chip: %d", __func__,
3301 priv->SetBWModeInProgress= FALSE;
3304 void InitialGain8192S(struct net_device *dev, u8 Operation)
3307 struct r8192_priv *priv = ieee80211_priv(dev);
3312 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
3314 struct r8192_priv *priv = ieee80211_priv(dev);
3316 priv->InitialGainOperateType = Operation;
3320 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
3324 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
3326 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3327 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
3328 struct net_device *dev = priv->ieee80211->dev;
3329 #define SCAN_RX_INITIAL_GAIN 0x17
3330 #define POWER_DETECTION_TH 0x08
3335 Operation = priv->InitialGainOperateType;
3340 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3341 initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
3342 BitMask = bMaskByte0;
3343 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3344 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3345 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3346 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3347 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3348 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3349 BitMask = bMaskByte2;
3350 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3352 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3353 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3354 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3355 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3356 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3358 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3359 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3360 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3361 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3362 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3363 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3364 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
3367 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3368 BitMask = 0x7f; //Bit0~ Bit6
3369 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3370 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3372 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3373 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3374 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3375 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3376 BitMask = bMaskByte2;
3377 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3379 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3380 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3381 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3382 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3383 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3385 PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
3387 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3388 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
3391 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
3397 //-----------------------------------------------------------------------------
3399 // Schedule workitem to send specific CMD IO to FW.
3400 // Added by Roger, 2008.12.03.
3402 //-----------------------------------------------------------------------------
3403 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO)
3405 struct r8192_priv *priv = ieee80211_priv(dev);
3406 u16 FwCmdWaitCounter = 0;
3408 u16 FwCmdWaitLimit = 1000;
3410 if(priv->bInHctTest)
3413 RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
3415 // Will be done by high power respectively.
3416 if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
3418 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
3423 while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
3426 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
3428 FwCmdWaitCounter ++;
3429 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
3433 if(FwCmdWaitCounter == FwCmdWaitLimit)
3435 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
3438 if (priv->SetFwCmdInProgress)
3440 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
3443 priv->SetFwCmdInProgress = TRUE;
3444 priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
3446 phy_SetFwCmdIOCallback(dev);
3449 void ChkFwCmdIoDone(struct net_device* dev)
3451 u16 PollingCnt = 1000;
3455 {// Make sure that CMD IO has be accepted by FW.
3457 if(RT_USB_CANNOT_IO(Adapter))
3459 RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
3463 udelay(10); // sleep 20us
3464 tmpValue = read_nic_dword(dev, WFM5);
3467 RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
3472 RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
3474 }while( --PollingCnt );
3478 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
3481 // Callback routine of the timer callback for FW Cmd IO.
3484 // This routine will send specific CMD IO to FW and check whether it is done.
3486 void phy_SetFwCmdIOCallback(struct net_device* dev)
3488 struct r8192_priv *priv = ieee80211_priv(dev);
3489 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
3490 rt_firmware *pFirmware = priv->pFirmware;
3491 u32 input, CurrentAID = 0;;
3494 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
3498 RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
3500 if(pFirmware->FirmwareVersion >= 0x34)
3502 switch(priv->CurrentFwCmdIO)
3504 case FW_CMD_RA_REFRESH_N:
3505 priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_N_COMB;
3507 case FW_CMD_RA_REFRESH_BG:
3508 priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_BG_COMB;
3514 switch(priv->CurrentFwCmdIO)
3517 case FW_CMD_RA_RESET:
3518 write_nic_dword(dev, WFM5, FW_RA_RESET);
3521 case FW_CMD_RA_ACTIVE:
3522 write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
3525 case FW_CMD_RA_REFRESH_N:
3526 RT_TRACE(COMP_CMD, "[FW CMD] Set RA n refresh!!\n");
3527 if(pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
3528 input = FW_RA_REFRESH;
3530 input = FW_RA_REFRESH | (pHTInfo->IOTRaFunc << 8);
3531 write_nic_dword(dev, WFM5, input);
3532 ChkFwCmdIoDone(dev);
3533 write_nic_dword(dev, WFM5, FW_RA_ENABLE_RSSI_MASK);
3534 ChkFwCmdIoDone(dev);
3536 case FW_CMD_RA_REFRESH_BG:
3537 RT_TRACE(COMP_CMD, "[FW CMD] Set RA BG refresh!!\n");
3538 write_nic_dword(dev, WFM5, FW_RA_REFRESH);
3539 ChkFwCmdIoDone(dev);
3540 write_nic_dword(dev, WFM5, FW_RA_DISABLE_RSSI_MASK);
3541 ChkFwCmdIoDone(dev);
3544 case FW_CMD_RA_REFRESH_N_COMB:
3545 RT_TRACE(COMP_CMD, "[FW CMD] Set RA n Combo refresh!!\n");
3546 if(pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
3547 input = FW_RA_IOT_N_COMB;
3549 input = FW_RA_IOT_N_COMB | (((pHTInfo->IOTRaFunc)&0x0f) << 8);
3550 input = input |((pHTInfo->IOTPeer & 0xf) <<12);
3551 RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in n mode!! input(%#x)\n", input);
3552 write_nic_dword(dev, WFM5, input);
3553 ChkFwCmdIoDone(dev);
3556 case FW_CMD_RA_REFRESH_BG_COMB:
3557 RT_TRACE(COMP_CMD, "[FW CMD] Set RA B/G Combo refresh!!\n");
3558 if(pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
3559 input = FW_RA_IOT_BG_COMB;
3561 input = FW_RA_IOT_BG_COMB | (((pHTInfo->IOTRaFunc)&0x0f) << 8);
3562 input = input |((pHTInfo->IOTPeer & 0xf) <<12);
3563 RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in B/G mode!! input(%#x)\n", input);
3564 write_nic_dword(dev, WFM5, input);
3565 ChkFwCmdIoDone(dev);
3568 case FW_CMD_IQK_ENABLE:
3569 write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
3570 ChkFwCmdIoDone(dev);
3573 case FW_CMD_TXPWR_TRACK_ENABLE:
3574 write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
3575 ChkFwCmdIoDone(dev);
3578 case FW_CMD_TXPWR_TRACK_DISABLE:
3579 write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
3580 ChkFwCmdIoDone(dev);
3583 case FW_CMD_PAUSE_DM_BY_SCAN:
3584 RT_TRACE(COMP_CMD,"[FW CMD] Pause DM by Scan!!\n");
3585 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
3586 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
3587 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
3590 case FW_CMD_RESUME_DM_BY_SCAN:
3591 RT_TRACE(COMP_CMD, "[FW CMD] Resume DM by Scan!!\n");
3592 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
3593 PHY_SetTxPowerLevel8192S(dev, priv->chan);
3595 case FW_CMD_HIGH_PWR_DISABLE:
3596 RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Disable!!\n");
3597 if(priv->DMFlag & HAL_DM_HIPWR_DISABLE)
3599 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
3600 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
3601 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
3604 case FW_CMD_HIGH_PWR_ENABLE:
3605 RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Enable!!\n");
3606 if(priv->DMFlag & HAL_DM_HIPWR_DISABLE)
3608 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
3611 case FW_CMD_LPS_ENTER:
3612 RT_TRACE(COMP_CMD, "[FW CMD] Enter LPS mode!!\n");
3613 CurrentAID = priv->ieee80211->assoc_id;
3614 write_nic_dword(dev, WFM5, (FW_LPS_ENTER| ((CurrentAID|0xc000)<<8)) );
3615 ChkFwCmdIoDone(dev);
3616 pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_EDCA_TURBO;
3619 case FW_CMD_LPS_LEAVE:
3620 RT_TRACE(COMP_CMD, "[FW CMD] Leave LPS mode!!\n");
3621 write_nic_dword(dev, WFM5, FW_LPS_LEAVE );
3622 ChkFwCmdIoDone(dev);
3623 pHTInfo->IOTAction &= (~HT_IOT_ACT_DISABLE_EDCA_TURBO);
3630 priv->SetFwCmdInProgress = false;
3631 RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");