drivers/staging/rtl8192su/r8192S_phy.c

   1 /******************************************************************************
   2
   3      (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
   4
   5  Module:        hal8192sphy.c
   6
   7  Note:          Merge 92SE/SU PHY config as below
   8                         1. BB register R/W API
   9                         2. RF register R/W API
  10                         3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
  11                         3. Power setting API
  12                         4. Channel switch API
  13                         5. Initial gain switch API.
  14                         6. Other BB/MAC/RF API.
  15
  16  Function:      PHY: Extern function, phy: local function
  17
  18  Export:        PHY_FunctionName
  19
  20  Abbrev:        NONE
  21
  22  History:
  23         Data            Who             Remark
  24         08/08/2008  MHC         1. Port from 9x series phycfg.c
  25                                                 2. Reorganize code arch and ad description.
  26                                                 3. Collect similar function.
  27                                                 4. Seperate extern/local API.
  28         08/12/2008      MHC             We must merge or move USB PHY relative function later.
  29         10/07/2008      MHC             Add IQ calibration for PHY.(Only 1T2R mode now!!!)
  30         11/06/2008      MHC             Add TX Power index PG file to config in 0xExx register
  31                                                 area to map with EEPROM/EFUSE tx pwr index.
  32
  33 ******************************************************************************/
  34 #include "r8192U.h"
  35 #include "r8192U_dm.h"
  36 #include "r8192S_rtl6052.h"
  37
  38 #ifdef RTL8192SU
  39 #include "r8192S_hw.h"
  40 #include "r8192S_phy.h"
  41 #include "r8192S_phyreg.h"
  42 #include "r8192SU_HWImg.h"
  43 //#include "r8192S_FwImgDTM.h"
  44 #else
  45 #include "r8192U_hw.h"
  46 #include "r819xU_phy.h"
  47 #include "r819xU_phyreg.h"
  48 #endif
  49
  50 #include "ieee80211/dot11d.h"
  51
  52 /*---------------------------Define Local Constant---------------------------*/
  53 /* Channel switch:The size of command tables for switch channel*/
  54 #define MAX_PRECMD_CNT 16
  55 #define MAX_RFDEPENDCMD_CNT 16
  56 #define MAX_POSTCMD_CNT 16
  57 #define MAX_DOZE_WAITING_TIMES_9x 64
  58
  59 /*------------------------Define local variable------------------------------*/
  60 // 2004-05-11
  61 #ifndef RTL8192SU
  62 static u32      RF_CHANNEL_TABLE_ZEBRA[]={
  63                 0,
  64                 0x085c,//2412 1
  65                 0x08dc,//2417 2
  66                 0x095c,//2422 3
  67                 0x09dc,//2427 4
  68                 0x0a5c,//2432 5
  69                 0x0adc,//2437 6
  70                 0x0b5c,//2442 7
  71                 0x0bdc,//2447 8
  72                 0x0c5c,//2452 9
  73                 0x0cdc,//2457 10
  74                 0x0d5c,//2462 11
  75                 0x0ddc,//2467 12
  76                 0x0e5c,//2472 13
  77                 //0x0f5c,//2484
  78                 0x0f72,//2484  //20040810
  79 };
  80 #endif
  81
  82 static  u32
  83 phy_CalculateBitShift(u32 BitMask);
  84 static  RT_STATUS
  85 phy_ConfigMACWithHeaderFile(struct net_device* dev);
  86 static void
  87 phy_InitBBRFRegisterDefinition(struct net_device* dev);
  88 static  RT_STATUS
  89 phy_BB8192S_Config_ParaFile(struct net_device* dev);
  90 static  RT_STATUS
  91 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
  92 static bool
  93 phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
  94 void
  95 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  96 void
  97 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  98 void
  99 SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
 100 static void
 101 phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
 102 static bool
 103 phy_SwChnlStepByStep(
 104         struct net_device* dev,
 105         u8              channel,
 106         u8              *stage,
 107         u8              *step,
 108         u32             *delay
 109         );
 110 static RT_STATUS
 111 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
 112 static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE   WirelessMode, u8 TxPwrIdx);
 113 static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
 114 void phy_SetFwCmdIOCallback(struct net_device* dev);
 115
 116 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 117 #ifdef RTL8192SU
 118 //
 119 // Description:
 120 //      Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
 121 //
 122 // Assumption:
 123 //              -       Only use on RTL8192S USB interface.
 124 //              -       PASSIVE LEVEL
 125 //
 126 // Created by Roger, 2008.09.06.
 127 //
 128 //use in phy only
 129 u32 phy_QueryUsbBBReg(struct net_device* dev, u32       RegAddr)
 130 {
 131         struct r8192_priv *priv = ieee80211_priv(dev);
 132         u32     ReturnValue = 0xffffffff;
 133         u8      PollingCnt = 50;
 134         u8      BBWaitCounter = 0;
 135
 136
 137         //
 138         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 139         // We have to make sure that previous BB I/O has been done.
 140         // 2008.08.20.
 141         //
 142         while(priv->bChangeBBInProgress)
 143         {
 144                 BBWaitCounter ++;
 145                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 146                 msleep(1); // 1 ms
 147
 148                 // Wait too long, return FALSE to avoid to be stuck here.
 149                 if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter))
 150                 {
 151                         RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 152                         return ReturnValue;
 153                 }
 154         }
 155
 156         priv->bChangeBBInProgress = true;
 157
 158         read_nic_dword(dev, RegAddr);
 159
 160         do
 161         {// Make sure that access could be done.
 162                 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
 163                         break;
 164         }while( --PollingCnt );
 165
 166         if(PollingCnt == 0)
 167         {
 168                 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
 169         }
 170         else
 171         {
 172                 // Data FW read back.
 173                 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
 174                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
 175         }
 176
 177         priv->bChangeBBInProgress = false;
 178
 179         return ReturnValue;
 180 }
 181
 182
 183
 184 //
 185 // Description:
 186 //      Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
 187 //
 188 // Assumption:
 189 //              -       Only use on RTL8192S USB interface.
 190 //              -       PASSIVE LEVEL
 191 //
 192 // Created by Roger, 2008.09.06.
 193 //
 194 //use in phy only
 195 void
 196 phy_SetUsbBBReg(struct net_device* dev,u32      RegAddr,u32 Data)
 197 {
 198         struct r8192_priv *priv = ieee80211_priv(dev);
 199         u8      BBWaitCounter = 0;
 200
 201         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
 202
 203         //
 204         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 205         // We have to make sure that previous BB I/O has been done.
 206         // 2008.08.20.
 207         //
 208         while(priv->bChangeBBInProgress)
 209         {
 210                 BBWaitCounter ++;
 211                 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 212                 msleep(1); // 1 ms
 213
 214                 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 215                 {
 216                         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 217                         return;
 218                 }
 219         }
 220
 221         priv->bChangeBBInProgress = true;
 222         //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
 223         write_nic_dword(dev, RegAddr, Data);
 224
 225         priv->bChangeBBInProgress = false;
 226 }
 227
 228
 229
 230 //
 231 // Description:
 232 //      RF read by 4181 to make sure that operation could be done in unlimited cycle.
 233 //
 234 // Assumption:
 235 //              -       Only use on RTL8192S USB interface.
 236 //              -       PASSIVE LEVEL
 237 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 238 //
 239 // Created by Roger, 2008.09.06.
 240 //
 241 //use in phy only
 242 u32 phy_QueryUsbRFReg(  struct net_device* dev, RF90_RADIO_PATH_E eRFPath,      u32     Offset)
 243 {
 244
 245         struct r8192_priv *priv = ieee80211_priv(dev);
 246         //u32   value  = 0, ReturnValue = 0;
 247         u32     ReturnValue = 0;
 248         //u32   tmplong,tmplong2;
 249         u8      PollingCnt = 50;
 250         u8      RFWaitCounter = 0;
 251
 252
 253         //
 254         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 255         // We have to make sure that previous RF I/O has been done.
 256         // 2008.08.20.
 257         //
 258         while(priv->bChangeRFInProgress)
 259         {
 260                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 261                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 262                 down(&priv->rf_sem);
 263
 264                 RFWaitCounter ++;
 265                 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 266                 msleep(1); // 1 ms
 267
 268                 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
 269                 {
 270                         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 271                         return 0xffffffff;
 272                 }
 273                 else
 274                 {
 275                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 276                 }
 277         }
 278
 279         priv->bChangeRFInProgress = true;
 280         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 281
 282
 283         Offset &= 0x3f; //RF_Offset= 0x00~0x3F
 284
 285         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
 286                                                 (Offset<<8)|    //RF_Offset= 0x00~0x3F
 287                                                 (eRFPath<<16));         //RF_Path = 0(A) or 1(B)
 288
 289         do
 290         {// Make sure that access could be done.
 291                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 292                         break;
 293         }while( --PollingCnt );
 294
 295         // Data FW read back.
 296         ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
 297
 298         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 299         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 300         up(&priv->rf_sem);
 301         priv->bChangeRFInProgress = false;
 302
 303         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
 304
 305         return ReturnValue;
 306
 307 }
 308
 309
 310 //
 311 // Description:
 312 //      RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
 313 //
 314 // Assumption:
 315 //              -       Only use on RTL8192S USB interface.
 316 //              -       PASSIVE LEVEL
 317 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 318 //
 319 // Created by Roger, 2008.09.06.
 320 //
 321 //use in phy only
 322 void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32       RegAddr,u32 Data)
 323 {
 324
 325         struct r8192_priv *priv = ieee80211_priv(dev);
 326         u8      PollingCnt = 50;
 327         u8      RFWaitCounter = 0;
 328
 329
 330         //
 331         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 332         // We have to make sure that previous BB I/O has been done.
 333         // 2008.08.20.
 334         //
 335         while(priv->bChangeRFInProgress)
 336         {
 337                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 338                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 339                 down(&priv->rf_sem);
 340
 341                 RFWaitCounter ++;
 342                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 343                 msleep(1); // 1 ms
 344
 345                 if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 346                 {
 347                         RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 348                         return;
 349                 }
 350                 else
 351                 {
 352                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 353                 }
 354         }
 355
 356         priv->bChangeRFInProgress = true;
 357         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 358
 359
 360         RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
 361
 362         write_nic_dword(dev, RF_BB_CMD_DATA, Data);
 363         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
 364                                         (RegAddr<<8)| //RF_Offset= 0x00~0x3F
 365                                         (eRFPath<<16));  //RF_Path = 0(A) or 1(B)
 366
 367         do
 368         {// Make sure that access could be done.
 369                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 370                                 break;
 371         }while( --PollingCnt );
 372
 373         if(PollingCnt == 0)
 374         {
 375                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
 376         }
 377
 378         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 379         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 380         up(&priv->rf_sem);
 381         priv->bChangeRFInProgress = false;
 382
 383 }
 384
 385 #endif
 386
 387 /*---------------------Define local function prototype-----------------------*/
 388
 389
 390 /*----------------------------Function Body----------------------------------*/
 391 //
 392 // 1. BB register R/W API
 393 //
 394 /**
 395 * Function:     PHY_QueryBBReg
 396 *
 397 * OverView:     Read "sepcific bits" from BB register
 398 *
 399 * Input:
 400 *                       PADAPTER                Adapter,
 401 *                       u32                     RegAddr,                //The target address to be readback
 402 *                       u32                     BitMask         //The target bit position in the target address
 403 *                                                                               //to be readback
 404 * Output:       None
 405 * Return:               u32                     Data                    //The readback register value
 406 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
 407 */
 408 //use phy dm core 8225 8256 6052
 409 //u32 PHY_QueryBBReg(struct net_device* dev,u32         RegAddr,        u32             BitMask)
 410 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
 411 {
 412
 413         u32     ReturnValue = 0, OriginalValue, BitShift;
 414
 415
 416         RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
 417
 418         //
 419         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 420         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 421         // infinite cycle.
 422         // 2008.09.06.
 423         //
 424 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 425 #ifdef RTL8192SU
 426         if(IS_BB_REG_OFFSET_92S(RegAddr))
 427         {
 428                 //if(RT_USB_CANNOT_IO(Adapter)) return  FALSE;
 429
 430                 if((RegAddr & 0x03) != 0)
 431                 {
 432                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 433                         return 0;
 434                 }
 435
 436         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 437         }
 438         else
 439 #endif
 440         {
 441         OriginalValue = read_nic_dword(dev, RegAddr);
 442         }
 443
 444         BitShift = phy_CalculateBitShift(BitMask);
 445         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 446
 447         //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue));
 448         RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
 449         return (ReturnValue);
 450 }
 451
 452 /**
 453 * Function:     PHY_SetBBReg
 454 *
 455 * OverView:     Write "Specific bits" to BB register (page 8~)
 456 *
 457 * Input:
 458 *                       PADAPTER                Adapter,
 459 *                       u32                     RegAddr,                //The target address to be modified
 460 *                       u32                     BitMask         //The target bit position in the target address
 461 *                                                                               //to be modified
 462 *                       u32                     Data                    //The new register value in the target bit position
 463 *                                                                               //of the target address
 464 *
 465 * Output:       None
 466 * Return:               None
 467 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 468 */
 469 //use phy dm core 8225 8256
 470 //void PHY_SetBBReg(struct net_device* dev,u32          RegAddr,        u32             BitMask,        u32             Data    )
 471 void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
 472 {
 473         u32     OriginalValue, BitShift, NewValue;
 474
 475
 476         RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 477
 478         //
 479         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 480         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 481         // infinite cycle.
 482         // 2008.09.06.
 483         //
 484 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 485 #ifdef RTL8192SU
 486         if(IS_BB_REG_OFFSET_92S(RegAddr))
 487         {
 488                 if((RegAddr & 0x03) != 0)
 489                 {
 490                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 491                         return;
 492                 }
 493
 494                 if(BitMask!= bMaskDWord)
 495                 {//if not "double word" write
 496                         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 497                         BitShift = phy_CalculateBitShift(BitMask);
 498             NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
 499                         phy_SetUsbBBReg(dev, RegAddr, NewValue);
 500                 }else
 501                         phy_SetUsbBBReg(dev, RegAddr, Data);
 502         }
 503         else
 504 #endif
 505         {
 506                 if(BitMask!= bMaskDWord)
 507                 {//if not "double word" write
 508                         OriginalValue = read_nic_dword(dev, RegAddr);
 509                         BitShift = phy_CalculateBitShift(BitMask);
 510                         NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
 511                         write_nic_dword(dev, RegAddr, NewValue);
 512                 }else
 513                         write_nic_dword(dev, RegAddr, Data);
 514         }
 515
 516         //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 517
 518         return;
 519 }
 520
 521
 522 //
 523 // 2. RF register R/W API
 524 //
 525 /**
 526 * Function:     PHY_QueryRFReg
 527 *
 528 * OverView:     Query "Specific bits" to RF register (page 8~)
 529 *
 530 * Input:
 531 *                       PADAPTER                Adapter,
 532 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 533 *                       u32                     RegAddr,                //The target address to be read
 534 *                       u32                     BitMask         //The target bit position in the target address
 535 *                                                                               //to be read
 536 *
 537 * Output:       None
 538 * Return:               u32                     Readback value
 539 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 540 */
 541 //in dm 8256 and phy
 542 //u32 PHY_QueryRFReg(struct net_device* dev,    RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 543 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 544 {
 545         u32 Original_Value, Readback_Value, BitShift;//, flags;
 546         struct r8192_priv *priv = ieee80211_priv(dev);
 547
 548
 549         RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
 550
 551         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 552         {
 553                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 554                 return 0;
 555         }
 556
 557         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 558         {
 559                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 560                 return 0;
 561         }
 562
 563         /* 2008/01/17 MH We get and release spin lock when reading RF register. */
 564         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM
 565         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 566         down(&priv->rf_sem);
 567         //
 568         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 569         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 570         // infinite cycle.
 571         // 2008.09.06.
 572         //
 573 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 574 #ifdef RTL8192SU
 575         //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
 576         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 577 #else
 578         if (priv->Rf_Mode == RF_OP_By_FW)
 579         {
 580                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 581         }
 582         else
 583         {
 584                 Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
 585         }
 586 #endif
 587
 588         BitShift =  phy_CalculateBitShift(BitMask);
 589         Readback_Value = (Original_Value & BitMask) >> BitShift;
 590         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 591         up(&priv->rf_sem);
 592         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 593
 594         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value));
 595
 596         return (Readback_Value);
 597 }
 598
 599 /**
 600 * Function:     PHY_SetRFReg
 601 *
 602 * OverView:     Write "Specific bits" to RF register (page 8~)
 603 *
 604 * Input:
 605 *                       PADAPTER                Adapter,
 606 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 607 *                       u32                     RegAddr,                //The target address to be modified
 608 *                       u32                     BitMask         //The target bit position in the target address
 609 *                                                                               //to be modified
 610 *                       u32                     Data                    //The new register Data in the target bit position
 611 *                                                                               //of the target address
 612 *
 613 * Output:       None
 614 * Return:               None
 615 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 616 */
 617 //use phy  8225 8256
 618 //void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32       RegAddr,        u32 BitMask,u32 Data    )
 619 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 620 {
 621
 622         struct r8192_priv *priv = ieee80211_priv(dev);
 623         u32 Original_Value, BitShift, New_Value;//, flags;
 624
 625         RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 626                 RegAddr, BitMask, Data, eRFPath);
 627
 628         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 629         {
 630                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 631                 return ;
 632         }
 633         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 634         {
 635                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 636                 return;
 637         }
 638
 639         /* 2008/01/17 MH We get and release spin lock when writing RF register. */
 640         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 641         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 642         down(&priv->rf_sem);
 643         //
 644         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 645         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 646         // infinite cycle.
 647         // 2008.09.06.
 648         //
 649 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 650 #ifdef RTL8192SU
 651                 //if(RT_USB_CANNOT_IO(Adapter)) return;
 652
 653                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 654                 {
 655                         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 656                         BitShift =  phy_CalculateBitShift(BitMask);
 657                         New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
 658                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
 659                 }
 660                 else
 661                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
 662 #else
 663         if (priv->Rf_Mode == RF_OP_By_FW)
 664         {
 665                 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
 666                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 667                 {
 668                         Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 669                         BitShift =  phy_CalculateBitShift(BitMask);
 670                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 671
 672                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 673                 }
 674                 else
 675                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
 676         }
 677         else
 678         {
 679                 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
 680                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 681                 {
 682                         Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
 683                         BitShift =  phy_CalculateBitShift(BitMask);
 684                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 685
 686                         phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 687                 }
 688                 else
 689                         phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
 690
 691         }
 692 #endif
 693         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 694         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 695         up(&priv->rf_sem);
 696         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data));
 697         RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 698                         RegAddr, BitMask, Data, eRFPath);
 699
 700 }
 701
 702 /**
 703 * Function:     phy_RFSerialRead
 704 *
 705 * OverView:     Read regster from RF chips
 706 *
 707 * Input:
 708 *                       PADAPTER                Adapter,
 709 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 710 *                       u4Byte                  Offset,         //The target address to be read
 711 *
 712 * Output:       None
 713 * Return:               u4Byte                  reback value
 714 * Note:         Threre are three types of serial operations:
 715 *                       1. Software serial write
 716 *                       2. Hardware LSSI-Low Speed Serial Interface
 717 *                       3. Hardware HSSI-High speed
 718 *                       serial write. Driver need to implement (1) and (2).
 719 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 720 */
 721 #if 0
 722 static  u32
 723 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
 724 {
 725
 726         u32                                             retValue = 0;
 727         struct r8192_priv *priv = ieee80211_priv(dev);
 728         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 729         u32                                             NewOffset;
 730         //u32                                           value  = 0;
 731         u32                                             tmplong,tmplong2;
 732         u32                                             RfPiEnable=0;
 733 #if 0
 734         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
 735                 return  retValue;
 736         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
 737                 return  retValue;
 738 #endif
 739         //
 740         // Make sure RF register offset is correct
 741         //
 742         Offset &= 0x3f;
 743
 744         //
 745         // Switch page for 8256 RF IC
 746         //
 747         NewOffset = Offset;
 748
 749         // For 92S LSSI Read RFLSSIRead
 750         // For RF A/B write 0x824/82c(does not work in the future)
 751         // We must use 0x824 for RF A and B to execute read trigger
 752         tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
 753         tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
 754         tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  //T65 RF
 755
 756         rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
 757         mdelay(1);
 758
 759         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
 760         mdelay(1);
 761
 762         rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
 763         mdelay(1);
 764
 765         if(eRFPath == RF90_PATH_A)
 766                 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
 767         else if(eRFPath == RF90_PATH_B)
 768                 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
 769
 770         if(RfPiEnable)
 771         {       // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
 772                 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
 773                 //DbgPrint("Readback from RF-PI : 0x%x\n", retValue);
 774         }
 775         else
 776         {       //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
 777                 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 778                 //DbgPrint("Readback from RF-SI : 0x%x\n", retValue);
 779         }
 780         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue));
 781
 782         return retValue;
 783
 784 }
 785 4
 786
 787
 788 /**
 789 * Function:     phy_RFSerialWrite
 790 *
 791 * OverView:     Write data to RF register (page 8~)
 792 *
 793 * Input:
 794 *                       PADAPTER                Adapter,
 795 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 796 *                       u4Byte                  Offset,         //The target address to be read
 797 *                       u4Byte                  Data                    //The new register Data in the target bit position
 798 *                                                                               //of the target to be read
 799 *
 800 * Output:       None
 801 * Return:               None
 802 * Note:         Threre are three types of serial operations:
 803 *                       1. Software serial write
 804 *                       2. Hardware LSSI-Low Speed Serial Interface
 805 *                       3. Hardware HSSI-High speed
 806 *                       serial write. Driver need to implement (1) and (2).
 807 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 808  *
 809  * Note:                  For RF8256 only
 810  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
 811  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
 812  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
 813  *                       programming guide" for more details.
 814  *                       Thus, we define a sub-finction for RTL8526 register address conversion
 815  *                     ===========================================================
 816  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
 817  *                                                              (Reg00[12])             (Reg00[10])
 818  *                     ===========================================================
 819  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
 820  *                     ------------------------------------------------------------------
 821  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
 822  *                     ------------------------------------------------------------------
 823  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 824  *                     ------------------------------------------------------------------
 825  *
 826  *      2008/09/02      MH      Add 92S RF definition
 827  *
 828  *
 829  *
 830 */
 831 static  void
 832 phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32       Data)
 833 {
 834         u32                                             DataAndAddr = 0;
 835         struct r8192_priv *priv = ieee80211_priv(dev);
 836         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 837         u32                                             NewOffset;
 838
 839 #if 0
 840         //<Roger_TODO> We should check valid regs for RF_6052 case.
 841         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
 842                 return;
 843         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
 844                 return;
 845 #endif
 846
 847         Offset &= 0x3f;
 848
 849         //
 850         // Shadow Update
 851         //
 852         PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
 853
 854         //
 855         // Switch page for 8256 RF IC
 856         //
 857                 NewOffset = Offset;
 858
 859         //
 860         // Put write addr in [5:0]  and write data in [31:16]
 861         //
 862         //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
 863         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       // T65 RF
 864
 865         //
 866         // Write Operation
 867         //
 868         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 869         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
 870
 871 }
 872 #endif
 873
 874 /**
 875 * Function:     phy_CalculateBitShift
 876 *
 877 * OverView:     Get shifted position of the BitMask
 878 *
 879 * Input:
 880 *                       u32             BitMask,
 881 *
 882 * Output:       none
 883 * Return:               u32             Return the shift bit bit position of the mask
 884 */
 885 //use in phy only
 886 static u32 phy_CalculateBitShift(u32 BitMask)
 887 {
 888         u32 i;
 889
 890         for(i=0; i<=31; i++)
 891         {
 892                 if ( ((BitMask>>i) &  0x1 ) == 1)
 893                         break;
 894         }
 895
 896         return (i);
 897 }
 898
 899
 900 //
 901 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
 902 //
 903 /*-----------------------------------------------------------------------------
 904  * Function:    PHY_MACConfig8192S
 905  *
 906  * Overview:    Condig MAC by header file or parameter file.
 907  *
 908  * Input:       NONE
 909  *
 910  * Output:      NONE
 911  *
 912  * Return:      NONE
 913  *
 914  * Revised History:
 915  *  When                Who             Remark
 916  *  08/12/2008  MHC             Create Version 0.
 917  *
 918  *---------------------------------------------------------------------------*/
 919 //adapter_start
 920 extern bool PHY_MACConfig8192S(struct net_device* dev)
 921 {
 922         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
 923
 924         //
 925         // Config MAC
 926         //
 927         rtStatus = phy_ConfigMACWithHeaderFile(dev);
 928         return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
 929
 930 }
 931
 932 //adapter_start
 933 extern  bool
 934 PHY_BBConfig8192S(struct net_device* dev)
 935 {
 936         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
 937
 938         u8 PathMap = 0, index = 0, rf_num = 0;
 939         struct r8192_priv       *priv = ieee80211_priv(dev);
 940         phy_InitBBRFRegisterDefinition(dev);
 941
 942         //
 943         // Config BB and AGC
 944         //
 945         //switch( Adapter->MgntInfo.bRegHwParaFile )
 946         //{
 947         //      case 0:
 948         //              phy_BB8190_Config_HardCode(dev);
 949         //              break;
 950
 951         //      case 1:
 952                         rtStatus = phy_BB8192S_Config_ParaFile(dev);
 953         //              break;
 954
 955         //      case 2:
 956                         // Partial Modify.
 957         //              phy_BB8190_Config_HardCode(dev);
 958         //              phy_BB8192S_Config_ParaFile(dev);
 959         //              break;
 960
 961         //      default:
 962         //              phy_BB8190_Config_HardCode(dev);
 963         //              break;
 964         //}
 965         PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
 966                                 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
 967         priv->rf_pathmap = PathMap;
 968         for(index = 0; index<4; index++)
 969         {
 970                 if((PathMap>>index)&0x1)
 971                         rf_num++;
 972         }
 973
 974         if((priv->rf_type==RF_1T1R && rf_num!=1) ||
 975                 (priv->rf_type==RF_1T2R && rf_num!=2) ||
 976                 (priv->rf_type==RF_2T2R && rf_num!=2) ||
 977                 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
 978                 (priv->rf_type==RF_2T4R && rf_num!=4))
 979         {
 980                 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
 981         }
 982         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
 983 }
 984
 985 //adapter_start
 986 extern  bool
 987 PHY_RFConfig8192S(struct net_device* dev)
 988 {
 989         struct r8192_priv       *priv = ieee80211_priv(dev);
 990         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
 991
 992         //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
 993
 994         //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
 995         priv->rf_chip = RF_6052;
 996
 997         //
 998         // RF config
 999         //
1000         switch(priv->rf_chip)
1001         {
1002         case RF_8225:
1003         case RF_6052:
1004                 rtStatus = PHY_RF6052_Config(dev);
1005                 break;
1006
1007         case RF_8256:
1008                 //rtStatus = PHY_RF8256_Config(dev);
1009                 break;
1010
1011         case RF_8258:
1012                 break;
1013
1014         case RF_PSEUDO_11N:
1015                 //rtStatus = PHY_RF8225_Config(dev);
1016                 break;
1017         default:
1018             break;
1019         }
1020
1021         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1022 }
1023
1024
1025 // Joseph test: new initialize order!!
1026 // Test only!! This part need to be re-organized.
1027 // Now it is just for 8256.
1028 //use in phy only
1029 #ifdef TO_DO_LIST
1030 static RT_STATUS
1031 phy_BB8190_Config_HardCode(struct net_device* dev)
1032 {
1033         //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
1034         return RT_STATUS_SUCCESS;
1035 }
1036 #endif
1037
1038 /*-----------------------------------------------------------------------------
1039  * Function:    phy_SetBBtoDiffRFWithHeaderFile()
1040  *
1041  * Overview:    This function
1042  *
1043  *
1044  * Input:       PADAPTER                Adapter
1045  *                      u1Byte                  ConfigType     0 => PHY_CONFIG
1046  *
1047  * Output:      NONE
1048  *
1049  * Return:      RT_STATUS_SUCCESS: configuration file exist
1050  * When                 Who             Remark
1051  * 2008/11/10   tynli
1052  * use in phy only
1053  *---------------------------------------------------------------------------*/
1054 static RT_STATUS
1055 phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
1056 {
1057         int i;
1058         struct r8192_priv       *priv = ieee80211_priv(dev);
1059         u32*                    Rtl819XPHY_REGArraytoXTXR_Table;
1060         u16                             PHY_REGArraytoXTXRLen;
1061
1062 //#if (HAL_CODE_BASE != RTL8192_S)
1063
1064         if(priv->rf_type == RF_1T1R)
1065         {
1066                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
1067                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
1068         }
1069         else if(priv->rf_type == RF_1T2R)
1070         {
1071                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
1072                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
1073         }
1074         //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN)
1075         //{
1076         //      Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array;
1077         //      PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength;
1078         //}
1079         else
1080         {
1081                 return RT_STATUS_FAILURE;
1082         }
1083
1084         if(ConfigType == BaseBand_Config_PHY_REG)
1085         {
1086                 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
1087                 {
1088                         if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
1089                                 mdelay(50);
1090                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
1091                                 mdelay(5);
1092                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
1093                                 mdelay(1);
1094                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
1095                                 udelay(50);
1096                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
1097                                 udelay(5);
1098                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
1099                                 udelay(1);
1100                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1101                         //RT_TRACE(COMP_SEND,
1102                         //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n",
1103                         //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1104                 }
1105         }
1106         else {
1107                 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1108         }
1109 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1110         return RT_STATUS_SUCCESS;
1111 }
1112
1113
1114 //use in phy only
1115 static  RT_STATUS
1116 phy_BB8192S_Config_ParaFile(struct net_device* dev)
1117 {
1118         struct r8192_priv       *priv = ieee80211_priv(dev);
1119         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
1120         //u8                            u2RegValue;
1121         //u16                           u4RegValue;
1122         //char                          szBBRegFile[] = RTL819X_PHY_REG;
1123         //char                          szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R;
1124         //char                          szBBRegPgFile[] = RTL819X_PHY_REG_PG;
1125         //char                          szAGCTableFile[] = RTL819X_AGC_TAB;
1126         //char                          szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R;
1127         //char                          szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R;
1128
1129         RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
1130
1131         //
1132         // 1. Read PHY_REG.TXT BB INIT!!
1133         // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R
1134         //
1135         if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
1136             priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
1137         {
1138                 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1139                 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
1140                 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
1141                   //so we should reconfig BB reg with the right PHY parameters.
1142                         rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1143                 }
1144         }else
1145                 rtStatus = RT_STATUS_FAILURE;
1146
1147         if(rtStatus != RT_STATUS_SUCCESS){
1148                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
1149                 goto phy_BB8190_Config_ParaFile_Fail;
1150         }
1151
1152         //
1153         // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
1154         //
1155         if (priv->AutoloadFailFlag == false)
1156         {
1157                 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
1158         }
1159         if(rtStatus != RT_STATUS_SUCCESS){
1160                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
1161                 goto phy_BB8190_Config_ParaFile_Fail;
1162         }
1163
1164         //
1165         // 3. BB AGC table Initialization
1166         //
1167         rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
1168
1169         if(rtStatus != RT_STATUS_SUCCESS){
1170                 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
1171                 goto phy_BB8190_Config_ParaFile_Fail;
1172         }
1173
1174
1175 #if 0   // 2008/08/18 MH Disable for 92SE
1176         if(pHalData->VersionID > VERSION_8190_BD)
1177         {
1178                 //if(pHalData->RF_Type == RF_2T4R)
1179                 //{
1180                 // Antenna gain offset from B/C/D to A
1181                 u4RegValue = (  pHalData->AntennaTxPwDiff[2]<<8 |
1182                                                 pHalData->AntennaTxPwDiff[1]<<4 |
1183                                                 pHalData->AntennaTxPwDiff[0]);
1184                 //}
1185                 //else
1186                 //u4RegValue = 0;
1187
1188                 PHY_SetBBReg(dev, rFPGA0_TxGainStage,
1189                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1190
1191                 // CrystalCap
1192                 // Simulate 8192???
1193                 u4RegValue = pHalData->CrystalCap;
1194                 PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
1195                 // Simulate 8190??
1196                 //u4RegValue = ((pHalData->CrystalCap & 0xc)>>2);       // bit2~3 of crystal cap
1197                 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, bXtalCap23, u4RegValue);
1198
1199         }
1200 #endif
1201
1202         // Check if the CCK HighPower is turned ON.
1203         // This is used to calculate PWDB.
1204         priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1205
1206
1207 phy_BB8190_Config_ParaFile_Fail:
1208         return rtStatus;
1209 }
1210
1211 /*-----------------------------------------------------------------------------
1212  * Function:    phy_ConfigMACWithHeaderFile()
1213  *
1214  * Overview:    This function read BB parameters from Header file we gen, and do register
1215  *                        Read/Write
1216  *
1217  * Input:       PADAPTER                Adapter
1218  *                      char*                   pFileName
1219  *
1220  * Output:      NONE
1221  *
1222  * Return:      RT_STATUS_SUCCESS: configuration file exist
1223  *
1224  * Note:                The format of MACPHY_REG.txt is different from PHY and RF.
1225  *                      [Register][Mask][Value]
1226  *---------------------------------------------------------------------------*/
1227 //use in phy only
1228 static  RT_STATUS
1229 phy_ConfigMACWithHeaderFile(struct net_device* dev)
1230 {
1231         u32                                     i = 0;
1232         u32                                     ArrayLength = 0;
1233         u32*                                    ptrArray;
1234         //struct r8192_priv     *priv = ieee80211_priv(dev);
1235
1236 //#if (HAL_CODE_BASE != RTL8192_S)
1237         /*if(Adapter->bInHctTest)
1238         {
1239                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
1240                 ArrayLength = MACPHY_ArrayLengthDTM;
1241                 ptrArray = Rtl819XMACPHY_ArrayDTM;
1242         }
1243         else if(pHalData->bTXPowerDataReadFromEEPORM)
1244         {
1245 //              RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n"));
1246 //              ArrayLength = MACPHY_Array_PGLength;
1247 //              ptrArray = Rtl819XMACPHY_Array_PG;
1248
1249         }else*/
1250         { //2008.11.06 Modified by tynli.
1251                 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
1252                 ArrayLength = MAC_2T_ArrayLength;
1253                 ptrArray = Rtl819XMAC_Array;
1254         }
1255
1256         /*for(i = 0 ;i < ArrayLength;i=i+3){
1257                 RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
1258                 if(ptrArray[i] == 0x318)
1259                 {
1260                         ptrArray[i+2] = 0x00000800;
1261                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1262                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1263                 }
1264                 PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1265         }*/
1266         for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
1267                 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
1268         }
1269 //#endif
1270         return RT_STATUS_SUCCESS;
1271 }
1272
1273 /*-----------------------------------------------------------------------------
1274  * Function:    phy_ConfigBBWithHeaderFile()
1275  *
1276  * Overview:    This function read BB parameters from general file format, and do register
1277  *                        Read/Write
1278  *
1279  * Input:       PADAPTER                Adapter
1280  *                      u8                      ConfigType     0 => PHY_CONFIG
1281  *                                                                               1 =>AGC_TAB
1282  *
1283  * Output:      NONE
1284  *
1285  * Return:      RT_STATUS_SUCCESS: configuration file exist
1286  *
1287  *---------------------------------------------------------------------------*/
1288 //use in phy only
1289 static  RT_STATUS
1290 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
1291 {
1292         int             i;
1293         //u8            ArrayLength;
1294         u32*    Rtl819XPHY_REGArray_Table;
1295         u32*    Rtl819XAGCTAB_Array_Table;
1296         u16             PHY_REGArrayLen, AGCTAB_ArrayLen;
1297         //struct r8192_priv *priv = ieee80211_priv(dev);
1298 //#if (HAL_CODE_BASE != RTL8192_S)
1299         /*if(Adapter->bInHctTest)
1300         {
1301
1302                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1303                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1304
1305                 if(pHalData->RF_Type == RF_2T4R)
1306                 {
1307                         PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1308                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1309                 }
1310                 else if (pHalData->RF_Type == RF_1T2R)
1311                 {
1312                         PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1313                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1314                 }
1315
1316         }
1317         else
1318         */
1319         //{
1320         //
1321         // 2008.11.06 Modified by tynli.
1322         //
1323         AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1324         Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1325         PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
1326         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
1327         //}
1328
1329         if(ConfigType == BaseBand_Config_PHY_REG)
1330         {
1331                 for(i=0;i<PHY_REGArrayLen;i=i+2)
1332                 {
1333                         if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1334                                 mdelay(50);
1335                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1336                                 mdelay(5);
1337                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1338                                 mdelay(1);
1339                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1340                                 udelay(50);
1341                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1342                                 udelay(5);
1343                         else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1344                                 udelay(1);
1345                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1346                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1347
1348                 }
1349         }
1350         else if(ConfigType == BaseBand_Config_AGC_TAB){
1351                 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1352                 {
1353                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1354                 }
1355         }
1356 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1357         return RT_STATUS_SUCCESS;
1358 }
1359
1360 /*-----------------------------------------------------------------------------
1361  * Function:    phy_ConfigBBWithPgHeaderFile
1362  *
1363  * Overview:    Config PHY_REG_PG array
1364  *
1365  * Input:       NONE
1366  *
1367  * Output:      NONE
1368  *
1369  * Return:      NONE
1370  *
1371  * Revised History:
1372  * When                 Who             Remark
1373  * 11/06/2008   MHC             Add later!!!!!!.. Please modify for new files!!!!
1374  * 11/10/2008   tynli           Modify to mew files.
1375  //use in phy only
1376  *---------------------------------------------------------------------------*/
1377 static RT_STATUS
1378 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1379 {
1380         int i;
1381         //u8 ArrayLength;
1382         u32*    Rtl819XPHY_REGArray_Table_PG;
1383         u16     PHY_REGArrayPGLen;
1384         //struct r8192_priv *priv = ieee80211_priv(dev);
1385 //#if (HAL_CODE_BASE != RTL8192_S)
1386         // Default: pHalData->RF_Type = RF_2T2R.
1387
1388         PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1389         Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1390
1391         if(ConfigType == BaseBand_Config_PHY_REG)
1392         {
1393                 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1394                 {
1395                         if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1396                                 mdelay(50);
1397                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1398                                 mdelay(5);
1399                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1400                                 mdelay(1);
1401                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1402                                 udelay(50);
1403                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1404                                 udelay(5);
1405                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1406                                 udelay(1);
1407                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1408                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",
1409                         //              Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]);
1410                 }
1411         }else{
1412                 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1413         }
1414         return RT_STATUS_SUCCESS;
1415
1416 }       /* phy_ConfigBBWithPgHeaderFile */
1417
1418 /*-----------------------------------------------------------------------------
1419  * Function:    PHY_ConfigRFWithHeaderFile()
1420  *
1421  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
1422  *
1423  * Input:       PADAPTER                        Adapter
1424  *                      char*                           pFileName
1425  *                      RF90_RADIO_PATH_E       eRFPath
1426  *
1427  * Output:      NONE
1428  *
1429  * Return:      RT_STATUS_SUCCESS: configuration file exist
1430  *
1431  * Note:                Delay may be required for RF configuration
1432  *---------------------------------------------------------------------------*/
1433 //in 8256 phy_RF8256_Config_ParaFile only
1434 //RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
1435 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1436 {
1437
1438         struct r8192_priv *priv = ieee80211_priv(dev);
1439         int                     i;
1440         //u32*  pRFArray;
1441         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1442         u32                     *Rtl819XRadioA_Array_Table;
1443         u32                     *Rtl819XRadioB_Array_Table;
1444         //u32*  Rtl819XRadioC_Array_Table;
1445         //u32*  Rtl819XRadioD_Array_Table;
1446         u16                     RadioA_ArrayLen,RadioB_ArrayLen;
1447
1448         {       //2008.11.06 Modified by tynli
1449                 RadioA_ArrayLen = RadioA_1T_ArrayLength;
1450                 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1451                 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1452                 RadioB_ArrayLen = RadioB_ArrayLength;
1453         }
1454
1455         if( priv->rf_type == RF_2T2R_GREEN )
1456         {
1457                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1458                 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1459         }
1460         else
1461         {
1462                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1463                 RadioB_ArrayLen = RadioB_ArrayLength;
1464         }
1465
1466         rtStatus = RT_STATUS_SUCCESS;
1467
1468         // When initialization, we want the delay function(mdelay(), delay_us()
1469         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1470         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1471         // to run at Dispatch level to achive it.
1472         //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
1473
1474         switch(eRFPath){
1475                 case RF90_PATH_A:
1476                         for(i = 0;i<RadioA_ArrayLen; i=i+2){
1477                                 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1478                                         { // Deay specific ms. Only RF configuration require delay.
1479 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1480 #ifdef RTL8192SU
1481                                                 mdelay(1000);
1482 #else
1483                                                 mdelay(50);
1484 #endif
1485                                 }
1486                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1487                                                 mdelay(5);
1488                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1489                                                 mdelay(1);
1490                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1491                                                 udelay(50);
1492                                                 //PlatformStallExecution(50);
1493                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1494                                                 udelay(5);
1495                                         else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1496                                                 udelay(1);
1497                                         else
1498                                         {
1499                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1500                                         }
1501                         }
1502                         break;
1503                 case RF90_PATH_B:
1504                         for(i = 0;i<RadioB_ArrayLen; i=i+2){
1505                                 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1506                                         { // Deay specific ms. Only RF configuration require delay.
1507 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1508 #ifdef RTL8192SU
1509                                                 mdelay(1000);
1510 #else
1511                                                 mdelay(50);
1512 #endif
1513                                 }
1514                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1515                                                 mdelay(5);
1516                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1517                                                 mdelay(1);
1518                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1519                                                 udelay(50);
1520                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1521                                                 udelay(5);
1522                                         else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1523                                                 udelay(1);
1524                                         else
1525                                         {
1526                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1527                                         }
1528                         }
1529                         break;
1530                 case RF90_PATH_C:
1531                         break;
1532                 case RF90_PATH_D:
1533                         break;
1534                 default:
1535                         break;
1536         }
1537
1538         return rtStatus;
1539
1540 }
1541
1542 /*-----------------------------------------------------------------------------
1543  * Function:    PHY_CheckBBAndRFOK()
1544  *
1545  * Overview:    This function is write register and then readback to make sure whether
1546  *                        BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
1547  *
1548  * Input:       PADAPTER                        Adapter
1549  *                      HW90_BLOCK_E            CheckBlock
1550  *                      RF90_RADIO_PATH_E       eRFPath         // it is used only when CheckBlock is HW90_BLOCK_RF
1551  *
1552  * Output:      NONE
1553  *
1554  * Return:      RT_STATUS_SUCCESS: PHY is OK
1555  *
1556  * Note:                This function may be removed in the ASIC
1557  *---------------------------------------------------------------------------*/
1558 //in 8256 phy_RF8256_Config_HardCode
1559 //but we don't use it temp
1560 RT_STATUS
1561 PHY_CheckBBAndRFOK(
1562         struct net_device* dev,
1563         HW90_BLOCK_E            CheckBlock,
1564         RF90_RADIO_PATH_E       eRFPath
1565         )
1566 {
1567         //struct r8192_priv *priv = ieee80211_priv(dev);
1568         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
1569         u32                             i, CheckTimes = 4,ulRegRead = 0;
1570         u32                             WriteAddr[4];
1571         u32                             WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1572
1573         // Initialize register address offset to be checked
1574         WriteAddr[HW90_BLOCK_MAC] = 0x100;
1575         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1576         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1577         WriteAddr[HW90_BLOCK_RF] = 0x3;
1578
1579         for(i=0 ; i < CheckTimes ; i++)
1580         {
1581
1582                 //
1583                 // Write Data to register and readback
1584                 //
1585                 switch(CheckBlock)
1586                 {
1587                 case HW90_BLOCK_MAC:
1588                         //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
1589                         RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1590                         break;
1591
1592                 case HW90_BLOCK_PHY0:
1593                 case HW90_BLOCK_PHY1:
1594                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
1595                         ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
1596                         break;
1597
1598                 case HW90_BLOCK_RF:
1599                         // When initialization, we want the delay function(mdelay(), delay_us()
1600                         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1601                         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1602                         // to run at Dispatch level to achive it.
1603                         //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK);
1604                         WriteData[i] &= 0xfff;
1605                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
1606                         // TODO: we should not delay for such a long time. Ask SD3
1607                         mdelay(10);
1608                         ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1609                         mdelay(10);
1610                         //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK);
1611                         break;
1612
1613                 default:
1614                         rtStatus = RT_STATUS_FAILURE;
1615                         break;
1616                 }
1617
1618
1619                 //
1620                 // Check whether readback data is correct
1621                 //
1622                 if(ulRegRead != WriteData[i])
1623                 {
1624                         //RT_TRACE(COMP_FPGA,  ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i]));
1625                         RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
1626                         rtStatus = RT_STATUS_FAILURE;
1627                         break;
1628                 }
1629         }
1630
1631         return rtStatus;
1632 }
1633
1634 //no use temp in windows driver
1635 #ifdef TO_DO_LIST
1636 void
1637 PHY_SetRFPowerState8192SUsb(
1638         struct net_device* dev,
1639         RF_POWER_STATE  RFPowerState
1640         )
1641 {
1642         struct r8192_priv *priv = ieee80211_priv(dev);
1643         bool                    WaitShutDown = FALSE;
1644         u32                     DWordContent;
1645         //RF90_RADIO_PATH_E     eRFPath;
1646         u8                              eRFPath;
1647         BB_REGISTER_DEFINITION_T        *pPhyReg;
1648
1649         if(priv->SetRFPowerStateInProgress == TRUE)
1650                 return;
1651
1652         priv->SetRFPowerStateInProgress = TRUE;
1653
1654         // TODO: Emily, 2006.11.21, we should rewrite this function
1655
1656         if(RFPowerState==RF_SHUT_DOWN)
1657         {
1658                 RFPowerState=RF_OFF;
1659                 WaitShutDown=TRUE;
1660         }
1661
1662
1663         priv->RFPowerState = RFPowerState;
1664         switch( priv->rf_chip )
1665         {
1666         case RF_8225:
1667         case RF_6052:
1668                 switch( RFPowerState )
1669                 {
1670                 case RF_ON:
1671                         break;
1672
1673                 case RF_SLEEP:
1674                         break;
1675
1676                 case RF_OFF:
1677                         break;
1678                 }
1679                 break;
1680
1681         case RF_8256:
1682                 switch( RFPowerState )
1683                 {
1684                 case RF_ON:
1685                         break;
1686
1687                 case RF_SLEEP:
1688                         break;
1689
1690                 case RF_OFF:
1691                         for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
1692                         {
1693                                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1694                                         continue;
1695
1696                                 pPhyReg = &priv->PHYRegDef[eRFPath];
1697                                 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
1698                                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
1699                         }
1700                         break;
1701                 }
1702                 break;
1703
1704         case RF_8258:
1705                 break;
1706         }// switch( priv->rf_chip )
1707
1708         priv->SetRFPowerStateInProgress = FALSE;
1709 }
1710 #endif
1711
1712 #ifdef RTL8192U
1713 //no use temp in windows driver
1714 void
1715 PHY_UpdateInitialGain(
1716         struct net_device* dev
1717         )
1718 {
1719         struct r8192_priv       *priv = ieee80211_priv(dev);
1720         //unsigned char                 *IGTable;
1721         //u8                    DIG_CurrentInitialGain = 4;
1722
1723         switch(priv->rf_chip)
1724         {
1725         case RF_8225:
1726                 break;
1727         case RF_8256:
1728                 break;
1729         case RF_8258:
1730                 break;
1731         case RF_PSEUDO_11N:
1732                 break;
1733         case RF_6052:
1734                 break;
1735         default:
1736                 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
1737                 break;
1738         }
1739 }
1740 #endif
1741
1742 //YJ,modified,090107
1743 void PHY_GetHWRegOriginalValue(struct net_device* dev)
1744 {
1745         struct r8192_priv *priv = ieee80211_priv(dev);
1746
1747         // read tx power offset
1748         // Simulate 8192
1749         priv->MCSTxPowerLevelOriginalOffset[0] =
1750                 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
1751         priv->MCSTxPowerLevelOriginalOffset[1] =
1752                 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
1753         priv->MCSTxPowerLevelOriginalOffset[2] =
1754                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
1755         priv->MCSTxPowerLevelOriginalOffset[3] =
1756                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
1757         priv->MCSTxPowerLevelOriginalOffset[4] =
1758                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
1759         priv->MCSTxPowerLevelOriginalOffset[5] =
1760                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
1761
1762         // Read CCK offset
1763         priv->MCSTxPowerLevelOriginalOffset[6] =
1764                 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
1765         RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
1766         priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
1767         priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
1768         priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
1769
1770         // read rx initial gain
1771         priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
1772         priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
1773         priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
1774         priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
1775         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
1776                         priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1777                         priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1778
1779         // read framesync
1780         priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
1781         priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
1782         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
1783                                 rOFDM0_RxDetector3, priv->framesync);
1784 }
1785 //YJ,modified,090107,end
1786
1787
1788
1789 /**
1790 * Function:     phy_InitBBRFRegisterDefinition
1791 *
1792 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
1793 *
1794 * Input:
1795 *                       PADAPTER                Adapter,
1796 *
1797 * Output:       None
1798 * Return:               None
1799 * Note:         The initialization value is constant and it should never be changes
1800 */
1801 //use in phy only
1802 static void phy_InitBBRFRegisterDefinition(     struct net_device* dev)
1803 {
1804         struct r8192_priv *priv = ieee80211_priv(dev);
1805
1806         // RF Interface Sowrtware Control
1807         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1808         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1809         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1810         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1811
1812         // RF Interface Readback Value
1813         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1814         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1815         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1816         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1817
1818         // RF Interface Output (and Enable)
1819         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1820         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1821         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1822         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1823
1824         // RF Interface (Output and)  Enable
1825         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1826         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1827         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1828         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1829
1830         //Addr of LSSI. Wirte RF register by driver
1831         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1832         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1833         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1834         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1835
1836         // RF parameter
1837         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
1838         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1839         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1840         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1841
1842         // Tx AGC Gain Stage (same for all path. Should we remove this?)
1843         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1844         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1845         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1846         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1847
1848         // Tranceiver A~D HSSI Parameter-1
1849         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
1850         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
1851         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
1852         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
1853
1854         // Tranceiver A~D HSSI Parameter-2
1855         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
1856         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
1857         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
1858         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
1859
1860         // RF switch Control
1861         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1862         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1863         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1864         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1865
1866         // AGC control 1
1867         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1868         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1869         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1870         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1871
1872         // AGC control 2
1873         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1874         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1875         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1876         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1877
1878         // RX AFE control 1
1879         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1880         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1881         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1882         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1883
1884         // RX AFE control 1
1885         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1886         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1887         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1888         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1889
1890         // Tx AFE control 1
1891         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1892         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1893         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1894         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1895
1896         // Tx AFE control 2
1897         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1898         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1899         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1900         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1901
1902         // Tranceiver LSSI Readback  SI mode
1903         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1904         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1905         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1906         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1907
1908         // Tranceiver LSSI Readback PI mode
1909         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
1910         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
1911         //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
1912         //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
1913
1914 }
1915
1916
1917 //
1918 //      Description:  Change RF power state.
1919 //
1920 //      Assumption: This function must be executed in re-schdulable context,
1921 //              ie. PASSIVE_LEVEL.
1922 //
1923 //      050823, by rcnjko.
1924 //not understand it seem's use in init
1925 //SetHwReg8192SUsb--->HalFunc.SetHwRegHandler
1926 bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
1927 {
1928         struct r8192_priv *priv = ieee80211_priv(dev);
1929         bool                    bResult = FALSE;
1930
1931         RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1932
1933         if(eRFPowerState == priv->ieee80211->eRFPowerState)
1934         {
1935                 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
1936                 return bResult;
1937         }
1938
1939         bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
1940
1941         RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
1942
1943         return bResult;
1944 }
1945
1946 //use in phy only
1947 static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
1948 {
1949         struct r8192_priv *priv = ieee80211_priv(dev);
1950         bool                    bResult = TRUE;
1951         //u8            eRFPath;
1952         //u8            i, QueueID;
1953         u8              u1bTmp;
1954
1955         if(priv->SetRFPowerStateInProgress == TRUE)
1956                 return FALSE;
1957
1958         priv->SetRFPowerStateInProgress = TRUE;
1959
1960         switch(priv->rf_chip )
1961         {
1962                 default:
1963                 switch( eRFPowerState )
1964                 {
1965                         case eRfOn:
1966                                 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
1967                                 write_nic_word(dev, CMDR, 0x37FC);
1968                                 write_nic_byte(dev, PHY_CCA, 0x3);
1969                                 write_nic_byte(dev, TXPAUSE, 0x00);
1970                                 write_nic_byte(dev, SPS1_CTRL, 0x64);
1971                                 break;
1972
1973                         //
1974                         // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
1975                         // By Bruce, 2008-01-16.
1976                         //
1977                         case eRfSleep:
1978                         case eRfOff:
1979                                 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
1980                                                 break;
1981 #ifdef NOT_YET
1982                                 // Make sure BusyQueue is empty befor turn off RFE pwoer.
1983                                 for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
1984                                 {
1985                                         if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID]))
1986                                         {
1987                                                 QueueID++;
1988                                                 continue;
1989                                         }
1990                                         else
1991                                         {
1992                                                 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1993                                                 udelay(10);
1994                                                 i++;
1995                                         }
1996
1997                                         if(i >= MAX_DOZE_WAITING_TIMES_9x)
1998                                         {
1999                                                 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
2000                                                 break;
2001                                         }
2002                                 }
2003 #endif
2004                                 //
2005                                 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
2006                                 // Added by Bruce, 2008-11-22.
2007                                 //
2008                                 //==================================================================
2009                                 // (0) Disable FW BB reset checking
2010                                 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
2011
2012                                 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
2013                                 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
2014                                 u1bTmp |= BIT0;
2015                                 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
2016
2017                                 write_nic_byte(dev, SPS1_CTRL, 0x0);
2018                                 write_nic_byte(dev, TXPAUSE, 0xFF);
2019
2020                                 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
2021                                 write_nic_word(dev, CMDR, 0x77FC);
2022                                 write_nic_byte(dev, PHY_CCA, 0x0);
2023                                 udelay(100);
2024
2025                                 write_nic_word(dev, CMDR, 0x37FC);
2026                                 udelay(10);
2027
2028                                 write_nic_word(dev, CMDR, 0x77FC);
2029                                 udelay(10);
2030
2031                                 // (3) Reset BB TRX blocks
2032                                 write_nic_word(dev, CMDR, 0x57FC);
2033                                 break;
2034
2035                         default:
2036                                 bResult = FALSE;
2037                                 //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState));
2038                                 break;
2039                 }
2040                 break;
2041
2042         }
2043         priv->ieee80211->eRFPowerState = eRFPowerState;
2044 #ifdef TO_DO_LIST
2045         if(bResult)
2046         {
2047                 // Update current RF state variable.
2048                 priv->ieee80211->eRFPowerState = eRFPowerState;
2049
2050                 switch(priv->rf_chip )
2051                 {
2052                         case RF_8256:
2053                         switch(priv->ieee80211->eRFPowerState)
2054                         {
2055                                 case eRfOff:
2056                                         //
2057                                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
2058                                         //
2059                                         if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
2060                                         {
2061                                                 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
2062                                         }
2063                                         else
2064                                         {
2065                                                 // Turn off LED if RF is not ON.
2066                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
2067                                         }
2068                                         break;
2069
2070                                 case eRfOn:
2071                                         // Turn on RF we are still linked, which might happen when
2072                                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
2073                                         if( pMgntInfo->bMediaConnect == TRUE )
2074                                         {
2075                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
2076                                         }
2077                                         else
2078                                         {
2079                                                 // Turn off LED if RF is not ON.
2080                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
2081                                         }
2082                                         break;
2083
2084                                 default:
2085                                         // do nothing.
2086                                         break;
2087                         }// Switch RF state
2088
2089                                 break;
2090
2091                         default:
2092                                 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
2093                                 break;
2094                 }// Switch rf_chip
2095         }
2096 #endif
2097         priv->SetRFPowerStateInProgress = FALSE;
2098
2099         return bResult;
2100 }
2101
2102 /*-----------------------------------------------------------------------------
2103  * Function:    GetTxPowerLevel8190()
2104  *
2105  * Overview:    This function is export to "common" moudule
2106  *
2107  * Input:       PADAPTER                Adapter
2108  *                      psByte                  Power Level
2109  *
2110  * Output:      NONE
2111  *
2112  * Return:      NONE
2113  *
2114  *---------------------------------------------------------------------------*/
2115  // no use temp
2116  void
2117 PHY_GetTxPowerLevel8192S(
2118         struct net_device* dev,
2119          long*                  powerlevel
2120         )
2121 {
2122         struct r8192_priv *priv = ieee80211_priv(dev);
2123         u8                      TxPwrLevel = 0;
2124         long                    TxPwrDbm;
2125         //
2126         // Because the Tx power indexes are different, we report the maximum of them to
2127         // meet the CCX TPC request. By Bruce, 2008-01-31.
2128         //
2129
2130         // CCK
2131         TxPwrLevel = priv->CurrentCckTxPwrIdx;
2132         TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
2133
2134         // Legacy OFDM
2135         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
2136
2137         // Compare with Legacy OFDM Tx power.
2138         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
2139                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
2140
2141         // HT OFDM
2142         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
2143
2144         // Compare with HT OFDM Tx power.
2145         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
2146                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
2147
2148         *powerlevel = TxPwrDbm;
2149 }
2150
2151 /*-----------------------------------------------------------------------------
2152  * Function:    SetTxPowerLevel8190()
2153  *
2154  * Overview:    This function is export to "HalCommon" moudule
2155  *
2156  * Input:       PADAPTER                Adapter
2157  *                      u1Byte          channel
2158  *
2159  * Output:      NONE
2160  *
2161  * Return:      NONE
2162  *      2008/11/04      MHC             We remove EEPROM_93C56.
2163  *                                              We need to move CCX relative code to independet file.
2164 *       2009/01/21      MHC             Support new EEPROM format from SD3 requirement.
2165   *---------------------------------------------------------------------------*/
2166  void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8       channel)
2167 {
2168         struct r8192_priv *priv = ieee80211_priv(dev);
2169         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(dev);
2170         u8      powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
2171         s8      ant_pwr_diff = 0;
2172         u32     u4RegValue;
2173         u8      index = (channel -1);
2174         // 2009/01/22 MH Add for new EEPROM format from SD3
2175         u8      pwrdiff[2] = {0};
2176         u8      ht20pwr[2] = {0}, ht40pwr[2] = {0};
2177         u8      rfpath = 0, rfpathnum = 2;
2178
2179         if(priv->bTXPowerDataReadFromEEPORM == FALSE)
2180                 return;
2181
2182         //
2183         // Read predefined TX power index in EEPROM
2184         //
2185 //      if(priv->epromtype == EPROM_93c46)
2186         {
2187                 //
2188                 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
2189                 // Power must be calculated by the antenna diff.
2190                 // So we have to rewrite Antenna gain offset register here.
2191                 // Please refer to BB register 0x80c
2192                 // 1. For CCK.
2193                 // 2. For OFDM 1T or 2T
2194                 //
2195
2196                 // 1. CCK
2197                 powerlevel = priv->RfTxPwrLevelCck[0][index];
2198
2199                 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
2200                 {
2201                 // Read HT 40 OFDM TX power
2202                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
2203                 // RF B HT OFDM pwr-RFA HT OFDM pwr
2204                 // Only one RF we need not to decide B <-> A pwr diff
2205
2206                 // Legacy<->HT pwr diff, we only care about path A.
2207
2208                 // We only assume 1T as RF path A
2209                 rfpathnum = 1;
2210                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
2211                 }
2212                 else if (priv->rf_type == RF_2T2R)
2213                 {
2214                 // Read HT 40 OFDM TX power
2215                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
2216                         // RF B HT OFDM pwr-RFA HT OFDM pwr
2217                 ant_pwr_diff =  priv->RfTxPwrLevelOfdm2T[1][index] -
2218                                                 priv->RfTxPwrLevelOfdm2T[0][index];
2219                         // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
2220                 // We can not handle Path B&A HT/Legacy pwr diff for 92S now.
2221
2222                 //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
2223                 //channel, priv->RfTxPwrLevelOfdm2T[0][index],
2224                 //priv->RfTxPwrLevelOfdm2T[1][index],
2225                 //priv->RfTxPwrLevelOfdm2T[0][index],
2226                 //priv->RfTxPwrLevelOfdm2T[1][index]));
2227
2228                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
2229                 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
2230         }
2231
2232         //
2233         // 2009/01/21 MH Support new EEPROM format from SD3 requirement
2234         // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
2235         //
2236         if (priv->EEPROMVersion == 2)   // Defined by SD1 Jong
2237         {
2238                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2239                 {
2240                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2241                         {
2242                                 // HT 20<->40 pwr diff
2243                                 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
2244
2245                                 // Calculate Antenna pwr diff
2246                                 if (pwrdiff[rfpath] < 8)        // 0~+7
2247                                 {
2248                                 #if 0//cosa, it doesn't need to add the offset here
2249                                         if (rfpath == 0)
2250                                                 powerlevelOFDM24G += pwrdiff[rfpath];
2251                                 #endif
2252                                         ht20pwr[rfpath] += pwrdiff[rfpath];
2253                                 }
2254                                 else                            // index8-15=-8~-1
2255                                 {
2256                                 #if 0//cosa, it doesn't need to add the offset here
2257                                         if (rfpath == 0)
2258                                                 powerlevelOFDM24G -= (15-pwrdiff[rfpath]);
2259                                 #endif
2260                                         ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
2261                                 }
2262                         }
2263
2264                         // RF B HT OFDM pwr-RFA HT OFDM pwr
2265                         if (priv->rf_type == RF_2T2R)
2266                                 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2267
2268                         //RTPRINT(FPHY, PHY_TXPWR,
2269                         //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2270                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2271                 }
2272
2273                 // Band Edge scheme is enabled for FCC mode
2274                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
2275                 {
2276                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2277                         {
2278                                 pwrdiff[rfpath] = 0;
2279                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2280                                 {
2281                                         if (channel <= 3)
2282                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
2283                                         else if (channel >= 9)
2284                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
2285                                         else
2286                                                 pwrdiff[rfpath] = 0;
2287
2288                                         ht40pwr[rfpath] -= pwrdiff[rfpath];
2289                                 }
2290                                 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2291                                 {
2292                                         if (channel == 1)
2293                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
2294                                         else if (channel >= 11)
2295                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
2296                                         else
2297                                                 pwrdiff[rfpath] = 0;
2298
2299                                         ht20pwr[rfpath] -= pwrdiff[rfpath];
2300                                 }
2301                         #if 0//cosa, it doesn't need to add the offset here
2302                                 if (rfpath == 0)
2303                                         powerlevelOFDM24G -= pwrdiff[rfpath];
2304                         #endif
2305                         }
2306
2307                         if (priv->rf_type == RF_2T2R)
2308                         {
2309                                 // HT 20/40 must decide if they need to minus  BD pwr offset
2310                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2311                                         ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
2312                                 else
2313                                         ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2314                         }
2315                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2316                         {
2317                                 if (channel <= 1 || channel >= 11)
2318                                 {
2319                                         //RTPRINT(FPHY, PHY_TXPWR,
2320                                         //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2321                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2322                                 }
2323                         }
2324                         else
2325                         {
2326                                 if (channel <= 3 || channel >= 9)
2327                                 {
2328                                         //RTPRINT(FPHY, PHY_TXPWR,
2329                                         //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2330                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
2331                                 }
2332                         }
2333                 }
2334 #if 0//cosa, useless
2335                 // Read HT/Legacy OFDM diff
2336                 legacy_ant_pwr_diff= pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][index];
2337 #endif
2338                 }
2339
2340         //Cosa added for protection, the reg rFPGA0_TxGainStage
2341         // range is from 7~-8, index = 0x0~0xf
2342         if(ant_pwr_diff > 7)
2343                 ant_pwr_diff = 7;
2344         if(ant_pwr_diff < -8)
2345                 ant_pwr_diff = -8;
2346
2347                 //RTPRINT(FPHY, PHY_TXPWR,
2348                 //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
2349                 //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
2350
2351                 ant_pwr_diff &= 0xf;
2352
2353                 // Antenna TX power difference
2354                 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2355                 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
2356                 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);          // RF-B
2357
2358                 // Antenna gain offset from B/C/D to A
2359                 u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
2360                                                 priv->AntennaTxPwDiff[1]<<4 |
2361                                                 priv->AntennaTxPwDiff[0]        );
2362
2363                 // Notify Tx power difference for B/C/D to A!!!
2364                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2365         }
2366
2367         //
2368         // CCX 2 S31, AP control of client transmit power:
2369         // 1. We shall not exceed Cell Power Limit as possible as we can.
2370         // 2. Tolerance is +/- 5dB.
2371         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2372         //
2373         // TODO:
2374         // 1. 802.11h power contraint
2375         //
2376         // 071011, by rcnjko.
2377         //
2378 #ifdef TODO //WB, 11h has not implemented now.
2379         if(     priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
2380                 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
2381         {
2382                 u8      CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
2383                 u8      LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
2384                 u8      OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
2385
2386                 RT_TRACE(COMP_TXAGC,
2387                 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2388                 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2389                 RT_TRACE(COMP_TXAGC,
2390                 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2391                 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2392
2393                 // CCK
2394                 if(powerlevel > CckCellPwrIdx)
2395                         powerlevel = CckCellPwrIdx;
2396                 // Legacy OFDM, HT OFDM
2397                 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2398                 {
2399                         if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
2400                         {
2401                                 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
2402                         }
2403                         else
2404                         {
2405                                 powerlevelOFDM24G = 0;
2406                         }
2407                 }
2408
2409                 RT_TRACE(COMP_TXAGC,
2410                 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2411                 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2412         }
2413 #endif
2414
2415         priv->CurrentCckTxPwrIdx = powerlevel;
2416         priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2417
2418         switch(priv->rf_chip)
2419         {
2420                 case RF_8225:
2421                         //PHY_SetRF8225CckTxPower(dev, powerlevel);
2422                         //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
2423                 break;
2424
2425                 case RF_8256:
2426 #if 0
2427                         PHY_SetRF8256CCKTxPower(dev, powerlevel);
2428                         PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2429 #endif
2430                         break;
2431
2432                 case RF_6052:
2433                         PHY_RF6052SetCckTxPower(dev, powerlevel);
2434                         PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
2435                         break;
2436
2437                 case RF_8258:
2438                         break;
2439                 default:
2440                         break;
2441         }
2442
2443 }
2444
2445 //
2446 //      Description:
2447 //              Update transmit power level of all channel supported.
2448 //
2449 //      TODO:
2450 //              A mode.
2451 //      By Bruce, 2008-02-04.
2452 //    no use temp
2453 bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
2454 {
2455         struct r8192_priv       *priv = ieee80211_priv(dev);
2456         u8                              idx;
2457         u8                              rf_path;
2458
2459         // TODO: A mode Tx power.
2460         u8      CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
2461         u8      OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
2462
2463         if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
2464                 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
2465         else
2466                 OfdmTxPwrIdx = 0;
2467
2468         for(idx = 0; idx < 14; idx++)
2469         {
2470                 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
2471                 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
2472                 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
2473                 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
2474                 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
2475                 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
2476
2477                 for (rf_path = 0; rf_path < 2; rf_path++)
2478                 {
2479                         priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2480                         priv->RfTxPwrLevelOfdm1T[rf_path][idx] =  \
2481                         priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
2482                 }
2483         }
2484
2485         PHY_SetTxPowerLevel8192S(dev, priv->chan);
2486
2487         return TRUE;
2488 }
2489
2490 /*
2491         Description:
2492                 When beacon interval is changed, the values of the
2493                 hw registers should be modified.
2494         By tynli, 2008.10.24.
2495
2496 */
2497
2498 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
2499 {
2500         u32 NewBeaconNum;
2501
2502         NewBeaconNum = BeaconInterval *32 - 64;
2503         //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum);
2504         //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C);
2505         write_nic_dword(dev, WFM3+4, NewBeaconNum);
2506         write_nic_dword(dev, WFM3, 0xB026007C);
2507 }
2508
2509 //
2510 //      Description:
2511 //              Map dBm into Tx power index according to
2512 //              current HW model, for example, RF and PA, and
2513 //              current wireless mode.
2514 //      By Bruce, 2008-01-29.
2515 //    use in phy only
2516 static u8 phy_DbmToTxPwrIdx(
2517         struct net_device* dev,
2518         WIRELESS_MODE   WirelessMode,
2519         long                    PowerInDbm
2520         )
2521 {
2522         //struct r8192_priv *priv = ieee80211_priv(dev);
2523         u8                              TxPwrIdx = 0;
2524         long                            Offset = 0;
2525
2526
2527         //
2528         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2529         // 3dbm, and OFDM HT equals to 0dbm repectively.
2530         // Note:
2531         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2532         // By Bruce, 2008-01-29.
2533         //
2534         switch(WirelessMode)
2535         {
2536         case WIRELESS_MODE_B:
2537                 Offset = -7;
2538                 break;
2539
2540         case WIRELESS_MODE_G:
2541         case WIRELESS_MODE_N_24G:
2542                 Offset = -8;
2543                 break;
2544         default:
2545                 break;
2546         }
2547
2548         if((PowerInDbm - Offset) > 0)
2549         {
2550                 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
2551         }
2552         else
2553         {
2554                 TxPwrIdx = 0;
2555         }
2556
2557         // Tx Power Index is too large.
2558         if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
2559                 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
2560
2561         return TxPwrIdx;
2562 }
2563 //
2564 //      Description:
2565 //              Map Tx power index into dBm according to
2566 //              current HW model, for example, RF and PA, and
2567 //              current wireless mode.
2568 //      By Bruce, 2008-01-29.
2569 //    use in phy only
2570 static long phy_TxPwrIdxToDbm(
2571         struct net_device* dev,
2572         WIRELESS_MODE   WirelessMode,
2573         u8                      TxPwrIdx
2574         )
2575 {
2576         //struct r8192_priv *priv = ieee80211_priv(dev);
2577         long                            Offset = 0;
2578         long                            PwrOutDbm = 0;
2579
2580         //
2581         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2582         // 3dbm, and OFDM HT equals to 0dbm repectively.
2583         // Note:
2584         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2585         // By Bruce, 2008-01-29.
2586         //
2587         switch(WirelessMode)
2588         {
2589         case WIRELESS_MODE_B:
2590                 Offset = -7;
2591                 break;
2592
2593         case WIRELESS_MODE_G:
2594         case WIRELESS_MODE_N_24G:
2595                 Offset = -8;
2596                 break;
2597         default:
2598                 break;
2599         }
2600
2601         PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
2602
2603         return PwrOutDbm;
2604 }
2605
2606 #ifdef TO_DO_LIST
2607 extern  VOID
2608 PHY_ScanOperationBackup8192S(
2609         IN      PADAPTER        Adapter,
2610         IN      u1Byte          Operation
2611         )
2612 {
2613
2614         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(Adapter);
2615         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
2616         u4Byte                          BitMask;
2617         u1Byte                          initial_gain;
2618
2619
2620
2621
2622
2623         if(!Adapter->bDriverStopped)
2624         {
2625                 switch(Operation)
2626                 {
2627                         case SCAN_OPT_BACKUP:
2628                                 //
2629                                 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
2630                                 // and resume both two DMs while scan complete.
2631                                 // 2008.11.27.
2632                                 //
2633                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
2634                                 break;
2635
2636                         case SCAN_OPT_RESTORE:
2637                                 //
2638                                 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
2639                                 // recover earlier DIG settings.
2640                                 // 2008.11.27.
2641                                 //
2642                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
2643                                 break;
2644
2645                         default:
2646                                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
2647                                 break;
2648                 }
2649         }
2650 }
2651 #endif
2652
2653 //nouse temp
2654 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation   )
2655 {
2656
2657         //struct r8192_priv *priv = ieee80211_priv(dev);
2658         //u32                                   BitMask;
2659         //u8                                    initial_gain;
2660
2661 #if 0   // For 8192s test disable
2662         if(!dev->bDriverStopped)
2663         {
2664                 switch(Operation)
2665                 {
2666                         case IG_Backup:
2667                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Backup, backup the initial gain.\n"));
2668                                 initial_gain = priv->DefaultInitialGain[0];
2669                                 BitMask = bMaskByte0;
2670                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
2671                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8);      // FW DIG OFF
2672                                 pMgntInfo->InitGain_Backup.XAAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
2673                                 pMgntInfo->InitGain_Backup.XBAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
2674                                 pMgntInfo->InitGain_Backup.XCAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
2675                                 pMgntInfo->InitGain_Backup.XDAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
2676                                 BitMask  = bMaskByte2;
2677                                 pMgntInfo->InitGain_Backup.CCA          = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
2678
2679                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
2680                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
2681                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
2682                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
2683                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
2684
2685                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Write scan initial gain = 0x%x \n", initial_gain));
2686                                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
2687                                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
2688                                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
2689                                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
2690                                 break;
2691                         case IG_Restore:
2692                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Restore, restore the initial gain.\n"));
2693                                 BitMask = 0x7f; //Bit0~ Bit6
2694                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
2695                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8);      // FW DIG OFF
2696
2697                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XAAGCCore1);
2698                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XBAGCCore1);
2699                                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XCAGCCore1);
2700                                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XDAGCCore1);
2701                                 BitMask  = (BIT22|BIT23);
2702                                 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)pMgntInfo->InitGain_Backup.CCA);
2703
2704                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
2705                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
2706                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
2707                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
2708                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
2709
2710                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
2711                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x1);      // FW DIG ON
2712                                 break;
2713                         default:
2714                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown IG Operation. \n"));
2715                                 break;
2716                 }
2717         }
2718 #endif
2719 }
2720
2721 /*-----------------------------------------------------------------------------
2722  * Function:    SetBWModeCallback8190Pci()
2723  *
2724  * Overview:    Timer callback function for SetSetBWMode
2725  *
2726  * Input:               PRT_TIMER               pTimer
2727  *
2728  * Output:      NONE
2729  *
2730  * Return:      NONE
2731  *
2732  * Note:                (1) We do not take j mode into consideration now
2733  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
2734  *                           concurrently?
2735  *---------------------------------------------------------------------------*/
2736 //    use in phy only (in win it's timer)
2737 void PHY_SetBWModeCallback8192S(struct net_device *dev)
2738 {
2739         struct r8192_priv *priv = ieee80211_priv(dev);
2740         u8                              regBwOpMode;
2741
2742         //return;
2743
2744         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2745         //u32                           NowL, NowH;
2746         //u8Byte                                BeginTime, EndTime;
2747         u8                              regRRSR_RSC;
2748
2749         RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
2750                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
2751
2752         if(priv->rf_chip == RF_PSEUDO_11N)
2753         {
2754                 priv->SetBWModeInProgress= FALSE;
2755                 return;
2756         }
2757
2758         if(!priv->up)
2759                 return;
2760
2761         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2762         //NowL = read_nic_dword(dev, TSFR);
2763         //NowH = read_nic_dword(dev, TSFR+4);
2764         //BeginTime = ((u8Byte)NowH << 32) + NowL;
2765
2766         //3//
2767         //3//<1>Set MAC register
2768         //3//
2769         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
2770         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
2771
2772         switch(priv->CurrentChannelBW)
2773         {
2774                 case HT_CHANNEL_WIDTH_20:
2775                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
2776                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2777
2778                         regBwOpMode |= BW_OPMODE_20MHZ;
2779                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2780                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2781                         break;
2782
2783                 case HT_CHANNEL_WIDTH_20_40:
2784                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
2785                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2786
2787                         regBwOpMode &= ~BW_OPMODE_20MHZ;
2788                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2789                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2790                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
2791                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
2792                         break;
2793
2794                 default:
2795                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\
2796                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
2797                         break;
2798         }
2799
2800         //3//
2801         //3//<2>Set PHY related register
2802         //3//
2803         switch(priv->CurrentChannelBW)
2804         {
2805                 /* 20 MHz channel*/
2806                 case HT_CHANNEL_WIDTH_20:
2807                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
2808                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
2809
2810                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2811                         // It is set in Tx descriptor for 8192x series
2812                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
2813                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
2814                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
2815                         #if 0 //LZM 090219
2816                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
2817                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
2818                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
2819                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
2820                         #endif
2821
2822                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
2823                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2824
2825
2826                         break;
2827
2828                 /* 40 MHz channel*/
2829                 case HT_CHANNEL_WIDTH_20_40:
2830                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
2831                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
2832
2833                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2834                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
2835                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
2836                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
2837                         #if 0 //LZM 090219
2838                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
2839                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
2840                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
2841                         #endif
2842
2843                         // Set Control channel to upper or lower. These settings are required only for 40MHz
2844                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2845                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2846
2847                         //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
2848                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
2849                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2850
2851                         break;
2852
2853                 default:
2854                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
2855                                                 ,priv->CurrentChannelBW);
2856                         break;
2857
2858         }
2859         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2860
2861         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2862         //NowL = read_nic_dword(dev, TSFR);
2863         //NowH = read_nic_dword(dev, TSFR+4);
2864         //EndTime = ((u8Byte)NowH << 32) + NowL;
2865         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
2866
2867         //3<3>Set RF related register
2868         switch( priv->rf_chip )
2869         {
2870                 case RF_8225:
2871                         //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
2872                         break;
2873
2874                 case RF_8256:
2875                         // Please implement this function in Hal8190PciPhy8256.c
2876                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
2877                         break;
2878
2879                 case RF_8258:
2880                         // Please implement this function in Hal8190PciPhy8258.c
2881                         // PHY_SetRF8258Bandwidth();
2882                         break;
2883
2884                 case RF_PSEUDO_11N:
2885                         // Do Nothing
2886                         break;
2887
2888                 case RF_6052:
2889                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
2890                         break;
2891                 default:
2892                         printk("Unknown rf_chip: %d\n", priv->rf_chip);
2893                         break;
2894         }
2895
2896         priv->SetBWModeInProgress= FALSE;
2897
2898         RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
2899 }
2900
2901
2902  /*-----------------------------------------------------------------------------
2903  * Function:   SetBWMode8190Pci()
2904  *
2905  * Overview:  This function is export to "HalCommon" moudule
2906  *
2907  * Input:               PADAPTER                        Adapter
2908  *                      HT_CHANNEL_WIDTH        Bandwidth       //20M or 40M
2909  *
2910  * Output:      NONE
2911  *
2912  * Return:      NONE
2913  *
2914  * Note:                We do not take j mode into consideration now
2915  *---------------------------------------------------------------------------*/
2916 //extern void PHY_SetBWMode8192S(       struct net_device* dev,
2917 //      HT_CHANNEL_WIDTH        Bandwidth,      // 20M or 40M
2918 //      HT_EXTCHNL_OFFSET       Offset          // Upper, Lower, or Don't care
2919 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2920 {
2921         struct r8192_priv *priv = ieee80211_priv(dev);
2922         HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
2923
2924
2925         // Modified it for 20/40 mhz switch by guangan 070531
2926
2927         //return;
2928
2929         //if(priv->SwChnlInProgress)
2930 //      if(pMgntInfo->bScanInProgress)
2931 //      {
2932 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n",
2933 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2934 //              return;
2935 //      }
2936
2937 //      if(priv->SetBWModeInProgress)
2938 //      {
2939 //              // Modified it for 20/40 mhz switch by guangan 070531
2940 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n",
2941 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2942 //              PlatformCancelTimer(dev, &priv->SetBWModeTimer);
2943 //              //return;
2944 //      }
2945
2946         if(priv->SetBWModeInProgress)
2947                 return;
2948
2949         priv->SetBWModeInProgress= TRUE;
2950
2951         priv->CurrentChannelBW = Bandwidth;
2952
2953         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2954                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2955         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2956                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2957         else
2958                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2959
2960 #if 0
2961         if(!priv->bDriverStopped)
2962         {
2963 #ifdef USE_WORKITEM
2964                 PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));//SetBWModeCallback8192SUsbWorkItem
2965 #else
2966                 PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);//PHY_SetBWModeCallback8192S
2967 #endif
2968         }
2969 #endif
2970         if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
2971         {
2972 #if   defined(RTL8192SU)
2973         SetBWModeCallback8192SUsbWorkItem(dev);
2974 #endif
2975         }
2976         else
2977         {
2978                 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
2979                 priv->SetBWModeInProgress= FALSE;
2980                 priv->CurrentChannelBW = tmpBW;
2981         }
2982 }
2983
2984 //    use in phy only (in win it's timer)
2985 void PHY_SwChnlCallback8192S(struct net_device *dev)
2986 {
2987
2988         struct r8192_priv *priv = ieee80211_priv(dev);
2989         u32             delay;
2990         //bool                  ret;
2991
2992         RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
2993
2994         if(!priv->up)
2995                 return;
2996
2997         if(priv->rf_chip == RF_PSEUDO_11N)
2998         {
2999                 priv->SwChnlInProgress=FALSE;
3000                 return;                                                                 //return immediately if it is peudo-phy
3001         }
3002
3003         do{
3004                 if(!priv->SwChnlInProgress)
3005                         break;
3006
3007                 //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3008                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3009                 {
3010                         if(delay>0)
3011                         {
3012                                 mdelay(delay);
3013                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3014                                 //mod_timer(&priv->SwChnlTimer,  jiffies + MSECS(delay));
3015                                 //==>PHY_SwChnlCallback8192S(dev); for 92se
3016                                 //==>SwChnlCallback8192SUsb(dev) for 92su
3017                         }
3018                         else
3019                         continue;
3020                 }
3021                 else
3022                 {
3023                         priv->SwChnlInProgress=FALSE;
3024                         break;
3025                 }
3026         }while(true);
3027 }
3028
3029 // Call after initialization
3030 //extern void PHY_SwChnl8192S(struct net_device* dev,   u8 channel)
3031 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
3032 {
3033         struct r8192_priv *priv = ieee80211_priv(dev);
3034         //u8                    tmpchannel =channel;
3035         //bool                  bResult = false;
3036
3037         if(!priv->up)
3038                 return false;
3039
3040         if(priv->SwChnlInProgress)
3041                 return false;
3042
3043         if(priv->SetBWModeInProgress)
3044                 return false;
3045
3046         //--------------------------------------------
3047         switch(priv->ieee80211->mode)
3048         {
3049         case WIRELESS_MODE_A:
3050         case WIRELESS_MODE_N_5G:
3051                 if (channel<=14){
3052                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
3053                         return false;
3054                 }
3055                 break;
3056
3057         case WIRELESS_MODE_B:
3058                 if (channel>14){
3059                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
3060                         return false;
3061                 }
3062                 break;
3063
3064         case WIRELESS_MODE_G:
3065         case WIRELESS_MODE_N_24G:
3066                 if (channel>14){
3067                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
3068                         return false;
3069                 }
3070                 break;
3071
3072         default:
3073                         ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode);
3074                 break;
3075         }
3076         //--------------------------------------------
3077
3078         priv->SwChnlInProgress = TRUE;
3079         if( channel == 0)
3080                 channel = 1;
3081
3082         priv->chan=channel;
3083
3084         priv->SwChnlStage=0;
3085         priv->SwChnlStep=0;
3086
3087         if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
3088         {
3089 #if   defined(RTL8192SU)
3090         SwChnlCallback8192SUsbWorkItem(dev);
3091 #endif
3092 #ifdef TO_DO_LIST
3093         if(bResult)
3094                 {
3095                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
3096                 }
3097                 else
3098                 {
3099                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
3100                         priv->SwChnlInProgress = false;
3101                         priv->CurrentChannel = tmpchannel;
3102                 }
3103 #endif
3104         }
3105         else
3106         {
3107                 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
3108                 priv->SwChnlInProgress = false;
3109                 //priv->CurrentChannel = tmpchannel;
3110         }
3111         return true;
3112 }
3113
3114
3115 //
3116 // Description:
3117 //      Switch channel synchronously. Called by SwChnlByDelayHandler.
3118 //
3119 // Implemented by Bruce, 2008-02-14.
3120 // The following procedure is operted according to SwChanlCallback8190Pci().
3121 // However, this procedure is performed synchronously  which should be running under
3122 // passive level.
3123 //
3124 //not understant it
3125 void PHY_SwChnlPhy8192S(        // Only called during initialize
3126         struct net_device* dev,
3127         u8              channel
3128         )
3129 {
3130         struct r8192_priv *priv = ieee80211_priv(dev);
3131
3132         RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
3133
3134 #ifdef TO_DO_LIST
3135         // Cannot IO.
3136         if(RT_CANNOT_IO(dev))
3137                 return;
3138 #endif
3139
3140         // Channel Switching is in progress.
3141         if(priv->SwChnlInProgress)
3142                 return;
3143
3144         //return immediately if it is peudo-phy
3145         if(priv->rf_chip == RF_PSEUDO_11N)
3146         {
3147                 priv->SwChnlInProgress=FALSE;
3148                 return;
3149         }
3150
3151         priv->SwChnlInProgress = TRUE;
3152         if( channel == 0)
3153                 channel = 1;
3154
3155         priv->chan=channel;
3156
3157         priv->SwChnlStage = 0;
3158         priv->SwChnlStep = 0;
3159
3160         phy_FinishSwChnlNow(dev,channel);
3161
3162         priv->SwChnlInProgress = FALSE;
3163 }
3164
3165 //    use in phy only
3166 static bool
3167 phy_SetSwChnlCmdArray(
3168         SwChnlCmd*              CmdTable,
3169         u32                     CmdTableIdx,
3170         u32                     CmdTableSz,
3171         SwChnlCmdID             CmdID,
3172         u32                     Para1,
3173         u32                     Para2,
3174         u32                     msDelay
3175         )
3176 {
3177         SwChnlCmd* pCmd;
3178
3179         if(CmdTable == NULL)
3180         {
3181                 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
3182                 return FALSE;
3183         }
3184         if(CmdTableIdx >= CmdTableSz)
3185         {
3186                 //RT_ASSERT(FALSE,
3187                         //      ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
3188                                 //CmdTableIdx, CmdTableSz));
3189                 return FALSE;
3190         }
3191
3192         pCmd = CmdTable + CmdTableIdx;
3193         pCmd->CmdID = CmdID;
3194         pCmd->Para1 = Para1;
3195         pCmd->Para2 = Para2;
3196         pCmd->msDelay = msDelay;
3197
3198         return TRUE;
3199 }
3200
3201 //    use in phy only
3202 static bool
3203 phy_SwChnlStepByStep(
3204         struct net_device* dev,
3205         u8              channel,
3206         u8              *stage,
3207         u8              *step,
3208         u32             *delay
3209         )
3210 {
3211         struct r8192_priv *priv = ieee80211_priv(dev);
3212         //PCHANNEL_ACCESS_SETTING       pChnlAccessSetting;
3213         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
3214         u32                                     PreCommonCmdCnt;
3215         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
3216         u32                                     PostCommonCmdCnt;
3217         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
3218         u32                                     RfDependCmdCnt;
3219         SwChnlCmd                               *CurrentCmd = NULL;
3220         u8                                      eRFPath;
3221
3222         //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n"));
3223         //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel));
3224         RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3225         //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
3226         if (!IsLegalChannel(priv->ieee80211, channel))
3227         {
3228                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
3229                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
3230         }
3231
3232         //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
3233         //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
3234
3235         //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
3236         //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3237         //{
3238                 // <1> Fill up pre common command.
3239         PreCommonCmdCnt = 0;
3240         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3241                                 CmdID_SetTxPowerLevel, 0, 0, 0);
3242         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3243                                 CmdID_End, 0, 0, 0);
3244
3245                 // <2> Fill up post common command.
3246         PostCommonCmdCnt = 0;
3247
3248         phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
3249                                 CmdID_End, 0, 0, 0);
3250
3251                 // <3> Fill up RF dependent command.
3252         RfDependCmdCnt = 0;
3253         switch( priv->rf_chip )
3254         {
3255                 case RF_8225:
3256                 if (channel < 1 || channel > 14)
3257                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3258                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3259                 // 2008/09/04 MH Change channel.
3260                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3261                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3262                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3263                 CmdID_End, 0, 0, 0);
3264                 break;
3265
3266         case RF_8256:
3267                 if (channel < 1 || channel > 14)
3268                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3269                 // TEST!! This is not the table for 8256!!
3270                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3271                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3272                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3273                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3274                 CmdID_End, 0, 0, 0);
3275                 break;
3276
3277         case RF_6052:
3278                 if (channel < 1 || channel > 14)
3279                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3280                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3281                         CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
3282                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3283                         CmdID_End, 0, 0, 0);
3284                 break;
3285
3286         case RF_8258:
3287                 break;
3288
3289         default:
3290                 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3291                 return FALSE;
3292                 break;
3293         }
3294
3295
3296         do{
3297                 switch(*stage)
3298                 {
3299                 case 0:
3300                         CurrentCmd=&PreCommonCmd[*step];
3301                         break;
3302                 case 1:
3303                         CurrentCmd=&RfDependCmd[*step];
3304                         break;
3305                 case 2:
3306                         CurrentCmd=&PostCommonCmd[*step];
3307                         break;
3308                 }
3309
3310                 if(CurrentCmd->CmdID==CmdID_End)
3311                 {
3312                         if((*stage)==2)
3313                         {
3314                                 return TRUE;
3315                         }
3316                         else
3317                         {
3318                                 (*stage)++;
3319                                 (*step)=0;
3320                                 continue;
3321                         }
3322                 }
3323
3324                 switch(CurrentCmd->CmdID)
3325                 {
3326                 case CmdID_SetTxPowerLevel:
3327                         //if(priv->card_8192_version > VERSION_8190_BD)
3328                                 PHY_SetTxPowerLevel8192S(dev,channel);
3329                         break;
3330                 case CmdID_WritePortUlong:
3331                         write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
3332                         break;
3333                 case CmdID_WritePortUshort:
3334                         write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
3335                         break;
3336                 case CmdID_WritePortUchar:
3337                         write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
3338                         break;
3339                 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
3340                         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3341                         {
3342 #if defined RTL8192SU
3343                         // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
3344                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
3345                                 //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
3346 #else
3347                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, ((CurrentCmd->Para2)<<7));
3348 #endif
3349                         }
3350                         break;
3351                 default:
3352                         break;
3353                 }
3354
3355                 break;
3356         }while(TRUE);
3357         //cosa }/*for(Number of RF paths)*/
3358
3359         (*delay)=CurrentCmd->msDelay;
3360         (*step)++;
3361         RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3362         return FALSE;
3363 }
3364
3365 //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
3366 //    use in phy only
3367 static void
3368 phy_FinishSwChnlNow(    // We should not call this function directly
3369         struct net_device* dev,
3370         u8              channel
3371                 )
3372 {
3373         struct r8192_priv       *priv = ieee80211_priv(dev);
3374         u32                     delay;
3375
3376         while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
3377         {
3378                 if(delay>0)
3379                         mdelay(delay);
3380                 if(!priv->up)
3381                         break;
3382         }
3383 }
3384
3385
3386 /*-----------------------------------------------------------------------------
3387  * Function:    PHYCheckIsLegalRfPath8190Pci()
3388  *
3389  * Overview:    Check different RF type to execute legal judgement. If RF Path is illegal
3390  *                      We will return false.
3391  *
3392  * Input:               NONE
3393  *
3394  * Output:              NONE
3395  *
3396  * Return:              NONE
3397  *
3398  * Revised History:
3399  *      When            Who             Remark
3400  *      11/15/2007      MHC             Create Version 0.
3401  *
3402  *---------------------------------------------------------------------------*/
3403  //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb
3404 //extern        bool
3405 //PHY_CheckIsLegalRfPath8192S(
3406 //      struct net_device* dev,
3407 //      u32     eRFPath)
3408 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
3409 {
3410 //      struct r8192_priv *priv = ieee80211_priv(dev);
3411         bool                            rtValue = TRUE;
3412
3413         // NOt check RF Path now.!
3414 #if 0
3415         if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3416         {
3417                 rtValue = FALSE;
3418         }
3419         if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3420         {
3421
3422         }
3423 #endif
3424         return  rtValue;
3425
3426 }       /* PHY_CheckIsLegalRfPath8192S */
3427
3428
3429
3430 /*-----------------------------------------------------------------------------
3431  * Function:    PHY_IQCalibrate8192S()
3432  *
3433  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3434  *                      to improve RF EVM!!?
3435  *
3436  * Input:               IN      PADAPTER        pAdapter
3437  *
3438  * Output:              NONE
3439  *
3440  * Return:              NONE
3441  *
3442  * Revised History:
3443  *      When            Who             Remark
3444  *      10/07/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3445  *
3446  *---------------------------------------------------------------------------*/
3447  //called by InitializeAdapter8192SE
3448 void
3449 PHY_IQCalibrate(        struct net_device* dev)
3450 {
3451         //struct r8192_priv     *priv = ieee80211_priv(dev);
3452         u32                             i, reg;
3453         u32                             old_value;
3454         long                            X, Y, TX0[4];
3455         u32                             TXA[4];
3456
3457         // 1. Check QFN68 or 64 92S (Read from EEPROM)
3458
3459         //
3460         // 2. QFN 68
3461         //
3462         // For 1T2R IQK only now !!!
3463         for (i = 0; i < 10; i++)
3464         {
3465                 // IQK
3466                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3467                 //PlatformStallExecution(5);
3468                 udelay(5);
3469                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3470                 udelay(5);
3471                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3472                 udelay(5);
3473                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
3474                 udelay(5);
3475                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
3476                 udelay(5);
3477                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3478                 udelay(5);
3479                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
3480                 udelay(5);
3481                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
3482                 udelay(5);
3483                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
3484                 udelay(5);
3485                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
3486                 udelay(5);
3487                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
3488                 udelay(2000);
3489                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3490                 udelay(5);
3491                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3492                 udelay(5);
3493                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3494
3495
3496                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3497
3498                 // Readback IQK value and rewrite
3499                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3500                 {
3501                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3502
3503                         // Calibrate init gain for A path for TX0
3504                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3505                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3506                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3507                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3508                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3509                         udelay(5);
3510
3511                         // Calibrate init gain for C path for TX0
3512                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3513                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3514                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3515                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3516                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3517                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3518                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3519                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3520                         udelay(5);
3521
3522                         // Calibrate RX A and B for RX0
3523                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3524                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3525                         reg = (reg & 0xFFFFFC00) |X;
3526                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3527                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3528                         reg = (reg & 0xFFFF03FF) |Y<<10;
3529                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3530                         udelay(5);
3531                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3532
3533                         // Calibrate init gain for A path for TX1 !!!!!!
3534                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3535                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3536                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3537                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3538                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3539                         udelay(5);
3540
3541                         // Calibrate init gain for C path for TX1
3542                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3543                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3544                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3545                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3546                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3547                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3548                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3549                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3550                         udelay(5);
3551
3552                         // Calibrate RX A and B for RX1
3553                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3554                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3555                         reg = (reg & 0xFFFFFC00) |X;
3556                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3557
3558                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3559                         reg = (reg & 0xFFFF03FF) |Y<<10;
3560                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3561                         udelay(5);
3562
3563                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3564                         break;
3565                 }
3566
3567         }
3568
3569
3570         //
3571         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3572         //
3573
3574
3575 }
3576
3577 /*-----------------------------------------------------------------------------
3578  * Function:    PHY_IQCalibrateBcut()
3579  *
3580  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3581  *                      to improve RF EVM!!?
3582  *
3583  * Input:               IN      PADAPTER        pAdapter
3584  *
3585  * Output:              NONE
3586  *
3587  * Return:              NONE
3588  *
3589  * Revised History:
3590  *      When            Who             Remark
3591  *      11/18/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3592  *                                              92S B-cut QFN 68 pin IQ calibration procedure.doc
3593  *
3594  *---------------------------------------------------------------------------*/
3595 extern void PHY_IQCalibrateBcut(struct net_device* dev)
3596 {
3597         //struct r8192_priv     *priv = ieee80211_priv(dev);
3598         //PMGNT_INFO            pMgntInfo = &pAdapter->MgntInfo;
3599         u32                             i, reg;
3600         u32                             old_value;
3601         long                            X, Y, TX0[4];
3602         u32                             TXA[4];
3603         u32                             calibrate_set[13] = {0};
3604         u32                             load_value[13];
3605         u8                              RfPiEnable=0;
3606
3607         // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
3608
3609         //
3610         // 1. Save e70~ee0 register setting, and load calibration setting
3611         //
3612         /*
3613         0xee0[31:0]=0x3fed92fb;
3614         0xedc[31:0] =0x3fed92fb;
3615         0xe70[31:0] =0x3fed92fb;
3616         0xe74[31:0] =0x3fed92fb;
3617         0xe78[31:0] =0x3fed92fb;
3618         0xe7c[31:0]= 0x3fed92fb;
3619         0xe80[31:0]= 0x3fed92fb;
3620         0xe84[31:0]= 0x3fed92fb;
3621         0xe88[31:0]= 0x3fed92fb;
3622         0xe8c[31:0]= 0x3fed92fb;
3623         0xed0[31:0]= 0x3fed92fb;
3624         0xed4[31:0]= 0x3fed92fb;
3625         0xed8[31:0]= 0x3fed92fb;
3626         */
3627         calibrate_set [0] = 0xee0;
3628         calibrate_set [1] = 0xedc;
3629         calibrate_set [2] = 0xe70;
3630         calibrate_set [3] = 0xe74;
3631         calibrate_set [4] = 0xe78;
3632         calibrate_set [5] = 0xe7c;
3633         calibrate_set [6] = 0xe80;
3634         calibrate_set [7] = 0xe84;
3635         calibrate_set [8] = 0xe88;
3636         calibrate_set [9] = 0xe8c;
3637         calibrate_set [10] = 0xed0;
3638         calibrate_set [11] = 0xed4;
3639         calibrate_set [12] = 0xed8;
3640         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n"));
3641         for (i = 0; i < 13; i++)
3642         {
3643                 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
3644                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
3645
3646         }
3647
3648         RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
3649
3650         //
3651         // 2. QFN 68
3652         //
3653         // For 1T2R IQK only now !!!
3654         for (i = 0; i < 10; i++)
3655         {
3656                 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
3657                 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
3658                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
3659                 {
3660                         //DbgPrint("IQK Switch to PI mode\n");
3661                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
3662                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
3663                 }
3664
3665                 // IQK
3666                 // 2. IQ calibration & LO leakage calibration
3667                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3668                 udelay(5);
3669                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3670                 udelay(5);
3671                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3672                 udelay(5);
3673                 //path-A IQ K and LO K gain setting
3674                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
3675                 udelay(5);
3676                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
3677                 udelay(5);
3678                 //set LO calibration
3679                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3680                 udelay(5);
3681                 //path-B IQ K and LO K gain setting
3682                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
3683                 udelay(5);
3684                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
3685                 udelay(5);
3686                 //K idac_I & IQ
3687                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
3688                 udelay(5);
3689                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
3690                 udelay(5);
3691
3692                 // delay 2ms
3693                 udelay(2000);
3694
3695                 //idac_Q setting
3696                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
3697                 udelay(5);
3698                 //K idac_Q & IQ
3699                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
3700                 udelay(5);
3701                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
3702
3703                 // delay 2ms
3704                 udelay(2000);
3705
3706                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3707                 udelay(5);
3708                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3709                 udelay(5);
3710                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3711
3712                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
3713                 {
3714                         //DbgPrint("IQK Switch back to SI mode\n");
3715                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
3716                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
3717                 }
3718
3719
3720                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3721
3722                 // 3.   check fail bit, and fill BB IQ matrix
3723                 // Readback IQK value and rewrite
3724                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3725                 {
3726                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3727
3728                         // Calibrate init gain for A path for TX0
3729                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3730                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3731                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3732                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3733                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3734                         udelay(5);
3735
3736                         // Calibrate init gain for C path for TX0
3737                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3738                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3739                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3740                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3741                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3742                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3743                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3744                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3745                         udelay(5);
3746
3747                         // Calibrate RX A and B for RX0
3748                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3749                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3750                         reg = (reg & 0xFFFFFC00) |X;
3751                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3752                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3753                         reg = (reg & 0xFFFF03FF) |Y<<10;
3754                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3755                         udelay(5);
3756                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3757
3758                         // Calibrate init gain for A path for TX1 !!!!!!
3759                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3760                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3761                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3762                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3763                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3764                         udelay(5);
3765
3766                         // Calibrate init gain for C path for TX1
3767                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3768                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3769                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3770                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3771                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3772                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3773                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3774                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3775                         udelay(5);
3776
3777                         // Calibrate RX A and B for RX1
3778                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3779                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3780                         reg = (reg & 0xFFFFFC00) |X;
3781                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3782
3783                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3784                         reg = (reg & 0xFFFF03FF) |Y<<10;
3785                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3786                         udelay(5);
3787
3788                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3789                         break;
3790                 }
3791
3792         }
3793
3794         //
3795         // 4. Reload e70~ee0 register setting.
3796         //
3797         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n"));
3798         for (i = 0; i < 13; i++)
3799                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
3800
3801
3802         //
3803         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3804         //
3805
3806
3807
3808 }       // PHY_IQCalibrateBcut
3809
3810
3811 //
3812 // Move from phycfg.c to gen.c to be code independent later
3813 //
3814 //-------------------------Move to other DIR later----------------------------*/
3815 //#if (DEV_BUS_TYPE == USB_INTERFACE)
3816 #ifdef RTL8192SU
3817
3818 //    use in phy only (in win it's timer)
3819 void SwChnlCallback8192SUsb(struct net_device *dev)
3820 {
3821
3822         struct r8192_priv *priv = ieee80211_priv(dev);
3823         u32                     delay;
3824 //      bool                    ret;
3825
3826         RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\
3827                                 %d\n", priv->chan);
3828
3829
3830         if(!priv->up)
3831                 return;
3832
3833         if(priv->rf_chip == RF_PSEUDO_11N)
3834         {
3835                 priv->SwChnlInProgress=FALSE;
3836                 return;                                                                 //return immediately if it is peudo-phy
3837         }
3838
3839         do{
3840                 if(!priv->SwChnlInProgress)
3841                         break;
3842
3843                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3844                 {
3845                         if(delay>0)
3846                         {
3847                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3848
3849                         }
3850                         else
3851                         continue;
3852                 }
3853                 else
3854                 {
3855                         priv->SwChnlInProgress=FALSE;
3856                 }
3857                 break;
3858         }while(TRUE);
3859 }
3860
3861
3862 //
3863 // Callback routine of the work item for switch channel.
3864 //
3865 //    use in phy only (in win it's work)
3866 void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
3867 {
3868         struct r8192_priv *priv = ieee80211_priv(dev);
3869
3870         RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
3871 #ifdef TO_DO_LIST
3872         if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
3873         {
3874                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
3875
3876                 pHalData->SwChnlInProgress = FALSE;
3877                 return;
3878         }
3879 #endif
3880         phy_FinishSwChnlNow(dev, priv->chan);
3881         priv->SwChnlInProgress = FALSE;
3882
3883         RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
3884 }
3885
3886
3887 /*-----------------------------------------------------------------------------
3888  * Function:    SetBWModeCallback8192SUsb()
3889  *
3890  * Overview:    Timer callback function for SetSetBWMode
3891  *
3892  * Input:               PRT_TIMER               pTimer
3893  *
3894  * Output:      NONE
3895  *
3896  * Return:      NONE
3897  *
3898  * Note:                (1) We do not take j mode into consideration now
3899  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3900  *                           concurrently?
3901  *---------------------------------------------------------------------------*/
3902 //====>//rtl8192_SetBWMode
3903 //    use in phy only (in win it's timer)
3904 void SetBWModeCallback8192SUsb(struct net_device *dev)
3905 {
3906         struct r8192_priv *priv = ieee80211_priv(dev);
3907         u8                              regBwOpMode;
3908
3909         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3910         //u32                           NowL, NowH;
3911         //u8Byte                                BeginTime, EndTime;
3912         u8                              regRRSR_RSC;
3913
3914         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
3915                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3916
3917         if(priv->rf_chip == RF_PSEUDO_11N)
3918         {
3919                 priv->SetBWModeInProgress= FALSE;
3920                 return;
3921         }
3922
3923         if(!priv->up)
3924                 return;
3925
3926         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3927         //NowL = read_nic_dword(dev, TSFR);
3928         //NowH = read_nic_dword(dev, TSFR+4);
3929         //BeginTime = ((u8Byte)NowH << 32) + NowL;
3930
3931         //3<1>Set MAC register
3932         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3933         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3934
3935         switch(priv->CurrentChannelBW)
3936         {
3937                 case HT_CHANNEL_WIDTH_20:
3938                         regBwOpMode |= BW_OPMODE_20MHZ;
3939                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3940                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3941                         break;
3942
3943                 case HT_CHANNEL_WIDTH_20_40:
3944                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3945                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3946                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3947
3948                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3949                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3950                         break;
3951
3952                 default:
3953                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\
3954                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3955                         break;
3956         }
3957
3958         //3 <2>Set PHY related register
3959         switch(priv->CurrentChannelBW)
3960         {
3961                 case HT_CHANNEL_WIDTH_20:
3962                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3963                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3964                         #if 0 //LZM090219
3965                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3966
3967                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
3968                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3969                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3970                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3971                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
3972                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
3973                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
3974                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3975                         #endif
3976
3977                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3978                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3979
3980                         break;
3981                 case HT_CHANNEL_WIDTH_20_40:
3982                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3983                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3984                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3985                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3986
3987                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3988                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
3989                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
3990                         //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409);
3991                         //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3992
3993                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3994                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3995
3996                         break;
3997                 default:
3998                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
3999                                                 ,priv->CurrentChannelBW);
4000                         break;
4001
4002         }
4003         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4004
4005         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4006         //NowL = read_nic_dword(dev, TSFR);
4007         //NowH = read_nic_dword(dev, TSFR+4);
4008         //EndTime = ((u8Byte)NowH << 32) + NowL;
4009         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
4010
4011 #if 1
4012         //3<3>Set RF related register
4013         switch( priv->rf_chip )
4014         {
4015                 case RF_8225:
4016                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4017                         break;
4018
4019                 case RF_8256:
4020                         // Please implement this function in Hal8190PciPhy8256.c
4021                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4022                         break;
4023
4024                 case RF_6052:
4025                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4026                         break;
4027
4028                 case RF_8258:
4029                         // Please implement this function in Hal8190PciPhy8258.c
4030                         // PHY_SetRF8258Bandwidth();
4031                         break;
4032
4033                 case RF_PSEUDO_11N:
4034                         // Do Nothing
4035                         break;
4036
4037                 default:
4038                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4039                         break;
4040         }
4041 #endif
4042         priv->SetBWModeInProgress= FALSE;
4043
4044         RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
4045 }
4046
4047 //
4048 // Callback routine of the work item for set bandwidth mode.
4049 //
4050 //    use in phy only (in win it's work)
4051 void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
4052 {
4053         struct r8192_priv               *priv = ieee80211_priv(dev);
4054         u8                              regBwOpMode;
4055
4056         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4057         //u32                           NowL, NowH;
4058         //u8Byte                                BeginTime, EndTime;
4059         u8                      regRRSR_RSC;
4060
4061         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem()  Switch to %s bandwidth\n", \
4062                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4063
4064         if(priv->rf_chip == RF_PSEUDO_11N)
4065         {
4066                 priv->SetBWModeInProgress= FALSE;
4067                 return;
4068         }
4069
4070         if(!priv->up)
4071                 return;
4072
4073         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4074         //NowL = read_nic_dword(dev, TSFR);
4075         //NowH = read_nic_dword(dev, TSFR+4);
4076         //BeginTime = ((u8Byte)NowH << 32) + NowL;
4077
4078         //3<1>Set MAC register
4079         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4080         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4081
4082         switch(priv->CurrentChannelBW)
4083         {
4084                 case HT_CHANNEL_WIDTH_20:
4085                         regBwOpMode |= BW_OPMODE_20MHZ;
4086                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4087                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4088                         break;
4089
4090                 case HT_CHANNEL_WIDTH_20_40:
4091                         regBwOpMode &= ~BW_OPMODE_20MHZ;
4092                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4093                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4094                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4095                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4096
4097                         break;
4098
4099                 default:
4100                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\
4101                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4102                         break;
4103         }
4104
4105         //3 <2>Set PHY related register
4106         switch(priv->CurrentChannelBW)
4107         {
4108                 case HT_CHANNEL_WIDTH_20:
4109                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4110                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4111
4112                         #if 0 //LZM 090219
4113                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
4114
4115                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4116                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4117                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4118                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4119                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
4120                         #endif
4121
4122                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4123
4124                         break;
4125                 case HT_CHANNEL_WIDTH_20_40:
4126                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4127                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4128                         #if 0 //LZM 090219
4129                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4130
4131                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4132
4133                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4134                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4135                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4136                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4137                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4138                         #endif
4139
4140                         // Set Control channel to upper or lower. These settings are required only for 40MHz
4141                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4142                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4143
4144                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4145
4146                         break;
4147
4148
4149                 default:
4150                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
4151                                                 ,priv->CurrentChannelBW);
4152                         break;
4153
4154         }
4155         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4156
4157         //3<3>Set RF related register
4158         switch( priv->rf_chip )
4159         {
4160                 case RF_8225:
4161                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4162                         break;
4163
4164                 case RF_8256:
4165                         // Please implement this function in Hal8190PciPhy8256.c
4166                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4167                         break;
4168
4169                 case RF_6052:
4170                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4171                         break;
4172
4173                 case RF_8258:
4174                         // Please implement this function in Hal8190PciPhy8258.c
4175                         // PHY_SetRF8258Bandwidth();
4176                         break;
4177
4178                 case RF_PSEUDO_11N:
4179                         // Do Nothing
4180                         break;
4181
4182                 default:
4183                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4184                         break;
4185         }
4186
4187         priv->SetBWModeInProgress= FALSE;
4188
4189         RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
4190 }
4191
4192 //--------------------------Move to oter DIR later-------------------------------*/
4193 #ifdef RTL8192SU
4194 void InitialGain8192S(struct net_device *dev,   u8 Operation)
4195 {
4196 #ifdef TO_DO_LIST
4197         struct r8192_priv *priv = ieee80211_priv(dev);
4198 #endif
4199
4200 }
4201 #endif
4202
4203 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
4204 {
4205         struct r8192_priv *priv = ieee80211_priv(dev);
4206
4207         priv->InitialGainOperateType = Operation;
4208
4209         if(priv->up)
4210         {
4211                 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
4212         }
4213 }
4214
4215 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
4216 {
4217         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4218        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
4219        struct net_device *dev = priv->ieee80211->dev;
4220 #define SCAN_RX_INITIAL_GAIN    0x17
4221 #define POWER_DETECTION_TH      0x08
4222         u32     BitMask;
4223         u8      initial_gain;
4224         u8      Operation;
4225
4226         Operation = priv->InitialGainOperateType;
4227
4228         switch(Operation)
4229         {
4230                 case IG_Backup:
4231                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
4232                         initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
4233                         BitMask = bMaskByte0;
4234                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4235                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
4236                         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
4237                         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
4238                         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
4239                         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
4240                         BitMask  = bMaskByte2;
4241                         priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
4242
4243                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4244                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4245                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4246                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4247                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
4248
4249                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
4250                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
4251                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
4252                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
4253                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
4254                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
4255                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
4256                         break;
4257                 case IG_Restore:
4258                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
4259                         BitMask = 0x7f; //Bit0~ Bit6
4260                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4261                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
4262
4263                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
4264                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
4265                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
4266                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
4267                         BitMask  = bMaskByte2;
4268                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
4269
4270                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4271                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4272                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4273                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4274                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
4275
4276                         PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
4277
4278                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4279                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
4280                         break;
4281                 default:
4282                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
4283                         break;
4284         }
4285 }
4286
4287 #endif  // #if (DEV_BUS_TYPE == USB_INTERFACE)
4288
4289 //-----------------------------------------------------------------------------
4290 //      Description:
4291 //              Schedule workitem to send specific CMD IO to FW.
4292 //      Added by Roger, 2008.12.03.
4293 //
4294 //-----------------------------------------------------------------------------
4295 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE    FwCmdIO)
4296 {
4297         struct r8192_priv *priv = ieee80211_priv(dev);
4298         u16     FwCmdWaitCounter = 0;
4299
4300         u16     FwCmdWaitLimit = 1000;
4301
4302         //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest)
4303         if(priv->bInHctTest)
4304                 return true;
4305
4306         RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
4307
4308         // Will be done by high power respectively.
4309         if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
4310         {
4311                 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
4312                 return false;
4313         }
4314
4315 #if 1
4316         while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
4317         {
4318                 //if(RT_USB_CANNOT_IO(Adapter))
4319                 //{
4320                 //      RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n"));
4321                 //      return FALSE;
4322                 //}
4323
4324                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
4325                 return false;
4326                 FwCmdWaitCounter ++;
4327                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
4328                 udelay(100);
4329         }
4330
4331         if(FwCmdWaitCounter == FwCmdWaitLimit)
4332         {
4333                 //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n"));
4334                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
4335                 //return false;
4336         }
4337 #endif
4338         if (priv->SetFwCmdInProgress)
4339         {
4340                 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
4341                 return false;
4342         }
4343         priv->SetFwCmdInProgress = TRUE;
4344         priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
4345
4346         phy_SetFwCmdIOCallback(dev);
4347         return true;
4348 }
4349 void ChkFwCmdIoDone(struct net_device* dev)
4350 {
4351         u16 PollingCnt = 1000;
4352         u32 tmpValue;
4353
4354         do
4355         {// Make sure that CMD IO has be accepted by FW.
4356 #ifdef TO_DO_LIST
4357                 if(RT_USB_CANNOT_IO(Adapter))
4358                 {
4359                         RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
4360                         return;
4361                 }
4362 #endif
4363                 udelay(10); // sleep 20us
4364                 tmpValue = read_nic_dword(dev, WFM5);
4365                 if(tmpValue == 0)
4366                 {
4367                         RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
4368                         break;
4369                 }
4370                 else
4371                 {
4372                         RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
4373                 }
4374         }while( --PollingCnt );
4375
4376         if(PollingCnt == 0)
4377         {
4378                 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
4379         }
4380 }
4381 //      Callback routine of the timer callback for FW Cmd IO.
4382 //
4383 //      Description:
4384 //              This routine will send specific CMD IO to FW and check whether it is done.
4385 //
4386 void phy_SetFwCmdIOCallback(struct net_device* dev)
4387 {
4388         //struct net_device* dev = (struct net_device*) data;
4389         u32             input;
4390         static u32 ScanRegister;
4391         struct r8192_priv *priv = ieee80211_priv(dev);
4392         if(!priv->up)
4393         {
4394                 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
4395                 return;
4396         }
4397
4398         RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
4399
4400         switch(priv->CurrentFwCmdIO)
4401         {
4402                 case FW_CMD_HIGH_PWR_ENABLE:
4403                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4404                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
4405                         break;
4406
4407                 case FW_CMD_HIGH_PWR_DISABLE:
4408                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
4409                         break;
4410
4411                 case FW_CMD_DIG_RESUME:
4412                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4413                         break;
4414
4415                 case FW_CMD_DIG_HALT:
4416                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4417                         break;
4418
4419                 //
4420                 // <Roger_Notes> The following FW CMD IO was combined into single operation
4421                 // (i.e., to prevent number of system workitem out of resource!!).
4422                 // 2008.12.04.
4423                 //
4424                 case FW_CMD_RESUME_DM_BY_SCAN:
4425                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
4426                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4427                         {
4428                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
4429                                 ChkFwCmdIoDone(dev);
4430                         }
4431                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4432                         break;
4433
4434                 case FW_CMD_PAUSE_DM_BY_SCAN:
4435                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
4436                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
4437                         ChkFwCmdIoDone(dev);
4438                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4439                         break;
4440
4441                 //
4442                 // <Roger_Notes> The following FW CMD IO should be checked
4443                 // (i.e., workitem schedule timing issue!!).
4444                 // 2008.12.04.
4445                 //
4446                 case FW_CMD_DIG_DISABLE:
4447                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
4448                         write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
4449                         break;
4450
4451                 case FW_CMD_DIG_ENABLE:
4452                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
4453                         write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
4454                         break;
4455
4456                 case FW_CMD_RA_RESET:
4457                         write_nic_dword(dev, WFM5, FW_RA_RESET);
4458                         break;
4459
4460                 case FW_CMD_RA_ACTIVE:
4461                         write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
4462                         break;
4463
4464                 case FW_CMD_RA_REFRESH_N:
4465                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
4466                         if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
4467                                 input = FW_RA_REFRESH;
4468                         else
4469                                 input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
4470                         write_nic_dword(dev, WFM5, input);
4471                         break;
4472                 case FW_CMD_RA_REFRESH_BG:
4473                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
4474                         write_nic_dword(dev, WFM5, FW_RA_REFRESH);
4475                         ChkFwCmdIoDone(dev);
4476                         write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
4477                         break;
4478
4479                 case FW_CMD_IQK_ENABLE:
4480                         write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
4481                         break;
4482
4483                 case FW_CMD_TXPWR_TRACK_ENABLE:
4484                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
4485                         break;
4486
4487                 case FW_CMD_TXPWR_TRACK_DISABLE:
4488                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
4489                         break;
4490
4491                 default:
4492                         RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
4493                         break;
4494         }
4495
4496         ChkFwCmdIoDone(dev);
4497
4498         switch(priv->CurrentFwCmdIO)
4499         {
4500                 case FW_CMD_HIGH_PWR_DISABLE:
4501                         //if(pMgntInfo->bTurboScan)
4502                         {
4503                                 //Lower initial gain
4504                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
4505                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
4506                                 // CCA threshold
4507                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
4508                                 // Disable OFDM Part
4509                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
4510                                 ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
4511                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
4512                                 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
4513                         }
4514                         break;
4515
4516                 case FW_CMD_HIGH_PWR_ENABLE:
4517                         //if(pMgntInfo->bTurboScan)
4518                         {
4519                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
4520                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
4521
4522                                 // CCA threshold
4523                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
4524                                 // Enable OFDM Part
4525                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
4526
4527                                 //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
4528                                 if(ScanRegister != 0){
4529                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
4530                                 }
4531
4532                                 if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
4533                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
4534                                 else
4535                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
4536                         }
4537                         break;
4538         }
4539
4540         priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
4541         RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
4542
4543 }
4544