1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
19 #ifndef __INC_FIRMWARE_H
20 #define __INC_FIRMWARE_H
23 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
24 #define MAX_FIRMWARE_CODE_SIZE 0xFF00 // Firmware Local buffer size.
25 #define RTL8190_CPU_START_OFFSET 0x80
26 #define RTL8192S_FW_PKT_FRAG_SIZE 0x4000
27 #define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
31 typedef enum _firmware_init_step{
32 FW_INIT_STEP0_IMEM = 0,
33 FW_INIT_STEP1_MAIN = 1,
34 FW_INIT_STEP2_DATA = 2,
35 }firmware_init_step_e;
37 typedef enum _firmware_init_step{
38 FW_INIT_STEP0_BOOT = 0,
39 FW_INIT_STEP1_MAIN = 1,
40 FW_INIT_STEP2_DATA = 2,
41 }firmware_init_step_e;
44 /* due to rtl8192 firmware */
45 typedef enum _desc_packet_type_e{
46 DESC_PACKET_TYPE_INIT = 0,
47 DESC_PACKET_TYPE_NORMAL = 1,
50 typedef enum _opt_rst_type{
52 OPT_FIRMWARE_RESET = 1,
55 //--------------------------------------------------------------------------------
56 // RTL8192S Firmware related
57 //--------------------------------------------------------------------------------
58 typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
60 //--- long word 0 ----
61 u8 signature_0; //0x12: CE product, 0x92: IT product
62 u8 signature_1; //0x87: CE product, 0x81: IT product
63 u8 hci_sel; //0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP, 0x12: 72S-U, 03:SDIO
64 u8 chip_version; //the same value as reigster value
65 u8 customer_ID_0; //customer ID low byte
66 u8 customer_ID_1; //customer ID high byte
67 u8 rf_config; //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
68 u8 usb_ep_num; // 4: 4EP, 6: 6EP, 11: 11EP
70 //--- long word 1 ----
71 u8 regulatory_class_0; //regulatory class bit map 0
72 u8 regulatory_class_1; //regulatory class bit map 1
73 u8 regulatory_class_2; //regulatory class bit map 2
74 u8 regulatory_class_3; //regulatory class bit map 3
75 u8 rfintfs; // 0:SWSI, 1:HWSI, 2:HWPI
81 //--- long word 2 ----
82 u8 lbk_mode; //0x00: normal, 0x03: MACLBK, 0x01: PHYLBK
83 u8 mp_mode; // 1: for MP use, 0: for normal driver (to be discussed)
91 //--- long word 3 ----
92 u8 qos_en; // QoS enable
93 u8 bw_40MHz_en; // 40MHz BW enable
94 u8 AMSDU2AMPDU_en; // 4181 convert AMSDU to AMPDU, 0: disable
95 u8 AMPDU_en; // 11n AMPDU enable
96 u8 rate_control_offload;//FW offloads, 0: driver handles
97 u8 aggregation_offload; // FW offloads, 0: driver handles
102 //--- long word 4 ----
103 unsigned char beacon_offload; // 1. FW offloads, 0: driver handles
104 unsigned char MLME_offload; // 2. FW offloads, 0: driver handles
105 unsigned char hwpc_offload; // 3. FW offloads, 0: driver handles
106 unsigned char tcp_checksum_offload; // 4. FW offloads, 0: driver handles
107 unsigned char tcp_offload; // 5. FW offloads, 0: driver handles
108 unsigned char ps_control_offload; // 6. FW offloads, 0: driver handles
109 unsigned char WWLAN_offload; // 7. FW offloads, 0: driver handles
110 unsigned char rsvd040;
112 //--- long word 5 ----
113 u8 tcp_tx_frame_len_L; //tcp tx packet length low byte
114 u8 tcp_tx_frame_len_H; //tcp tx packet length high byte
115 u8 tcp_rx_frame_len_L; //tcp rx packet length low byte
116 u8 tcp_rx_frame_len_H; //tcp rx packet length high byte
121 }RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
123 typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
125 //--- LONG WORD 0 ----
127 u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
128 u32 DMEMSize; //define the size of boot loader
131 //--- LONG WORD 1 ----
132 u32 IMG_IMEM_SIZE; //define the size of FW in IMEM
133 u32 IMG_SRAM_SIZE; //define the size of FW in SRAM
135 //--- LONG WORD 2 ----
136 u32 FW_PRIV_SIZE; //define the size of DMEM variable
139 //--- LONG WORD 3 ----
143 RT_8192S_FIRMWARE_PRIV FWPriv;
145 }RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
147 #define RT_8192S_FIRMWARE_HDR_SIZE 80
148 #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
150 typedef enum _FIRMWARE_8192S_STATUS{
152 FW_STATUS_LOAD_IMEM = 1,
153 FW_STATUS_LOAD_EMEM = 2,
154 FW_STATUS_LOAD_DMEM = 3,
156 }FIRMWARE_8192S_STATUS;
158 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
160 typedef struct _rt_firmware{
161 PRT_8192S_FIRMWARE_HDR pFwHeader;
162 FIRMWARE_8192S_STATUS FWStatus;
163 u8 FwIMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
164 u8 FwEMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
167 u8 szFwTmpBuffer[164000];
168 u32 szFwTmpBufferLen;
169 u16 CmdPacketFragThresold;
171 }rt_firmware, *prt_firmware;
173 #define FW_DIG_ENABLE_CTL BIT0
174 #define FW_HIGH_PWR_ENABLE_CTL BIT1
175 #define FW_SS_CTL BIT2
176 #define FW_RA_INIT_CTL BIT3
177 #define FW_RA_BG_CTL BIT4
178 #define FW_RA_N_CTL BIT5
179 #define FW_PWR_TRK_CTL BIT6
180 #define FW_IQK_CTL BIT7
181 #define FW_ANTENNA_SW BIT8
182 #define FW_DISABLE_ALL_DM 0
184 #define FW_PWR_TRK_PARAM_CLR 0x0000ffff
185 #define FW_RA_PARAM_CLR 0xffff0000
187 #define FW_CMD_IO_CLR(_pdev, _Bit) \
189 ((struct r8192_priv *)ieee80211_priv(_pdev))->FwCmdIOMap &= (~_Bit);
191 #define FW_CMD_IO_UPDATE(_pdev, _val) \
192 ((struct r8192_priv *)ieee80211_priv(_pdev))->FwCmdIOMap = _val;
194 #define FW_CMD_IO_SET(_pdev, _val) \
195 write_nic_word(_pdev, LBUS_MON_ADDR, (u16)_val); \
196 FW_CMD_IO_UPDATE(_pdev, _val);
198 #define FW_CMD_PARA_SET(_pdev, _val) \
199 write_nic_dword(_pdev, LBUS_ADDR_MASK, _val); \
200 ((struct r8192_priv *)ieee80211_priv(_pdev))->FwCmdIOParam = _val;
202 #define FW_CMD_IO_QUERY(_pdev) (u16)(((struct r8192_priv *)ieee80211_priv(_pdev))->FwCmdIOMap)
203 #define FW_CMD_IO_PARA_QUERY(_pdev) (u32)(((struct r8192_priv *)ieee80211_priv(_pdev))->FwCmdIOParam)
207 bool FirmwareDownload92S(struct net_device *dev);