1 #ifndef _R819XU_PHYREG_H
2 #define _R819XU_PHYREG_H
5 #define RF_DATA 0x1d4 // FW will write RF data in the register.
7 //Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
9 #define rPMAC_Reset 0x100
10 #define rPMAC_TxStart 0x104
11 #define rPMAC_TxLegacySIG 0x108
12 #define rPMAC_TxHTSIG1 0x10c
13 #define rPMAC_TxHTSIG2 0x110
14 #define rPMAC_PHYDebug 0x114
15 #define rPMAC_TxPacketNum 0x118
16 #define rPMAC_TxIdle 0x11c
17 #define rPMAC_TxMACHeader0 0x120
18 #define rPMAC_TxMACHeader1 0x124
19 #define rPMAC_TxMACHeader2 0x128
20 #define rPMAC_TxMACHeader3 0x12c
21 #define rPMAC_TxMACHeader4 0x130
22 #define rPMAC_TxMACHeader5 0x134
23 #define rPMAC_TxDataType 0x138
24 #define rPMAC_TxRandomSeed 0x13c
25 #define rPMAC_CCKPLCPPreamble 0x140
26 #define rPMAC_CCKPLCPHeader 0x144
27 #define rPMAC_CCKCRC16 0x148
28 #define rPMAC_OFDMRxCRC32OK 0x170
29 #define rPMAC_OFDMRxCRC32Er 0x174
30 #define rPMAC_OFDMRxParityEr 0x178
31 #define rPMAC_OFDMRxCRC8Er 0x17c
32 #define rPMAC_CCKCRxRC16Er 0x180
33 #define rPMAC_CCKCRxRC32Er 0x184
34 #define rPMAC_CCKCRxRC32OK 0x188
35 #define rPMAC_TxStatus 0x18c
38 #define MCS_TXAGC 0x340 // MCS AGC
39 #define CCK_TXAGC 0x348 // CCK AGC
41 #define MacBlkCtrl 0x403 // Mac block on/off control register
44 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC
45 #define rFPGA0_TxInfo 0x804
46 #define rFPGA0_PSDFunction 0x808
47 #define rFPGA0_TxGainStage 0x80c
48 #define rFPGA0_RFTiming1 0x810
49 #define rFPGA0_RFTiming2 0x814
50 //#define rFPGA0_XC_RFTiming 0x818
51 //#define rFPGA0_XD_RFTiming 0x81c
52 #define rFPGA0_XA_HSSIParameter1 0x820
53 #define rFPGA0_XA_HSSIParameter2 0x824
54 #define rFPGA0_XB_HSSIParameter1 0x828
55 #define rFPGA0_XB_HSSIParameter2 0x82c
56 #define rFPGA0_XC_HSSIParameter1 0x830
57 #define rFPGA0_XC_HSSIParameter2 0x834
58 #define rFPGA0_XD_HSSIParameter1 0x838
59 #define rFPGA0_XD_HSSIParameter2 0x83c
60 #define rFPGA0_XA_LSSIParameter 0x840
61 #define rFPGA0_XB_LSSIParameter 0x844
62 #define rFPGA0_XC_LSSIParameter 0x848
63 #define rFPGA0_XD_LSSIParameter 0x84c
64 #define rFPGA0_RFWakeUpParameter 0x850
65 #define rFPGA0_RFSleepUpParameter 0x854
66 #define rFPGA0_XAB_SwitchControl 0x858
67 #define rFPGA0_XCD_SwitchControl 0x85c
68 #define rFPGA0_XA_RFInterfaceOE 0x860
69 #define rFPGA0_XB_RFInterfaceOE 0x864
70 #define rFPGA0_XC_RFInterfaceOE 0x868
71 #define rFPGA0_XD_RFInterfaceOE 0x86c
72 #define rFPGA0_XAB_RFInterfaceSW 0x870
73 #define rFPGA0_XCD_RFInterfaceSW 0x874
74 #define rFPGA0_XAB_RFParameter 0x878
75 #define rFPGA0_XCD_RFParameter 0x87c
76 #define rFPGA0_AnalogParameter1 0x880
77 #define rFPGA0_AnalogParameter2 0x884
78 #define rFPGA0_AnalogParameter3 0x888
79 #define rFPGA0_AnalogParameter4 0x88c
80 #define rFPGA0_XA_LSSIReadBack 0x8a0
81 #define rFPGA0_XB_LSSIReadBack 0x8a4
82 #define rFPGA0_XC_LSSIReadBack 0x8a8
83 #define rFPGA0_XD_LSSIReadBack 0x8ac
84 #define rFPGA0_PSDReport 0x8b4
85 #define rFPGA0_XAB_RFInterfaceRB 0x8e0
86 #define rFPGA0_XCD_RFInterfaceRB 0x8e4
89 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC
90 #define rFPGA1_TxBlock 0x904
91 #define rFPGA1_DebugSelect 0x908
92 #define rFPGA1_TxInfo 0x90c
95 #define rCCK0_System 0xa00
96 #define rCCK0_AFESetting 0xa04
97 #define rCCK0_CCA 0xa08
98 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level
99 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC
100 #define rCCK0_RxHP 0xa14
101 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
102 #define rCCK0_DSPParameter2 0xa1c //SQ threshold
103 #define rCCK0_TxFilter1 0xa20
104 #define rCCK0_TxFilter2 0xa24
105 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
106 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d
107 #define rCCK0_TRSSIReport 0xa50
108 #define rCCK0_RxReport 0xa54 //0xa57
109 #define rCCK0_FACounterLower 0xa5c //0xa5b
110 #define rCCK0_FACounterUpper 0xa58 //0xa5c
113 #define rOFDM0_LSTF 0xc00
114 #define rOFDM0_TRxPathEnable 0xc04
115 #define rOFDM0_TRMuxPar 0xc08
116 #define rOFDM0_TRSWIsolation 0xc0c
117 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
118 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
119 #define rOFDM0_XBRxAFE 0xc18
120 #define rOFDM0_XBRxIQImbalance 0xc1c
121 #define rOFDM0_XCRxAFE 0xc20
122 #define rOFDM0_XCRxIQImbalance 0xc24
123 #define rOFDM0_XDRxAFE 0xc28
124 #define rOFDM0_XDRxIQImbalance 0xc2c
125 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD
126 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
127 #define rOFDM0_RxDetector3 0xc38 //Frame Sync.
128 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
129 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path
130 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
131 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
132 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA
133 #define rOFDM0_XAAGCCore1 0xc50
134 #define rOFDM0_XAAGCCore2 0xc54
135 #define rOFDM0_XBAGCCore1 0xc58
136 #define rOFDM0_XBAGCCore2 0xc5c
137 #define rOFDM0_XCAGCCore1 0xc60
138 #define rOFDM0_XCAGCCore2 0xc64
139 #define rOFDM0_XDAGCCore1 0xc68
140 #define rOFDM0_XDAGCCore2 0xc6c
141 #define rOFDM0_AGCParameter1 0xc70
142 #define rOFDM0_AGCParameter2 0xc74
143 #define rOFDM0_AGCRSSITable 0xc78
144 #define rOFDM0_HTSTFAGC 0xc7c
145 #define rOFDM0_XATxIQImbalance 0xc80
146 #define rOFDM0_XATxAFE 0xc84
147 #define rOFDM0_XBTxIQImbalance 0xc88
148 #define rOFDM0_XBTxAFE 0xc8c
149 #define rOFDM0_XCTxIQImbalance 0xc90
150 #define rOFDM0_XCTxAFE 0xc94
151 #define rOFDM0_XDTxIQImbalance 0xc98
152 #define rOFDM0_XDTxAFE 0xc9c
153 #define rOFDM0_RxHPParameter 0xce0
154 #define rOFDM0_TxPseudoNoiseWgt 0xce4
155 #define rOFDM0_FrameSync 0xcf0
156 #define rOFDM0_DFSReport 0xcf4
157 #define rOFDM0_TxCoeff1 0xca4
158 #define rOFDM0_TxCoeff2 0xca8
159 #define rOFDM0_TxCoeff3 0xcac
160 #define rOFDM0_TxCoeff4 0xcb0
161 #define rOFDM0_TxCoeff5 0xcb4
162 #define rOFDM0_TxCoeff6 0xcb8
166 #define rOFDM1_LSTF 0xd00
167 #define rOFDM1_TRxPathEnable 0xd04
168 #define rOFDM1_CFO 0xd08
169 #define rOFDM1_CSI1 0xd10
170 #define rOFDM1_SBD 0xd14
171 #define rOFDM1_CSI2 0xd18
172 #define rOFDM1_CFOTracking 0xd2c
173 #define rOFDM1_TRxMesaure1 0xd34
174 #define rOFDM1_IntfDet 0xd3c
175 #define rOFDM1_PseudoNoiseStateAB 0xd50
176 #define rOFDM1_PseudoNoiseStateCD 0xd54
177 #define rOFDM1_RxPseudoNoiseWgt 0xd58
178 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail
179 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
180 #define rOFDM_PHYCounter3 0xda8 //MCS not support
181 #define rOFDM_ShortCFOAB 0xdac
182 #define rOFDM_ShortCFOCD 0xdb0
183 #define rOFDM_LongCFOAB 0xdb4
184 #define rOFDM_LongCFOCD 0xdb8
185 #define rOFDM_TailCFOAB 0xdbc
186 #define rOFDM_TailCFOCD 0xdc0
187 #define rOFDM_PWMeasure1 0xdc4
188 #define rOFDM_PWMeasure2 0xdc8
189 #define rOFDM_BWReport 0xdcc
190 #define rOFDM_AGCReport 0xdd0
191 #define rOFDM_RxSNR 0xdd4
192 #define rOFDM_RxEVMCSI 0xdd8
193 #define rOFDM_SIGReport 0xddc
196 #define rTxAGC_Rate18_06 0xe00
197 #define rTxAGC_Rate54_24 0xe04
198 #define rTxAGC_CCK_Mcs32 0xe08
199 #define rTxAGC_Mcs03_Mcs00 0xe10
200 #define rTxAGC_Mcs07_Mcs04 0xe14
201 #define rTxAGC_Mcs11_Mcs08 0xe18
202 #define rTxAGC_Mcs15_Mcs12 0xe1c
207 #define rZebra1_HSSIEnable 0x0
208 #define rZebra1_TRxEnable1 0x1
209 #define rZebra1_TRxEnable2 0x2
210 #define rZebra1_AGC 0x4
211 #define rZebra1_ChargePump 0x5
212 #define rZebra1_Channel 0x7
213 #define rZebra1_TxGain 0x8
214 #define rZebra1_TxLPF 0x9
215 #define rZebra1_RxLPF 0xb
216 #define rZebra1_RxHPFCorner 0xc
219 #define rGlobalCtrl 0
220 #define rRTL8256_TxLPF 19
221 #define rRTL8256_RxLPF 11
224 #define rRTL8258_TxLPF 0x11
225 #define rRTL8258_RxLPF 0x13
226 #define rRTL8258_RSSILPF 0xa
230 #define bBBResetB 0x100
231 #define bGlobalResetB 0x200
232 #define bOFDMTxStart 0x4
233 #define bCCKTxStart 0x8
234 #define bCRC32Debug 0x100
235 #define bPMACLoopback 0x10
236 #define bTxLSIG 0xffffff
237 #define bOFDMTxRate 0xf
238 #define bOFDMTxReserved 0x10
239 #define bOFDMTxLength 0x1ffe0
240 #define bOFDMTxParity 0x20000
241 #define bTxHTSIG1 0xffffff
242 #define bTxHTMCSRate 0x7f
244 #define bTxHTLength 0xffff00
245 #define bTxHTSIG2 0xffffff
246 #define bTxHTSmoothing 0x1
247 #define bTxHTSounding 0x2
248 #define bTxHTReserved 0x4
249 #define bTxHTAggreation 0x8
250 #define bTxHTSTBC 0x30
251 #define bTxHTAdvanceCoding 0x40
252 #define bTxHTShortGI 0x80
253 #define bTxHTNumberHT_LTF 0x300
254 #define bTxHTCRC8 0x3fc00
255 #define bCounterReset 0x10000
256 #define bNumOfOFDMTx 0xffff
257 #define bNumOfCCKTx 0xffff0000
258 #define bTxIdleInterval 0xffff
259 #define bOFDMService 0xffff0000
260 #define bTxMACHeader 0xffffffff
261 #define bTxDataInit 0xff
262 #define bTxHTMode 0x100
263 #define bTxDataType 0x30000
264 #define bTxRandomSeed 0xffffffff
265 #define bCCKTxPreamble 0x1
266 #define bCCKTxSFD 0xffff0000
267 #define bCCKTxSIG 0xff
268 #define bCCKTxService 0xff00
269 #define bCCKLengthExt 0x8000
270 #define bCCKTxLength 0xffff0000
271 #define bCCKTxCRC16 0xffff
272 #define bCCKTxStatus 0x1
273 #define bOFDMTxStatus 0x2
277 #define bJapanMode 0x2
278 #define bCCKTxSC 0x30
279 #define bCCKEn 0x1000000
280 #define bOFDMEn 0x2000000
281 #define bOFDMRxADCPhase 0x10000
282 #define bOFDMTxDACPhase 0x40000
283 #define bXATxAGC 0x3f
284 #define bXBTxAGC 0xf00
285 #define bXCTxAGC 0xf000
286 #define bXDTxAGC 0xf0000
287 #define bPAStart 0xf0000000
288 #define bTRStart 0x00f00000
289 #define bRFStart 0x0000f000
290 #define bBBStart 0x000000f0
291 #define bBBCCKStart 0x0000000f
292 #define bPAEnd 0xf //Reg0x814
293 #define bTREnd 0x0f000000
294 #define bRFEnd 0x000f0000
295 #define bCCAMask 0x000000f0 //T2R
296 #define bR2RCCAMask 0x00000f00
297 #define bHSSI_R2TDelay 0xf8000000
298 #define bHSSI_T2RDelay 0xf80000
299 #define bContTxHSSI 0x400 //channel gain at continue Tx
300 #define bIGFromCCK 0x200
301 #define bAGCAddress 0x3f
302 #define bRxHPTx 0x7000
303 #define bRxHPT2R 0x38000
304 #define bRxHPCCKIni 0xc0000
305 #define bAGCTxCode 0xc00000
306 #define bAGCRxCode 0x300000
307 #define b3WireDataLength 0x800
308 #define b3WireAddressLength 0x400
309 #define b3WireRFPowerDown 0x1
310 //#define bHWSISelect 0x8
311 #define b5GPAPEPolarity 0x40000000
312 #define b2GPAPEPolarity 0x80000000
313 #define bRFSW_TxDefaultAnt 0x3
314 #define bRFSW_TxOptionAnt 0x30
315 #define bRFSW_RxDefaultAnt 0x300
316 #define bRFSW_RxOptionAnt 0x3000
317 #define bRFSI_3WireData 0x1
318 #define bRFSI_3WireClock 0x2
319 #define bRFSI_3WireLoad 0x4
320 #define bRFSI_3WireRW 0x8
321 #define bRFSI_3Wire 0xf //3-wire total control
322 #define bRFSI_RFENV 0x10
323 #define bRFSI_TRSW 0x20
324 #define bRFSI_TRSWB 0x40
325 #define bRFSI_ANTSW 0x100
326 #define bRFSI_ANTSWB 0x200
327 #define bRFSI_PAPE 0x400
328 #define bRFSI_PAPE5G 0x800
329 #define bBandSelect 0x1
330 #define bHTSIG2_GI 0x80
331 #define bHTSIG2_Smoothing 0x01
332 #define bHTSIG2_Sounding 0x02
333 #define bHTSIG2_Aggreaton 0x08
334 #define bHTSIG2_STBC 0x30
335 #define bHTSIG2_AdvCoding 0x40
336 #define bHTSIG2_NumOfHTLTF 0x300
337 #define bHTSIG2_CRC8 0x3fc
338 #define bHTSIG1_MCS 0x7f
339 #define bHTSIG1_BandWidth 0x80
340 #define bHTSIG1_HTLength 0xffff
341 #define bLSIG_Rate 0xf
342 #define bLSIG_Reserved 0x10
343 #define bLSIG_Length 0x1fffe
344 #define bLSIG_Parity 0x20
345 #define bCCKRxPhase 0x4
346 #define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address
347 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
348 #define bLSSIReadBackData 0xfff
349 #define bLSSIReadOKFlag 0x1000
350 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
352 #define bRegulator0Standby 0x1
353 #define bRegulatorPLLStandby 0x2
354 #define bRegulator1Standby 0x4
355 #define bPLLPowerUp 0x8
356 #define bDPLLPowerUp 0x10
357 #define bDA10PowerUp 0x20
358 #define bAD7PowerUp 0x200
359 #define bDA6PowerUp 0x2000
360 #define bXtalPowerUp 0x4000
361 #define b40MDClkPowerUP 0x8000
362 #define bDA6DebugMode 0x20000
363 #define bDA6Swing 0x380000
364 #define bADClkPhase 0x4000000
365 #define b80MClkDelay 0x18000000
366 #define bAFEWatchDogEnable 0x20000000
367 #define bXtalCap 0x0f000000
368 #define bXtalCap01 0xc0000000
369 #define bXtalCap23 0x3
370 #define bXtalCap92x 0x0f000000
371 #define bIntDifClkEnable 0x400
372 #define bExtSigClkEnable 0x800
373 #define bBandgapMbiasPowerUp 0x10000
374 #define bAD11SHGain 0xc0000
375 #define bAD11InputRange 0x700000
376 #define bAD11OPCurrent 0x3800000
377 #define bIPathLoopback 0x4000000
378 #define bQPathLoopback 0x8000000
379 #define bAFELoopback 0x10000000
380 #define bDA10Swing 0x7e0
381 #define bDA10Reverse 0x800
382 #define bDAClkSource 0x1000
383 #define bAD7InputRange 0x6000
384 #define bAD7Gain 0x38000
385 #define bAD7OutputCMMode 0x40000
386 #define bAD7InputCMMode 0x380000
387 #define bAD7Current 0xc00000
388 #define bRegulatorAdjust 0x7000000
389 #define bAD11PowerUpAtTx 0x1
390 #define bDA10PSAtTx 0x10
391 #define bAD11PowerUpAtRx 0x100
392 #define bDA10PSAtRx 0x1000
394 #define bCCKRxAGCFormat 0x200
396 #define bPSDFFTSamplepPoint 0xc000
397 #define bPSDAverageNum 0x3000
398 #define bIQPathControl 0xc00
399 #define bPSDFreq 0x3ff
400 #define bPSDAntennaPath 0x30
401 #define bPSDIQSwitch 0x40
402 #define bPSDRxTrigger 0x400000
403 #define bPSDTxTrigger 0x80000000
404 #define bPSDSineToneScale 0x7f000000
405 #define bPSDReport 0xffff
408 #define bOFDMTxSC 0x30000000
410 #define bOFDMTxOn 0x2
411 #define bDebugPage 0xfff //reset debug page and also HWord, LWord
412 #define bDebugItem 0xff //reset debug page and LWord
414 #define bAntNonHT 0x100
415 #define bAntHT1 0x1000
416 #define bAntHT2 0x10000
417 #define bAntHT1S1 0x100000
418 #define bAntNonHTS1 0x1000000
421 #define bCCKBBMode 0x3
422 #define bCCKTxPowerSaving 0x80
423 #define bCCKRxPowerSaving 0x40
424 #define bCCKSideBand 0x10
425 #define bCCKScramble 0x8
426 #define bCCKAntDiversity 0x8000
427 #define bCCKCarrierRecovery 0x4000
428 #define bCCKTxRate 0x3000
429 #define bCCKDCCancel 0x0800
430 #define bCCKISICancel 0x0400
431 #define bCCKMatchFilter 0x0200
432 #define bCCKEqualizer 0x0100
433 #define bCCKPreambleDetect 0x800000
434 #define bCCKFastFalseCCA 0x400000
435 #define bCCKChEstStart 0x300000
436 #define bCCKCCACount 0x080000
437 #define bCCKcs_lim 0x070000
438 #define bCCKBistMode 0x80000000
439 #define bCCKCCAMask 0x40000000
440 #define bCCKTxDACPhase 0x4
441 #define bCCKRxADCPhase 0x20000000 //r_rx_clk
442 #define bCCKr_cp_mode0 0x0100
443 #define bCCKTxDCOffset 0xf0
444 #define bCCKRxDCOffset 0xf
445 #define bCCKCCAMode 0xc000
446 #define bCCKFalseCS_lim 0x3f00
447 #define bCCKCS_ratio 0xc00000
448 #define bCCKCorgBit_sel 0x300000
449 #define bCCKPD_lim 0x0f0000
450 #define bCCKNewCCA 0x80000000
451 #define bCCKRxHPofIG 0x8000
452 #define bCCKRxIG 0x7f00
453 #define bCCKLNAPolarity 0x800000
454 #define bCCKRx1stGain 0x7f0000
455 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
456 #define bCCKRxAGCSatLevel 0x1f000000
457 #define bCCKRxAGCSatCount 0xe0
458 #define bCCKRxRFSettle 0x1f //AGCsamp_dly
459 #define bCCKFixedRxAGC 0x8000
460 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
461 #define bCCKAntennaPolarity 0x2000
462 #define bCCKTxFilterType 0x0c00
463 #define bCCKRxAGCReportType 0x0300
464 #define bCCKRxDAGCEn 0x80000000
465 #define bCCKRxDAGCPeriod 0x20000000
466 #define bCCKRxDAGCSatLevel 0x1f000000
467 #define bCCKTimingRecovery 0x800000
468 #define bCCKTxC0 0x3f0000
469 #define bCCKTxC1 0x3f000000
470 #define bCCKTxC2 0x3f
471 #define bCCKTxC3 0x3f00
472 #define bCCKTxC4 0x3f0000
473 #define bCCKTxC5 0x3f000000
474 #define bCCKTxC6 0x3f
475 #define bCCKTxC7 0x3f00
476 #define bCCKDebugPort 0xff0000
477 #define bCCKDACDebug 0x0f000000
478 #define bCCKFalseAlarmEnable 0x8000
479 #define bCCKFalseAlarmRead 0x4000
480 #define bCCKTRSSI 0x7f
481 #define bCCKRxAGCReport 0xfe
482 #define bCCKRxReport_AntSel 0x80000000
483 #define bCCKRxReport_MFOff 0x40000000
484 #define bCCKRxRxReport_SQLoss 0x20000000
485 #define bCCKRxReport_Pktloss 0x10000000
486 #define bCCKRxReport_Lockedbit 0x08000000
487 #define bCCKRxReport_RateError 0x04000000
488 #define bCCKRxReport_RxRate 0x03000000
489 #define bCCKRxFACounterLower 0xff
490 #define bCCKRxFACounterUpper 0xff000000
491 #define bCCKRxHPAGCStart 0xe000
492 #define bCCKRxHPAGCFinal 0x1c00
494 #define bCCKRxFalseAlarmEnable 0x8000
495 #define bCCKFACounterFreeze 0x4000
497 #define bCCKTxPathSel 0x10000000
498 #define bCCKDefaultRxPath 0xc000000
499 #define bCCKOptionRxPath 0x3000000
502 #define bNumOfSTF 0x3
503 #define bShift_L 0xc0
513 #define bTRSSIFreq 0x200
514 #define bADCBackoff 0x3000
515 #define bDFIRBackoff 0xc000
516 #define bTRSSILatchPhase 0x10000
517 #define bRxIDCOffset 0xff
518 #define bRxQDCOffset 0xff00
519 #define bRxDFIRMode 0x1800000
520 #define bRxDCNFType 0xe000000
521 #define bRXIQImb_A 0x3ff
522 #define bRXIQImb_B 0xfc00
523 #define bRXIQImb_C 0x3f0000
524 #define bRXIQImb_D 0xffc00000
525 #define bDC_dc_Notch 0x60000
526 #define bRxNBINotch 0x1f000000
528 #define bPD_TH_Opt2 0xc000
529 #define bPWED_TH 0x700
530 #define bIfMF_Win_L 0x800
531 #define bPD_Option 0x1000
532 #define bMF_Win_L 0xe000
533 #define bBW_Search_L 0x30000
534 #define bwin_enh_L 0xc0000
535 #define bBW_TH 0x700000
536 #define bED_TH2 0x3800000
537 #define bBW_option 0x4000000
538 #define bRatio_TH 0x18000000
539 #define bWindow_L 0xe0000000
540 #define bSBD_Option 0x1
541 #define bFrame_TH 0x1c
542 #define bFS_Option 0x60
543 #define bDC_Slope_check 0x80
544 #define bFGuard_Counter_DC_L 0xe00
545 #define bFrame_Weight_Short 0x7000
546 #define bSub_Tune 0xe00000
547 #define bFrame_DC_Length 0xe000000
548 #define bSBD_start_offset 0x30000000
549 #define bFrame_TH_2 0x7
550 #define bFrame_GI2_TH 0x38
551 #define bGI2_Sync_en 0x40
552 #define bSarch_Short_Early 0x300
553 #define bSarch_Short_Late 0xc00
554 #define bSarch_GI2_Late 0x70000
555 #define bCFOAntSum 0x1
557 #define bCFOStartOffset 0xc
558 #define bCFOLookBack 0x70
559 #define bCFOSumWeight 0x80
560 #define bDAGCEnable 0x10000
561 #define bTXIQImb_A 0x3ff
562 #define bTXIQImb_B 0xfc00
563 #define bTXIQImb_C 0x3f0000
564 #define bTXIQImb_D 0xffc00000
565 #define bTxIDCOffset 0xff
566 #define bTxQDCOffset 0xff00
567 #define bTxDFIRMode 0x10000
568 #define bTxPesudoNoiseOn 0x4000000
569 #define bTxPesudoNoise_A 0xff
570 #define bTxPesudoNoise_B 0xff00
571 #define bTxPesudoNoise_C 0xff0000
572 #define bTxPesudoNoise_D 0xff000000
573 #define bCCADropOption 0x20000
574 #define bCCADropThres 0xfff00000
576 #define bEDCCA_L 0xf0
577 #define bLambda_ED 0x300
578 #define bRxInitialGain 0x7f
579 #define bRxAntDivEn 0x80
580 #define bRxAGCAddressForLNA 0x7f00
581 #define bRxHighPowerFlow 0x8000
582 #define bRxAGCFreezeThres 0xc0000
583 #define bRxFreezeStep_AGC1 0x300000
584 #define bRxFreezeStep_AGC2 0xc00000
585 #define bRxFreezeStep_AGC3 0x3000000
586 #define bRxFreezeStep_AGC0 0xc000000
587 #define bRxRssi_Cmp_En 0x10000000
588 #define bRxQuickAGCEn 0x20000000
589 #define bRxAGCFreezeThresMode 0x40000000
590 #define bRxOverFlowCheckType 0x80000000
591 #define bRxAGCShift 0x7f
592 #define bTRSW_Tri_Only 0x80
593 #define bPowerThres 0x300
595 #define bRxAGCTogetherEn 0x2
596 #define bRxAGCMin 0x4
597 #define bRxHP_Ini 0x7
598 #define bRxHP_TRLNA 0x70
599 #define bRxHP_RSSI 0x700
600 #define bRxHP_BBP1 0x7000
601 #define bRxHP_BBP2 0x70000
602 #define bRxHP_BBP3 0x700000
603 #define bRSSI_H 0x7f0000 //the threshold for high power
604 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
605 #define bRxSettle_TRSW 0x7
606 #define bRxSettle_LNA 0x38
607 #define bRxSettle_RSSI 0x1c0
608 #define bRxSettle_BBP 0xe00
609 #define bRxSettle_RxHP 0x7000
610 #define bRxSettle_AntSW_RSSI 0x38000
611 #define bRxSettle_AntSW 0xc0000
612 #define bRxProcessTime_DAGC 0x300000
613 #define bRxSettle_HSSI 0x400000
614 #define bRxProcessTime_BBPPW 0x800000
615 #define bRxAntennaPowerShift 0x3000000
616 #define bRSSITableSelect 0xc000000
617 #define bRxHP_Final 0x7000000
618 #define bRxHTSettle_BBP 0x7
619 #define bRxHTSettle_HSSI 0x8
620 #define bRxHTSettle_RxHP 0x70
621 #define bRxHTSettle_BBPPW 0x80
622 #define bRxHTSettle_Idle 0x300
623 #define bRxHTSettle_Reserved 0x1c00
624 #define bRxHTRxHPEn 0x8000
625 #define bRxHTAGCFreezeThres 0x30000
626 #define bRxHTAGCTogetherEn 0x40000
627 #define bRxHTAGCMin 0x80000
628 #define bRxHTAGCEn 0x100000
629 #define bRxHTDAGCEn 0x200000
630 #define bRxHTRxHP_BBP 0x1c00000
631 #define bRxHTRxHP_Final 0xe0000000
632 #define bRxPWRatioTH 0x3
633 #define bRxPWRatioEn 0x4
634 #define bRxMFHold 0x3800
635 #define bRxPD_Delay_TH1 0x38
636 #define bRxPD_Delay_TH2 0x1c0
637 #define bRxPD_DC_COUNT_MAX 0x600
638 //#define bRxMF_Hold 0x3800
639 #define bRxPD_Delay_TH 0x8000
640 #define bRxProcess_Delay 0xf0000
641 #define bRxSearchrange_GI2_Early 0x700000
642 #define bRxFrame_Guard_Counter_L 0x3800000
643 #define bRxSGI_Guard_L 0xc000000
644 #define bRxSGI_Search_L 0x30000000
645 #define bRxSGI_TH 0xc0000000
646 #define bDFSCnt0 0xff
647 #define bDFSCnt1 0xff00
648 #define bDFSFlag 0xf0000
650 #define bMFWeightSum 0x300000
651 #define bMinIdxTH 0x7f000000
653 #define bDAFormat 0x40000
655 #define bTxChEmuEnable 0x01000000
657 #define bTRSWIsolation_A 0x7f
658 #define bTRSWIsolation_B 0x7f00
659 #define bTRSWIsolation_C 0x7f0000
660 #define bTRSWIsolation_D 0x7f000000
662 #define bExtLNAGain 0x7c00
666 #define bAntennaMapping 0x10
668 #define bCFOAntSumD 0x200
669 #define bPHYCounterReset 0x8000000
670 #define bCFOReportGet 0x4000000
671 #define bOFDMContinueTx 0x10000000
672 #define bOFDMSingleCarrier 0x20000000
673 #define bOFDMSingleTone 0x40000000
674 //#define bRxPath1 0x01
675 //#define bRxPath2 0x02
676 //#define bRxPath3 0x04
677 //#define bRxPath4 0x08
678 //#define bTxPath1 0x10
679 //#define bTxPath2 0x20
680 #define bHTDetect 0x100
681 #define bCFOEn 0x10000
682 #define bCFOValue 0xfff00000
683 #define bSigTone_Re 0x3f
684 #define bSigTone_Im 0x7f00
685 #define bCounter_CCA 0xffff
686 #define bCounter_ParityFail 0xffff0000
687 #define bCounter_RateIllegal 0xffff
688 #define bCounter_CRC8Fail 0xffff0000
689 #define bCounter_MCSNoSupport 0xffff
690 #define bCounter_FastSync 0xffff
691 #define bShortCFO 0xfff
692 #define bShortCFOTLength 12 //total
693 #define bShortCFOFLength 11 //fraction
694 #define bLongCFO 0x7ff
695 #define bLongCFOTLength 11
696 #define bLongCFOFLength 11
697 #define bTailCFO 0x1fff
698 #define bTailCFOTLength 13
699 #define bTailCFOFLength 12
701 #define bmax_en_pwdB 0xffff
702 #define bCC_power_dB 0xffff0000
703 #define bnoise_pwdB 0xffff
704 #define bPowerMeasTLength 10
705 #define bPowerMeasFLength 3
706 #define bRx_HT_BW 0x1
710 #define bNB_intf_det_on 0x1
711 #define bIntf_win_len_cfg 0x30
712 #define bNB_Intf_TH_cfg 0x1c0
715 #define bTableSel 0x40
718 #define bRxSNR_A 0xff
719 #define bRxSNR_B 0xff00
720 #define bRxSNR_C 0xff0000
721 #define bRxSNR_D 0xff000000
722 #define bSNREVMTLength 8
723 #define bSNREVMFLength 1
726 #define bCSI2nd 0xff00
727 #define bRxEVM1st 0xff0000
728 #define bRxEVM2nd 0xff000000
732 #define bSGIEN 0x10000
734 #define bSFactorQAM1 0xf
735 #define bSFactorQAM2 0xf0
736 #define bSFactorQAM3 0xf00
737 #define bSFactorQAM4 0xf000
738 #define bSFactorQAM5 0xf0000
739 #define bSFactorQAM6 0xf0000
740 #define bSFactorQAM7 0xf00000
741 #define bSFactorQAM8 0xf000000
742 #define bSFactorQAM9 0xf0000000
743 #define bCSIScheme 0x100000
745 #define bNoiseLvlTopSet 0x3
746 #define bChSmooth 0x4
747 #define bChSmoothCfg1 0x38
748 #define bChSmoothCfg2 0x1c0
749 #define bChSmoothCfg3 0xe00
750 #define bChSmoothCfg4 0x7000
751 #define bMRCMode 0x800000
752 #define bTHEVMCfg 0x7000000
754 #define bLoopFitType 0x1
756 #define bUpdCFOOffData 0x80
757 #define bAdvUpdCFO 0x100
758 #define bAdvTimeCtrl 0x800
759 #define bUpdClko 0x1000
761 #define bTrackingMode 0x8000
762 #define bPhCmpEnable 0x10000
763 #define bUpdClkoLTF 0x20000
764 #define bComChCFO 0x40000
765 #define bCSIEstiMode 0x80000
766 #define bAdvUpdEqz 0x100000
767 #define bUChCfg 0x7000000
768 #define bUpdEqz 0x8000000
771 #define bTxAGCRate18_06 0x7f7f7f7f
772 #define bTxAGCRate54_24 0x7f7f7f7f
773 #define bTxAGCRateMCS32 0x7f
774 #define bTxAGCRateCCK 0x7f00
775 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
776 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
777 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
778 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
782 #define bRxPesudoNoiseOn 0x20000000
783 #define bRxPesudoNoise_A 0xff
784 #define bRxPesudoNoise_B 0xff00
785 #define bRxPesudoNoise_C 0xff0000
786 #define bRxPesudoNoise_D 0xff000000
787 #define bPesudoNoiseState_A 0xffff
788 #define bPesudoNoiseState_B 0xffff0000
789 #define bPesudoNoiseState_C 0xffff
790 #define bPesudoNoiseState_D 0xffff0000
794 #define bZebra1_HSSIEnable 0x8
795 #define bZebra1_TRxControl 0xc00
796 #define bZebra1_TRxGainSetting 0x07f
797 #define bZebra1_RxCorner 0xc00
798 #define bZebra1_TxChargePump 0x38
799 #define bZebra1_RxChargePump 0x7
800 #define bZebra1_ChannelNum 0xf80
801 #define bZebra1_TxLPFBW 0x400
802 #define bZebra1_RxLPFBW 0x600
805 #define bRTL8256RegModeCtrl1 0x100
806 #define bRTL8256RegModeCtrl0 0x40
807 #define bRTL8256_TxLPFBW 0x18
808 #define bRTL8256_RxLPFBW 0x600
811 #define bRTL8258_TxLPFBW 0xc
812 #define bRTL8258_RxLPFBW 0xc00
813 #define bRTL8258_RSSILPFBW 0xc0
815 //byte endable for sb_write
824 //for PutRegsetting & GetRegSetting BitMask
825 #define bMaskByte0 0xff
826 #define bMaskByte1 0xff00
827 #define bMaskByte2 0xff0000
828 #define bMaskByte3 0xff000000
829 #define bMaskHWord 0xffff0000
830 #define bMaskLWord 0x0000ffff
831 #define bMaskDWord 0xffffffff
833 //for PutRFRegsetting & GetRFRegSetting BitMask
834 #define bMask12Bits 0xfff
839 #define LeftAntenna 0x0
840 #define RightAntenna 0x1
842 #define tCheckTxStatus 500 //500ms
843 #define tUpdateRxCounter 100 //100ms
849 //define Register-End
850 #define bPMAC_End 0x1ff
851 #define bFPGAPHY0_End 0x8ff
852 #define bFPGAPHY1_End 0x9ff
853 #define bCCKPHY0_End 0xaff
854 #define bOFDMPHY0_End 0xcff
855 #define bOFDMPHY1_End 0xdff
857 //define max debug item in each debug page
858 //#define bMaxItem_FPGA_PHY0 0x9
859 //#define bMaxItem_FPGA_PHY1 0x3
860 //#define bMaxItem_PHY_11B 0x16
861 //#define bMaxItem_OFDM_PHY0 0x29
862 //#define bMaxItem_OFDM_PHY1 0x0
864 #define bPMACControl 0x0
865 #define bWMACControl 0x1
866 #define bWNICControl 0x2
873 #define rRTL8256RxMixerPole 0xb
874 #define bZebraRxMixerPole 0x6
875 #define rRTL8256TxBBOPBias 0x9
876 #define bRTL8256TxBBOPBias 0x400
877 #define rRTL8256TxBBBW 19
878 #define bRTL8256TxBBBW 0x18
881 #endif //__INC_HAL8190PCIPHYREG_H