4 /* Channel switch: the size of command tables for switch channel */
5 #define MAX_PRECMD_CNT 16
6 #define MAX_RFDEPENDCMD_CNT 16
7 #define MAX_POSTCMD_CNT 16
10 #define MACPHY_Array_PGLength 21
11 #define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG
12 #define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array
13 #define RadioC_ArrayLength 246
14 #define RadioD_ArrayLength 78
15 #define Rtl819XRadioA_Array Rtl8190PciRadioA_Array
16 #define Rtl819XRadioB_Array Rtl8190PciRadioB_Array
17 #define Rtl819XRadioC_Array Rtl8190PciRadioC_Array
18 #define Rtl819XRadioD_Array Rtl8190PciRadioD_Array
19 #define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array
20 #define PHY_REGArrayLength 280
21 #define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray
22 #define PHY_REG_1T2RArrayLength 280
23 #define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray
28 #define MACPHY_Array_PGLength 30
29 #define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
30 #define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
31 #define RadioC_ArrayLength 1
32 #define RadioD_ArrayLength 1
33 #define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
34 #define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
35 #define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
36 #define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
37 #define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
38 #define PHY_REGArrayLength 1
39 #define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
40 #define PHY_REG_1T2RArrayLength 296
41 #define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
44 #define AGCTAB_ArrayLength 384
45 #define MACPHY_ArrayLength 18
47 #define RadioA_ArrayLength 246
48 #define RadioB_ArrayLength 78
51 typedef enum _SwChnlCmdID {
53 CmdID_SetTxPowerLevel,
56 CmdID_WritePortUshort,
61 /* switch channel data structure */
62 typedef struct _SwChnlCmd {
67 } __attribute__ ((packed)) SwChnlCmd;
69 extern u32 rtl819XMACPHY_Array_PG[];
70 extern u32 rtl819XPHY_REG_1T2RArray[];
71 extern u32 rtl819XAGCTAB_Array[];
72 extern u32 rtl819XRadioA_Array[];
73 extern u32 rtl819XRadioB_Array[];
74 extern u32 rtl819XRadioC_Array[];
75 extern u32 rtl819XRadioD_Array[];
77 typedef enum _HW90_BLOCK {
82 /* Don't ever use this. */
83 HW90_BLOCK_MAXIMUM = 4,
84 } HW90_BLOCK_E, *PHW90_BLOCK_E;
86 typedef enum _RF90_RADIO_PATH {
93 /* Max RF number 92 support */
95 } RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
97 #define bMaskByte0 0xff
98 #define bMaskByte1 0xff00
99 #define bMaskByte2 0xff0000
100 #define bMaskByte3 0xff000000
101 #define bMaskHWord 0xffff0000
102 #define bMaskLWord 0x0000ffff
103 #define bMaskDWord 0xffffffff
105 /*extern u32 rtl8192_CalculateBitShift(u32 dwBitMask);
107 extern u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
108 RF90_RADIO_PATH_E eRFPath, u32 Offset);
110 extern void rtl8192_phy_RFSerialWrite(struct net_device *dev,
111 RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
113 extern void rtl8192_InitBBRFRegDef(struct net_device *dev);
115 extern RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device *dev); */
117 extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath);
119 extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr,
120 u32 dwBitMask, u32 dwData);
122 extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr,
125 extern void rtl8192_phy_SetRFReg(struct net_device *dev,
126 RF90_RADIO_PATH_E eRFPath, u32 RegAddr,
127 u32 BitMask, u32 Data);
129 extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
130 RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
132 extern void rtl8192_phy_configmac(struct net_device *dev);
134 extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType);
136 extern RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device *dev,
137 HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
139 extern RT_STATUS rtl8192_BBConfig(struct net_device *dev);
141 extern void rtl8192_phy_getTxPower(struct net_device *dev);
143 extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel);
145 extern RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev);
147 extern void rtl8192_phy_updateInitGain(struct net_device* dev);
149 extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
150 RF90_RADIO_PATH_E eRFPath);
152 extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
154 extern void rtl8192_SetBWMode(struct net_device *dev,
155 HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
157 extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
159 extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
161 extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
163 #endif /* _R819XU_PHY_H */