drivers/staging/rtl8192e/r8192E_phy.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19
  20 #include "rtl_core.h"
  21 #include "r8192E_hw.h"
  22 #include "r8192E_phyreg.h"
  23 #include "r8190P_rtl8256.h"
  24 #include "r8192E_phy.h"
  25 #include "rtl_dm.h"
  26 #include "dot11d.h"
  27
  28 #include "r8192E_hwimg.h"
  29
  30 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  31         0,
  32         0x085c,
  33         0x08dc,
  34         0x095c,
  35         0x09dc,
  36         0x0a5c,
  37         0x0adc,
  38         0x0b5c,
  39         0x0bdc,
  40         0x0c5c,
  41         0x0cdc,
  42         0x0d5c,
  43         0x0ddc,
  44         0x0e5c,
  45         0x0f72,
  46 };
  47
  48 /*************************Define local function prototype**********************/
  49
  50 static u32 phy_FwRFSerialRead(struct net_device *dev,
  51                               enum rf90_radio_path eRFPath,
  52                               u32 Offset);
  53 static void phy_FwRFSerialWrite(struct net_device *dev,
  54                                 enum rf90_radio_path eRFPath,
  55                                 u32 Offset, u32 Data);
  56
  57 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
  58 {
  59         u32 i;
  60         for (i = 0; i <= 31; i++) {
  61                 if (((dwBitMask >> i) & 0x1) == 1)
  62                         break;
  63         }
  64         return i;
  65 }
  66
  67 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
  68 {
  69         u8 ret = 1;
  70         struct r8192_priv *priv = rtllib_priv(dev);
  71         if (priv->rf_type == RF_2T4R)
  72                 ret = 0;
  73         else if (priv->rf_type == RF_1T2R) {
  74                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  75                         ret = 1;
  76                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  77                         ret = 0;
  78         }
  79         return ret;
  80 }
  81
  82 void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
  83                       u32 dwData)
  84 {
  85
  86         u32 OriginalValue, BitShift, NewValue;
  87
  88         if (dwBitMask != bMaskDWord) {
  89                 OriginalValue = read_nic_dword(dev, dwRegAddr);
  90                 BitShift = rtl8192_CalculateBitShift(dwBitMask);
  91                 NewValue = (((OriginalValue) & (~dwBitMask)) |
  92                             (dwData << BitShift));
  93                 write_nic_dword(dev, dwRegAddr, NewValue);
  94         } else
  95                 write_nic_dword(dev, dwRegAddr, dwData);
  96         return;
  97 }
  98
  99 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
 100 {
 101         u32 Ret = 0, OriginalValue, BitShift;
 102
 103         OriginalValue = read_nic_dword(dev, dwRegAddr);
 104         BitShift = rtl8192_CalculateBitShift(dwBitMask);
 105         Ret = (OriginalValue & dwBitMask) >> BitShift;
 106
 107         return Ret;
 108 }
 109 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
 110                                     enum rf90_radio_path eRFPath, u32 Offset)
 111 {
 112         struct r8192_priv *priv = rtllib_priv(dev);
 113         u32 ret = 0;
 114         u32 NewOffset = 0;
 115         struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
 116         Offset &= 0x3f;
 117
 118         if (priv->rf_chip == RF_8256) {
 119                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
 120                 if (Offset >= 31) {
 121                         priv->RfReg0Value[eRFPath] |= 0x140;
 122                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 123                                          bMaskDWord,
 124                                          (priv->RfReg0Value[eRFPath]<<16));
 125                         NewOffset = Offset - 30;
 126                 } else if (Offset >= 16) {
 127                         priv->RfReg0Value[eRFPath] |= 0x100;
 128                         priv->RfReg0Value[eRFPath] &= (~0x40);
 129                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 130                                          bMaskDWord,
 131                                          (priv->RfReg0Value[eRFPath]<<16));
 132
 133                         NewOffset = Offset - 15;
 134                 } else
 135                         NewOffset = Offset;
 136         } else {
 137                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need"
 138                          " to be 8256\n");
 139                 NewOffset = Offset;
 140         }
 141         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
 142                          NewOffset);
 143         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 144         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 145
 146         mdelay(1);
 147
 148         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
 149                                  bLSSIReadBackData);
 150
 151         if (priv->rf_chip == RF_8256) {
 152                 priv->RfReg0Value[eRFPath] &= 0xebf;
 153
 154                 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
 155                                 (priv->RfReg0Value[eRFPath] << 16));
 156
 157                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
 158         }
 159
 160
 161         return ret;
 162
 163 }
 164
 165 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 166                                       enum rf90_radio_path eRFPath, u32 Offset,
 167                                       u32 Data)
 168 {
 169         struct r8192_priv *priv = rtllib_priv(dev);
 170         u32 DataAndAddr = 0, NewOffset = 0;
 171         struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
 172
 173         Offset &= 0x3f;
 174         if (priv->rf_chip == RF_8256) {
 175                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
 176
 177                 if (Offset >= 31) {
 178                         priv->RfReg0Value[eRFPath] |= 0x140;
 179                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 180                                          bMaskDWord,
 181                                          (priv->RfReg0Value[eRFPath] << 16));
 182                         NewOffset = Offset - 30;
 183                 } else if (Offset >= 16) {
 184                         priv->RfReg0Value[eRFPath] |= 0x100;
 185                         priv->RfReg0Value[eRFPath] &= (~0x40);
 186                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 187                                          bMaskDWord,
 188                                          (priv->RfReg0Value[eRFPath] << 16));
 189                         NewOffset = Offset - 15;
 190                 } else
 191                         NewOffset = Offset;
 192         } else {
 193                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be"
 194                          " 8256\n");
 195                 NewOffset = Offset;
 196         }
 197
 198         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
 199
 200         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 201
 202         if (Offset == 0x0)
 203                 priv->RfReg0Value[eRFPath] = Data;
 204
 205         if (priv->rf_chip == RF_8256) {
 206                 if (Offset != 0) {
 207                         priv->RfReg0Value[eRFPath] &= 0xebf;
 208                         rtl8192_setBBreg(
 209                                 dev,
 210                                 pPhyReg->rf3wireOffset,
 211                                 bMaskDWord,
 212                                 (priv->RfReg0Value[eRFPath] << 16));
 213                 }
 214                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
 215         }
 216         return;
 217 }
 218
 219 void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
 220                           u32 RegAddr, u32 BitMask, u32 Data)
 221 {
 222         struct r8192_priv *priv = rtllib_priv(dev);
 223         u32 Original_Value, BitShift, New_Value;
 224
 225         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 226                 return;
 227         if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
 228                 return;
 229
 230         RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
 231         if (priv->Rf_Mode == RF_OP_By_FW) {
 232                 if (BitMask != bMask12Bits) {
 233                         Original_Value = phy_FwRFSerialRead(dev, eRFPath,
 234                                                             RegAddr);
 235                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 236                         New_Value = (((Original_Value) & (~BitMask)) |
 237                                     (Data << BitShift));
 238
 239                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 240                 } else
 241                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
 242                 udelay(200);
 243
 244         } else {
 245                 if (BitMask != bMask12Bits) {
 246                         Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
 247                                                                   RegAddr);
 248                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 249                         New_Value = (((Original_Value) & (~BitMask)) |
 250                                      (Data << BitShift));
 251
 252                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
 253                                                   New_Value);
 254                 } else
 255                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
 256         }
 257         return;
 258 }
 259
 260 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
 261                            u32 RegAddr, u32 BitMask)
 262 {
 263         u32 Original_Value, Readback_Value, BitShift;
 264         struct r8192_priv *priv = rtllib_priv(dev);
 265         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 266                 return 0;
 267         if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
 268                 return  0;
 269         down(&priv->rf_sem);
 270         if (priv->Rf_Mode == RF_OP_By_FW) {
 271                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 272                 udelay(200);
 273         } else {
 274                 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
 275                                                           RegAddr);
 276         }
 277         BitShift =  rtl8192_CalculateBitShift(BitMask);
 278         Readback_Value = (Original_Value & BitMask) >> BitShift;
 279         up(&priv->rf_sem);
 280         return Readback_Value;
 281 }
 282
 283 static u32 phy_FwRFSerialRead(struct net_device *dev,
 284                               enum rf90_radio_path eRFPath, u32 Offset)
 285 {
 286         u32             retValue = 0;
 287         u32             Data = 0;
 288         u8              time = 0;
 289         Data |= ((Offset & 0xFF) << 12);
 290         Data |= ((eRFPath & 0x3) << 20);
 291         Data |= 0x80000000;
 292         while (read_nic_dword(dev, QPNR)&0x80000000) {
 293                 if (time++ < 100)
 294                         udelay(10);
 295                 else
 296                         break;
 297         }
 298         write_nic_dword(dev, QPNR, Data);
 299         while (read_nic_dword(dev, QPNR) & 0x80000000) {
 300                 if (time++ < 100)
 301                         udelay(10);
 302                 else
 303                         return 0;
 304         }
 305         retValue = read_nic_dword(dev, RF_DATA);
 306
 307         return  retValue;
 308
 309 }       /* phy_FwRFSerialRead */
 310
 311 static void phy_FwRFSerialWrite(struct net_device *dev,
 312                                 enum rf90_radio_path eRFPath,
 313                                 u32 Offset, u32 Data)
 314 {
 315         u8      time = 0;
 316
 317         Data |= ((Offset & 0xFF) << 12);
 318         Data |= ((eRFPath & 0x3) << 20);
 319         Data |= 0x400000;
 320         Data |= 0x80000000;
 321
 322         while (read_nic_dword(dev, QPNR) & 0x80000000) {
 323                 if (time++ < 100)
 324                         udelay(10);
 325                 else
 326                         break;
 327         }
 328         write_nic_dword(dev, QPNR, Data);
 329
 330 }       /* phy_FwRFSerialWrite */
 331
 332
 333 void rtl8192_phy_configmac(struct net_device *dev)
 334 {
 335         u32 dwArrayLen = 0, i = 0;
 336         u32 *pdwArray = NULL;
 337         struct r8192_priv *priv = rtllib_priv(dev);
 338
 339         if (priv->bTXPowerDataReadFromEEPORM) {
 340                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 341                 dwArrayLen = MACPHY_Array_PGLength;
 342                 pdwArray = Rtl819XMACPHY_Array_PG;
 343
 344         } else {
 345                 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
 346                 dwArrayLen = MACPHY_ArrayLength;
 347                 pdwArray = Rtl819XMACPHY_Array;
 348         }
 349         for (i = 0; i < dwArrayLen; i += 3) {
 350                 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC"
 351                          "PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
 352                          pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 353                 if (pdwArray[i] == 0x318)
 354                         pdwArray[i+2] = 0x00000800;
 355                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
 356                                  pdwArray[i+2]);
 357         }
 358         return;
 359
 360 }
 361
 362 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 363 {
 364         int i;
 365         u32 *Rtl819XPHY_REGArray_Table = NULL;
 366         u32 *Rtl819XAGCTAB_Array_Table = NULL;
 367         u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
 368         struct r8192_priv *priv = rtllib_priv(dev);
 369
 370         AGCTAB_ArrayLen = AGCTAB_ArrayLength;
 371         Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
 372         if (priv->rf_type == RF_2T4R) {
 373                 PHY_REGArrayLen = PHY_REGArrayLength;
 374                 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
 375         } else if (priv->rf_type == RF_1T2R) {
 376                 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
 377                 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
 378         }
 379
 380         if (ConfigType == BaseBand_Config_PHY_REG) {
 381                 for (i = 0; i < PHY_REGArrayLen; i += 2) {
 382                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i],
 383                                          bMaskDWord,
 384                                          Rtl819XPHY_REGArray_Table[i+1]);
 385                         RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray"
 386                                  "[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
 387                                  i, Rtl819XPHY_REGArray_Table[i],
 388                                  Rtl819XPHY_REGArray_Table[i+1]);
 389                 }
 390         } else if (ConfigType == BaseBand_Config_AGC_TAB) {
 391                 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
 392                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i],
 393                                          bMaskDWord,
 394                                          Rtl819XAGCTAB_Array_Table[i+1]);
 395                         RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] "
 396                                  "is %x rtl819XAGCTAB_Array[1] is %x\n", i,
 397                                  Rtl819XAGCTAB_Array_Table[i],
 398                                  Rtl819XAGCTAB_Array_Table[i+1]);
 399                 }
 400         }
 401         return;
 402 }
 403
 404 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
 405 {
 406         struct r8192_priv *priv = rtllib_priv(dev);
 407
 408         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 409         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 410         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 411         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 412
 413         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 414         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 415         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 416         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 417
 418         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 419         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 420         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 421         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 422
 423         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 424         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 425         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 426         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 427
 428         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 429         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 430         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 431         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 432
 433         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 434         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 435         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 436         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 437
 438         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 439         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 440         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 441         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 442
 443         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 444         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 445         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 446         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 447
 448         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 449         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 450         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 451         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 452
 453         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 454         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 455         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 456         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 457
 458         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 459         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 460         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 461         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 462
 463         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 464         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 465         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 466         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 467
 468         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 469         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 470         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 471         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 472
 473         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 474         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 475         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 476         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 477
 478         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 479         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 480         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 481         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 482
 483         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 484         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 485         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 486         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 487
 488         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 489         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 490         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 491         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 492
 493 }
 494
 495 bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
 496                               enum hw90_block CheckBlock,
 497                               enum rf90_radio_path eRFPath)
 498 {
 499         bool ret = true;
 500         u32 i, CheckTimes = 4, dwRegRead = 0;
 501         u32 WriteAddr[4];
 502         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 503
 504         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 505         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 506         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 507         WriteAddr[HW90_BLOCK_RF] = 0x3;
 508         RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
 509                  CheckBlock);
 510         for (i = 0; i < CheckTimes; i++) {
 511                 switch (CheckBlock) {
 512                 case HW90_BLOCK_MAC:
 513                         RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write "
 514                                  "0x100 here!");
 515                         break;
 516
 517                 case HW90_BLOCK_PHY0:
 518                 case HW90_BLOCK_PHY1:
 519                         write_nic_dword(dev, WriteAddr[CheckBlock],
 520                                         WriteData[i]);
 521                         dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
 522                         break;
 523
 524                 case HW90_BLOCK_RF:
 525                         WriteData[i] &= 0xfff;
 526                         rtl8192_phy_SetRFReg(dev, eRFPath,
 527                                                  WriteAddr[HW90_BLOCK_RF],
 528                                                  bMask12Bits, WriteData[i]);
 529                         mdelay(10);
 530                         dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath,
 531                                                  WriteAddr[HW90_BLOCK_RF],
 532                                                  bMaskDWord);
 533                         mdelay(10);
 534                         break;
 535
 536                 default:
 537                         ret = false;
 538                         break;
 539                 }
 540
 541
 542                 if (dwRegRead != WriteData[i]) {
 543                         RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, "
 544                                  "WriteData: %x\n", dwRegRead, WriteData[i]);
 545                         ret = false;
 546                         break;
 547                 }
 548         }
 549
 550         return ret;
 551 }
 552
 553 static bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
 554 {
 555         struct r8192_priv *priv = rtllib_priv(dev);
 556         bool rtStatus = true;
 557         u8 bRegValue = 0, eCheckItem = 0;
 558         u32 dwRegValue = 0;
 559
 560         bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
 561         write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
 562
 563         dwRegValue = read_nic_dword(dev, CPU_GEN);
 564         write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
 565
 566         for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
 567              eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
 568                 rtStatus  = rtl8192_phy_checkBBAndRF(dev,
 569                                          (enum hw90_block)eCheckItem,
 570                                          (enum rf90_radio_path)0);
 571                 if (rtStatus != true) {
 572                         RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():"
 573                                  "Check PHY%d Fail!!\n", eCheckItem-1);
 574                         return rtStatus;
 575                 }
 576         }
 577         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 578         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 579
 580         dwRegValue = read_nic_dword(dev, CPU_GEN);
 581         write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
 582
 583         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 584
 585         if (priv->IC_Cut  > VERSION_8190_BD) {
 586                 if (priv->rf_type == RF_2T4R)
 587                         dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
 588                                       priv->AntennaTxPwDiff[1]<<4 |
 589                                       priv->AntennaTxPwDiff[0]);
 590                 else
 591                         dwRegValue = 0x0;
 592                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
 593                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
 594
 595
 596                 dwRegValue = priv->CrystalCap;
 597                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
 598                                  dwRegValue);
 599         }
 600
 601         return rtStatus;
 602 }
 603 bool rtl8192_BBConfig(struct net_device *dev)
 604 {
 605         bool rtStatus = true;
 606
 607         rtl8192_InitBBRFRegDef(dev);
 608         rtStatus = rtl8192_BB_Config_ParaFile(dev);
 609         return rtStatus;
 610 }
 611
 612 void rtl8192_phy_getTxPower(struct net_device *dev)
 613 {
 614         struct r8192_priv *priv = rtllib_priv(dev);
 615
 616         priv->MCSTxPowerLevelOriginalOffset[0] =
 617                 read_nic_dword(dev, rTxAGC_Rate18_06);
 618         priv->MCSTxPowerLevelOriginalOffset[1] =
 619                 read_nic_dword(dev, rTxAGC_Rate54_24);
 620         priv->MCSTxPowerLevelOriginalOffset[2] =
 621                 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
 622         priv->MCSTxPowerLevelOriginalOffset[3] =
 623                 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
 624         priv->MCSTxPowerLevelOriginalOffset[4] =
 625                 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
 626         priv->MCSTxPowerLevelOriginalOffset[5] =
 627                 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
 628
 629         priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
 630         priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
 631         priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
 632         priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
 633         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, "
 634                 "c60=0x%x, c68=0x%x)\n",
 635                 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 636                 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 637
 638         priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
 639         priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
 640         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
 641                 rOFDM0_RxDetector3, priv->framesync);
 642         priv->SifsTime = read_nic_word(dev, SIFS);
 643         return;
 644 }
 645
 646 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 647 {
 648         struct r8192_priv *priv = rtllib_priv(dev);
 649         u8      powerlevel = 0, powerlevelOFDM24G = 0;
 650         char ant_pwr_diff;
 651         u32     u4RegValue;
 652
 653         if (priv->epromtype == EEPROM_93C46) {
 654                 powerlevel = priv->TxPowerLevelCCK[channel-1];
 655                 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 656         } else if (priv->epromtype == EEPROM_93C56) {
 657                 if (priv->rf_type == RF_1T2R) {
 658                         powerlevel = priv->TxPowerLevelCCK_C[channel-1];
 659                         powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
 660                 } else if (priv->rf_type == RF_2T4R) {
 661                         powerlevel = priv->TxPowerLevelCCK_A[channel-1];
 662                         powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
 663
 664                         ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
 665                                        - priv->TxPowerLevelOFDM24G_A[channel-1];
 666
 667                         priv->RF_C_TxPwDiff = ant_pwr_diff;
 668
 669                         ant_pwr_diff &= 0xf;
 670
 671                         priv->AntennaTxPwDiff[2] = 0;
 672                         priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
 673                         priv->AntennaTxPwDiff[0] = 0;
 674
 675                         u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
 676                                       priv->AntennaTxPwDiff[1]<<4 |
 677                                       priv->AntennaTxPwDiff[0]);
 678
 679                         rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
 680                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
 681                 }
 682         }
 683         switch (priv->rf_chip) {
 684         case RF_8225:
 685                 break;
 686         case RF_8256:
 687                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 688                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 689                 break;
 690         case RF_8258:
 691                 break;
 692         default:
 693                 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n",
 694                          __func__);
 695                 break;
 696         }
 697         return;
 698 }
 699
 700 bool rtl8192_phy_RFConfig(struct net_device *dev)
 701 {
 702         struct r8192_priv *priv = rtllib_priv(dev);
 703         bool rtStatus = true;
 704         switch (priv->rf_chip) {
 705         case RF_8225:
 706                 break;
 707         case RF_8256:
 708                 rtStatus = PHY_RF8256_Config(dev);
 709                 break;
 710
 711         case RF_8258:
 712                 break;
 713         case RF_PSEUDO_11N:
 714                 break;
 715
 716         default:
 717                 RT_TRACE(COMP_ERR, "error chip id\n");
 718                 break;
 719         }
 720         return rtStatus;
 721 }
 722
 723 void rtl8192_phy_updateInitGain(struct net_device *dev)
 724 {
 725         return;
 726 }
 727
 728 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 729                                       enum rf90_radio_path eRFPath)
 730 {
 731
 732         int i;
 733         u8 ret = 0;
 734
 735         switch (eRFPath) {
 736         case RF90_PATH_A:
 737                 for (i = 0; i < RadioA_ArrayLength; i += 2) {
 738                         if (Rtl819XRadioA_Array[i] == 0xfe) {
 739                                 msleep(100);
 740                                 continue;
 741                         }
 742                         rtl8192_phy_SetRFReg(dev, eRFPath,
 743                                              Rtl819XRadioA_Array[i],
 744                                              bMask12Bits,
 745                                              Rtl819XRadioA_Array[i+1]);
 746
 747                 }
 748                 break;
 749         case RF90_PATH_B:
 750                 for (i = 0; i < RadioB_ArrayLength; i += 2) {
 751                         if (Rtl819XRadioB_Array[i] == 0xfe) {
 752                                 msleep(100);
 753                                 continue;
 754                         }
 755                         rtl8192_phy_SetRFReg(dev, eRFPath,
 756                                              Rtl819XRadioB_Array[i],
 757                                              bMask12Bits,
 758                                              Rtl819XRadioB_Array[i+1]);
 759
 760                 }
 761                 break;
 762         case RF90_PATH_C:
 763                 for (i = 0; i < RadioC_ArrayLength; i += 2) {
 764                         if (Rtl819XRadioC_Array[i] == 0xfe) {
 765                                 msleep(100);
 766                                 continue;
 767                         }
 768                         rtl8192_phy_SetRFReg(dev, eRFPath,
 769                                              Rtl819XRadioC_Array[i],
 770                                              bMask12Bits,
 771                                              Rtl819XRadioC_Array[i+1]);
 772
 773                 }
 774                 break;
 775         case RF90_PATH_D:
 776                 for (i = 0; i < RadioD_ArrayLength; i += 2) {
 777                         if (Rtl819XRadioD_Array[i] == 0xfe) {
 778                                         msleep(100);
 779                                         continue;
 780                         }
 781                         rtl8192_phy_SetRFReg(dev, eRFPath,
 782                                          Rtl819XRadioD_Array[i], bMask12Bits,
 783                                          Rtl819XRadioD_Array[i+1]);
 784
 785                 }
 786                 break;
 787         default:
 788                 break;
 789         }
 790
 791         return ret;
 792
 793 }
 794 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
 795 {
 796         struct r8192_priv *priv = rtllib_priv(dev);
 797         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 798         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 799
 800         switch (priv->rf_chip) {
 801         case RF_8225:
 802                 break;
 803
 804         case RF_8256:
 805                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 806                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 807                 break;
 808
 809         case RF_8258:
 810                 break;
 811         default:
 812                 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower"
 813                          "Level()\n");
 814                 break;
 815         }
 816         return;
 817 }
 818
 819 static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable,
 820                                         u32 CmdTableIdx, u32 CmdTableSz,
 821                                         enum sw_chnl_cmd_id CmdID,
 822                                         u32 Para1, u32 Para2, u32 msDelay)
 823 {
 824         struct sw_chnl_cmd *pCmd;
 825
 826         if (CmdTable == NULL) {
 827                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot "
 828                          "be NULL.\n");
 829                 return false;
 830         }
 831         if (CmdTableIdx >= CmdTableSz) {
 832                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid"
 833                          " index, please check size of the table, CmdTableIdx:"
 834                          "%d, CmdTableSz:%d\n",
 835                                 CmdTableIdx, CmdTableSz);
 836                 return false;
 837         }
 838
 839         pCmd = CmdTable + CmdTableIdx;
 840         pCmd->CmdID = CmdID;
 841         pCmd->Para1 = Para1;
 842         pCmd->Para2 = Para2;
 843         pCmd->msDelay = msDelay;
 844
 845         return true;
 846 }
 847
 848 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
 849                                        u8 *stage, u8 *step, u32 *delay)
 850 {
 851         struct r8192_priv *priv = rtllib_priv(dev);
 852         struct rtllib_device *ieee = priv->rtllib;
 853         u32                                     PreCommonCmdCnt;
 854         u32                                     PostCommonCmdCnt;
 855         u32                                     RfDependCmdCnt;
 856         struct sw_chnl_cmd *CurrentCmd = NULL;
 857         u8              eRFPath;
 858
 859         RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
 860                   __func__, *stage, *step, channel);
 861
 862         if (!IsLegalChannel(priv->rtllib, channel)) {
 863                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n",
 864                          channel);
 865                 return true;
 866         }
 867
 868         {
 869                 PreCommonCmdCnt = 0;
 870                 rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd,
 871                                         PreCommonCmdCnt++,
 872                                         MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
 873                                         0, 0, 0);
 874                 rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd,
 875                                         PreCommonCmdCnt++,
 876                                         MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
 877
 878                 PostCommonCmdCnt = 0;
 879
 880                 rtl8192_phy_SetSwChnlCmdArray(ieee->PostCommonCmd,
 881                                         PostCommonCmdCnt++,
 882                                         MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
 883
 884                 RfDependCmdCnt = 0;
 885                 switch (priv->rf_chip) {
 886                 case RF_8225:
 887                         if (!(channel >= 1 && channel <= 14)) {
 888                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra "
 889                                          "8225: %d\n", channel);
 890                                 return false;
 891                         }
 892                         rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
 893                                 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
 894                                 CmdID_RF_WriteReg, rZebra1_Channel,
 895                                 RF_CHANNEL_TABLE_ZEBRA[channel], 10);
 896                         rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
 897                                 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
 898                                 CmdID_End, 0, 0, 0);
 899                         break;
 900
 901                 case RF_8256:
 902                         if (!(channel >= 1 && channel <= 14)) {
 903                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra"
 904                                          " 8256: %d\n", channel);
 905                                 return false;
 906                         }
 907                         rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
 908                                  RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
 909                                 CmdID_RF_WriteReg, rZebra1_Channel, channel,
 910                                  10);
 911                         rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
 912
 913                                                       RfDependCmdCnt++,
 914                                                       MAX_RFDEPENDCMD_CNT,
 915                         CmdID_End, 0, 0, 0);
 916                         break;
 917
 918                 case RF_8258:
 919                         break;
 920
 921                 default:
 922                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n",
 923                                  priv->rf_chip);
 924                         return false;
 925                         break;
 926                 }
 927
 928
 929                 do {
 930                         switch (*stage) {
 931                         case 0:
 932                                 CurrentCmd = &ieee->PreCommonCmd[*step];
 933                                 break;
 934                         case 1:
 935                                 CurrentCmd = &ieee->RfDependCmd[*step];
 936                                 break;
 937                         case 2:
 938                                 CurrentCmd = &ieee->PostCommonCmd[*step];
 939                                 break;
 940                         }
 941
 942                         if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
 943                                 if ((*stage) == 2) {
 944                                         return true;
 945                                 } else {
 946                                         (*stage)++;
 947                                         (*step) = 0;
 948                                         continue;
 949                                 }
 950                         }
 951
 952                         if (!CurrentCmd)
 953                                 continue;
 954                         switch (CurrentCmd->CmdID) {
 955                         case CmdID_SetTxPowerLevel:
 956                                 if (priv->IC_Cut > (u8)VERSION_8190_BD)
 957                                         rtl8192_SetTxPowerLevel(dev, channel);
 958                                 break;
 959                         case CmdID_WritePortUlong:
 960                                 write_nic_dword(dev, CurrentCmd->Para1,
 961                                                 CurrentCmd->Para2);
 962                                 break;
 963                         case CmdID_WritePortUshort:
 964                                 write_nic_word(dev, CurrentCmd->Para1,
 965                                                (u16)CurrentCmd->Para2);
 966                                 break;
 967                         case CmdID_WritePortUchar:
 968                                 write_nic_byte(dev, CurrentCmd->Para1,
 969                                                (u8)CurrentCmd->Para2);
 970                                 break;
 971                         case CmdID_RF_WriteReg:
 972                                 for (eRFPath = 0; eRFPath <
 973                                      priv->NumTotalRFPath; eRFPath++)
 974                                         rtl8192_phy_SetRFReg(dev,
 975                                                  (enum rf90_radio_path)eRFPath,
 976                                                  CurrentCmd->Para1, bMask12Bits,
 977                                                  CurrentCmd->Para2<<7);
 978                                 break;
 979                         default:
 980                                 break;
 981                         }
 982
 983                         break;
 984                 } while (true);
 985         } /*for (Number of RF paths)*/
 986
 987         (*delay) = CurrentCmd->msDelay;
 988         (*step)++;
 989         return false;
 990 }
 991
 992 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
 993 {
 994         struct r8192_priv *priv = rtllib_priv(dev);
 995         u32 delay = 0;
 996
 997         while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
 998               &priv->SwChnlStep, &delay)) {
 999                 if (delay > 0)
1000                         msleep(delay);
1001                 if (IS_NIC_DOWN(priv))
1002                         break;
1003         }
1004 }
1005 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1006 {
1007
1008         struct r8192_priv *priv = rtllib_priv(dev);
1009
1010         RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1011
1012         RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
1013                  priv->chan, priv);
1014
1015         rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1016
1017         RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1018 }
1019
1020 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1021 {
1022         struct r8192_priv *priv = rtllib_priv(dev);
1023         RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1024         if (IS_NIC_DOWN(priv)) {
1025                 RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__);
1026                 return false;
1027         }
1028         if (priv->SwChnlInProgress)
1029                 return false;
1030
1031
1032         switch (priv->rtllib->mode) {
1033         case WIRELESS_MODE_A:
1034         case WIRELESS_MODE_N_5G:
1035                 if (channel <= 14) {
1036                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1037                         return false;
1038                 }
1039                 break;
1040         case WIRELESS_MODE_B:
1041                 if (channel > 14) {
1042                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1043                         return false;
1044                 }
1045                 break;
1046         case WIRELESS_MODE_G:
1047         case WIRELESS_MODE_N_24G:
1048                 if (channel > 14) {
1049                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1050                         return false;
1051                 }
1052                 break;
1053         }
1054
1055         priv->SwChnlInProgress = true;
1056         if (channel == 0)
1057                 channel = 1;
1058
1059         priv->chan = channel;
1060
1061         priv->SwChnlStage = 0;
1062         priv->SwChnlStep = 0;
1063
1064         if (!IS_NIC_DOWN(priv))
1065                 rtl8192_SwChnl_WorkItem(dev);
1066         priv->SwChnlInProgress = false;
1067         return true;
1068 }
1069
1070 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev)
1071 {
1072         struct r8192_priv *priv = rtllib_priv(dev);
1073
1074         switch (priv->CurrentChannelBW) {
1075         case HT_CHANNEL_WIDTH_20:
1076                 priv->CCKPresentAttentuation =
1077                         priv->CCKPresentAttentuation_20Mdefault +
1078                             priv->CCKPresentAttentuation_difference;
1079
1080                 if (priv->CCKPresentAttentuation >
1081                     (CCKTxBBGainTableLength-1))
1082                         priv->CCKPresentAttentuation =
1083                                          CCKTxBBGainTableLength-1;
1084                 if (priv->CCKPresentAttentuation < 0)
1085                         priv->CCKPresentAttentuation = 0;
1086
1087                 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent"
1088                          "Attentuation = %d\n",
1089                          priv->CCKPresentAttentuation);
1090
1091                 if (priv->rtllib->current_network.channel == 14 &&
1092                     !priv->bcck_in_ch14) {
1093                         priv->bcck_in_ch14 = true;
1094                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1095                 } else if (priv->rtllib->current_network.channel !=
1096                            14 && priv->bcck_in_ch14) {
1097                         priv->bcck_in_ch14 = false;
1098                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1099                 } else {
1100                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1101                 }
1102                 break;
1103
1104         case HT_CHANNEL_WIDTH_20_40:
1105                 priv->CCKPresentAttentuation =
1106                         priv->CCKPresentAttentuation_40Mdefault +
1107                         priv->CCKPresentAttentuation_difference;
1108
1109                 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent"
1110                          "Attentuation = %d\n",
1111                          priv->CCKPresentAttentuation);
1112                 if (priv->CCKPresentAttentuation >
1113                     (CCKTxBBGainTableLength - 1))
1114                         priv->CCKPresentAttentuation =
1115                                          CCKTxBBGainTableLength-1;
1116                 if (priv->CCKPresentAttentuation < 0)
1117                         priv->CCKPresentAttentuation = 0;
1118
1119                 if (priv->rtllib->current_network.channel == 14 &&
1120                     !priv->bcck_in_ch14) {
1121                         priv->bcck_in_ch14 = true;
1122                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1123                 } else if (priv->rtllib->current_network.channel != 14
1124                            && priv->bcck_in_ch14) {
1125                         priv->bcck_in_ch14 = false;
1126                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1127                 } else {
1128                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1129                 }
1130                 break;
1131         }
1132 }
1133
1134 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1135 {
1136         struct r8192_priv *priv = rtllib_priv(dev);
1137
1138         if (priv->rtllib->current_network.channel == 14 &&
1139             !priv->bcck_in_ch14)
1140                 priv->bcck_in_ch14 = true;
1141         else if (priv->rtllib->current_network.channel != 14 &&
1142                  priv->bcck_in_ch14)
1143                 priv->bcck_in_ch14 = false;
1144
1145         switch (priv->CurrentChannelBW) {
1146         case HT_CHANNEL_WIDTH_20:
1147                 if (priv->Record_CCK_20Mindex == 0)
1148                         priv->Record_CCK_20Mindex = 6;
1149                 priv->CCK_index = priv->Record_CCK_20Mindex;
1150                 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_"
1151                          "Switch_ThermalMeter(),CCK_index = %d\n",
1152                          priv->CCK_index);
1153         break;
1154
1155         case HT_CHANNEL_WIDTH_20_40:
1156                 priv->CCK_index = priv->Record_CCK_40Mindex;
1157                 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_"
1158                          "Switch_ThermalMeter(), CCK_index = %d\n",
1159                          priv->CCK_index);
1160         break;
1161         }
1162         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1163 }
1164
1165 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
1166 {
1167         struct r8192_priv *priv = rtllib_priv(dev);
1168
1169         if (priv->IC_Cut >= IC_VersionCut_D)
1170                 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1171         else
1172                 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
1173 }
1174
1175 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1176 {
1177
1178         struct r8192_priv *priv = rtllib_priv(dev);
1179         u8 regBwOpMode;
1180
1181         RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem()  Switch to %s "
1182                  "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1183                  "20MHz" : "40MHz")
1184
1185
1186         if (priv->rf_chip == RF_PSEUDO_11N) {
1187                 priv->SetBWModeInProgress = false;
1188                 return;
1189         }
1190         if (IS_NIC_DOWN(priv)) {
1191                 RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__);
1192                 return;
1193         }
1194         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
1195
1196         switch (priv->CurrentChannelBW) {
1197         case HT_CHANNEL_WIDTH_20:
1198                 regBwOpMode |= BW_OPMODE_20MHZ;
1199                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1200                 break;
1201
1202         case HT_CHANNEL_WIDTH_20_40:
1203                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1204                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1205                 break;
1206
1207         default:
1208                 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
1209                          "Bandwidth: %#X\n", priv->CurrentChannelBW);
1210                 break;
1211         }
1212
1213         switch (priv->CurrentChannelBW) {
1214         case HT_CHANNEL_WIDTH_20:
1215                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1216                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1217
1218                 if (!priv->btxpower_tracking) {
1219                         write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
1220                         write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
1221                         write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
1222                 } else {
1223                         CCK_Tx_Power_Track_BW_Switch(dev);
1224                 }
1225
1226                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1227
1228                 break;
1229         case HT_CHANNEL_WIDTH_20_40:
1230                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1231                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1232
1233                 if (!priv->btxpower_tracking) {
1234                         write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
1235                         write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
1236                         write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
1237                 } else {
1238                         CCK_Tx_Power_Track_BW_Switch(dev);
1239                 }
1240
1241                 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1242                                  (priv->nCur40MhzPrimeSC>>1));
1243                 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1244                                  priv->nCur40MhzPrimeSC);
1245
1246                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1247                 break;
1248         default:
1249                 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
1250                          "Bandwidth: %#X\n", priv->CurrentChannelBW);
1251                 break;
1252
1253         }
1254
1255         switch (priv->rf_chip) {
1256         case RF_8225:
1257                 break;
1258
1259         case RF_8256:
1260                 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1261                 break;
1262
1263         case RF_8258:
1264                 break;
1265
1266         case RF_PSEUDO_11N:
1267                 break;
1268
1269         default:
1270                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1271                 break;
1272         }
1273
1274         atomic_dec(&(priv->rtllib->atm_swbw));
1275         priv->SetBWModeInProgress = false;
1276
1277         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1278 }
1279
1280 void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
1281                        enum ht_extchnl_offset Offset)
1282 {
1283         struct r8192_priv *priv = rtllib_priv(dev);
1284
1285
1286         if (priv->SetBWModeInProgress)
1287                 return;
1288
1289         atomic_inc(&(priv->rtllib->atm_swbw));
1290         priv->SetBWModeInProgress = true;
1291
1292         priv->CurrentChannelBW = Bandwidth;
1293
1294         if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1295                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1296         else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1297                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1298         else
1299                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1300
1301         rtl8192_SetBWModeWorkItem(dev);
1302
1303 }
1304
1305 void InitialGain819xPci(struct net_device *dev, u8 Operation)
1306 {
1307 #define SCAN_RX_INITIAL_GAIN    0x17
1308 #define POWER_DETECTION_TH      0x08
1309         struct r8192_priv *priv = rtllib_priv(dev);
1310         u32 BitMask;
1311         u8 initial_gain;
1312
1313         if (!IS_NIC_DOWN(priv)) {
1314                 switch (Operation) {
1315                 case IG_Backup:
1316                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial"
1317                                  " gain.\n");
1318                         initial_gain = SCAN_RX_INITIAL_GAIN;
1319                         BitMask = bMaskByte0;
1320                         if (dm_digtable.dig_algorithm ==
1321                             DIG_ALGO_BY_FALSE_ALARM)
1322                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1323                         priv->initgain_backup.xaagccore1 =
1324                                  (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1,
1325                                  BitMask);
1326                         priv->initgain_backup.xbagccore1 =
1327                                  (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1,
1328                                  BitMask);
1329                         priv->initgain_backup.xcagccore1 =
1330                                  (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1,
1331                                  BitMask);
1332                         priv->initgain_backup.xdagccore1 =
1333                                  (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1,
1334                                  BitMask);
1335                         BitMask = bMaskByte2;
1336                         priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev,
1337                                                     rCCK0_CCA, BitMask);
1338
1339                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is"
1340                                  " %x\n", priv->initgain_backup.xaagccore1);
1341                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is"
1342                                  " %x\n", priv->initgain_backup.xbagccore1);
1343                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is"
1344                                  " %x\n", priv->initgain_backup.xcagccore1);
1345                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is"
1346                                  " %x\n", priv->initgain_backup.xdagccore1);
1347                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is"
1348                                  " %x\n", priv->initgain_backup.cca);
1349
1350                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1351                                  initial_gain);
1352                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1353                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1354                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1355                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1356                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1357                                  POWER_DETECTION_TH);
1358                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1359                         break;
1360                 case IG_Restore:
1361                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial "
1362                                  "gain.\n");
1363                         BitMask = 0x7f;
1364                         if (dm_digtable.dig_algorithm ==
1365                             DIG_ALGO_BY_FALSE_ALARM)
1366                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1367
1368                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask,
1369                                          (u32)priv->initgain_backup.xaagccore1);
1370                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask,
1371                                          (u32)priv->initgain_backup.xbagccore1);
1372                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask,
1373                                          (u32)priv->initgain_backup.xcagccore1);
1374                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask,
1375                                          (u32)priv->initgain_backup.xdagccore1);
1376                         BitMask  = bMaskByte2;
1377                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask,
1378                                          (u32)priv->initgain_backup.cca);
1379
1380                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50"
1381                                  " is %x\n", priv->initgain_backup.xaagccore1);
1382                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58"
1383                                  " is %x\n", priv->initgain_backup.xbagccore1);
1384                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60"
1385                                  " is %x\n", priv->initgain_backup.xcagccore1);
1386                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68"
1387                                  " is %x\n", priv->initgain_backup.xdagccore1);
1388                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a"
1389                                  " is %x\n", priv->initgain_backup.cca);
1390
1391                         rtl8192_phy_setTxPower(dev,
1392                                          priv->rtllib->current_network.channel);
1393
1394                         if (dm_digtable.dig_algorithm ==
1395                             DIG_ALGO_BY_FALSE_ALARM)
1396                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1397                         break;
1398                 default:
1399                         RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1400                         break;
1401                 }
1402         }
1403 }
1404
1405 void PHY_SetRtl8192eRfOff(struct net_device *dev)
1406 {
1407
1408         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1409         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1410         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1411         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1412         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1413         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1414         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1415         write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
1416
1417 }
1418
1419 static bool SetRFPowerState8190(struct net_device *dev,
1420                                 enum rt_rf_power_state eRFPowerState)
1421 {
1422         struct r8192_priv *priv = rtllib_priv(dev);
1423         struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1424                                         (&(priv->rtllib->PowerSaveControl));
1425         bool bResult = true;
1426         u8      i = 0, QueueID = 0;
1427         struct rtl8192_tx_ring  *ring = NULL;
1428
1429         if (priv->SetRFPowerStateInProgress == true)
1430                 return false;
1431         RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
1432         priv->SetRFPowerStateInProgress = true;
1433
1434         switch (priv->rf_chip) {
1435         case RF_8256:
1436                 switch (eRFPowerState) {
1437                 case eRfOn:
1438                         RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n");
1439                         if ((priv->rtllib->eRFPowerState == eRfOff) &&
1440                              RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1441                                 bool rtstatus = true;
1442                                 u32 InitilizeCount = 3;
1443                                 do {
1444                                         InitilizeCount--;
1445                                         priv->RegRfOff = false;
1446                                         rtstatus = NicIFEnableNIC(dev);
1447                                 } while ((rtstatus != true) &&
1448                                          (InitilizeCount > 0));
1449
1450                                 if (rtstatus != true) {
1451                                         RT_TRACE(COMP_ERR, "%s():Initialize Ada"
1452                                                  "pter fail,return\n",
1453                                                  __func__);
1454                                         priv->SetRFPowerStateInProgress = false;
1455                                         return false;
1456                                 }
1457
1458                                 RT_CLEAR_PS_LEVEL(pPSC,
1459                                                   RT_RF_OFF_LEVL_HALT_NIC);
1460                         } else {
1461                                 write_nic_byte(dev, ANAPAR, 0x37);
1462                                 mdelay(1);
1463                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1464                                                  0x4, 0x1);
1465                                 priv->bHwRfOffAction = 0;
1466
1467                                 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE,
1468                                                  BIT4, 0x1);
1469                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4,
1470                                                  0x300, 0x3);
1471                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1472                                                  0x18, 0x3);
1473                                 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3,
1474                                                  0x3);
1475                                 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3,
1476                                                  0x3);
1477                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1478                                                  0x60, 0x3);
1479
1480                         }
1481
1482                         break;
1483
1484                 case eRfSleep:
1485                         if (priv->rtllib->eRFPowerState == eRfOff)
1486                                 break;
1487
1488
1489                         for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1490                                 ring = &priv->tx_ring[QueueID];
1491
1492                                 if (skb_queue_len(&ring->queue) == 0) {
1493                                         QueueID++;
1494                                         continue;
1495                                 } else {
1496                                         RT_TRACE((COMP_POWER|COMP_RF), "eRf Off"
1497                                                  "/Sleep: %d times TcbBusyQueue"
1498                                                  "[%d] !=0 before doze!\n",
1499                                                  (i+1), QueueID);
1500                                         udelay(10);
1501                                         i++;
1502                                 }
1503
1504                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1505                                         RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! "
1506                                                  "SetRFPowerState8190(): eRfOff"
1507                                                  ": %d times TcbBusyQueue[%d] "
1508                                                  "!= 0 !!!\n",
1509                                                  MAX_DOZE_WAITING_TIMES_9x,
1510                                                  QueueID);
1511                                         break;
1512                                 }
1513                         }
1514                         PHY_SetRtl8192eRfOff(dev);
1515                         break;
1516
1517                 case eRfOff:
1518                         RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/"
1519                                  "Sleep !\n");
1520
1521                         for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1522                                 ring = &priv->tx_ring[QueueID];
1523
1524                                 if (skb_queue_len(&ring->queue) == 0) {
1525                                         QueueID++;
1526                                         continue;
1527                                 } else {
1528                                         RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d"
1529                                                  " times TcbBusyQueue[%d] !=0 b"
1530                                                  "efore doze!\n", (i+1),
1531                                                  QueueID);
1532                                         udelay(10);
1533                                         i++;
1534                                 }
1535
1536                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1537                                         RT_TRACE(COMP_POWER, "\n\n\n SetZebra: "
1538                                                  "RFPowerState8185B(): eRfOff:"
1539                                                  " %d times TcbBusyQueue[%d] "
1540                                                  "!= 0 !!!\n",
1541                                                  MAX_DOZE_WAITING_TIMES_9x,
1542                                                  QueueID);
1543                                         break;
1544                                 }
1545                         }
1546
1547                         if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1548                             !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1549                                 NicIFDisableNIC(dev);
1550                                 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1551                         } else if (!(pPSC->RegRfPsLevel &
1552                                    RT_RF_OFF_LEVL_HALT_NIC)) {
1553                                 PHY_SetRtl8192eRfOff(dev);
1554                         }
1555
1556                         break;
1557
1558                 default:
1559                         bResult = false;
1560                         RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state"
1561                                  " to set: 0x%X!!!\n", eRFPowerState);
1562                         break;
1563                 }
1564
1565                 break;
1566
1567         default:
1568                 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1569                 break;
1570         }
1571
1572         if (bResult) {
1573                 priv->rtllib->eRFPowerState = eRFPowerState;
1574
1575                 switch (priv->rf_chip) {
1576                 case RF_8256:
1577                         break;
1578
1579                 default:
1580                         RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown "
1581                                  "RF type\n");
1582                         break;
1583                 }
1584         }
1585
1586         priv->SetRFPowerStateInProgress = false;
1587         RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n",
1588                  bResult);
1589         return bResult;
1590 }
1591
1592 bool SetRFPowerState(struct net_device *dev,
1593                      enum rt_rf_power_state eRFPowerState)
1594 {
1595         struct r8192_priv *priv = rtllib_priv(dev);
1596
1597         bool bResult = false;
1598
1599         RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n",
1600                  eRFPowerState);
1601         if (eRFPowerState == priv->rtllib->eRFPowerState &&
1602             priv->bHwRfOffAction == 0) {
1603                 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the "
1604                          "request for eRFPowerState(%d) is the same.\n",
1605                          eRFPowerState);
1606                 return bResult;
1607         }
1608
1609         bResult = SetRFPowerState8190(dev, eRFPowerState);
1610
1611         RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n",
1612                  bResult);
1613
1614         return bResult;
1615 }
1616
1617 void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation)
1618 {
1619         struct r8192_priv *priv = rtllib_priv(dev);
1620
1621         if (priv->up) {
1622                 switch (Operation) {
1623                 case SCAN_OPT_BACKUP:
1624                         priv->rtllib->InitialGainHandler(dev, IG_Backup);
1625                         break;
1626
1627                 case SCAN_OPT_RESTORE:
1628                         priv->rtllib->InitialGainHandler(dev, IG_Restore);
1629                         break;
1630
1631                 default:
1632                         RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
1633                         break;
1634                 }
1635         }
1636
1637 }