drivers/staging/rtl8192e/r8192E_dm.h

   1 /*****************************************************************************
   2  *      Copyright(c) 2007,  RealTEK Technology Inc. All Right Reserved.
   3  *
   4  * Module:              Hal819xUsbDM.h  (RTL8192  Header H File)
   5  *
   6  *
   7  * Note:                For dynamic control definition constant structure.
   8  *
   9  *
  10  * Export:
  11  *
  12  * Abbrev:
  13  *
  14  * History:
  15  *      Data            Who             Remark
  16  *      10/04/2007  MHC         Create initial version.
  17  *
  18  *****************************************************************************/
  19
  20 #ifndef __R8192UDM_H__
  21 #define __R8192UDM_H__
  22
  23 #define                 OFDM_Table_Length       19
  24 #define         CCK_Table_length        12
  25
  26 #define         DM_DIG_THRESH_HIGH                                      40
  27 #define         DM_DIG_THRESH_LOW                                       35
  28
  29 #define         DM_DIG_HIGH_PWR_THRESH_HIGH             75
  30 #define         DM_DIG_HIGH_PWR_THRESH_LOW              70
  31
  32 #define         BW_AUTO_SWITCH_HIGH_LOW                 25
  33 #define         BW_AUTO_SWITCH_LOW_HIGH                 30
  34
  35 #define         DM_check_fsync_time_interval                            500
  36
  37
  38 #define         DM_DIG_BACKOFF                          12
  39 #define         DM_DIG_MAX                                      0x36
  40 #define         DM_DIG_MIN                                      0x1c
  41 #define         DM_DIG_MIN_Netcore                      0x12
  42
  43 #define         RxPathSelection_SS_TH_low               30
  44 #define         RxPathSelection_diff_TH                 18
  45
  46 #define         RateAdaptiveTH_High                     50
  47 #define         RateAdaptiveTH_Low_20M          30
  48 #define         RateAdaptiveTH_Low_40M          10
  49 #define         VeryLowRSSI                                     15
  50 #define         CTSToSelfTHVal                                  35
  51
  52 //defined by vivi, for tx power track
  53 #define         E_FOR_TX_POWER_TRACK               300
  54 //Dynamic Tx Power Control Threshold
  55 #define         TX_POWER_NEAR_FIELD_THRESH_HIGH         68
  56 #define         TX_POWER_NEAR_FIELD_THRESH_LOW          62
  57 //added by amy for atheros AP
  58 #define         TX_POWER_ATHEROAP_THRESH_HIGH           78
  59 #define         TX_POWER_ATHEROAP_THRESH_LOW            72
  60
  61 //defined by vivi, for showing on UI. Newer firmware has changed to 0x1e0
  62 #define                 Current_Tx_Rate_Reg         0x1e0//0x1b8
  63 #define                 Initial_Tx_Rate_Reg         0x1e1 //0x1b9
  64 #define                 Tx_Retry_Count_Reg         0x1ac
  65 #define         RegC38_TH                                20
  66
  67 /* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
  68 typedef struct _dynamic_initial_gain_threshold_
  69 {
  70         u8              dig_enable_flag;
  71         u8              dig_algorithm;
  72         u8              dbg_mode;
  73         u8              dig_algorithm_switch;
  74
  75         long            rssi_low_thresh;
  76         long            rssi_high_thresh;
  77
  78         long            rssi_high_power_lowthresh;
  79         long            rssi_high_power_highthresh;
  80
  81         u8              dig_state;
  82         u8              dig_highpwr_state;
  83         u8              cur_connect_state;
  84         u8              pre_connect_state;
  85
  86         u8              curpd_thstate;
  87         u8              prepd_thstate;
  88         u8              curcs_ratio_state;
  89         u8              precs_ratio_state;
  90
  91         u32             pre_ig_value;
  92         u32             cur_ig_value;
  93
  94         u8              backoff_val;
  95         u8              rx_gain_range_max;
  96         u8              rx_gain_range_min;
  97         bool            initialgain_lowerbound_state;
  98
  99         long            rssi_val;
 100 }dig_t;
 101
 102 typedef enum tag_dynamic_init_gain_state_definition
 103 {
 104         DM_STA_DIG_OFF = 0,
 105         DM_STA_DIG_ON,
 106         DM_STA_DIG_MAX
 107 }dm_dig_sta_e;
 108
 109
 110 /* 2007/10/08 MH Define RATR state. */
 111 typedef enum tag_dynamic_ratr_state_definition
 112 {
 113         DM_RATR_STA_HIGH = 0,
 114         DM_RATR_STA_MIDDLE = 1,
 115         DM_RATR_STA_LOW = 2,
 116         DM_RATR_STA_MAX
 117 }dm_ratr_sta_e;
 118
 119 /* 2007/10/11 MH Define DIG operation type. */
 120 typedef enum tag_dynamic_init_gain_operation_type_definition
 121 {
 122         DIG_TYPE_THRESH_HIGH    = 0,
 123         DIG_TYPE_THRESH_LOW     = 1,
 124         DIG_TYPE_THRESH_HIGHPWR_HIGH    = 2,
 125         DIG_TYPE_THRESH_HIGHPWR_LOW     = 3,
 126         DIG_TYPE_DBG_MODE                               = 4,
 127         DIG_TYPE_RSSI                                           = 5,
 128         DIG_TYPE_ALGORITHM                              = 6,
 129         DIG_TYPE_BACKOFF                                        = 7,
 130         DIG_TYPE_PWDB_FACTOR                    = 8,
 131         DIG_TYPE_RX_GAIN_MIN                            = 9,
 132         DIG_TYPE_RX_GAIN_MAX                            = 10,
 133         DIG_TYPE_ENABLE                 = 20,
 134         DIG_TYPE_DISABLE                = 30,
 135         DIG_OP_TYPE_MAX
 136 }dm_dig_op_e;
 137
 138 typedef enum tag_dig_algorithm_definition
 139 {
 140         DIG_ALGO_BY_FALSE_ALARM = 0,
 141         DIG_ALGO_BY_RSSI        = 1,
 142         DIG_ALGO_MAX
 143 }dm_dig_alg_e;
 144
 145 typedef enum tag_dig_dbgmode_definition
 146 {
 147         DIG_DBG_OFF = 0,
 148         DIG_DBG_ON = 1,
 149         DIG_DBG_MAX
 150 }dm_dig_dbg_e;
 151
 152 typedef enum tag_dig_connect_definition
 153 {
 154         DIG_DISCONNECT = 0,
 155         DIG_CONNECT = 1,
 156         DIG_CONNECT_MAX
 157 }dm_dig_connect_e;
 158
 159 typedef enum tag_dig_packetdetection_threshold_definition
 160 {
 161         DIG_PD_AT_LOW_POWER = 0,
 162         DIG_PD_AT_NORMAL_POWER = 1,
 163         DIG_PD_AT_HIGH_POWER = 2,
 164         DIG_PD_MAX
 165 }dm_dig_pd_th_e;
 166
 167 typedef enum tag_dig_cck_cs_ratio_state_definition
 168 {
 169         DIG_CS_RATIO_LOWER = 0,
 170         DIG_CS_RATIO_HIGHER = 1,
 171         DIG_CS_MAX
 172 }dm_dig_cs_ratio_e;
 173 typedef struct _Dynamic_Rx_Path_Selection_
 174 {
 175         u8              Enable;
 176         u8              DbgMode;
 177         u8              cck_method;
 178         u8              cck_Rx_path;
 179
 180         u8              SS_TH_low;
 181         u8              diff_TH;
 182         u8              disabledRF;
 183         u8              reserved;
 184
 185         u8              rf_rssi[4];
 186         u8              rf_enable_rssi_th[4];
 187         long            cck_pwdb_sta[4];
 188 }DRxPathSel;
 189
 190 typedef enum tag_CCK_Rx_Path_Method_Definition
 191 {
 192         CCK_Rx_Version_1 = 0,
 193         CCK_Rx_Version_2= 1,
 194         CCK_Rx_Version_MAX
 195 }DM_CCK_Rx_Path_Method;
 196
 197 typedef enum tag_DM_DbgMode_Definition
 198 {
 199         DM_DBG_OFF = 0,
 200         DM_DBG_ON = 1,
 201         DM_DBG_MAX
 202 }DM_DBG_E;
 203
 204 typedef struct tag_Tx_Config_Cmd_Format
 205 {
 206         u32     Op;                                                                             /* Command packet type. */
 207         u32     Length;                                                                 /* Command packet length. */
 208         u32     Value;
 209 }DCMD_TXCMD_T, *PDCMD_TXCMD_T;
 210
 211
 212 extern dig_t dm_digtable;
 213 extern DRxPathSel DM_RxPathSelTable;
 214
 215 void init_hal_dm(struct r8192_priv *priv);
 216 void deinit_hal_dm(struct r8192_priv *priv);
 217
 218 void hal_dm_watchdog(struct r8192_priv *priv);
 219
 220 void init_rate_adaptive(struct r8192_priv *priv);
 221 void dm_txpower_trackingcallback(struct work_struct *work);
 222 void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
 223 void dm_initialize_txpower_tracking(struct r8192_priv *priv);
 224 void dm_cck_txpower_adjust(struct r8192_priv *priv, bool binch14);
 225
 226
 227 #endif  /*__R8192UDM_H__ */
 228