drivers/staging/rt2860/pci_main_dev.c

   1 /*
   2  *************************************************************************
   3  * Ralink Tech Inc.
   4  * 5F., No.36, Taiyuan St., Jhubei City,
   5  * Hsinchu County 302,
   6  * Taiwan, R.O.C.
   7  *
   8  * (c) Copyright 2002-2007, Ralink Technology, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify  *
  11  * it under the terms of the GNU General Public License as published by  *
  12  * the Free Software Foundation; either version 2 of the License, or     *
  13  * (at your option) any later version.                                   *
  14  *                                                                       *
  15  * This program is distributed in the hope that it will be useful,       *
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  * GNU General Public License for more details.                          *
  19  *                                                                       *
  20  * You should have received a copy of the GNU General Public License     *
  21  * along with this program; if not, write to the                         *
  22  * Free Software Foundation, Inc.,                                       *
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  *                                                                       *
  25  *************************************************************************
  26
  27     Module Name:
  28     pci_main_dev.c
  29
  30     Abstract:
  31     Create and register network interface for PCI based chipsets in Linux platform.
  32
  33     Revision History:
  34     Who         When            What
  35     --------    ----------      ----------------------------------------------
  36 */
  37
  38 #include "rt_config.h"
  39 #include <linux/pci.h>
  40
  41 //
  42 // Function declarations
  43 //
  44 extern int rt28xx_close(IN struct net_device *net_dev);
  45 extern int rt28xx_open(struct net_device *net_dev);
  46
  47 static VOID __devexit rt2860_remove_one(struct pci_dev *pci_dev);
  48 static INT __devinit rt2860_probe(struct pci_dev *pci_dev, const struct pci_device_id  *ent);
  49 static void __exit rt2860_cleanup_module(void);
  50 static int __init rt2860_init_module(void);
  51
  52  static VOID RTMPInitPCIeDevice(
  53     IN  struct pci_dev   *pci_dev,
  54     IN PRTMP_ADAPTER     pAd);
  55
  56 #ifdef CONFIG_PM
  57 static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state);
  58 static int rt2860_resume(struct pci_dev *pci_dev);
  59 #endif // CONFIG_PM //
  60
  61 //
  62 // Ralink PCI device table, include all supported chipsets
  63 //
  64 static struct pci_device_id rt2860_pci_tbl[] __devinitdata =
  65 {
  66         {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCI_DEVICE_ID)},         //RT28602.4G
  67         {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCIe_DEVICE_ID)},
  68         {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2760_PCI_DEVICE_ID)},
  69         {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2790_PCIe_DEVICE_ID)},
  70         {PCI_DEVICE(VEN_AWT_PCI_VENDOR_ID, VEN_AWT_PCIe_DEVICE_ID)},
  71         {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7708)},
  72         {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7728)},
  73         {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7758)},
  74         {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7727)},
  75         {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7738)},
  76         {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7748)},
  77         {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7768)},
  78     {0,}                // terminate list
  79 };
  80
  81 MODULE_DEVICE_TABLE(pci, rt2860_pci_tbl);
  82 MODULE_LICENSE("GPL");
  83 #ifdef MODULE_VERSION
  84 MODULE_VERSION(STA_DRIVER_VERSION);
  85 #endif
  86
  87
  88 //
  89 // Our PCI driver structure
  90 //
  91 static struct pci_driver rt2860_driver =
  92 {
  93     name:       "rt2860",
  94     id_table:   rt2860_pci_tbl,
  95     probe:      rt2860_probe,
  96     remove:     __devexit_p(rt2860_remove_one),
  97 #ifdef CONFIG_PM
  98         suspend:        rt2860_suspend,
  99         resume:         rt2860_resume,
 100 #endif
 101 };
 102
 103
 104 /***************************************************************************
 105  *
 106  *      PCI device initialization related procedures.
 107  *
 108  ***************************************************************************/
 109 #ifdef CONFIG_PM
 110
 111 VOID RT2860RejectPendingPackets(
 112         IN      PRTMP_ADAPTER   pAd)
 113 {
 114         // clear PS packets
 115         // clear TxSw packets
 116 }
 117
 118 static int rt2860_suspend(
 119         struct pci_dev *pci_dev,
 120         pm_message_t state)
 121 {
 122         struct net_device *net_dev = pci_get_drvdata(pci_dev);
 123         PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)NULL;
 124         INT32 retval = 0;
 125
 126
 127         DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_suspend()\n"));
 128
 129         if (net_dev == NULL)
 130         {
 131                 DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n"));
 132         }
 133         else
 134         {
 135                 GET_PAD_FROM_NET_DEV(pAd, net_dev);
 136
 137                 /* we can not use IFF_UP because ra0 down but ra1 up */
 138                 /* and 1 suspend/resume function for 1 module, not for each interface */
 139                 /* so Linux will call suspend/resume function once */
 140                 if (VIRTUAL_IF_NUM(pAd) > 0)
 141                 {
 142                         // avoid users do suspend after interface is down
 143
 144                         // stop interface
 145                         netif_carrier_off(net_dev);
 146                         netif_stop_queue(net_dev);
 147
 148                         // mark device as removed from system and therefore no longer available
 149                         netif_device_detach(net_dev);
 150
 151                         // mark halt flag
 152                         RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
 153                         RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
 154
 155                         // take down the device
 156                         rt28xx_close((PNET_DEV)net_dev);
 157
 158                         RT_MOD_DEC_USE_COUNT();
 159                 }
 160         }
 161
 162         // reference to http://vovo2000.com/type-lab/linux/kernel-api/linux-kernel-api.html
 163         // enable device to generate PME# when suspended
 164         // pci_choose_state(): Choose the power state of a PCI device to be suspended
 165         retval = pci_enable_wake(pci_dev, pci_choose_state(pci_dev, state), 1);
 166         // save the PCI configuration space of a device before suspending
 167         pci_save_state(pci_dev);
 168         // disable PCI device after use
 169         pci_disable_device(pci_dev);
 170
 171         retval = pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
 172
 173         DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_suspend()\n"));
 174         return retval;
 175 }
 176
 177 static int rt2860_resume(
 178         struct pci_dev *pci_dev)
 179 {
 180         struct net_device *net_dev = pci_get_drvdata(pci_dev);
 181         PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)NULL;
 182         INT32 retval;
 183
 184
 185         // set the power state of a PCI device
 186         // PCI has 4 power states, DO (normal) ~ D3(less power)
 187         // in include/linux/pci.h, you can find that
 188         // #define PCI_D0          ((pci_power_t __force) 0)
 189         // #define PCI_D1          ((pci_power_t __force) 1)
 190         // #define PCI_D2          ((pci_power_t __force) 2)
 191         // #define PCI_D3hot       ((pci_power_t __force) 3)
 192         // #define PCI_D3cold      ((pci_power_t __force) 4)
 193         // #define PCI_UNKNOWN     ((pci_power_t __force) 5)
 194         // #define PCI_POWER_ERROR ((pci_power_t __force) -1)
 195         retval = pci_set_power_state(pci_dev, PCI_D0);
 196
 197         // restore the saved state of a PCI device
 198         pci_restore_state(pci_dev);
 199
 200         // initialize device before it's used by a driver
 201         if (pci_enable_device(pci_dev))
 202         {
 203                 printk("pci enable fail!\n");
 204                 return 0;
 205         }
 206
 207         DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_resume()\n"));
 208
 209         if (net_dev == NULL)
 210         {
 211                 DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n"));
 212         }
 213         else
 214                 GET_PAD_FROM_NET_DEV(pAd, net_dev);
 215
 216         if (pAd != NULL)
 217         {
 218                 /* we can not use IFF_UP because ra0 down but ra1 up */
 219                 /* and 1 suspend/resume function for 1 module, not for each interface */
 220                 /* so Linux will call suspend/resume function once */
 221                 if (VIRTUAL_IF_NUM(pAd) > 0)
 222                 {
 223                         // mark device as attached from system and restart if needed
 224                         netif_device_attach(net_dev);
 225
 226                         if (rt28xx_open((PNET_DEV)net_dev) != 0)
 227                         {
 228                                 // open fail
 229                                 DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_resume()\n"));
 230                                 return 0;
 231                         }
 232
 233                         // increase MODULE use count
 234                         RT_MOD_INC_USE_COUNT();
 235
 236                         RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
 237                         RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
 238
 239                         netif_start_queue(net_dev);
 240                         netif_carrier_on(net_dev);
 241                         netif_wake_queue(net_dev);
 242                 }
 243         }
 244
 245         DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_resume()\n"));
 246         return 0;
 247 }
 248 #endif // CONFIG_PM //
 249
 250
 251 static INT __init rt2860_init_module(VOID)
 252 {
 253         return pci_register_driver(&rt2860_driver);
 254 }
 255
 256
 257 //
 258 // Driver module unload function
 259 //
 260 static VOID __exit rt2860_cleanup_module(VOID)
 261 {
 262     pci_unregister_driver(&rt2860_driver);
 263 }
 264
 265 module_init(rt2860_init_module);
 266 module_exit(rt2860_cleanup_module);
 267
 268
 269 //
 270 // PCI device probe & initialization function
 271 //
 272 static INT __devinit   rt2860_probe(
 273     IN  struct pci_dev              *pci_dev,
 274     IN  const struct pci_device_id  *pci_id)
 275 {
 276         PRTMP_ADAPTER           pAd = (PRTMP_ADAPTER)NULL;
 277         struct  net_device              *net_dev;
 278         PVOID                           handle;
 279         PSTRING                         print_name;
 280         ULONG                           csr_addr;
 281         INT rv = 0;
 282         RTMP_OS_NETDEV_OP_HOOK  netDevHook;
 283
 284         DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_probe\n"));
 285
 286 //PCIDevInit==============================================
 287         // wake up and enable device
 288         if ((rv = pci_enable_device(pci_dev))!= 0)
 289         {
 290                 DBGPRINT(RT_DEBUG_ERROR, ("Enable PCI device failed, errno=%d!\n", rv));
 291                 return rv;
 292         }
 293
 294         print_name = pci_name(pci_dev);
 295
 296         if ((rv = pci_request_regions(pci_dev, print_name)) != 0)
 297         {
 298                 DBGPRINT(RT_DEBUG_ERROR, ("Request PCI resource failed, errno=%d!\n", rv));
 299                 goto err_out;
 300         }
 301
 302         // map physical address to virtual address for accessing register
 303         csr_addr = (unsigned long) ioremap(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0));
 304         if (!csr_addr)
 305         {
 306                 DBGPRINT(RT_DEBUG_ERROR, ("ioremap failed for device %s, region 0x%lX @ 0x%lX\n",
 307                                         print_name, (ULONG)pci_resource_len(pci_dev, 0), (ULONG)pci_resource_start(pci_dev, 0)));
 308                 goto err_out_free_res;
 309         }
 310         else
 311         {
 312                 DBGPRINT(RT_DEBUG_TRACE, ("%s: at 0x%lx, VA 0x%lx, IRQ %d. \n",  print_name,
 313                                         (ULONG)pci_resource_start(pci_dev, 0), (ULONG)csr_addr, pci_dev->irq));
 314         }
 315
 316         // Set DMA master
 317         pci_set_master(pci_dev);
 318
 319
 320 //RtmpDevInit==============================================
 321         // Allocate RTMP_ADAPTER adapter structure
 322         handle = kmalloc(sizeof(struct os_cookie), GFP_KERNEL);
 323         if (handle == NULL)
 324         {
 325                 DBGPRINT(RT_DEBUG_ERROR, ("%s(): Allocate memory for os handle failed!\n", __func__));
 326                 goto err_out_iounmap;
 327         }
 328
 329         ((POS_COOKIE)handle)->pci_dev = pci_dev;
 330
 331         rv = RTMPAllocAdapterBlock(handle, &pAd);       //shiang: we may need the pci_dev for allocate structure of "RTMP_ADAPTER"
 332         if (rv != NDIS_STATUS_SUCCESS)
 333                 goto err_out_iounmap;
 334         // Here are the RTMP_ADAPTER structure with pci-bus specific parameters.
 335         pAd->CSRBaseAddress = (PUCHAR)csr_addr;
 336         DBGPRINT(RT_DEBUG_ERROR, ("pAd->CSRBaseAddress =0x%lx, csr_addr=0x%lx!\n", (ULONG)pAd->CSRBaseAddress, csr_addr));
 337         RtmpRaDevCtrlInit(pAd, RTMP_DEV_INF_PCI);
 338
 339
 340 //NetDevInit==============================================
 341         net_dev = RtmpPhyNetDevInit(pAd, &netDevHook);
 342         if (net_dev == NULL)
 343                 goto err_out_free_radev;
 344
 345         // Here are the net_device structure with pci-bus specific parameters.
 346         net_dev->irq = pci_dev->irq;            // Interrupt IRQ number
 347         net_dev->base_addr = csr_addr;          // Save CSR virtual address and irq to device structure
 348         pci_set_drvdata(pci_dev, net_dev);      // Set driver data
 349
 350 /* for supporting Network Manager */
 351         /* Set the sysfs physical device reference for the network logical device
 352           * if set prior to registration will cause a symlink during initialization.
 353          */
 354         SET_NETDEV_DEV(net_dev, &(pci_dev->dev));
 355
 356
 357 //All done, it's time to register the net device to linux kernel.
 358         // Register this device
 359         rv = RtmpOSNetDevAttach(net_dev, &netDevHook);
 360         if (rv)
 361                 goto err_out_free_netdev;
 362
 363         pAd->StaCfg.OriDevType = net_dev->type;
 364         RTMPInitPCIeDevice(pci_dev, pAd);
 365
 366 #ifdef KTHREAD_SUPPORT
 367 #endif // KTHREAD_SUPPORT //
 368
 369         DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_probe\n"));
 370
 371         return 0; // probe ok
 372
 373
 374         /* --------------------------- ERROR HANDLE --------------------------- */
 375 err_out_free_netdev:
 376         RtmpOSNetDevFree(net_dev);
 377
 378 err_out_free_radev:
 379         /* free RTMP_ADAPTER strcuture and os_cookie*/
 380         RTMPFreeAdapter(pAd);
 381
 382 err_out_iounmap:
 383         iounmap((void *)(csr_addr));
 384         release_mem_region(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0));
 385
 386 err_out_free_res:
 387         pci_release_regions(pci_dev);
 388
 389 err_out:
 390         pci_disable_device(pci_dev);
 391
 392         DBGPRINT(RT_DEBUG_ERROR, ("<=== rt2860_probe failed with rv = %d!\n", rv));
 393
 394         return -ENODEV; /* probe fail */
 395 }
 396
 397
 398 static VOID __devexit rt2860_remove_one(
 399     IN  struct pci_dev  *pci_dev)
 400 {
 401         PNET_DEV        net_dev = pci_get_drvdata(pci_dev);
 402         RTMP_ADAPTER    *pAd = NULL;
 403         ULONG                   csr_addr = net_dev->base_addr; // pAd->CSRBaseAddress;
 404
 405         GET_PAD_FROM_NET_DEV(pAd, net_dev);
 406
 407     DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_remove_one\n"));
 408
 409         if (pAd != NULL)
 410         {
 411                 // Unregister/Free all allocated net_device.
 412                 RtmpPhyNetDevExit(pAd, net_dev);
 413
 414                 // Unmap CSR base address
 415                 iounmap((char *)(csr_addr));
 416
 417                 // release memory region
 418                 release_mem_region(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0));
 419
 420                 // Free RTMP_ADAPTER related structures.
 421                 RtmpRaDevCtrlExit(pAd);
 422
 423         }
 424         else
 425         {
 426                 // Unregister network device
 427                 RtmpOSNetDevDetach(net_dev);
 428
 429                 // Unmap CSR base address
 430                 iounmap((char *)(net_dev->base_addr));
 431
 432                 // release memory region
 433                 release_mem_region(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0));
 434         }
 435
 436         // Free the root net_device
 437         RtmpOSNetDevFree(net_dev);
 438
 439 }
 440
 441
 442 /*
 443 ========================================================================
 444 Routine Description:
 445     Check the chipset vendor/product ID.
 446
 447 Arguments:
 448     _dev_p                              Point to the PCI or USB device
 449
 450 Return Value:
 451     TRUE                                Check ok
 452         FALSE                           Check fail
 453
 454 Note:
 455 ========================================================================
 456 */
 457 BOOLEAN RT28XXChipsetCheck(
 458         IN void *_dev_p)
 459 {
 460         /* always TRUE */
 461         return TRUE;
 462 }
 463
 464
 465 /***************************************************************************
 466  *
 467  *      PCIe device initialization related procedures.
 468  *
 469  ***************************************************************************/
 470  static VOID RTMPInitPCIeDevice(
 471     IN  struct pci_dev   *pci_dev,
 472     IN PRTMP_ADAPTER     pAd)
 473 {
 474         USHORT  device_id;
 475         POS_COOKIE pObj;
 476
 477         pObj = (POS_COOKIE) pAd->OS_Cookie;
 478         pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id);
 479         device_id = le2cpu16(device_id);
 480         pObj->DeviceID = device_id;
 481         OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE);
 482         if (
 483                 (device_id == NIC2860_PCIe_DEVICE_ID) ||
 484                 (device_id == NIC2790_PCIe_DEVICE_ID) ||
 485                 (device_id == VEN_AWT_PCIe_DEVICE_ID) ||
 486                  0)
 487         {
 488                 UINT32 MacCsr0 = 0, Index= 0;
 489                 do
 490                 {
 491                         RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
 492
 493                         if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF))
 494                                 break;
 495
 496                         RTMPusecDelay(10);
 497                 } while (Index++ < 100);
 498
 499                 // Support advanced power save after 2892/2790.
 500                 // MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO).
 501                 if ((MacCsr0&0xffff0000) != 0x28600000)
 502                 {
 503                         OPSTATUS_SET_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE);
 504                 }
 505         }
 506 }
 507
 508
 509 VOID RTMPInitPCIeLinkCtrlValue(
 510         IN      PRTMP_ADAPTER   pAd)
 511 {
 512     INT     pos;
 513     USHORT      reg16, data2, PCIePowerSaveLevel, Configuration;
 514     BOOLEAN     bFindIntel = FALSE;
 515         POS_COOKIE pObj;
 516
 517         pObj = (POS_COOKIE) pAd->OS_Cookie;
 518
 519         if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
 520                 return;
 521
 522     DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
 523         // Init EEPROM, and save settings
 524         if (!IS_RT3090(pAd))
 525         {
 526                 RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
 527                 pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff;
 528
 529                 if ((PCIePowerSaveLevel&0xff) == 0xff)
 530                 {
 531                         OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE);
 532                         DBGPRINT(RT_DEBUG_TRACE, ("====> PCIePowerSaveLevel = 0x%x.\n", PCIePowerSaveLevel));
 533                         return;
 534                 }
 535         else
 536         {
 537                 PCIePowerSaveLevel &= 0x3;
 538                 RT28xx_EEPROM_READ16(pAd, 0x24, data2);
 539
 540                 if( !(((data2&0xff00) == 0x9200) && ((data2&0x80) !=0)) )
 541                 {
 542                         if (PCIePowerSaveLevel > 1 )
 543                                 PCIePowerSaveLevel = 1;
 544                 }
 545
 546                 DBGPRINT(RT_DEBUG_TRACE, ("====> Write 0x83 = 0x%x.\n", PCIePowerSaveLevel));
 547                 AsicSendCommandToMcu(pAd, 0x83, 0xff, (UCHAR)PCIePowerSaveLevel, 0x00);
 548                 RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
 549                 PCIePowerSaveLevel &= 0xff;
 550                 PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
 551                 switch(PCIePowerSaveLevel)
 552                 {
 553                                 case 0: // Only support L0
 554                                         pAd->LnkCtrlBitMask = 0;
 555                                 break;
 556                                 case 1: // Only enable L0s
 557                                         pAd->LnkCtrlBitMask = 1;
 558                                 break;
 559                                 case 2: // enable L1, L0s
 560                                         pAd->LnkCtrlBitMask = 3;
 561                                 break;
 562                                 case 3: // sync with host clk and enable L1, L0s
 563                                 pAd->LnkCtrlBitMask = 0x103;
 564                                 break;
 565                 }
 566                 DBGPRINT(RT_DEBUG_TRACE, ("====> LnkCtrlBitMask = 0x%x.\n", pAd->LnkCtrlBitMask));
 567         }
 568         }
 569         else if (IS_RT3090(pAd))
 570         {
 571                 // 1. read setting from inf file.
 572                 // .....
 573                 USHORT  PCIePowerSetting = 0;
 574                 /* code from windows, default value of rt30xxPowerMode = 0
 575                 PCIePowerSetting = pAd->StaCfg.PSControl.field.rt30xxPowerMode;
 576                 */
 577                 DBGPRINT(RT_DEBUG_TRACE, ("====> rt30xx Read PowerLevelMode =  0x%x.\n", PCIePowerSetting));
 578                 // 2. Check EnableNewPS
 579                 /*
 580                 if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
 581                         PCIePowerSetting = 1;
 582                 */
 583
 584                 if ((pAd->MACVersion&0xffff) <= 0x0211)
 585                 {
 586                         // Chip Version E only allow 1
 587                         PCIePowerSetting = 1;
 588                         DBGPRINT(RT_DEBUG_TRACE, ("====> rt30xx Write 0x83 Command = 0x%x.\n", PCIePowerSetting));
 589                         AsicSendCommandToMcu(pAd, 0x83, 0xff, (UCHAR)PCIePowerSetting, 0x00);
 590                 }
 591                 else
 592                 {
 593                         // Chip Version F only allow 1 or 2
 594                         if ((PCIePowerSetting > 2) || (PCIePowerSetting == 0))
 595                                 PCIePowerSetting = 1;
 596                         DBGPRINT(RT_DEBUG_TRACE, ("====> rt30xx Write 0x83 Command = 0x%x.\n", PCIePowerSetting));
 597                         AsicSendCommandToMcu(pAd, 0x83, 0xff, (UCHAR)PCIePowerSetting, 0x00);
 598                 }
 599
 600         }
 601
 602     // Find Ralink PCIe Device's Express Capability Offset
 603         pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
 604
 605     if (pos != 0)
 606     {
 607         // Ralink PCIe Device's Link Control Register Offset
 608         pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
 609         pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset, &reg16);
 610         Configuration = le2cpu16(reg16);
 611         DBGPRINT(RT_DEBUG_TRACE, ("Read (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
 612                                     pAd->RLnkCtrlOffset, Configuration));
 613         pAd->RLnkCtrlConfiguration = (Configuration & 0x103);
 614         Configuration &= 0xfefc;
 615         Configuration |= (0x0);
 616                 if ((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
 617                         ||(pObj->DeviceID == NIC2790_PCIe_DEVICE_ID))
 618                 {
 619                         reg16 = cpu2le16(Configuration);
 620                         pci_write_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset, reg16);
 621                         DBGPRINT(RT_DEBUG_TRACE, ("Write (Ralink PCIe Link Control Register)  offset 0x%x = 0x%x\n",
 622                                     pos + PCI_EXP_LNKCTL, Configuration));
 623                 }
 624
 625         RTMPFindHostPCIDev(pAd);
 626         if (pObj->parent_pci_dev)
 627         {
 628                 USHORT  vendor_id;
 629
 630                 pci_read_config_word(pObj->parent_pci_dev, PCI_VENDOR_ID, &vendor_id);
 631                 vendor_id = le2cpu16(vendor_id);
 632                 if (vendor_id == PCIBUS_INTEL_VENDOR)
 633                         bFindIntel = TRUE;
 634
 635                 // Find PCI-to-PCI Bridge Express Capability Offset
 636                 pos = pci_find_capability(pObj->parent_pci_dev, PCI_CAP_ID_EXP);
 637
 638                 if (pos != 0)
 639                 {
 640                         BOOLEAN         bChange = FALSE;
 641                         // PCI-to-PCI Bridge Link Control Register Offset
 642                         pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
 643                         pci_read_config_word(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset, &reg16);
 644                         Configuration = le2cpu16(reg16);
 645                         DBGPRINT(RT_DEBUG_TRACE, ("Read (Host PCI-to-PCI Bridge Link Control Register) offset 0x%x = 0x%x\n",
 646                                                     pAd->HostLnkCtrlOffset, Configuration));
 647                         pAd->HostLnkCtrlConfiguration = (Configuration & 0x103);
 648                         Configuration &= 0xfefc;
 649                         Configuration |= (0x0);
 650
 651                         switch (pObj->DeviceID)
 652                         {
 653                                 case NIC2860_PCIe_DEVICE_ID:
 654                                 case NIC2790_PCIe_DEVICE_ID:
 655                                         bChange = TRUE;
 656                                         break;
 657                                 default:
 658                                         break;
 659                         }
 660
 661                         if (bChange)
 662                         {
 663                                 reg16 = cpu2le16(Configuration);
 664                                 pci_write_config_word(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset, reg16);
 665                                 DBGPRINT(RT_DEBUG_TRACE, ("Write (Host PCI-to-PCI Bridge Link Control Register) offset 0x%x = 0x%x\n",
 666                                                 pAd->HostLnkCtrlOffset, Configuration));
 667                         }
 668                 }
 669                 else
 670                 {
 671                         pAd->HostLnkCtrlOffset = 0;
 672                         DBGPRINT(RT_DEBUG_ERROR, ("%s: cannot find PCI-to-PCI Bridge PCI Express Capability!\n", __func__));
 673                 }
 674         }
 675     }
 676     else
 677     {
 678         pAd->RLnkCtrlOffset = 0;
 679         pAd->HostLnkCtrlOffset = 0;
 680         DBGPRINT(RT_DEBUG_ERROR, ("%s: cannot find Ralink PCIe Device's PCI Express Capability!\n", __func__));
 681     }
 682
 683     if (bFindIntel == FALSE)
 684         {
 685                 DBGPRINT(RT_DEBUG_TRACE, ("Doesn't find Intel PCI host controller. \n"));
 686                 // Doesn't switch L0, L1, So set PCIePowerSaveLevel to 0xff
 687                 pAd->PCIePowerSaveLevel = 0xff;
 688                 if ((pAd->RLnkCtrlOffset != 0)
 689                 )
 690                 {
 691                         pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset, &reg16);
 692                         Configuration = le2cpu16(reg16);
 693                         DBGPRINT(RT_DEBUG_TRACE, ("Read (Ralink 30xx PCIe Link Control Register) offset 0x%x = 0x%x\n",
 694                                                 pAd->RLnkCtrlOffset, Configuration));
 695                         pAd->RLnkCtrlConfiguration = (Configuration & 0x103);
 696                         Configuration &= 0xfefc;
 697                         Configuration |= (0x0);
 698                         reg16 = cpu2le16(Configuration);
 699                         pci_write_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset, reg16);
 700                         DBGPRINT(RT_DEBUG_TRACE, ("Write (Ralink PCIe Link Control Register)  offset 0x%x = 0x%x\n",
 701                                                 pos + PCI_EXP_LNKCTL, Configuration));
 702                 }
 703         }
 704 }
 705
 706 VOID RTMPFindHostPCIDev(
 707     IN  PRTMP_ADAPTER   pAd)
 708 {
 709     USHORT  reg16;
 710     UCHAR   reg8;
 711         UINT    DevFn;
 712     PPCI_DEV    pPci_dev;
 713         POS_COOKIE      pObj;
 714
 715         pObj = (POS_COOKIE) pAd->OS_Cookie;
 716
 717         if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
 718                 return;
 719
 720     DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
 721
 722     pObj->parent_pci_dev = NULL;
 723     if (pObj->pci_dev->bus->parent)
 724     {
 725         for (DevFn = 0; DevFn < 255; DevFn++)
 726         {
 727             pPci_dev = pci_get_slot(pObj->pci_dev->bus->parent, DevFn);
 728             if (pPci_dev)
 729             {
 730                 pci_read_config_word(pPci_dev, PCI_CLASS_DEVICE, &reg16);
 731                 reg16 = le2cpu16(reg16);
 732                 pci_read_config_byte(pPci_dev, PCI_CB_CARD_BUS, &reg8);
 733                 if ((reg16 == PCI_CLASS_BRIDGE_PCI) &&
 734                     (reg8 == pObj->pci_dev->bus->number))
 735                 {
 736                     pObj->parent_pci_dev = pPci_dev;
 737                 }
 738             }
 739         }
 740     }
 741 }
 742
 743 /*
 744         ========================================================================
 745
 746         Routine Description:
 747
 748         Arguments:
 749                 Level = RESTORE_HALT : Restore PCI host and Ralink PCIe Link Control field to its default value.
 750                 Level = Other Value : Restore from dot11 power save or radio off status. And force PCI host Link Control fields to 0x1
 751
 752         ========================================================================
 753 */
 754 VOID RTMPPCIeLinkCtrlValueRestore(
 755         IN      PRTMP_ADAPTER   pAd,
 756         IN   UCHAR              Level)
 757 {
 758         USHORT  PCIePowerSaveLevel, reg16;
 759         USHORT  Configuration;
 760         POS_COOKIE      pObj;
 761
 762         pObj = (POS_COOKIE) pAd->OS_Cookie;
 763
 764         if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
 765                 return;
 766
 767         if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
 768                 ||(pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
 769                 return;
 770
 771         DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
 772         PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
 773         if ((PCIePowerSaveLevel&0xff) == 0xff)
 774         {
 775                 DBGPRINT(RT_DEBUG_TRACE,("return  \n"));
 776                 return;
 777         }
 778
 779         if (pObj->parent_pci_dev && (pAd->HostLnkCtrlOffset != 0))
 780     {
 781         PCI_REG_READ_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset, Configuration);
 782         if ((Configuration != 0) &&
 783             (Configuration != 0xFFFF))
 784         {
 785                 Configuration &= 0xfefc;
 786                 // If call from interface down, restore to orginial setting.
 787                 if (Level == RESTORE_CLOSE)
 788                 {
 789                         Configuration |= pAd->HostLnkCtrlConfiguration;
 790                 }
 791                 else
 792                         Configuration |= 0x0;
 793             PCI_REG_WIRTE_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset, Configuration);
 794                 DBGPRINT(RT_DEBUG_TRACE, ("Restore PCI host : offset 0x%x = 0x%x\n", pAd->HostLnkCtrlOffset, Configuration));
 795         }
 796         else
 797             DBGPRINT(RT_DEBUG_ERROR, ("Restore PCI host : PCI_REG_READ_WORD failed (Configuration = 0x%x)\n", Configuration));
 798     }
 799
 800     if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0))
 801     {
 802         PCI_REG_READ_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset, Configuration);
 803         if ((Configuration != 0) &&
 804             (Configuration != 0xFFFF))
 805         {
 806                 Configuration &= 0xfefc;
 807                         // If call from interface down, restore to orginial setting.
 808                         if (Level == RESTORE_CLOSE)
 809                 Configuration |= pAd->RLnkCtrlConfiguration;
 810                         else
 811                                 Configuration |= 0x0;
 812             PCI_REG_WIRTE_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset, Configuration);
 813                 DBGPRINT(RT_DEBUG_TRACE, ("Restore Ralink : offset 0x%x = 0x%x\n", pAd->RLnkCtrlOffset, Configuration));
 814         }
 815         else
 816             DBGPRINT(RT_DEBUG_ERROR, ("Restore Ralink : PCI_REG_READ_WORD failed (Configuration = 0x%x)\n", Configuration));
 817         }
 818
 819         DBGPRINT(RT_DEBUG_TRACE,("%s <===\n", __func__));
 820 }
 821
 822 /*
 823         ========================================================================
 824
 825         Routine Description:
 826
 827         Arguments:
 828                 Max : limit Host PCI and Ralink PCIe device's LINK CONTROL field's value.
 829                 Because now frequently set our device to mode 1 or mode 3 will cause problem.
 830
 831         ========================================================================
 832 */
 833 VOID RTMPPCIeLinkCtrlSetting(
 834         IN      PRTMP_ADAPTER   pAd,
 835         IN      USHORT          Max)
 836 {
 837         USHORT  PCIePowerSaveLevel, reg16;
 838         USHORT  Configuration;
 839         POS_COOKIE      pObj;
 840
 841         pObj = (POS_COOKIE) pAd->OS_Cookie;
 842
 843         if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
 844                 return;
 845
 846         if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
 847                 ||(pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
 848                 return;
 849
 850         DBGPRINT(RT_DEBUG_TRACE,("%s===>\n", __func__));
 851         PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
 852         if ((PCIePowerSaveLevel&0xff) == 0xff)
 853         {
 854                 DBGPRINT(RT_DEBUG_TRACE,("return  \n"));
 855                 return;
 856         }
 857         PCIePowerSaveLevel = PCIePowerSaveLevel>>6;
 858
 859
 860         if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0))
 861         {
 862                 // first 2892 chip not allow to frequently set mode 3. will cause hang problem.
 863                 if (PCIePowerSaveLevel > Max)
 864                         PCIePowerSaveLevel = Max;
 865
 866         PCI_REG_READ_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset, Configuration);
 867                 Configuration |= 0x100;
 868         PCI_REG_WIRTE_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset, Configuration);
 869                 DBGPRINT(RT_DEBUG_TRACE, ("Write Ralink device : offset 0x%x = 0x%x\n", pAd->RLnkCtrlOffset, Configuration));
 870         }
 871
 872         DBGPRINT(RT_DEBUG_TRACE,("RTMPPCIePowerLinkCtrl <==============\n"));
 873 }