2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 #include <linux/export.h>
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/clk-provider.h>
24 #include <linux/clkdev.h>
26 #include "imx-ipu-v3.h"
33 struct clk *clk_di; /* display input clock */
34 struct clk *clk_ipu; /* IPU bus clock */
35 struct clk *clk_di_pixel; /* resulting pixel clock */
36 struct clk_hw clk_hw_out;
39 unsigned long clkflags;
43 static DEFINE_MUTEX(di_mutex);
45 struct di_sync_config {
52 int cnt_polarity_gen_en;
53 int cnt_polarity_clr_src;
54 int cnt_polarity_trigger_src;
76 DI_SYNC_INT_HSYNC = 2,
84 #define DI_GENERAL 0x0000
85 #define DI_BS_CLKGEN0 0x0004
86 #define DI_BS_CLKGEN1 0x0008
87 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
88 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
89 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
90 #define DI_SYNC_AS_GEN 0x0054
91 #define DI_DW_GEN(gen) (0x0058 + 4 * (gen))
92 #define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set)))
93 #define DI_SER_CONF 0x015c
98 #define DI_SCR_CONF 0x0170
99 #define DI_STAT 0x0174
101 #define DI_SW_GEN0_RUN_COUNT(x) ((x) << 19)
102 #define DI_SW_GEN0_RUN_SRC(x) ((x) << 16)
103 #define DI_SW_GEN0_OFFSET_COUNT(x) ((x) << 3)
104 #define DI_SW_GEN0_OFFSET_SRC(x) ((x) << 0)
106 #define DI_SW_GEN1_CNT_POL_GEN_EN(x) ((x) << 29)
107 #define DI_SW_GEN1_CNT_CLR_SRC(x) ((x) << 25)
108 #define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x) ((x) << 12)
109 #define DI_SW_GEN1_CNT_POL_CLR_SRC(x) ((x) << 9)
110 #define DI_SW_GEN1_CNT_DOWN(x) ((x) << 16)
111 #define DI_SW_GEN1_CNT_UP(x) (x)
112 #define DI_SW_GEN1_AUTO_RELOAD (0x10000000)
114 #define DI_DW_GEN_ACCESS_SIZE_OFFSET 24
115 #define DI_DW_GEN_COMPONENT_SIZE_OFFSET 16
117 #define DI_GEN_POLARITY_1 (1 << 0)
118 #define DI_GEN_POLARITY_2 (1 << 1)
119 #define DI_GEN_POLARITY_3 (1 << 2)
120 #define DI_GEN_POLARITY_4 (1 << 3)
121 #define DI_GEN_POLARITY_5 (1 << 4)
122 #define DI_GEN_POLARITY_6 (1 << 5)
123 #define DI_GEN_POLARITY_7 (1 << 6)
124 #define DI_GEN_POLARITY_8 (1 << 7)
125 #define DI_GEN_POLARITY_DISP_CLK (1 << 17)
126 #define DI_GEN_DI_CLK_EXT (1 << 20)
127 #define DI_GEN_DI_VSYNC_EXT (1 << 21)
129 #define DI_POL_DRDY_DATA_POLARITY (1 << 7)
130 #define DI_POL_DRDY_POLARITY_15 (1 << 4)
132 #define DI_VSYNC_SEL_OFFSET 13
134 static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset)
136 return readl(di->base + offset);
139 static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset)
141 writel(value, di->base + offset);
144 static int ipu_di_clk_calc_div(unsigned long inrate, unsigned long outrate)
151 do_div(tmp, outrate);
160 * Freescale has this in their Kernel. It is neither clear what
161 * it does nor why it does it
166 /* Round up divider if it gets us closer to desired pix clk */
167 if ((div & 0xC) == 0xC) {
176 static unsigned long clk_di_recalc_rate(struct clk_hw *hw,
177 unsigned long parent_rate)
179 struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
180 unsigned long outrate;
181 u32 div = ipu_di_read(di, DI_BS_CLKGEN0);
186 outrate = (parent_rate / div) * 16;
191 static long clk_di_round_rate(struct clk_hw *hw, unsigned long rate,
192 unsigned long *prate)
194 struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
195 unsigned long outrate;
199 div = ipu_di_clk_calc_div(*prate, rate);
201 outrate = (*prate / div) * 16;
203 val = ipu_di_read(di, DI_GENERAL);
205 if (!(val & DI_GEN_DI_CLK_EXT) && outrate > *prate / 2)
206 outrate = *prate / 2;
208 dev_dbg(di->ipu->dev,
209 "%s: inrate: %ld div: 0x%08x outrate: %ld wanted: %ld\n",
210 __func__, *prate, div, outrate, rate);
215 static int clk_di_set_rate(struct clk_hw *hw, unsigned long rate,
216 unsigned long parent_rate)
218 struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
222 clkgen0 = ipu_di_read(di, DI_BS_CLKGEN0) & ~0xfff;
224 div = ipu_di_clk_calc_div(parent_rate, rate);
226 ipu_di_write(di, clkgen0 | div, DI_BS_CLKGEN0);
228 dev_dbg(di->ipu->dev, "%s: inrate: %ld desired: %ld div: 0x%08x\n",
229 __func__, parent_rate, rate, div);
233 static u8 clk_di_get_parent(struct clk_hw *hw)
235 struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
238 val = ipu_di_read(di, DI_GENERAL);
240 return val & DI_GEN_DI_CLK_EXT ? 1 : 0;
243 static int clk_di_set_parent(struct clk_hw *hw, u8 index)
245 struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
248 val = ipu_di_read(di, DI_GENERAL);
251 val |= DI_GEN_DI_CLK_EXT;
253 val &= ~DI_GEN_DI_CLK_EXT;
255 ipu_di_write(di, val, DI_GENERAL);
260 static struct clk_ops clk_di_ops = {
261 .round_rate = clk_di_round_rate,
262 .set_rate = clk_di_set_rate,
263 .recalc_rate = clk_di_recalc_rate,
264 .set_parent = clk_di_set_parent,
265 .get_parent = clk_di_get_parent,
268 static void ipu_di_data_wave_config(struct ipu_di *di,
270 int access_size, int component_size)
273 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
274 (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
275 ipu_di_write(di, reg, DI_DW_GEN(wave_gen));
278 static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin,
279 int set, int up, int down)
283 reg = ipu_di_read(di, DI_DW_GEN(wave_gen));
284 reg &= ~(0x3 << (di_pin * 2));
285 reg |= set << (di_pin * 2);
286 ipu_di_write(di, reg, DI_DW_GEN(wave_gen));
288 ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set));
291 static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
292 int start, int count)
297 for (i = 0; i < count; i++) {
298 struct di_sync_config *c = &config[i];
299 int wave_gen = start + i + 1;
301 if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) ||
302 (c->repeat_count >= 0x1000) ||
303 (c->cnt_up >= 0x400) ||
304 (c->cnt_down >= 0x400)) {
305 dev_err(di->ipu->dev, "DI%d counters out of range.\n",
310 reg = DI_SW_GEN0_RUN_COUNT(c->run_count) |
311 DI_SW_GEN0_RUN_SRC(c->run_src) |
312 DI_SW_GEN0_OFFSET_COUNT(c->offset_count) |
313 DI_SW_GEN0_OFFSET_SRC(c->offset_src);
314 ipu_di_write(di, reg, DI_SW_GEN0(wave_gen));
316 reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) |
317 DI_SW_GEN1_CNT_CLR_SRC(c->cnt_clr_src) |
318 DI_SW_GEN1_CNT_POL_TRIGGER_SRC(
319 c->cnt_polarity_trigger_src) |
320 DI_SW_GEN1_CNT_POL_CLR_SRC(c->cnt_polarity_clr_src) |
321 DI_SW_GEN1_CNT_DOWN(c->cnt_down) |
322 DI_SW_GEN1_CNT_UP(c->cnt_up);
324 /* Enable auto reload */
325 if (c->repeat_count == 0)
326 reg |= DI_SW_GEN1_AUTO_RELOAD;
328 ipu_di_write(di, reg, DI_SW_GEN1(wave_gen));
330 reg = ipu_di_read(di, DI_STP_REP(wave_gen));
331 reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1)));
332 reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1));
333 ipu_di_write(di, reg, DI_STP_REP(wave_gen));
337 static void ipu_di_sync_config_interlaced(struct ipu_di *di,
338 struct ipu_di_signal_cfg *sig)
340 u32 h_total = sig->width + sig->h_sync_width +
341 sig->h_start_width + sig->h_end_width;
342 u32 v_total = sig->height + sig->v_sync_width +
343 sig->v_start_width + sig->v_end_width;
345 struct di_sync_config cfg[] = {
347 .run_count = h_total / 2 - 1,
348 .run_src = DI_SYNC_CLK,
350 .run_count = h_total - 11,
351 .run_src = DI_SYNC_CLK,
354 .run_count = v_total * 2 - 1,
355 .run_src = DI_SYNC_INT_HSYNC,
357 .offset_src = DI_SYNC_INT_HSYNC,
360 .run_count = v_total / 2 - 1,
361 .run_src = DI_SYNC_HSYNC,
362 .offset_count = sig->v_start_width,
363 .offset_src = DI_SYNC_HSYNC,
365 .cnt_clr_src = DI_SYNC_VSYNC,
367 .run_src = DI_SYNC_HSYNC,
368 .repeat_count = sig->height / 2,
371 .run_count = v_total - 1,
372 .run_src = DI_SYNC_HSYNC,
374 .run_count = v_total / 2 - 1,
375 .run_src = DI_SYNC_HSYNC,
377 .offset_src = DI_SYNC_HSYNC,
379 .cnt_clr_src = DI_SYNC_VSYNC,
381 .run_src = DI_SYNC_CLK,
382 .offset_count = sig->h_start_width,
383 .offset_src = DI_SYNC_CLK,
384 .repeat_count = sig->width,
387 .run_count = v_total - 1,
388 .run_src = DI_SYNC_INT_HSYNC,
389 .offset_count = v_total / 2,
390 .offset_src = DI_SYNC_INT_HSYNC,
391 .cnt_clr_src = DI_SYNC_HSYNC,
396 ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
398 /* set gentime select and tag sel */
399 reg = ipu_di_read(di, DI_SW_GEN1(9));
401 reg |= (3 - 1) << 29 | 0x00008000;
402 ipu_di_write(di, reg, DI_SW_GEN1(9));
404 ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF);
407 static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
408 struct ipu_di_signal_cfg *sig, int div)
410 u32 h_total = sig->width + sig->h_sync_width + sig->h_start_width +
412 u32 v_total = sig->height + sig->v_sync_width + sig->v_start_width +
414 struct di_sync_config cfg[] = {
417 .run_count = h_total - 1,
418 .run_src = DI_SYNC_CLK,
421 .run_count = h_total - 1,
422 .run_src = DI_SYNC_CLK,
423 .offset_count = div * sig->v_to_h_sync,
424 .offset_src = DI_SYNC_CLK,
425 .cnt_polarity_gen_en = 1,
426 .cnt_polarity_trigger_src = DI_SYNC_CLK,
427 .cnt_down = sig->h_sync_width * 2,
430 .run_count = v_total - 1,
431 .run_src = DI_SYNC_INT_HSYNC,
432 .cnt_polarity_gen_en = 1,
433 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
434 .cnt_down = sig->v_sync_width * 2,
437 .run_src = DI_SYNC_HSYNC,
438 .offset_count = sig->v_sync_width + sig->v_start_width,
439 .offset_src = DI_SYNC_HSYNC,
440 .repeat_count = sig->height,
441 .cnt_clr_src = DI_SYNC_VSYNC,
443 /* 5: Pixel Active, referenced by DC */
444 .run_src = DI_SYNC_CLK,
445 .offset_count = sig->h_sync_width + sig->h_start_width,
446 .offset_src = DI_SYNC_CLK,
447 .repeat_count = sig->width,
448 .cnt_clr_src = 5, /* Line Active */
459 /* can't use #7 and #8 for line active and pixel active counters */
460 struct di_sync_config cfg_vga[] = {
463 .run_count = h_total - 1,
464 .run_src = DI_SYNC_CLK,
467 .run_count = v_total - 1,
468 .run_src = DI_SYNC_INT_HSYNC,
471 .run_src = DI_SYNC_INT_HSYNC,
472 .offset_count = sig->v_sync_width + sig->v_start_width,
473 .offset_src = DI_SYNC_INT_HSYNC,
474 .repeat_count = sig->height,
475 .cnt_clr_src = 3 /* VSYNC */,
477 /* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */
478 .run_count = h_total - 1,
479 .run_src = DI_SYNC_CLK,
480 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
481 .offset_src = DI_SYNC_CLK,
482 .cnt_polarity_gen_en = 1,
483 .cnt_polarity_trigger_src = DI_SYNC_CLK,
484 .cnt_down = sig->h_sync_width * 2,
486 /* 5: Pixel Active signal to DC */
487 .run_src = DI_SYNC_CLK,
488 .offset_count = sig->h_sync_width + sig->h_start_width,
489 .offset_src = DI_SYNC_CLK,
490 .repeat_count = sig->width,
491 .cnt_clr_src = 4, /* Line Active */
493 /* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */
494 .run_count = v_total - 1,
495 .run_src = DI_SYNC_INT_HSYNC,
496 .offset_count = 1, /* magic value from Freescale TVE driver */
497 .offset_src = DI_SYNC_INT_HSYNC,
498 .cnt_polarity_gen_en = 1,
499 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
500 .cnt_down = sig->v_sync_width * 2,
502 /* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */
503 .run_count = h_total - 1,
504 .run_src = DI_SYNC_CLK,
505 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
506 .offset_src = DI_SYNC_CLK,
507 .cnt_polarity_gen_en = 1,
508 .cnt_polarity_trigger_src = DI_SYNC_CLK,
509 .cnt_down = sig->h_sync_width * 2,
511 /* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */
512 .run_count = v_total - 1,
513 .run_src = DI_SYNC_INT_HSYNC,
514 .offset_count = 1, /* magic value from Freescale TVE driver */
515 .offset_src = DI_SYNC_INT_HSYNC,
516 .cnt_polarity_gen_en = 1,
517 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
518 .cnt_down = sig->v_sync_width * 2,
524 ipu_di_write(di, v_total - 1, DI_SCR_CONF);
525 if (sig->hsync_pin == 2 && sig->vsync_pin == 3)
526 ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
528 ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga));
531 int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
534 u32 di_gen, vsync_cnt;
536 u32 h_total, v_total;
541 dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
542 di->id, sig->width, sig->height);
544 if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
547 if (sig->clkflags & IPU_DI_CLKMODE_EXT)
550 parent = di->clk_ipu;
552 ret = clk_set_parent(di->clk_di_pixel, parent);
554 dev_err(di->ipu->dev,
555 "setting pixel clock to parent %s failed with %d\n",
556 __clk_get_name(parent), ret);
560 if (sig->clkflags & IPU_DI_CLKMODE_SYNC)
561 round = clk_get_rate(parent);
563 round = clk_round_rate(di->clk_di_pixel, sig->pixelclock);
565 ret = clk_set_rate(di->clk_di_pixel, round);
567 h_total = sig->width + sig->h_sync_width + sig->h_start_width +
569 v_total = sig->height + sig->v_sync_width + sig->v_start_width +
572 mutex_lock(&di_mutex);
574 div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff;
575 div = div / 16; /* Now divider is integer portion */
577 /* Setup pixel clock timing */
578 /* Down time is half of period */
579 ipu_di_write(di, (div << 16), DI_BS_CLKGEN1);
581 ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1);
582 ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
584 di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT;
585 di_gen |= DI_GEN_DI_VSYNC_EXT;
587 if (sig->interlaced) {
588 ipu_di_sync_config_interlaced(di, sig);
591 di_gen |= 0x10000000;
592 di_gen |= DI_GEN_POLARITY_5;
593 di_gen |= DI_GEN_POLARITY_8;
598 di_gen |= DI_GEN_POLARITY_3;
600 di_gen |= DI_GEN_POLARITY_2;
602 ipu_di_sync_config_noninterlaced(di, sig, div);
607 * TODO: change only for TVEv2, parallel display
610 if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
613 if (sig->Hsync_pol) {
614 if (sig->hsync_pin == 2)
615 di_gen |= DI_GEN_POLARITY_2;
616 else if (sig->hsync_pin == 4)
617 di_gen |= DI_GEN_POLARITY_4;
618 else if (sig->hsync_pin == 7)
619 di_gen |= DI_GEN_POLARITY_7;
621 if (sig->Vsync_pol) {
622 if (sig->vsync_pin == 3)
623 di_gen |= DI_GEN_POLARITY_3;
624 else if (sig->vsync_pin == 6)
625 di_gen |= DI_GEN_POLARITY_6;
626 else if (sig->vsync_pin == 8)
627 di_gen |= DI_GEN_POLARITY_8;
632 di_gen |= DI_GEN_POLARITY_DISP_CLK;
634 ipu_di_write(di, di_gen, DI_GENERAL);
636 ipu_di_write(di, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002,
639 reg = ipu_di_read(di, DI_POL);
640 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
643 reg |= DI_POL_DRDY_POLARITY_15;
645 reg |= DI_POL_DRDY_DATA_POLARITY;
647 ipu_di_write(di, reg, DI_POL);
649 mutex_unlock(&di_mutex);
653 EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel);
655 int ipu_di_enable(struct ipu_di *di)
657 clk_prepare_enable(di->clk_di_pixel);
659 ipu_module_enable(di->ipu, di->module);
663 EXPORT_SYMBOL_GPL(ipu_di_enable);
665 int ipu_di_disable(struct ipu_di *di)
667 ipu_module_disable(di->ipu, di->module);
669 clk_disable_unprepare(di->clk_di_pixel);
673 EXPORT_SYMBOL_GPL(ipu_di_disable);
675 int ipu_di_get_num(struct ipu_di *di)
679 EXPORT_SYMBOL_GPL(ipu_di_get_num);
681 static DEFINE_MUTEX(ipu_di_lock);
683 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp)
688 return ERR_PTR(-EINVAL);
690 di = ipu->di_priv[disp];
692 mutex_lock(&ipu_di_lock);
695 di = ERR_PTR(-EBUSY);
701 mutex_unlock(&ipu_di_lock);
705 EXPORT_SYMBOL_GPL(ipu_di_get);
707 void ipu_di_put(struct ipu_di *di)
709 mutex_lock(&ipu_di_lock);
713 mutex_unlock(&ipu_di_lock);
715 EXPORT_SYMBOL_GPL(ipu_di_put);
717 int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
719 u32 module, struct clk *clk_ipu)
723 const char *di_parent[2];
724 struct clk_init_data init = {
733 di = devm_kzalloc(dev, sizeof(*di), GFP_KERNEL);
737 ipu->di_priv[id] = di;
739 di->clk_di = devm_clk_get(dev, id ? "di1" : "di0");
740 if (IS_ERR(di->clk_di))
741 return PTR_ERR(di->clk_di);
745 di->clk_ipu = clk_ipu;
746 di->base = devm_ioremap(dev, base, PAGE_SIZE);
750 di_parent[0] = __clk_get_name(di->clk_ipu);
751 di_parent[1] = __clk_get_name(di->clk_di);
753 ipu_di_write(di, 0x10, DI_BS_CLKGEN0);
755 init.parent_names = (const char **)&di_parent;
756 di->clk_name = kasprintf(GFP_KERNEL, "%s_di%d_pixel",
761 init.name = di->clk_name;
763 di->clk_hw_out.init = &init;
764 di->clk_di_pixel = clk_register(dev, &di->clk_hw_out);
766 if (IS_ERR(di->clk_di_pixel)) {
767 ret = PTR_ERR(di->clk_di_pixel);
768 goto failed_clk_register;
771 dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n",
785 void ipu_di_exit(struct ipu_soc *ipu, int id)
787 struct ipu_di *di = ipu->di_priv[id];
789 clk_unregister(di->clk_di_pixel);