3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
12 * for processing interrupts from the device.
14 *------------------------------------------------------------------------------
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59 #include "et131x_version.h"
60 #include "et131x_defs.h"
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <linux/pci.h>
79 #include <asm/system.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
87 #include "et1310_phy.h"
88 #include "et131x_adapter.h"
92 * For interrupts, normal running is:
93 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
94 * watchdog_interrupt & txdma_xfer_done
96 * In both cases, when flow control is enabled for either Tx or bi-direction,
97 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
98 * buffer rings are running low.
100 #define INT_MASK_DISABLE 0xffffffff
102 /* NOTE: Masking out MAC_STAT Interrupt for now...
103 * #define INT_MASK_ENABLE 0xfff6bf17
104 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
106 #define INT_MASK_ENABLE 0xfffebf17
107 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
111 * et131x_enable_interrupts - enable interrupt
112 * @adapter: et131x device
114 * Enable the appropriate interrupts on the ET131x according to our
118 void et131x_enable_interrupts(struct et131x_adapter *adapter)
122 /* Enable all global interrupts */
123 if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both)
124 mask = INT_MASK_ENABLE;
126 mask = INT_MASK_ENABLE_NO_FLOW;
128 adapter->CachedMaskValue = mask;
129 writel(mask, &adapter->regs->global.int_mask);
133 * et131x_disable_interrupts - interrupt disable
134 * @adapter: et131x device
136 * Block all interrupts from the et131x device at the device itself
139 void et131x_disable_interrupts(struct et131x_adapter *adapter)
141 /* Disable all global interrupts */
142 adapter->CachedMaskValue = INT_MASK_DISABLE;
143 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
148 * et131x_isr - The Interrupt Service Routine for the driver.
149 * @irq: the IRQ on which the interrupt was received.
150 * @dev_id: device-specific info (here a pointer to a net_device struct)
152 * Returns a value indicating if the interrupt was handled.
155 irqreturn_t et131x_isr(int irq, void *dev_id)
158 struct net_device *netdev = (struct net_device *)dev_id;
159 struct et131x_adapter *adapter = NULL;
162 if (!netif_device_present(netdev)) {
167 adapter = netdev_priv(netdev);
169 /* If the adapter is in low power state, then it should not
170 * recognize any interrupt
173 /* Disable Device Interrupts */
174 et131x_disable_interrupts(adapter);
176 /* Get a copy of the value in the interrupt status register
177 * so we can process the interrupting section
179 status = readl(&adapter->regs->global.int_status);
181 if (adapter->FlowControl == TxOnly ||
182 adapter->FlowControl == Both) {
183 status &= ~INT_MASK_ENABLE;
185 status &= ~INT_MASK_ENABLE_NO_FLOW;
188 /* Make sure this is our interrupt */
191 et131x_enable_interrupts(adapter);
195 /* This is our interrupt, so process accordingly */
197 if (status & ET_INTR_WATCHDOG) {
198 struct tcb *tcb = adapter->tx_ring.send_head;
201 if (++tcb->stale > 1)
202 status |= ET_INTR_TXDMA_ISR;
204 if (adapter->rx_ring.UnfinishedReceives)
205 status |= ET_INTR_RXDMA_XFR_DONE;
206 else if (tcb == NULL)
207 writel(0, &adapter->regs->global.watchdog_timer);
209 status &= ~ET_INTR_WATCHDOG;
213 /* This interrupt has in some way been "handled" by
214 * the ISR. Either it was a spurious Rx interrupt, or
215 * it was a Tx interrupt that has been filtered by
218 et131x_enable_interrupts(adapter);
222 /* We need to save the interrupt status value for use in our
223 * DPC. We will clear the software copy of that in that
226 adapter->Stats.InterruptStatus = status;
228 /* Schedule the ISR handler as a bottom-half task in the
229 * kernel's tq_immediate queue, and mark the queue for
232 schedule_work(&adapter->task);
234 return IRQ_RETVAL(handled);
238 * et131x_isr_handler - The ISR handler
239 * @p_adapter, a pointer to the device's private adapter structure
241 * scheduled to run in a deferred context by the ISR. This is where the ISR's
242 * work actually gets done.
244 void et131x_isr_handler(struct work_struct *work)
246 struct et131x_adapter *etdev =
247 container_of(work, struct et131x_adapter, task);
248 u32 status = etdev->Stats.InterruptStatus;
249 ADDRESS_MAP_t __iomem *iomem = etdev->regs;
252 * These first two are by far the most common. Once handled, we clear
253 * their two bits in the status word. If the word is now zero, we
256 /* Handle all the completed Transmit interrupts */
257 if (status & ET_INTR_TXDMA_ISR) {
258 et131x_handle_send_interrupt(etdev);
261 /* Handle all the completed Receives interrupts */
262 if (status & ET_INTR_RXDMA_XFR_DONE) {
263 et131x_handle_recv_interrupt(etdev);
266 status &= 0xffffffd7;
269 /* Handle the TXDMA Error interrupt */
270 if (status & ET_INTR_TXDMA_ERR) {
273 /* Following read also clears the register (COR) */
274 txdma_err = readl(&iomem->txdma.TxDmaError);
276 dev_warn(&etdev->pdev->dev,
277 "TXDMA_ERR interrupt, error = %d\n",
281 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
282 if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
284 * This indicates the number of unused buffers in
285 * RXDMA free buffer ring 0 is <= the limit you
286 * programmed. Free buffer resources need to be
287 * returned. Free buffers are consumed as packets
288 * are passed from the network to the host. The host
289 * becomes aware of the packets from the contents of
290 * the packet status ring. This ring is queried when
291 * the packet done interrupt occurs. Packets are then
292 * passed to the OS. When the OS is done with the
293 * packets the resources can be returned to the
294 * ET1310 for re-use. This interrupt is one method of
295 * returning resources.
298 /* If the user has flow control on, then we will
299 * send a pause packet, otherwise just exit
301 if (etdev->FlowControl == TxOnly ||
302 etdev->FlowControl == Both) {
305 /* Tell the device to send a pause packet via
306 * the back pressure register (bp req and
309 pm_csr = readl(&iomem->global.pm_csr);
310 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
311 writel(3, &iomem->txmac.bp_ctrl);
315 /* Handle Packet Status Ring Low Interrupt */
316 if (status & ET_INTR_RXDMA_STAT_LOW) {
319 * Same idea as with the two Free Buffer Rings.
320 * Packets going from the network to the host each
321 * consume a free buffer resource and a packet status
322 * resource. These resoures are passed to the OS.
323 * When the OS is done with the resources, they need
324 * to be returned to the ET1310. This is one method
325 * of returning the resources.
329 /* Handle RXDMA Error Interrupt */
330 if (status & ET_INTR_RXDMA_ERR) {
332 * The rxdma_error interrupt is sent when a time-out
333 * on a request issued by the JAGCore has occurred or
334 * a completion is returned with an un-successful
335 * status. In both cases the request is considered
336 * complete. The JAGCore will automatically re-try the
337 * request in question. Normally information on events
338 * like these are sent to the host using the "Advanced
339 * Error Reporting" capability. This interrupt is
340 * another way of getting similar information. The
341 * only thing required is to clear the interrupt by
342 * reading the ISR in the global resources. The
343 * JAGCore will do a re-try on the request. Normally
344 * you should never see this interrupt. If you start
345 * to see this interrupt occurring frequently then
346 * something bad has occurred. A reset might be the
351 dev_warn(&etdev->pdev->dev,
352 "RxDMA_ERR interrupt, error %x\n",
353 readl(&iomem->txmac.tx_test));
356 /* Handle the Wake on LAN Event */
357 if (status & ET_INTR_WOL) {
359 * This is a secondary interrupt for wake on LAN.
360 * The driver should never see this, if it does,
361 * something serious is wrong. We will TRAP the
362 * message when we are in DBG mode, otherwise we
365 dev_err(&etdev->pdev->dev, "WAKE_ON_LAN interrupt\n");
368 /* Handle the PHY interrupt */
369 if (status & ET_INTR_PHY) {
371 MI_BMSR_t BmsrInts, BmsrData;
374 /* If we are in coma mode when we get this interrupt,
375 * we need to disable it.
377 pm_csr = readl(&iomem->global.pm_csr);
378 if (pm_csr & ET_PM_PHY_SW_COMA) {
380 * Check to see if we are in coma mode and if
381 * so, disable it because we will not be able
382 * to read PHY values until we are out.
384 DisablePhyComa(etdev);
387 /* Read the PHY ISR to clear the reason for the
390 MiRead(etdev, (uint8_t) offsetof(MI_REGS_t, isr),
393 if (!etdev->ReplicaPhyLoopbk) {
395 (uint8_t) offsetof(MI_REGS_t, bmsr),
399 etdev->Bmsr.value ^ BmsrData.value;
400 etdev->Bmsr.value = BmsrData.value;
402 /* Do all the cable in / cable out stuff */
403 et131x_Mii_check(etdev, BmsrData, BmsrInts);
407 /* Let's move on to the TxMac */
408 if (status & ET_INTR_TXMAC) {
409 u32 err = readl(&iomem->txmac.err);
412 * When any of the errors occur and TXMAC generates
413 * an interrupt to report these errors, it usually
414 * means that TXMAC has detected an error in the data
415 * stream retrieved from the on-chip Tx Q. All of
416 * these errors are catastrophic and TXMAC won't be
417 * able to recover data when these errors occur. In
418 * a nutshell, the whole Tx path will have to be reset
419 * and re-configured afterwards.
421 dev_warn(&etdev->pdev->dev,
422 "TXMAC interrupt, error 0x%08x\n",
425 /* If we are debugging, we want to see this error,
426 * otherwise we just want the device to be reset and
431 /* Handle RXMAC Interrupt */
432 if (status & ET_INTR_RXMAC) {
434 * These interrupts are catastrophic to the device,
435 * what we need to do is disable the interrupts and
436 * set the flag to cause us to reset so we can solve
439 /* MP_SET_FLAG( etdev,
440 fMP_ADAPTER_HARDWARE_ERROR); */
442 dev_warn(&etdev->pdev->dev,
443 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
444 readl(&iomem->rxmac.err_reg.value));
446 dev_warn(&etdev->pdev->dev,
447 "Enable 0x%08x, Diag 0x%08x\n",
448 readl(&iomem->rxmac.ctrl.value),
449 readl(&iomem->rxmac.rxq_diag.value));
452 * If we are debugging, we want to see this error,
453 * otherwise we just want the device to be reset and
458 /* Handle MAC_STAT Interrupt */
459 if (status & ET_INTR_MAC_STAT) {
461 * This means at least one of the un-masked counters
462 * in the MAC_STAT block has rolled over. Use this
463 * to maintain the top, software managed bits of the
466 HandleMacStatInterrupt(etdev);
469 /* Handle SLV Timeout Interrupt */
470 if (status & ET_INTR_SLV_TIMEOUT) {
472 * This means a timeout has occured on a read or
473 * write request to one of the JAGCore registers. The
474 * Global Resources block has terminated the request
475 * and on a read request, returned a "fake" value.
476 * The most likely reasons are: Bad Address or the
477 * addressed module is in a power-down state and
482 et131x_enable_interrupts(etdev);