3 * 10/100/1000 Base-T Ethernet Driver for the ET1310 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et131x_initpci.c - Routines and data used to register the driver with the
12 * PCI (and PCI Express) subsystem, as well as basic driver
15 *------------------------------------------------------------------------------
19 * This software is provided subject to the following terms and conditions,
20 * which you should read carefully before using the software. Using this
21 * software indicates your acceptance of these terms and conditions. If you do
22 * not agree with these terms and conditions, do not use the software.
24 * Copyright © 2005 Agere Systems Inc.
25 * All rights reserved.
27 * Redistribution and use in source or binary forms, with or without
28 * modifications, are permitted provided that the following conditions are met:
30 * . Redistributions of source code must retain the above copyright notice, this
31 * list of conditions and the following Disclaimer as comments in the code as
32 * well as in the documentation and/or other materials provided with the
35 * . Redistributions in binary form must reproduce the above copyright notice,
36 * this list of conditions and the following Disclaimer in the documentation
37 * and/or other materials provided with the distribution.
39 * . Neither the name of Agere Systems Inc. nor the names of the contributors
40 * may be used to endorse or promote products derived from this software
41 * without specific prior written permission.
45 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
46 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
48 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
49 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
50 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
52 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
53 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
55 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
60 #include "et131x_version.h"
61 #include "et131x_defs.h"
63 #include <linux/pci.h>
64 #include <linux/init.h>
65 #include <linux/module.h>
66 #include <linux/types.h>
67 #include <linux/kernel.h>
69 #include <linux/sched.h>
70 #include <linux/ptrace.h>
71 #include <linux/ctype.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/interrupt.h>
76 #include <linux/delay.h>
78 #include <linux/bitops.h>
79 #include <asm/system.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
86 #include <linux/random.h>
88 #include "et1310_phy.h"
90 #include "et131x_adapter.h"
92 #include "et1310_address_map.h"
93 #include "et1310_tx.h"
94 #include "et1310_rx.h"
97 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
98 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
101 * et131x_hwaddr_init - set up the MAC Address on the ET1310
102 * @adapter: pointer to our private adapter structure
104 void et131x_hwaddr_init(struct et131x_adapter *adapter)
106 /* If have our default mac from init and no mac address from
107 * EEPROM then we need to generate the last octet and set it on the
110 if (adapter->rom_addr[0] == 0x00 &&
111 adapter->rom_addr[1] == 0x00 &&
112 adapter->rom_addr[2] == 0x00 &&
113 adapter->rom_addr[3] == 0x00 &&
114 adapter->rom_addr[4] == 0x00 &&
115 adapter->rom_addr[5] == 0x00) {
117 * We need to randomly generate the last octet so we
118 * decrease our chances of setting the mac address to
119 * same as another one of our cards in the system
121 get_random_bytes(&adapter->addr[5], 1);
123 * We have the default value in the register we are
124 * working with so we need to copy the current
125 * address into the permanent address
127 memcpy(adapter->rom_addr,
128 adapter->addr, ETH_ALEN);
130 /* We do not have an override address, so set the
131 * current address to the permanent address and add
134 memcpy(adapter->addr,
135 adapter->rom_addr, ETH_ALEN);
141 * et131x_pci_init - initial PCI setup
142 * @adapter: pointer to our private adapter structure
143 * @pdev: our PCI device
145 * Perform the initial setup of PCI registers and if possible initialise
146 * the MAC address. At this point the I/O registers have yet to be mapped
149 static int et131x_pci_init(struct et131x_adapter *adapter,
150 struct pci_dev *pdev)
156 if (et131x_init_eeprom(adapter) < 0)
159 /* Let's set up the PORT LOGIC Register. First we need to know what
160 * the max_payload_size is
162 if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) {
164 "Could not read PCI config space for Max Payload Size\n");
168 /* Program the Ack/Nak latency and replay timers */
169 max_payload &= 0x07; /* Only the lower 3 bits are valid */
171 if (max_payload < 2) {
172 static const u16 acknak[2] = { 0x76, 0xD0 };
173 static const u16 replay[2] = { 0x1E0, 0x2ED };
175 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
176 acknak[max_payload])) {
178 "Could not write PCI config space for ACK/NAK\n");
181 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
182 replay[max_payload])) {
184 "Could not write PCI config space for Replay Timer\n");
189 /* l0s and l1 latency timers. We are using default values.
190 * Representing 001 for L0s and 010 for L1
192 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
194 "Could not write PCI config space for Latency Timers\n");
198 /* Change the max read size to 2k */
199 if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) {
201 "Could not read PCI config space for Max read size\n");
205 read_size_reg &= 0x8f;
206 read_size_reg |= 0x40;
208 if (pci_write_config_byte(pdev, 0x51, read_size_reg)) {
210 "Could not write PCI config space for Max read size\n");
214 /* Get MAC address from config space if an eeprom exists, otherwise
215 * the MAC address there will not be valid
217 if (!adapter->has_eeprom) {
218 et131x_hwaddr_init(adapter);
222 for (i = 0; i < ETH_ALEN; i++) {
223 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
224 adapter->rom_addr + i)) {
225 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
229 memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
234 * et131x_error_timer_handler
235 * @data: timer-specific variable; here a pointer to our adapter structure
237 * The routine called when the error timer expires, to track the number of
240 void et131x_error_timer_handler(unsigned long data)
242 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
245 pm_csr = readl(&adapter->regs->global.pm_csr);
247 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
248 et1310_update_macstat_host_counters(adapter);
250 dev_err(&adapter->pdev->dev,
251 "No interrupts, in PHY coma, pm_csr = 0x%x\n", pm_csr);
253 if (!(adapter->bmsr & MI_BMSR_LINK_STATUS) &&
254 adapter->registry_phy_coma &&
255 adapter->boot_coma < 11) {
256 adapter->boot_coma++;
259 if (adapter->boot_coma == 10) {
260 if (!(adapter->bmsr & MI_BMSR_LINK_STATUS)
261 && adapter->registry_phy_coma) {
262 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
263 /* NOTE - This was originally a 'sync with
264 * interrupt'. How to do that under Linux?
266 et131x_enable_interrupts(adapter);
267 et1310_enable_phy_coma(adapter);
272 /* This is a periodic timer, so reschedule */
273 mod_timer(&adapter->error_timer, jiffies +
274 TX_ERROR_PERIOD * HZ / 1000);
278 * et131x_configure_global_regs - configure JAGCore global regs
279 * @adapter: pointer to our adapter structure
281 * Used to configure the global registers on the JAGCore
283 void et131x_configure_global_regs(struct et131x_adapter *adapter)
285 struct global_regs __iomem *regs = &adapter->regs->global;
287 writel(0, ®s->rxq_start_addr);
288 writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
290 if (adapter->registry_jumbo_packet < 2048) {
291 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
292 * block of RAM that the driver can split between Tx
293 * and Rx as it desires. Our default is to split it
296 writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
297 writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
298 } else if (adapter->registry_jumbo_packet < 8192) {
299 /* For jumbo packets > 2k but < 8k, split 50-50. */
300 writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
301 writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
303 /* 9216 is the only packet size greater than 8k that
304 * is available. The Tx buffer has to be big enough
305 * for one whole packet on the Tx side. We'll make
306 * the Tx 9408, and give the rest to Rx
308 writel(0x01b3, ®s->rxq_end_addr);
309 writel(0x01b4, ®s->txq_start_addr);
312 /* Initialize the loopback register. Disable all loopbacks. */
313 writel(0, ®s->loopback);
316 writel(0, ®s->msi_config);
318 /* By default, disable the watchdog timer. It will be enabled when
319 * a packet is queued.
321 writel(0, ®s->watchdog_timer);
325 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
326 * @adapter: pointer to our private adapter structure
328 * Returns 0 on success, errno on failure (as defined in errno.h)
330 int et131x_adapter_setup(struct et131x_adapter *adapter)
334 /* Configure the JAGCore */
335 et131x_configure_global_regs(adapter);
337 et1310_config_mac_regs1(adapter);
339 /* Configure the MMC registers */
340 /* All we need to do is initialize the Memory Control Register */
341 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
343 et1310_config_rxmac_regs(adapter);
344 et1310_config_txmac_regs(adapter);
346 et131x_config_rx_dma_regs(adapter);
347 et131x_config_tx_dma_regs(adapter);
349 et1310_config_macstat_regs(adapter);
351 /* Move the following code to Timer function?? */
352 status = et131x_xcvr_find(adapter);
355 dev_warn(&adapter->pdev->dev, "Could not find the xcvr\n");
357 /* Prepare the TRUEPHY library. */
358 et1310_phy_init(adapter);
360 /* Reset the phy now so changes take place */
361 et1310_phy_reset(adapter);
364 et1310_phy_power_down(adapter, 1);
367 * We need to turn off 1000 base half dulplex, the mac does not
368 * support it. For the 10/100 part, turn off all gig advertisement
370 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
371 et1310_phy_advertise_1000BaseT(adapter, TRUEPHY_ADV_DUPLEX_FULL);
373 et1310_phy_advertise_1000BaseT(adapter, TRUEPHY_ADV_DUPLEX_NONE);
376 et1310_phy_power_down(adapter, 0);
378 et131x_setphy_normal(adapter);
383 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
384 * @adapter: pointer to our private adapter structure
386 void et131x_soft_reset(struct et131x_adapter *adapter)
388 /* Disable MAC Core */
389 writel(0xc00f0000, &adapter->regs->mac.cfg1);
391 /* Set everything to a reset value */
392 writel(0x7F, &adapter->regs->global.sw_reset);
393 writel(0x000f0000, &adapter->regs->mac.cfg1);
394 writel(0x00000000, &adapter->regs->mac.cfg1);
398 * et131x_align_allocated_memory - Align allocated memory on a given boundary
399 * @adapter: pointer to our adapter structure
400 * @phys_addr: pointer to Physical address
401 * @offset: pointer to the offset variable
402 * @mask: correct mask
404 void et131x_align_allocated_memory(struct et131x_adapter *adapter,
406 uint64_t *offset, uint64_t mask)
412 new_addr = *phys_addr & ~mask;
414 if (new_addr != *phys_addr) {
415 /* Move to next aligned block */
416 new_addr += mask + 1;
417 /* Return offset for adjusting virt addr */
418 *offset = new_addr - *phys_addr;
419 /* Return new physical address */
420 *phys_addr = new_addr;
425 * et131x_adapter_memory_alloc
426 * @adapter: pointer to our private adapter structure
428 * Returns 0 on success, errno on failure (as defined in errno.h).
430 * Allocate all the memory blocks for send, receive and others.
432 int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
436 /* Allocate memory for the Tx Ring */
437 status = et131x_tx_dma_memory_alloc(adapter);
439 dev_err(&adapter->pdev->dev,
440 "et131x_tx_dma_memory_alloc FAILED\n");
443 /* Receive buffer memory allocation */
444 status = et131x_rx_dma_memory_alloc(adapter);
446 dev_err(&adapter->pdev->dev,
447 "et131x_rx_dma_memory_alloc FAILED\n");
448 et131x_tx_dma_memory_free(adapter);
452 /* Init receive data structures */
453 status = et131x_init_recv(adapter);
455 dev_err(&adapter->pdev->dev,
456 "et131x_init_recv FAILED\n");
457 et131x_tx_dma_memory_free(adapter);
458 et131x_rx_dma_memory_free(adapter);
464 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
465 * @adapter: pointer to our private adapter structure
467 void et131x_adapter_memory_free(struct et131x_adapter *adapter)
469 /* Free DMA memory */
470 et131x_tx_dma_memory_free(adapter);
471 et131x_rx_dma_memory_free(adapter);
475 * et131x_adapter_init
476 * @adapter: pointer to the private adapter struct
477 * @pdev: pointer to the PCI device
479 * Initialize the data structures for the et131x_adapter object and link
480 * them together with the platform provided device structures.
482 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
483 struct pci_dev *pdev)
485 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
486 static const u8 duplex[] = { 0, 1, 2, 1, 2, 2 };
487 static const u16 speed[] = { 0, 10, 10, 100, 100, 1000 };
489 struct et131x_adapter *adapter;
491 /* Allocate private adapter struct and copy in relevant information */
492 adapter = netdev_priv(netdev);
493 adapter->pdev = pci_dev_get(pdev);
494 adapter->netdev = netdev;
496 /* Do the same for the netdev struct */
497 netdev->irq = pdev->irq;
498 netdev->base_addr = pci_resource_start(pdev, 0);
500 /* Initialize spinlocks here */
501 spin_lock_init(&adapter->lock);
502 spin_lock_init(&adapter->tcb_send_qlock);
503 spin_lock_init(&adapter->tcb_ready_qlock);
504 spin_lock_init(&adapter->send_hw_lock);
505 spin_lock_init(&adapter->rcv_lock);
506 spin_lock_init(&adapter->rcv_pend_lock);
507 spin_lock_init(&adapter->fbr_lock);
508 spin_lock_init(&adapter->phy_lock);
510 adapter->speed_duplex = 0; /* Auto Speed Auto Duplex */
511 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
513 /* Set the MAC address to a default */
514 memcpy(adapter->addr, default_mac, ETH_ALEN);
516 adapter->ai_force_speed = speed[adapter->speed_duplex];
517 adapter->ai_force_duplex = duplex[adapter->speed_duplex]; /* Auto FDX */
523 * et131x_pci_setup - Perform device initialization
524 * @pdev: a pointer to the device's pci_dev structure
525 * @ent: this device's entry in the pci_device_id table
527 * Returns 0 on success, errno on failure (as defined in errno.h)
529 * Registered in the pci_driver structure, this function is called when the
530 * PCI subsystem finds a new PCI device which matches the information
531 * contained in the pci_device_id table. This routine is the equivalent to
532 * a device insertion routine.
534 static int __devinit et131x_pci_setup(struct pci_dev *pdev,
535 const struct pci_device_id *ent)
539 struct net_device *netdev;
540 struct et131x_adapter *adapter;
542 /* Enable the device via the PCI subsystem */
543 result = pci_enable_device(pdev);
545 dev_err(&pdev->dev, "pci_enable_device() failed\n");
549 /* Perform some basic PCI checks */
550 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
551 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
555 if (pci_request_regions(pdev, DRIVER_NAME)) {
556 dev_err(&pdev->dev, "Can't get PCI resources\n");
560 pci_set_master(pdev);
562 /* Query PCI for Power Mgmt Capabilities
564 * NOTE: Now reading PowerMgmt in another location; is this still
567 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
570 "Cannot find Power Management capabilities\n");
572 goto err_release_res;
575 /* Check the DMA addressing support of this device */
576 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
577 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
580 "Unable to obtain 64 bit DMA for consistent allocations\n");
581 goto err_release_res;
583 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
584 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
587 "Unable to obtain 32 bit DMA for consistent allocations\n");
588 goto err_release_res;
591 dev_err(&pdev->dev, "No usable DMA addressing method\n");
593 goto err_release_res;
596 /* Allocate netdev and private adapter structs */
597 netdev = et131x_device_alloc();
599 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
601 goto err_release_res;
604 SET_NETDEV_DEV(netdev, &pdev->dev);
606 adapter = et131x_adapter_init(netdev, pdev);
607 /* Initialise the PCI setup for the device */
608 et131x_pci_init(adapter, pdev);
610 /* Map the bus-relative registers to system virtual memory */
611 adapter->regs = pci_ioremap_bar(pdev, 0);
612 if (!adapter->regs) {
613 dev_err(&pdev->dev, "Cannot map device registers\n");
618 /* If Phy COMA mode was enabled when we went down, disable it here. */
619 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
621 /* Issue a global reset to the et1310 */
622 et131x_soft_reset(adapter);
624 /* Disable all interrupts (paranoid) */
625 et131x_disable_interrupts(adapter);
627 /* Allocate DMA memory */
628 result = et131x_adapter_memory_alloc(adapter);
630 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
634 /* Init send data structures */
635 et131x_init_send(adapter);
637 /* Set up the task structure for the ISR's deferred handler */
638 INIT_WORK(&adapter->task, et131x_isr_handler);
640 /* Copy address into the net_device struct */
641 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
643 /* Setup et1310 as per the documentation */
644 et131x_adapter_setup(adapter);
646 /* Create a timer to count errors received by the NIC */
647 init_timer(&adapter->error_timer);
649 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
650 adapter->error_timer.function = et131x_error_timer_handler;
651 adapter->error_timer.data = (unsigned long)adapter;
653 /* Initialize link state */
654 netif_carrier_off(adapter->netdev);
656 /* Init variable for counting how long we do not have link status */
657 adapter->boot_coma = 0;
659 /* We can enable interrupts now
661 * NOTE - Because registration of interrupt handler is done in the
662 * device's open(), defer enabling device interrupts to that
666 /* Register the net_device struct with the Linux network layer */
667 result = register_netdev(netdev);
669 dev_err(&pdev->dev, "register_netdev() failed\n");
673 /* Register the net_device struct with the PCI subsystem. Save a copy
674 * of the PCI config space for this device now that the device has
675 * been initialized, just in case it needs to be quickly restored.
677 pci_set_drvdata(pdev, netdev);
678 pci_save_state(adapter->pdev);
683 et131x_adapter_memory_free(adapter);
685 iounmap(adapter->regs);
690 pci_release_regions(pdev);
692 pci_disable_device(pdev);
699 * @pdev: a pointer to the device's pci_dev structure
701 * Registered in the pci_driver structure, this function is called when the
702 * PCI subsystem detects that a PCI device which matches the information
703 * contained in the pci_device_id table has been removed.
705 static void __devexit et131x_pci_remove(struct pci_dev *pdev)
707 struct net_device *netdev;
708 struct et131x_adapter *adapter;
710 /* Retrieve the net_device pointer from the pci_dev struct, as well
711 * as the private adapter struct
713 netdev = pci_get_drvdata(pdev);
714 adapter = netdev_priv(netdev);
716 /* Perform device cleanup */
717 unregister_netdev(netdev);
718 et131x_adapter_memory_free(adapter);
719 iounmap(adapter->regs);
720 pci_dev_put(adapter->pdev);
722 pci_release_regions(pdev);
723 pci_disable_device(pdev);
726 static struct pci_device_id et131x_pci_table[] __devinitdata = {
727 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
728 PCI_ANY_ID, 0, 0, 0UL},
729 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
730 PCI_ANY_ID, 0, 0, 0UL},
734 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
736 static struct pci_driver et131x_driver = {
738 .id_table = et131x_pci_table,
739 .probe = et131x_pci_setup,
740 .remove = __devexit_p(et131x_pci_remove),
741 .suspend = NULL, /* et131x_pci_suspend */
742 .resume = NULL, /* et131x_pci_resume */
746 * et131x_init_module - The "main" entry point called on driver initialization
748 * Returns 0 on success, errno on failure (as defined in errno.h)
750 static int __init et131x_init_module(void)
752 return pci_register_driver(&et131x_driver);
756 * et131x_cleanup_module - The entry point called on driver cleanup
758 static void __exit et131x_cleanup_module(void)
760 pci_unregister_driver(&et131x_driver);
763 module_init(et131x_init_module);
764 module_exit(et131x_cleanup_module);
766 /* Modinfo parameters (filled out using defines from et131x_version.h) */
767 MODULE_AUTHOR(DRIVER_AUTHOR);
768 MODULE_DESCRIPTION(DRIVER_INFO);
769 MODULE_LICENSE(DRIVER_LICENSE);