3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
11 *------------------------------------------------------------------------------
15 * This software is provided subject to the following terms and conditions,
16 * which you should read carefully before using the software. Using this
17 * software indicates your acceptance of these terms and conditions. If you do
18 * not agree with these terms and conditions, do not use the software.
20 * Copyright © 2005 Agere Systems Inc.
21 * All rights reserved.
23 * Redistribution and use in source or binary forms, with or without
24 * modifications, are permitted provided that the following conditions are met:
26 * . Redistributions of source code must retain the above copyright notice, this
27 * list of conditions and the following Disclaimer as comments in the code as
28 * well as in the documentation and/or other materials provided with the
31 * . Redistributions in binary form must reproduce the above copyright notice,
32 * this list of conditions and the following Disclaimer in the documentation
33 * and/or other materials provided with the distribution.
35 * . Neither the name of Agere Systems Inc. nor the names of the contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
41 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
42 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
44 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
45 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
46 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
48 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
49 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56 #include <linux/pci.h>
57 #include <linux/init.h>
58 #include <linux/module.h>
59 #include <linux/types.h>
60 #include <linux/kernel.h>
62 #include <linux/sched.h>
63 #include <linux/ptrace.h>
64 #include <linux/slab.h>
65 #include <linux/ctype.h>
66 #include <linux/string.h>
67 #include <linux/timer.h>
68 #include <linux/interrupt.h>
70 #include <linux/delay.h>
71 #include <linux/bitops.h>
73 #include <asm/system.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_arp.h>
79 #include <linux/ioport.h>
80 #include <linux/crc32.h>
81 #include <linux/random.h>
82 #include <linux/phy.h>
86 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
87 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
88 MODULE_LICENSE("Dual BSD/GPL");
89 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
90 "for the ET1310 by Agere Systems");
93 #define MAX_NUM_REGISTER_POLLS 1000
94 #define MAX_NUM_WRITE_RETRIES 2
97 #define COUNTER_WRAP_16_BIT 0x10000
98 #define COUNTER_WRAP_12_BIT 0x1000
101 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
102 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
106 * For interrupts, normal running is:
107 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
108 * watchdog_interrupt & txdma_xfer_done
110 * In both cases, when flow control is enabled for either Tx or bi-direction,
111 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
112 * buffer rings are running low.
114 #define INT_MASK_DISABLE 0xffffffff
116 /* NOTE: Masking out MAC_STAT Interrupt for now...
117 * #define INT_MASK_ENABLE 0xfff6bf17
118 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
120 #define INT_MASK_ENABLE 0xfffebf17
121 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
123 /* General defines */
124 /* Packet and header sizes */
125 #define NIC_MIN_PACKET_SIZE 60
127 /* Multicast list size */
128 #define NIC_MAX_MCAST_LIST 128
130 /* Supported Filters */
131 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
132 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
133 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
134 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
135 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
138 #define ET131X_TX_TIMEOUT (1 * HZ)
139 #define NIC_SEND_HANG_THRESHOLD 0
142 #define fMP_DEST_MULTI 0x00000001
143 #define fMP_DEST_BROAD 0x00000002
145 /* MP_ADAPTER flags */
146 #define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
147 #define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
149 /* MP_SHARED flags */
150 #define fMP_ADAPTER_LOWER_POWER 0x00200000
152 #define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
153 #define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
155 #define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
157 /* Some offsets in PCI config space that are actually used. */
158 #define ET1310_PCI_MAX_PYLD 0x4C
159 #define ET1310_PCI_MAC_ADDRESS 0xA4
160 #define ET1310_PCI_EEPROM_STATUS 0xB2
161 #define ET1310_PCI_ACK_NACK 0xC0
162 #define ET1310_PCI_REPLAY 0xC2
163 #define ET1310_PCI_L0L1LATENCY 0xCF
165 /* PCI Product IDs */
166 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
167 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
169 /* Define order of magnitude converter */
170 #define NANO_IN_A_MICRO 1000
172 #define PARM_RX_NUM_BUFS_DEF 4
173 #define PARM_RX_TIME_INT_DEF 10
174 #define PARM_RX_MEM_END_DEF 0x2bc
175 #define PARM_TX_TIME_INT_DEF 40
176 #define PARM_TX_NUM_BUFS_DEF 4
177 #define PARM_DMA_CACHE_DEF 0
182 #define FBR_CHUNKS 32
184 #define MAX_DESC_PER_RING_RX 1024
186 /* number of RFDs - default and min */
188 #define RFD_LOW_WATER_MARK 40
189 #define NIC_DEFAULT_NUM_RFD 1024
192 #define RFD_LOW_WATER_MARK 20
193 #define NIC_DEFAULT_NUM_RFD 256
197 #define NIC_MIN_NUM_RFD 64
199 #define NUM_PACKETS_HANDLED 256
201 #define ALCATEL_MULTICAST_PKT 0x01000000
202 #define ALCATEL_BROADCAST_PKT 0x02000000
204 /* typedefs for Free Buffer Descriptors */
208 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
211 /* Packet Status Ring Descriptors
215 * top 16 bits are from the Alcatel Status Word as enumerated in
216 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
219 * 1: ipa IP checksum assist
220 * 2: ipp IP checksum pass
221 * 3: tcpa TCP checksum assist
222 * 4: tcpp TCP checksum pass
224 * 6: rxmac_error RXMAC Error Indicator
225 * 7: drop Drop packet
226 * 8: ft Frame Truncated
230 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
231 * 17: asw_RX_DV_event short receive event detected
232 * 18: asw_false_carrier_event bad carrier since last good packet
233 * 19: asw_code_err one or more nibbles signalled as errors
234 * 20: asw_CRC_err CRC error
235 * 21: asw_len_chk_err frame length field incorrect
236 * 22: asw_too_long frame length > 1518 bytes
237 * 23: asw_OK valid CRC + no code error
238 * 24: asw_multicast has a multicast address
239 * 25: asw_broadcast has a broadcast address
240 * 26: asw_dribble_nibble spurious bits after EOP
241 * 27: asw_control_frame is a control frame
242 * 28: asw_pause_frame is a pause frame
243 * 29: asw_unsupported_op unsupported OP code
244 * 30: asw_VLAN_tag VLAN tag detected
245 * 31: asw_long_evt Rx long event
248 * 0-15: length length in bytes
249 * 16-25: bi Buffer Index
250 * 26-27: ri Ring Index
254 struct pkt_stat_desc {
259 /* Typedefs for the RX DMA status word */
262 * rx status word 0 holds part of the status bits of the Rx DMA engine
263 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
264 * which contains the Free Buffer ring 0 and 1 available offset.
266 * bit 0-9 FBR1 offset
267 * bit 10 Wrap flag for FBR1
268 * bit 16-25 FBR0 offset
269 * bit 26 Wrap flag for FBR0
273 * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
274 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
275 * which contains the Packet Status Ring available offset.
278 * bit 16-27 PSRoffset
284 * struct rx_status_block is a structure representing the status of the Rx
285 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
287 struct rx_status_block {
293 * Structure for look-up table holding free buffer ring pointers, addresses
297 void *virt[MAX_DESC_PER_RING_RX];
298 void *buffer1[MAX_DESC_PER_RING_RX];
299 void *buffer2[MAX_DESC_PER_RING_RX];
300 u32 bus_high[MAX_DESC_PER_RING_RX];
301 u32 bus_low[MAX_DESC_PER_RING_RX];
303 dma_addr_t ring_physaddr;
304 void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
305 dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
306 uint64_t real_physaddr;
314 * struct rx_ring is the sructure representing the adaptor's local
315 * reference(s) to the rings
317 ******************************************************************************
318 * IMPORTANT NOTE :- fbr_lookup *fbr[NUM_FBRS] uses index 0 to refer to FBR1
319 * and index 1 to refer to FRB0
320 ******************************************************************************
323 struct fbr_lookup *fbr[NUM_FBRS];
324 void *ps_ring_virtaddr;
325 dma_addr_t ps_ring_physaddr;
329 struct rx_status_block *rx_status_block;
330 dma_addr_t rx_status_bus;
333 struct list_head recv_list;
338 bool unfinished_receives;
340 /* lookaside lists */
341 struct kmem_cache *recv_lookaside;
346 * word 2 of the control bits in the Tx Descriptor ring for the ET-1310
348 * 0-15: length of packet
351 * 29-31: VLAN priority
353 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
355 * 0: last packet in the sequence
356 * 1: first packet in the sequence
357 * 2: interrupt the processor when this pkt sent
358 * 3: Control word - no packet data
359 * 4: Issue half-duplex backpressure : XON/XOFF
360 * 5: send pause frame
361 * 6: Tx frame has error
365 * 10: Packet is a Huge packet
366 * 11: append VLAN tag
367 * 12: IP checksum assist
368 * 13: TCP checksum assist
369 * 14: UDP checksum assist
372 /* struct tx_desc represents each descriptor on the ring */
376 u32 len_vlan; /* control words how to xmit the */
377 u32 flags; /* data (detailed above) */
381 * The status of the Tx DMA engine it sits in free memory, and is pointed to
382 * by 0x101c / 0x1020. This is a DMA10 type
385 /* TCB (Transmit Control Block: Host Side) */
387 struct tcb *next; /* Next entry in ring */
388 u32 flags; /* Our flags for the packet */
389 u32 count; /* Used to spot stuck/lost packets */
390 u32 stale; /* Used to spot stuck/lost packets */
391 struct sk_buff *skb; /* Network skb we are tied to */
392 u32 index; /* Ring indexes */
396 /* Structure representing our local reference(s) to the ring */
398 /* TCB (Transmit Control Block) memory and lists */
399 struct tcb *tcb_ring;
401 /* List of TCBs that are ready to be used */
402 struct tcb *tcb_qhead;
403 struct tcb *tcb_qtail;
405 /* list of TCBs that are currently being sent. NOTE that access to all
406 * three of these (including used) are controlled via the
407 * TCBSendQLock. This lock should be secured prior to incementing /
408 * decrementing used, or any queue manipulation on send_head /
411 struct tcb *send_head;
412 struct tcb *send_tail;
415 /* The actual descriptor ring */
416 struct tx_desc *tx_desc_ring;
417 dma_addr_t tx_desc_ring_pa;
419 /* send_idx indicates where we last wrote to in the descriptor ring. */
422 /* The location of the write-back status block */
424 dma_addr_t tx_status_pa;
426 /* Packets since the last IRQ: used for interrupt coalescing */
430 /* ADAPTER defines */
432 * Do not change these values: if changed, then change also in respective
433 * TXdma and Rxdma engines
435 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
439 * These values are all superseded by registry entries to facilitate tuning.
440 * Once the desired performance has been achieved, the optimal registry values
441 * should be re-populated to these #defines:
443 #define TX_ERROR_PERIOD 1000
445 #define LO_MARK_PERCENT_FOR_PSR 15
446 #define LO_MARK_PERCENT_FOR_RX 15
448 /* RFD (Receive Frame Descriptor) */
450 struct list_head list_node;
452 u32 len; /* total size of receive frame */
459 #define FLOW_TXONLY 1
460 #define FLOW_RXONLY 2
463 /* Struct to define some device statistics */
467 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
468 * MUST have 32, then we'll need another way to perform atomic
471 u32 unicast_pkts_rcvd;
472 atomic_t unicast_pkts_xmtd;
473 u32 multicast_pkts_rcvd;
474 atomic_t multicast_pkts_xmtd;
475 u32 broadcast_pkts_rcvd;
476 atomic_t broadcast_pkts_xmtd;
477 u32 rcvd_pkts_dropped;
483 u32 tx_excessive_collisions;
484 u32 tx_first_collisions;
485 u32 tx_late_collisions;
495 u32 rx_code_violations;
498 u32 synchronous_iterations;
499 u32 interrupt_status;
502 /* The private adapter structure */
503 struct et131x_adapter {
504 struct net_device *netdev;
505 struct pci_dev *pdev;
506 struct mii_bus *mii_bus;
507 struct phy_device *phydev;
508 struct work_struct task;
510 /* Flags that indicate current state of the adapter */
513 /* local link state, to determine if a state change has occurred */
517 u8 rom_addr[ETH_ALEN];
525 spinlock_t tcb_send_qlock;
526 spinlock_t tcb_ready_qlock;
527 spinlock_t send_hw_lock;
530 spinlock_t rcv_pend_lock;
535 /* Packet Filter and look ahead size */
539 u32 multicast_addr_count;
540 u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
542 /* Pointer to the device's PCI register space */
543 struct address_map __iomem *regs;
545 /* Registry parameters */
546 u8 wanted_flow; /* Flow we want for 802.3x flow control */
547 u32 registry_jumbo_packet; /* Max supported ethernet packet size */
549 /* Derived from the registry: */
550 u8 flowcontrol; /* flow control validated by the far-end */
552 /* Minimize init-time */
553 struct timer_list error_timer;
555 /* variable putting the phy into coma mode when boot up with no cable
556 * plugged in after 5 seconds
560 /* Next two used to save power information at power down. This
561 * information will be used during power up to set up parts of Power
562 * Management in JAGCore
567 /* Tx Memory Variables */
568 struct tx_ring tx_ring;
570 /* Rx Memory Variables */
571 struct rx_ring rx_ring;
574 struct ce_stats stats;
576 struct net_device_stats net_stats;
579 void et1310_setup_device_for_multicast(struct et131x_adapter *adapter);
580 void et1310_setup_device_for_unicast(struct et131x_adapter *adapter);
581 void et131x_up(struct net_device *netdev);
582 void et131x_down(struct net_device *netdev);
583 void et131x_enable_txrx(struct net_device *netdev);
584 void et131x_disable_txrx(struct net_device *netdev);
585 int et1310_in_phy_coma(struct et131x_adapter *adapter);
586 void et1310_phy_access_mii_bit(struct et131x_adapter *adapter,
588 u16 regnum, u16 bitnum, u8 *value);
589 int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
591 int32_t et131x_mii_write(struct et131x_adapter *adapter,
593 void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
594 void et131x_rx_dma_disable(struct et131x_adapter *adapter);
595 void et131x_rx_dma_enable(struct et131x_adapter *adapter);
596 void et131x_init_send(struct et131x_adapter *adapter);
597 void et131x_tx_dma_enable(struct et131x_adapter *adapter);
599 /* EEPROM functions */
601 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
607 * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
608 * bits 7,1:0 both equal to 1, at least once after reset.
609 * Subsequent operations need only to check that bits 1:0 are equal
610 * to 1 prior to starting a single byte read/write
613 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
614 /* Read registers grouped in DWORD1 */
615 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
618 /* I2C idle and Phy Queue Avail both true */
619 if ((reg & 0x3000) == 0x3000) {
630 * eeprom_write - Write a byte to the ET1310's EEPROM
631 * @adapter: pointer to our private adapter structure
632 * @addr: the address to write
633 * @data: the value to write
635 * Returns 1 for a successful write.
637 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
639 struct pci_dev *pdev = adapter->pdev;
649 * For an EEPROM, an I2C single byte write is defined as a START
650 * condition followed by the device address, EEPROM address, one byte
651 * of data and a STOP condition. The STOP condition will trigger the
652 * EEPROM's internally timed write cycle to the nonvolatile memory.
653 * All inputs are disabled during this write cycle and the EEPROM will
654 * not respond to any access until the internal write is complete.
657 err = eeprom_wait_ready(pdev, NULL);
662 * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
663 * and bits 1:0 both =0. Bit 5 should be set according to the
664 * type of EEPROM being accessed (1=two byte addressing, 0=one
667 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
668 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
673 /* Prepare EEPROM address for Step 3 */
675 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
676 /* Write the address to the LBCIF Address Register */
677 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
680 * Write the data to the LBCIF Data Register (the I2C write
683 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
686 * Monitor bit 1:0 of the LBCIF Status Register. When bits
687 * 1:0 are both equal to 1, the I2C write has completed and the
688 * internal write cycle of the EEPROM is about to start.
689 * (bits 1:0 = 01 is a legal state while waiting from both
690 * equal to 1, but bits 1:0 = 10 is invalid and implies that
691 * something is broken).
693 err = eeprom_wait_ready(pdev, &status);
698 * Check bit 3 of the LBCIF Status Register. If equal to 1,
699 * an error has occurred.Don't break here if we are revision
700 * 1, this is so we do a blind write for load bug.
702 if ((status & LBCIF_STATUS_GENERAL_ERROR)
703 && adapter->pdev->revision == 0)
707 * Check bit 2 of the LBCIF Status Register. If equal to 1 an
708 * ACK error has occurred on the address phase of the write.
709 * This could be due to an actual hardware failure or the
710 * EEPROM may still be in its internal write cycle from a
711 * previous write. This write operation was ignored and must be
714 if (status & LBCIF_STATUS_ACK_ERROR) {
716 * This could be due to an actual hardware failure
717 * or the EEPROM may still be in its internal write
718 * cycle from a previous write. This write operation
719 * was ignored and must be repeated later.
730 * Set bit 6 of the LBCIF Control Register = 0.
735 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
736 LBCIF_CONTROL_LBCIF_ENABLE))
739 /* Do read until internal ACK_ERROR goes away meaning write
743 pci_write_config_dword(pdev,
744 LBCIF_ADDRESS_REGISTER,
747 pci_read_config_dword(pdev,
748 LBCIF_DATA_REGISTER, &val);
749 } while ((val & 0x00010000) == 0);
750 } while (val & 0x00040000);
752 if ((val & 0xFF00) != 0xC000 || index == 10000)
756 return writeok ? 0 : -EIO;
760 * eeprom_read - Read a byte from the ET1310's EEPROM
761 * @adapter: pointer to our private adapter structure
762 * @addr: the address from which to read
763 * @pdata: a pointer to a byte in which to store the value of the read
764 * @eeprom_id: the ID of the EEPROM
765 * @addrmode: how the EEPROM is to be accessed
767 * Returns 1 for a successful read
769 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
771 struct pci_dev *pdev = adapter->pdev;
776 * A single byte read is similar to the single byte write, with the
777 * exception of the data flow:
780 err = eeprom_wait_ready(pdev, NULL);
784 * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
785 * and bits 1:0 both =0. Bit 5 should be set according to the type
786 * of EEPROM being accessed (1=two byte addressing, 0=one byte
789 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
790 LBCIF_CONTROL_LBCIF_ENABLE))
793 * Write the address to the LBCIF Address Register (I2C read will
796 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
799 * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
800 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
803 err = eeprom_wait_ready(pdev, &status);
807 * Regardless of error status, read data byte from LBCIF Data
812 * Check bit 2 of the LBCIF Status Register. If = 1,
813 * then an error has occurred.
815 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
818 int et131x_init_eeprom(struct et131x_adapter *adapter)
820 struct pci_dev *pdev = adapter->pdev;
823 /* We first need to check the EEPROM Status code located at offset
824 * 0xB2 of config space
826 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
829 /* THIS IS A WORKAROUND:
830 * I need to call this function twice to get my card in a
831 * LG M1 Express Dual running. I tried also a msleep before this
832 * function, because I thougth there could be some time condidions
833 * but it didn't work. Call the whole function twice also work.
835 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
837 "Could not read PCI config space for EEPROM Status\n");
841 /* Determine if the error(s) we care about are present. If they are
842 * present we need to fail.
844 if (eestatus & 0x4C) {
845 int write_failed = 0;
846 if (pdev->revision == 0x01) {
848 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
850 /* Re-write the first 4 bytes if we have an eeprom
851 * present and the revision id is 1, this fixes the
852 * corruption seen with 1310 B Silicon
854 for (i = 0; i < 3; i++)
855 if (eeprom_write(adapter, i, eedata[i]) < 0)
858 if (pdev->revision != 0x01 || write_failed) {
860 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
862 /* This error could mean that there was an error
863 * reading the eeprom or that the eeprom doesn't exist.
864 * We will treat each case the same and not try to
865 * gather additional information that normally would
866 * come from the eeprom, like MAC Address
868 adapter->has_eeprom = 0;
872 adapter->has_eeprom = 1;
874 /* Read the EEPROM for information regarding LED behavior. Refer to
875 * ET1310_phy.c, et131x_xcvr_init(), for its use.
877 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
878 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
880 if (adapter->eeprom_data[0] != 0xcd)
881 /* Disable all optional features */
882 adapter->eeprom_data[1] = 0x00;
890 * et1310_config_mac_regs1 - Initialize the first part of MAC regs
891 * @adapter: pointer to our adapter structure
893 void et1310_config_mac_regs1(struct et131x_adapter *adapter)
895 struct mac_regs __iomem *macregs = &adapter->regs->mac;
900 /* First we need to reset everything. Write to MAC configuration
901 * register 1 to perform reset.
903 writel(0xC00F0000, ¯egs->cfg1);
905 /* Next lets configure the MAC Inter-packet gap register */
906 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
907 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
908 writel(ipg, ¯egs->ipg);
910 /* Next lets configure the MAC Half Duplex register */
911 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
912 writel(0x00A1F037, ¯egs->hfdp);
914 /* Next lets configure the MAC Interface Control register */
915 writel(0, ¯egs->if_ctrl);
917 /* Let's move on to setting up the mii management configuration */
918 writel(0x07, ¯egs->mii_mgmt_cfg); /* Clock reset 0x7 */
920 /* Next lets configure the MAC Station Address register. These
921 * values are read from the EEPROM during initialization and stored
922 * in the adapter structure. We write what is stored in the adapter
923 * structure to the MAC Station Address registers high and low. This
924 * station address is used for generating and checking pause control
927 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
928 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
929 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
930 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
931 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
933 writel(station1, ¯egs->station_addr_1);
934 writel(station2, ¯egs->station_addr_2);
936 /* Max ethernet packet in bytes that will passed by the mac without
937 * being truncated. Allow the MAC to pass 4 more than our max packet
938 * size. This is 4 for the Ethernet CRC.
940 * Packets larger than (registry_jumbo_packet) that do not contain a
941 * VLAN ID will be dropped by the Rx function.
943 writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
945 /* clear out MAC config reset */
946 writel(0, ¯egs->cfg1);
950 * et1310_config_mac_regs2 - Initialize the second part of MAC regs
951 * @adapter: pointer to our adapter structure
953 void et1310_config_mac_regs2(struct et131x_adapter *adapter)
956 struct mac_regs __iomem *mac = &adapter->regs->mac;
957 struct phy_device *phydev = adapter->phydev;
963 ctl = readl(&adapter->regs->txmac.ctl);
964 cfg1 = readl(&mac->cfg1);
965 cfg2 = readl(&mac->cfg2);
966 ifctrl = readl(&mac->if_ctrl);
968 /* Set up the if mode bits */
970 if (phydev && phydev->speed == SPEED_1000) {
973 ifctrl &= ~(1 << 24);
979 /* We need to enable Rx/Tx */
980 cfg1 |= CFG1_RX_ENABLE | CFG1_TX_ENABLE | CFG1_TX_FLOW;
981 /* Initialize loop back to off */
982 cfg1 &= ~(CFG1_LOOPBACK | CFG1_RX_FLOW);
983 if (adapter->flowcontrol == FLOW_RXONLY ||
984 adapter->flowcontrol == FLOW_BOTH)
985 cfg1 |= CFG1_RX_FLOW;
986 writel(cfg1, &mac->cfg1);
988 /* Now we need to initialize the MAC Configuration 2 register */
989 /* preamble 7, check length, huge frame off, pad crc, crc enable
994 /* Turn on duplex if needed */
995 if (phydev && phydev->duplex == DUPLEX_FULL)
998 ifctrl &= ~(1 << 26);
999 if (phydev && phydev->duplex == DUPLEX_HALF)
1000 ifctrl |= (1<<26); /* Enable ghd */
1002 writel(ifctrl, &mac->if_ctrl);
1003 writel(cfg2, &mac->cfg2);
1008 cfg1 = readl(&mac->cfg1);
1009 } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
1012 dev_warn(&adapter->pdev->dev,
1013 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1018 ctl |= 0x09; /* TX mac enable, FC disable */
1019 writel(ctl, &adapter->regs->txmac.ctl);
1021 /* Ready to start the RXDMA/TXDMA engine */
1022 if (adapter->flags & fMP_ADAPTER_LOWER_POWER) {
1023 et131x_rx_dma_enable(adapter);
1024 et131x_tx_dma_enable(adapter);
1028 void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1030 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1031 struct phy_device *phydev = adapter->phydev;
1036 /* Disable the MAC while it is being configured (also disable WOL) */
1037 writel(0x8, &rxmac->ctrl);
1039 /* Initialize WOL to disabled. */
1040 writel(0, &rxmac->crc0);
1041 writel(0, &rxmac->crc12);
1042 writel(0, &rxmac->crc34);
1044 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1045 * its default Values of 0x00000000 because there are not WOL masks
1048 writel(0, &rxmac->mask0_word0);
1049 writel(0, &rxmac->mask0_word1);
1050 writel(0, &rxmac->mask0_word2);
1051 writel(0, &rxmac->mask0_word3);
1053 writel(0, &rxmac->mask1_word0);
1054 writel(0, &rxmac->mask1_word1);
1055 writel(0, &rxmac->mask1_word2);
1056 writel(0, &rxmac->mask1_word3);
1058 writel(0, &rxmac->mask2_word0);
1059 writel(0, &rxmac->mask2_word1);
1060 writel(0, &rxmac->mask2_word2);
1061 writel(0, &rxmac->mask2_word3);
1063 writel(0, &rxmac->mask3_word0);
1064 writel(0, &rxmac->mask3_word1);
1065 writel(0, &rxmac->mask3_word2);
1066 writel(0, &rxmac->mask3_word3);
1068 writel(0, &rxmac->mask4_word0);
1069 writel(0, &rxmac->mask4_word1);
1070 writel(0, &rxmac->mask4_word2);
1071 writel(0, &rxmac->mask4_word3);
1073 /* Lets setup the WOL Source Address */
1074 sa_lo = (adapter->addr[2] << ET_WOL_LO_SA3_SHIFT) |
1075 (adapter->addr[3] << ET_WOL_LO_SA4_SHIFT) |
1076 (adapter->addr[4] << ET_WOL_LO_SA5_SHIFT) |
1078 writel(sa_lo, &rxmac->sa_lo);
1080 sa_hi = (u32) (adapter->addr[0] << ET_WOL_HI_SA1_SHIFT) |
1082 writel(sa_hi, &rxmac->sa_hi);
1084 /* Disable all Packet Filtering */
1085 writel(0, &rxmac->pf_ctrl);
1087 /* Let's initialize the Unicast Packet filtering address */
1088 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1089 et1310_setup_device_for_unicast(adapter);
1090 pf_ctrl |= 4; /* Unicast filter */
1092 writel(0, &rxmac->uni_pf_addr1);
1093 writel(0, &rxmac->uni_pf_addr2);
1094 writel(0, &rxmac->uni_pf_addr3);
1097 /* Let's initialize the Multicast hash */
1098 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1099 pf_ctrl |= 2; /* Multicast filter */
1100 et1310_setup_device_for_multicast(adapter);
1103 /* Runt packet filtering. Didn't work in version A silicon. */
1104 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
1105 pf_ctrl |= 8; /* Fragment filter */
1107 if (adapter->registry_jumbo_packet > 8192)
1108 /* In order to transmit jumbo packets greater than 8k, the
1109 * FIFO between RxMAC and RxDMA needs to be reduced in size
1110 * to (16k - Jumbo packet size). In order to implement this,
1111 * we must use "cut through" mode in the RxMAC, which chops
1112 * packets down into segments which are (max_size * 16). In
1113 * this case we selected 256 bytes, since this is the size of
1114 * the PCI-Express TLP's that the 1310 uses.
1116 * seg_en on, fc_en off, size 0x10
1118 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1120 writel(0, &rxmac->mcif_ctrl_max_seg);
1122 /* Initialize the MCIF water marks */
1123 writel(0, &rxmac->mcif_water_mark);
1125 /* Initialize the MIF control */
1126 writel(0, &rxmac->mif_ctrl);
1128 /* Initialize the Space Available Register */
1129 writel(0, &rxmac->space_avail);
1131 /* Initialize the the mif_ctrl register
1132 * bit 3: Receive code error. One or more nibbles were signaled as
1133 * errors during the reception of the packet. Clear this
1134 * bit in Gigabit, set it in 100Mbit. This was derived
1135 * experimentally at UNH.
1136 * bit 4: Receive CRC error. The packet's CRC did not match the
1137 * internally generated CRC.
1138 * bit 5: Receive length check error. Indicates that frame length
1139 * field value in the packet does not match the actual data
1140 * byte length and is not a type field.
1141 * bit 16: Receive frame truncated.
1142 * bit 17: Drop packet enable
1144 if (phydev && phydev->speed == SPEED_100)
1145 writel(0x30038, &rxmac->mif_ctrl);
1147 writel(0x30030, &rxmac->mif_ctrl);
1149 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1150 * filter is always enabled since it is where the runt packets are
1151 * supposed to be dropped. For version A silicon, runt packet
1152 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1153 * but we still leave the packet filter on.
1155 writel(pf_ctrl, &rxmac->pf_ctrl);
1156 writel(0x9, &rxmac->ctrl);
1159 void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1161 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1163 /* We need to update the Control Frame Parameters
1164 * cfpt - control frame pause timer set to 64 (0x40)
1165 * cfep - control frame extended pause timer set to 0x0
1167 if (adapter->flowcontrol == FLOW_NONE)
1168 writel(0, &txmac->cf_param);
1170 writel(0x40, &txmac->cf_param);
1173 void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1175 struct macstat_regs __iomem *macstat =
1176 &adapter->regs->macstat;
1178 /* Next we need to initialize all the macstat registers to zero on
1181 writel(0, &macstat->txrx_0_64_byte_frames);
1182 writel(0, &macstat->txrx_65_127_byte_frames);
1183 writel(0, &macstat->txrx_128_255_byte_frames);
1184 writel(0, &macstat->txrx_256_511_byte_frames);
1185 writel(0, &macstat->txrx_512_1023_byte_frames);
1186 writel(0, &macstat->txrx_1024_1518_byte_frames);
1187 writel(0, &macstat->txrx_1519_1522_gvln_frames);
1189 writel(0, &macstat->rx_bytes);
1190 writel(0, &macstat->rx_packets);
1191 writel(0, &macstat->rx_fcs_errs);
1192 writel(0, &macstat->rx_multicast_packets);
1193 writel(0, &macstat->rx_broadcast_packets);
1194 writel(0, &macstat->rx_control_frames);
1195 writel(0, &macstat->rx_pause_frames);
1196 writel(0, &macstat->rx_unknown_opcodes);
1197 writel(0, &macstat->rx_align_errs);
1198 writel(0, &macstat->rx_frame_len_errs);
1199 writel(0, &macstat->rx_code_errs);
1200 writel(0, &macstat->rx_carrier_sense_errs);
1201 writel(0, &macstat->rx_undersize_packets);
1202 writel(0, &macstat->rx_oversize_packets);
1203 writel(0, &macstat->rx_fragment_packets);
1204 writel(0, &macstat->rx_jabbers);
1205 writel(0, &macstat->rx_drops);
1207 writel(0, &macstat->tx_bytes);
1208 writel(0, &macstat->tx_packets);
1209 writel(0, &macstat->tx_multicast_packets);
1210 writel(0, &macstat->tx_broadcast_packets);
1211 writel(0, &macstat->tx_pause_frames);
1212 writel(0, &macstat->tx_deferred);
1213 writel(0, &macstat->tx_excessive_deferred);
1214 writel(0, &macstat->tx_single_collisions);
1215 writel(0, &macstat->tx_multiple_collisions);
1216 writel(0, &macstat->tx_late_collisions);
1217 writel(0, &macstat->tx_excessive_collisions);
1218 writel(0, &macstat->tx_total_collisions);
1219 writel(0, &macstat->tx_pause_honored_frames);
1220 writel(0, &macstat->tx_drops);
1221 writel(0, &macstat->tx_jabbers);
1222 writel(0, &macstat->tx_fcs_errs);
1223 writel(0, &macstat->tx_control_frames);
1224 writel(0, &macstat->tx_oversize_frames);
1225 writel(0, &macstat->tx_undersize_frames);
1226 writel(0, &macstat->tx_fragments);
1227 writel(0, &macstat->carry_reg1);
1228 writel(0, &macstat->carry_reg2);
1230 /* Unmask any counters that we want to track the overflow of.
1231 * Initially this will be all counters. It may become clear later
1232 * that we do not need to track all counters.
1234 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1235 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1238 void et1310_config_flow_control(struct et131x_adapter *adapter)
1240 struct phy_device *phydev = adapter->phydev;
1242 if (phydev->duplex == DUPLEX_HALF) {
1243 adapter->flowcontrol = FLOW_NONE;
1245 char remote_pause, remote_async_pause;
1247 et1310_phy_access_mii_bit(adapter,
1248 TRUEPHY_BIT_READ, 5, 10, &remote_pause);
1249 et1310_phy_access_mii_bit(adapter,
1250 TRUEPHY_BIT_READ, 5, 11,
1251 &remote_async_pause);
1253 if ((remote_pause == TRUEPHY_BIT_SET) &&
1254 (remote_async_pause == TRUEPHY_BIT_SET)) {
1255 adapter->flowcontrol = adapter->wanted_flow;
1256 } else if ((remote_pause == TRUEPHY_BIT_SET) &&
1257 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
1258 if (adapter->wanted_flow == FLOW_BOTH)
1259 adapter->flowcontrol = FLOW_BOTH;
1261 adapter->flowcontrol = FLOW_NONE;
1262 } else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
1263 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
1264 adapter->flowcontrol = FLOW_NONE;
1265 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
1266 remote_async_pause == TRUEPHY_SET_BIT) */
1267 if (adapter->wanted_flow == FLOW_BOTH)
1268 adapter->flowcontrol = FLOW_RXONLY;
1270 adapter->flowcontrol = FLOW_NONE;
1276 * et1310_update_macstat_host_counters - Update the local copy of the statistics
1277 * @adapter: pointer to the adapter structure
1279 void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1281 struct ce_stats *stats = &adapter->stats;
1282 struct macstat_regs __iomem *macstat =
1283 &adapter->regs->macstat;
1285 stats->tx_collisions += readl(&macstat->tx_total_collisions);
1286 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
1287 stats->tx_deferred += readl(&macstat->tx_deferred);
1288 stats->tx_excessive_collisions +=
1289 readl(&macstat->tx_multiple_collisions);
1290 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
1291 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
1292 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
1294 stats->rx_align_errs += readl(&macstat->rx_align_errs);
1295 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
1296 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
1297 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
1298 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
1299 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
1300 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
1304 * et1310_handle_macstat_interrupt
1305 * @adapter: pointer to the adapter structure
1307 * One of the MACSTAT counters has wrapped. Update the local copy of
1308 * the statistics held in the adapter structure, checking the "wrap"
1309 * bit for each counter.
1311 void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1316 /* Read the interrupt bits from the register(s). These are Clear On
1319 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1320 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1322 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1323 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1325 /* We need to do update the host copy of all the MAC_STAT counters.
1326 * For each counter, check it's overflow bit. If the overflow bit is
1327 * set, then increment the host version of the count by one complete
1328 * revolution of the counter. This routine is called when the counter
1329 * block indicates that one of the counters has wrapped.
1331 if (carry_reg1 & (1 << 14))
1332 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
1333 if (carry_reg1 & (1 << 8))
1334 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
1335 if (carry_reg1 & (1 << 7))
1336 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
1337 if (carry_reg1 & (1 << 2))
1338 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
1339 if (carry_reg1 & (1 << 6))
1340 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
1341 if (carry_reg1 & (1 << 3))
1342 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
1343 if (carry_reg1 & (1 << 0))
1344 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
1345 if (carry_reg2 & (1 << 16))
1346 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
1347 if (carry_reg2 & (1 << 15))
1348 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
1349 if (carry_reg2 & (1 << 6))
1350 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1351 if (carry_reg2 & (1 << 8))
1352 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
1353 if (carry_reg2 & (1 << 5))
1354 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1355 if (carry_reg2 & (1 << 4))
1356 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
1357 if (carry_reg2 & (1 << 2))
1358 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
1361 void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1363 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1372 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1373 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1374 * specified) then we should pass NO multi-cast addresses to the
1377 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1378 /* Loop through our multicast array and set up the device */
1379 for (nIndex = 0; nIndex < adapter->multicast_addr_count;
1381 result = ether_crc(6, adapter->multicast_list[nIndex]);
1383 result = (result & 0x3F800000) >> 23;
1386 hash1 |= (1 << result);
1387 } else if ((31 < result) && (result < 64)) {
1389 hash2 |= (1 << result);
1390 } else if ((63 < result) && (result < 96)) {
1392 hash3 |= (1 << result);
1395 hash4 |= (1 << result);
1400 /* Write out the new hash to the device */
1401 pm_csr = readl(&adapter->regs->global.pm_csr);
1402 if (!et1310_in_phy_coma(adapter)) {
1403 writel(hash1, &rxmac->multi_hash1);
1404 writel(hash2, &rxmac->multi_hash2);
1405 writel(hash3, &rxmac->multi_hash3);
1406 writel(hash4, &rxmac->multi_hash4);
1410 void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1412 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1418 /* Set up unicast packet filter reg 3 to be the first two octets of
1419 * the MAC address for both address
1421 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1422 * MAC address for second address
1424 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1425 * MAC address for first address
1427 uni_pf3 = (adapter->addr[0] << ET_UNI_PF_ADDR2_1_SHIFT) |
1428 (adapter->addr[1] << ET_UNI_PF_ADDR2_2_SHIFT) |
1429 (adapter->addr[0] << ET_UNI_PF_ADDR1_1_SHIFT) |
1432 uni_pf2 = (adapter->addr[2] << ET_UNI_PF_ADDR2_3_SHIFT) |
1433 (adapter->addr[3] << ET_UNI_PF_ADDR2_4_SHIFT) |
1434 (adapter->addr[4] << ET_UNI_PF_ADDR2_5_SHIFT) |
1437 uni_pf1 = (adapter->addr[2] << ET_UNI_PF_ADDR1_3_SHIFT) |
1438 (adapter->addr[3] << ET_UNI_PF_ADDR1_4_SHIFT) |
1439 (adapter->addr[4] << ET_UNI_PF_ADDR1_5_SHIFT) |
1442 pm_csr = readl(&adapter->regs->global.pm_csr);
1443 if (!et1310_in_phy_coma(adapter)) {
1444 writel(uni_pf1, &rxmac->uni_pf_addr1);
1445 writel(uni_pf2, &rxmac->uni_pf_addr2);
1446 writel(uni_pf3, &rxmac->uni_pf_addr3);
1452 int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1454 struct net_device *netdev = bus->priv;
1455 struct et131x_adapter *adapter = netdev_priv(netdev);
1459 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1467 int et131x_mdio_write(struct mii_bus *bus, int phy_addr, int reg, u16 value)
1469 struct net_device *netdev = bus->priv;
1470 struct et131x_adapter *adapter = netdev_priv(netdev);
1472 return et131x_mii_write(adapter, reg, value);
1475 int et131x_mdio_reset(struct mii_bus *bus)
1477 struct net_device *netdev = bus->priv;
1478 struct et131x_adapter *adapter = netdev_priv(netdev);
1480 et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
1485 int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1487 struct phy_device *phydev = adapter->phydev;
1492 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1496 * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1497 * @adapter: pointer to our private adapter structure
1498 * @addr: the address of the transceiver
1499 * @reg: the register to read
1500 * @value: pointer to a 16-bit value in which the value will be stored
1502 * Returns 0 on success, errno on failure (as defined in errno.h)
1504 int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1507 struct mac_regs __iomem *mac = &adapter->regs->mac;
1514 /* Save a local copy of the registers we are dealing with so we can
1517 mii_addr = readl(&mac->mii_mgmt_addr);
1518 mii_cmd = readl(&mac->mii_mgmt_cmd);
1520 /* Stop the current operation */
1521 writel(0, &mac->mii_mgmt_cmd);
1523 /* Set up the register we need to read from on the correct PHY */
1524 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1526 writel(0x1, &mac->mii_mgmt_cmd);
1531 mii_indicator = readl(&mac->mii_mgmt_indicator);
1532 } while ((mii_indicator & MGMT_WAIT) && delay < 50);
1534 /* If we hit the max delay, we could not read the register */
1536 dev_warn(&adapter->pdev->dev,
1537 "reg 0x%08x could not be read\n", reg);
1538 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1544 /* If we hit here we were able to read the register and we need to
1545 * return the value to the caller */
1546 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
1548 /* Stop the read operation */
1549 writel(0, &mac->mii_mgmt_cmd);
1551 /* set the registers we touched back to the state at which we entered
1554 writel(mii_addr, &mac->mii_mgmt_addr);
1555 writel(mii_cmd, &mac->mii_mgmt_cmd);
1561 * et131x_mii_write - Write to a PHY register through the MII interface of the MAC
1562 * @adapter: pointer to our private adapter structure
1563 * @reg: the register to read
1564 * @value: 16-bit value to write
1566 * FIXME: one caller in netdev still
1568 * Return 0 on success, errno on failure (as defined in errno.h)
1570 int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
1572 struct mac_regs __iomem *mac = &adapter->regs->mac;
1573 struct phy_device *phydev = adapter->phydev;
1584 addr = phydev->addr;
1586 /* Save a local copy of the registers we are dealing with so we can
1589 mii_addr = readl(&mac->mii_mgmt_addr);
1590 mii_cmd = readl(&mac->mii_mgmt_cmd);
1592 /* Stop the current operation */
1593 writel(0, &mac->mii_mgmt_cmd);
1595 /* Set up the register we need to write to on the correct PHY */
1596 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1598 /* Add the value to write to the registers to the mac */
1599 writel(value, &mac->mii_mgmt_ctrl);
1604 mii_indicator = readl(&mac->mii_mgmt_indicator);
1605 } while ((mii_indicator & MGMT_BUSY) && delay < 100);
1607 /* If we hit the max delay, we could not write the register */
1611 dev_warn(&adapter->pdev->dev,
1612 "reg 0x%08x could not be written", reg);
1613 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1615 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1616 readl(&mac->mii_mgmt_cmd));
1618 et131x_mii_read(adapter, reg, &tmp);
1622 /* Stop the write operation */
1623 writel(0, &mac->mii_mgmt_cmd);
1626 * set the registers we touched back to the state at which we entered
1629 writel(mii_addr, &mac->mii_mgmt_addr);
1630 writel(mii_cmd, &mac->mii_mgmt_cmd);
1636 * et1310_phy_power_down - PHY power control
1637 * @adapter: device to control
1638 * @down: true for off/false for back on
1640 * one hundred, ten, one thousand megs
1641 * How would you like to have your LAN accessed
1642 * Can't you see that this code processed
1643 * Phy power, phy power..
1645 void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
1649 et131x_mii_read(adapter, MII_BMCR, &data);
1650 data &= ~BMCR_PDOWN;
1653 et131x_mii_write(adapter, MII_BMCR, data);
1656 /* Still used from _mac for BIT_READ */
1657 void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action,
1658 u16 regnum, u16 bitnum, u8 *value)
1661 u16 mask = 0x0001 << bitnum;
1663 /* Read the requested register */
1664 et131x_mii_read(adapter, regnum, ®);
1667 case TRUEPHY_BIT_READ:
1668 *value = (reg & mask) >> bitnum;
1671 case TRUEPHY_BIT_SET:
1672 et131x_mii_write(adapter, regnum, reg | mask);
1675 case TRUEPHY_BIT_CLEAR:
1676 et131x_mii_write(adapter, regnum, reg & ~mask);
1685 * et131x_xcvr_init - Init the phy if we are setting it into force mode
1686 * @adapter: pointer to our private adapter structure
1689 void et131x_xcvr_init(struct et131x_adapter *adapter)
1695 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr);
1696 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr);
1698 /* Set the link status interrupt only. Bad behavior when link status
1699 * and auto neg are set, we run into a nested interrupt problem
1701 imr |= (ET_PHY_INT_MASK_AUTONEGSTAT &
1702 ET_PHY_INT_MASK_LINKSTAT &
1703 ET_PHY_INT_MASK_ENABLE);
1705 et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr);
1707 /* Set the LED behavior such that LED 1 indicates speed (off =
1708 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1709 * link and activity (on for link, blink off for activity).
1711 * NOTE: Some customizations have been added here for specific
1712 * vendors; The LED behavior is now determined by vendor data in the
1713 * EEPROM. However, the above description is the default.
1715 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1716 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1718 lcr2 &= (ET_LED2_LED_100TX & ET_LED2_LED_1000T);
1719 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1721 if ((adapter->eeprom_data[1] & 0x8) == 0)
1722 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1724 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1726 et131x_mii_write(adapter, PHY_LED_2, lcr2);
1731 * et131x_configure_global_regs - configure JAGCore global regs
1732 * @adapter: pointer to our adapter structure
1734 * Used to configure the global registers on the JAGCore
1736 void et131x_configure_global_regs(struct et131x_adapter *adapter)
1738 struct global_regs __iomem *regs = &adapter->regs->global;
1740 writel(0, ®s->rxq_start_addr);
1741 writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
1743 if (adapter->registry_jumbo_packet < 2048) {
1744 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1745 * block of RAM that the driver can split between Tx
1746 * and Rx as it desires. Our default is to split it
1749 writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
1750 writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
1751 } else if (adapter->registry_jumbo_packet < 8192) {
1752 /* For jumbo packets > 2k but < 8k, split 50-50. */
1753 writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
1754 writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
1756 /* 9216 is the only packet size greater than 8k that
1757 * is available. The Tx buffer has to be big enough
1758 * for one whole packet on the Tx side. We'll make
1759 * the Tx 9408, and give the rest to Rx
1761 writel(0x01b3, ®s->rxq_end_addr);
1762 writel(0x01b4, ®s->txq_start_addr);
1765 /* Initialize the loopback register. Disable all loopbacks. */
1766 writel(0, ®s->loopback);
1769 writel(0, ®s->msi_config);
1771 /* By default, disable the watchdog timer. It will be enabled when
1772 * a packet is queued.
1774 writel(0, ®s->watchdog_timer);
1780 * et1310_in_phy_coma - check if the device is in phy coma
1781 * @adapter: pointer to our adapter structure
1783 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1785 int et1310_in_phy_coma(struct et131x_adapter *adapter)
1789 pmcsr = readl(&adapter->regs->global.pm_csr);
1791 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1795 * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence
1796 * @adapter: pointer to our adapter structure
1798 void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1800 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1801 struct rx_ring *rx_local = &adapter->rx_ring;
1802 struct fbr_desc *fbr_entry;
1805 unsigned long flags;
1807 /* Halt RXDMA to perform the reconfigure. */
1808 et131x_rx_dma_disable(adapter);
1810 /* Load the completion writeback physical address
1812 * NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
1813 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
1814 * are ever returned, make sure the high part is retrieved here
1815 * before storing the adjusted address.
1817 writel((u32) ((u64)rx_local->rx_status_bus >> 32),
1818 &rx_dma->dma_wb_base_hi);
1819 writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo);
1821 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1823 /* Set the address and parameters of the packet status ring into the
1826 writel((u32) ((u64)rx_local->ps_ring_physaddr >> 32),
1827 &rx_dma->psr_base_hi);
1828 writel((u32) rx_local->ps_ring_physaddr, &rx_dma->psr_base_lo);
1829 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1830 writel(0, &rx_dma->psr_full_offset);
1832 psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
1833 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1834 &rx_dma->psr_min_des);
1836 spin_lock_irqsave(&adapter->rcv_lock, flags);
1838 /* These local variables track the PSR in the adapter structure */
1839 rx_local->local_psr_full = 0;
1841 /* Now's the best time to initialize FBR1 contents */
1842 fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
1843 for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
1844 fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
1845 fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
1846 fbr_entry->word2 = entry;
1850 /* Set the address and parameters of Free buffer ring 1 (and 0 if
1851 * required) into the 1310's registers
1853 writel((u32) (rx_local->fbr[0]->real_physaddr >> 32),
1854 &rx_dma->fbr1_base_hi);
1855 writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr1_base_lo);
1856 writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr1_num_des);
1857 writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
1859 /* This variable tracks the free buffer ring 1 full position, so it
1860 * has to match the above.
1862 rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
1864 ((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1865 &rx_dma->fbr1_min_des);
1868 /* Now's the best time to initialize FBR0 contents */
1869 fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
1870 for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
1871 fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
1872 fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
1873 fbr_entry->word2 = entry;
1877 writel((u32) (rx_local->fbr[1]->real_physaddr >> 32),
1878 &rx_dma->fbr0_base_hi);
1879 writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr0_base_lo);
1880 writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr0_num_des);
1881 writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
1883 /* This variable tracks the free buffer ring 0 full position, so it
1884 * has to match the above.
1886 rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
1888 ((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1889 &rx_dma->fbr0_min_des);
1892 /* Program the number of packets we will receive before generating an
1894 * For version B silicon, this value gets updated once autoneg is
1897 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1899 /* The "time_done" is not working correctly to coalesce interrupts
1900 * after a given time period, but rather is giving us an interrupt
1901 * regardless of whether we have received packets.
1902 * This value gets updated once autoneg is complete.
1904 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1906 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1910 * et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1911 * @adapter: pointer to our private adapter structure
1913 * Configure the transmit engine with the ring buffers we have created
1914 * and prepare it for use.
1916 void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
1918 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
1920 /* Load the hardware with the start of the transmit descriptor ring. */
1921 writel((u32) ((u64)adapter->tx_ring.tx_desc_ring_pa >> 32),
1922 &txdma->pr_base_hi);
1923 writel((u32) adapter->tx_ring.tx_desc_ring_pa,
1924 &txdma->pr_base_lo);
1926 /* Initialise the transmit DMA engine */
1927 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
1929 /* Load the completion writeback physical address */
1930 writel((u32)((u64)adapter->tx_ring.tx_status_pa >> 32),
1931 &txdma->dma_wb_base_hi);
1932 writel((u32)adapter->tx_ring.tx_status_pa, &txdma->dma_wb_base_lo);
1934 *adapter->tx_ring.tx_status = 0;
1936 writel(0, &txdma->service_request);
1937 adapter->tx_ring.send_idx = 0;
1941 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
1942 * @adapter: pointer to our private adapter structure
1944 * Returns 0 on success, errno on failure (as defined in errno.h)
1946 void et131x_adapter_setup(struct et131x_adapter *adapter)
1948 /* Configure the JAGCore */
1949 et131x_configure_global_regs(adapter);
1951 et1310_config_mac_regs1(adapter);
1953 /* Configure the MMC registers */
1954 /* All we need to do is initialize the Memory Control Register */
1955 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
1957 et1310_config_rxmac_regs(adapter);
1958 et1310_config_txmac_regs(adapter);
1960 et131x_config_rx_dma_regs(adapter);
1961 et131x_config_tx_dma_regs(adapter);
1963 et1310_config_macstat_regs(adapter);
1965 et1310_phy_power_down(adapter, 0);
1966 et131x_xcvr_init(adapter);
1970 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
1971 * @adapter: pointer to our private adapter structure
1973 void et131x_soft_reset(struct et131x_adapter *adapter)
1975 /* Disable MAC Core */
1976 writel(0xc00f0000, &adapter->regs->mac.cfg1);
1978 /* Set everything to a reset value */
1979 writel(0x7F, &adapter->regs->global.sw_reset);
1980 writel(0x000f0000, &adapter->regs->mac.cfg1);
1981 writel(0x00000000, &adapter->regs->mac.cfg1);
1985 * et1310_enable_phy_coma - called when network cable is unplugged
1986 * @adapter: pointer to our adapter structure
1988 * driver receive an phy status change interrupt while in D0 and check that
1989 * phy_status is down.
1991 * -- gate off JAGCore;
1992 * -- set gigE PHY in Coma mode
1993 * -- wake on phy_interrupt; Perform software reset JAGCore,
1994 * re-initialize jagcore and gigE PHY
1996 * Add D0-ASPM-PhyLinkDown Support:
1997 * -- while in D0, when there is a phy_interrupt indicating phy link
1998 * down status, call the MPSetPhyComa routine to enter this active
1999 * state power saving mode
2000 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
2001 * indicating linkup status, call the MPDisablePhyComa routine to
2002 * restore JAGCore and gigE PHY
2004 void et1310_enable_phy_coma(struct et131x_adapter *adapter)
2006 unsigned long flags;
2009 pmcsr = readl(&adapter->regs->global.pm_csr);
2011 /* Save the GbE PHY speed and duplex modes. Need to restore this
2012 * when cable is plugged back in
2015 * TODO - when PM is re-enabled, check if we need to
2016 * perform a similar task as this -
2017 * adapter->pdown_speed = adapter->ai_force_speed;
2018 * adapter->pdown_duplex = adapter->ai_force_duplex;
2021 /* Stop sending packets. */
2022 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2023 adapter->flags |= fMP_ADAPTER_LOWER_POWER;
2024 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2026 /* Wait for outstanding Receive packets */
2028 et131x_disable_txrx(adapter->netdev);
2030 /* Gate off JAGCore 3 clock domains */
2031 pmcsr &= ~ET_PMCSR_INIT;
2032 writel(pmcsr, &adapter->regs->global.pm_csr);
2034 /* Program gigE PHY in to Coma mode */
2035 pmcsr |= ET_PM_PHY_SW_COMA;
2036 writel(pmcsr, &adapter->regs->global.pm_csr);
2040 * et1310_disable_phy_coma - Disable the Phy Coma Mode
2041 * @adapter: pointer to our adapter structure
2043 void et1310_disable_phy_coma(struct et131x_adapter *adapter)
2047 pmcsr = readl(&adapter->regs->global.pm_csr);
2049 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
2050 pmcsr |= ET_PMCSR_INIT;
2051 pmcsr &= ~ET_PM_PHY_SW_COMA;
2052 writel(pmcsr, &adapter->regs->global.pm_csr);
2054 /* Restore the GbE PHY speed and duplex modes;
2055 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
2057 /* TODO - when PM is re-enabled, check if we need to
2058 * perform a similar task as this -
2059 * adapter->ai_force_speed = adapter->pdown_speed;
2060 * adapter->ai_force_duplex = adapter->pdown_duplex;
2063 /* Re-initialize the send structures */
2064 et131x_init_send(adapter);
2066 /* Bring the device back to the state it was during init prior to
2067 * autonegotiation being complete. This way, when we get the auto-neg
2068 * complete interrupt, we can complete init by calling ConfigMacREGS2.
2070 et131x_soft_reset(adapter);
2072 /* setup et1310 as per the documentation ?? */
2073 et131x_adapter_setup(adapter);
2075 /* Allow Tx to restart */
2076 adapter->flags &= ~fMP_ADAPTER_LOWER_POWER;
2078 et131x_enable_txrx(adapter->netdev);
2083 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
2085 u32 tmp_free_buff_ring = *free_buff_ring;
2086 tmp_free_buff_ring++;
2087 /* This works for all cases where limit < 1024. The 1023 case
2088 works because 1023++ is 1024 which means the if condition is not
2089 taken but the carry of the bit into the wrap bit toggles the wrap
2091 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
2092 tmp_free_buff_ring &= ~ET_DMA10_MASK;
2093 tmp_free_buff_ring ^= ET_DMA10_WRAP;
2095 /* For the 1023 case */
2096 tmp_free_buff_ring &= (ET_DMA10_MASK|ET_DMA10_WRAP);
2097 *free_buff_ring = tmp_free_buff_ring;
2098 return tmp_free_buff_ring;
2102 * et131x_align_allocated_memory - Align allocated memory on a given boundary
2103 * @adapter: pointer to our adapter structure
2104 * @phys_addr: pointer to Physical address
2105 * @offset: pointer to the offset variable
2106 * @mask: correct mask
2108 void et131x_align_allocated_memory(struct et131x_adapter *adapter,
2109 uint64_t *phys_addr,
2110 uint64_t *offset, uint64_t mask)
2116 new_addr = *phys_addr & ~mask;
2118 if (new_addr != *phys_addr) {
2119 /* Move to next aligned block */
2120 new_addr += mask + 1;
2121 /* Return offset for adjusting virt addr */
2122 *offset = new_addr - *phys_addr;
2123 /* Return new physical address */
2124 *phys_addr = new_addr;
2129 * et131x_rx_dma_memory_alloc
2130 * @adapter: pointer to our private adapter structure
2132 * Returns 0 on success and errno on failure (as defined in errno.h)
2134 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
2135 * and the Packet Status Ring.
2137 int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
2141 u32 pktstat_ringsize, fbr_chunksize;
2142 struct rx_ring *rx_ring;
2144 /* Setup some convenience pointers */
2145 rx_ring = &adapter->rx_ring;
2147 /* Alloc memory for the lookup table */
2149 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2151 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2153 /* The first thing we will do is configure the sizes of the buffer
2154 * rings. These will change based on jumbo packet support. Larger
2155 * jumbo packets increases the size of each entry in FBR0, and the
2156 * number of entries in FBR0, while at the same time decreasing the
2157 * number of entries in FBR1.
2159 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
2160 * entries are huge in order to accommodate a "jumbo" frame, then it
2161 * will have less entries. Conversely, FBR1 will now be relied upon
2162 * to carry more "normal" frames, thus it's entry size also increases
2163 * and the number of entries goes up too (since it now carries
2164 * "small" + "regular" packets.
2166 * In this scheme, we try to maintain 512 entries between the two
2167 * rings. Also, FBR1 remains a constant size - when it's size doubles
2168 * the number of entries halves. FBR0 increases in size, however.
2171 if (adapter->registry_jumbo_packet < 2048) {
2173 rx_ring->fbr[1]->buffsize = 256;
2174 rx_ring->fbr[1]->num_entries = 512;
2176 rx_ring->fbr[0]->buffsize = 2048;
2177 rx_ring->fbr[0]->num_entries = 512;
2178 } else if (adapter->registry_jumbo_packet < 4096) {
2180 rx_ring->fbr[1]->buffsize = 512;
2181 rx_ring->fbr[1]->num_entries = 1024;
2183 rx_ring->fbr[0]->buffsize = 4096;
2184 rx_ring->fbr[0]->num_entries = 512;
2187 rx_ring->fbr[1]->buffsize = 1024;
2188 rx_ring->fbr[1]->num_entries = 768;
2190 rx_ring->fbr[0]->buffsize = 16384;
2191 rx_ring->fbr[0]->num_entries = 128;
2195 adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[1]->num_entries +
2196 adapter->rx_ring.fbr[0]->num_entries;
2198 adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[0]->num_entries;
2201 /* Allocate an area of memory for Free Buffer Ring 1 */
2202 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) + 0xfff;
2203 rx_ring->fbr[0]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2205 &rx_ring->fbr[0]->ring_physaddr,
2207 if (!rx_ring->fbr[0]->ring_virtaddr) {
2208 dev_err(&adapter->pdev->dev,
2209 "Cannot alloc memory for Free Buffer Ring 1\n");
2213 /* Save physical address
2215 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2216 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2217 * are ever returned, make sure the high part is retrieved here
2218 * before storing the adjusted address.
2220 rx_ring->fbr[0]->real_physaddr = rx_ring->fbr[0]->ring_physaddr;
2222 /* Align Free Buffer Ring 1 on a 4K boundary */
2223 et131x_align_allocated_memory(adapter,
2224 &rx_ring->fbr[0]->real_physaddr,
2225 &rx_ring->fbr[0]->offset, 0x0FFF);
2227 rx_ring->fbr[0]->ring_virtaddr =
2228 (void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr +
2229 rx_ring->fbr[0]->offset);
2232 /* Allocate an area of memory for Free Buffer Ring 0 */
2233 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) + 0xfff;
2234 rx_ring->fbr[1]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2236 &rx_ring->fbr[1]->ring_physaddr,
2238 if (!rx_ring->fbr[1]->ring_virtaddr) {
2239 dev_err(&adapter->pdev->dev,
2240 "Cannot alloc memory for Free Buffer Ring 0\n");
2244 /* Save physical address
2246 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2247 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2248 * are ever returned, make sure the high part is retrieved here before
2249 * storing the adjusted address.
2251 rx_ring->fbr[1]->real_physaddr = rx_ring->fbr[1]->ring_physaddr;
2253 /* Align Free Buffer Ring 0 on a 4K boundary */
2254 et131x_align_allocated_memory(adapter,
2255 &rx_ring->fbr[1]->real_physaddr,
2256 &rx_ring->fbr[1]->offset, 0x0FFF);
2258 rx_ring->fbr[1]->ring_virtaddr =
2259 (void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr +
2260 rx_ring->fbr[1]->offset);
2262 for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) {
2264 u64 fbr1_tmp_physaddr;
2267 /* This code allocates an area of memory big enough for N
2268 * free buffers + (buffer_size - 1) so that the buffers can
2269 * be aligned on 4k boundaries. If each buffer were aligned
2270 * to a buffer_size boundary, the effect would be to double
2271 * the size of FBR0. By allocating N buffers at once, we
2272 * reduce this overhead.
2274 if (rx_ring->fbr[0]->buffsize > 4096)
2277 fbr1_align = rx_ring->fbr[0]->buffsize;
2280 (FBR_CHUNKS * rx_ring->fbr[0]->buffsize) + fbr1_align - 1;
2281 rx_ring->fbr[0]->mem_virtaddrs[i] =
2282 dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize,
2283 &rx_ring->fbr[0]->mem_physaddrs[i], GFP_KERNEL);
2285 if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
2286 dev_err(&adapter->pdev->dev,
2287 "Could not alloc memory\n");
2291 /* See NOTE in "Save Physical Address" comment above */
2292 fbr1_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i];
2294 et131x_align_allocated_memory(adapter,
2296 &fbr1_offset, (fbr1_align - 1));
2298 for (j = 0; j < FBR_CHUNKS; j++) {
2299 u32 index = (i * FBR_CHUNKS) + j;
2301 /* Save the Virtual address of this index for quick
2304 rx_ring->fbr[0]->virt[index] =
2305 (u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] +
2306 (j * rx_ring->fbr[0]->buffsize) + fbr1_offset;
2308 /* now store the physical address in the descriptor
2309 * so the device can access it
2311 rx_ring->fbr[0]->bus_high[index] =
2312 (u32) (fbr1_tmp_physaddr >> 32);
2313 rx_ring->fbr[0]->bus_low[index] =
2314 (u32) fbr1_tmp_physaddr;
2316 fbr1_tmp_physaddr += rx_ring->fbr[0]->buffsize;
2318 rx_ring->fbr[0]->buffer1[index] =
2319 rx_ring->fbr[0]->virt[index];
2320 rx_ring->fbr[0]->buffer2[index] =
2321 rx_ring->fbr[0]->virt[index] - 4;
2326 /* Same for FBR0 (if in use) */
2327 for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) {
2329 u64 fbr0_tmp_physaddr;
2332 ((FBR_CHUNKS + 1) * rx_ring->fbr[1]->buffsize) - 1;
2333 rx_ring->fbr[1]->mem_virtaddrs[i] =
2334 dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize,
2335 &rx_ring->fbr[1]->mem_physaddrs[i], GFP_KERNEL);
2337 if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
2338 dev_err(&adapter->pdev->dev,
2339 "Could not alloc memory\n");
2343 /* See NOTE in "Save Physical Address" comment above */
2344 fbr0_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i];
2346 et131x_align_allocated_memory(adapter,
2349 rx_ring->fbr[1]->buffsize - 1);
2351 for (j = 0; j < FBR_CHUNKS; j++) {
2352 u32 index = (i * FBR_CHUNKS) + j;
2354 rx_ring->fbr[1]->virt[index] =
2355 (u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] +
2356 (j * rx_ring->fbr[1]->buffsize) + fbr0_offset;
2358 rx_ring->fbr[1]->bus_high[index] =
2359 (u32) (fbr0_tmp_physaddr >> 32);
2360 rx_ring->fbr[1]->bus_low[index] =
2361 (u32) fbr0_tmp_physaddr;
2363 fbr0_tmp_physaddr += rx_ring->fbr[1]->buffsize;
2365 rx_ring->fbr[1]->buffer1[index] =
2366 rx_ring->fbr[1]->virt[index];
2367 rx_ring->fbr[1]->buffer2[index] =
2368 rx_ring->fbr[1]->virt[index] - 4;
2373 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2375 sizeof(struct pkt_stat_desc) * adapter->rx_ring.psr_num_entries;
2377 rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2379 &rx_ring->ps_ring_physaddr,
2382 if (!rx_ring->ps_ring_virtaddr) {
2383 dev_err(&adapter->pdev->dev,
2384 "Cannot alloc memory for Packet Status Ring\n");
2387 printk(KERN_INFO "Packet Status Ring %lx\n",
2388 (unsigned long) rx_ring->ps_ring_physaddr);
2391 * NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2392 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2393 * are ever returned, make sure the high part is retrieved here before
2394 * storing the adjusted address.
2397 /* Allocate an area of memory for writeback of status information */
2398 rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
2399 sizeof(struct rx_status_block),
2400 &rx_ring->rx_status_bus,
2402 if (!rx_ring->rx_status_block) {
2403 dev_err(&adapter->pdev->dev,
2404 "Cannot alloc memory for Status Block\n");
2407 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2408 printk(KERN_INFO "PRS %lx\n", (unsigned long)rx_ring->rx_status_bus);
2411 * kmem_cache_create initializes a lookaside list. After successful
2412 * creation, nonpaged fixed-size blocks can be allocated from and
2413 * freed to the lookaside list.
2414 * RFDs will be allocated from this pool.
2416 rx_ring->recv_lookaside = kmem_cache_create(adapter->netdev->name,
2423 adapter->flags |= fMP_ADAPTER_RECV_LOOKASIDE;
2425 /* The RFDs are going to be put on lists later on, so initialize the
2428 INIT_LIST_HEAD(&rx_ring->recv_list);
2433 * et131x_rx_dma_memory_free - Free all memory allocated within this module.
2434 * @adapter: pointer to our private adapter structure
2436 void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2440 u32 pktstat_ringsize;
2442 struct rx_ring *rx_ring;
2444 /* Setup some convenience pointers */
2445 rx_ring = &adapter->rx_ring;
2447 /* Free RFDs and associated packet descriptors */
2448 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2450 while (!list_empty(&rx_ring->recv_list)) {
2451 rfd = (struct rfd *) list_entry(rx_ring->recv_list.next,
2452 struct rfd, list_node);
2454 list_del(&rfd->list_node);
2456 kmem_cache_free(adapter->rx_ring.recv_lookaside, rfd);
2459 /* Free Free Buffer Ring 1 */
2460 if (rx_ring->fbr[0]->ring_virtaddr) {
2461 /* First the packet memory */
2462 for (index = 0; index <
2463 (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) {
2464 if (rx_ring->fbr[0]->mem_virtaddrs[index]) {
2467 if (rx_ring->fbr[0]->buffsize > 4096)
2470 fbr1_align = rx_ring->fbr[0]->buffsize;
2473 (rx_ring->fbr[0]->buffsize * FBR_CHUNKS) +
2476 dma_free_coherent(&adapter->pdev->dev,
2478 rx_ring->fbr[0]->mem_virtaddrs[index],
2479 rx_ring->fbr[0]->mem_physaddrs[index]);
2481 rx_ring->fbr[0]->mem_virtaddrs[index] = NULL;
2485 /* Now the FIFO itself */
2486 rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *)
2487 rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset);
2489 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries)
2492 dma_free_coherent(&adapter->pdev->dev, bufsize,
2493 rx_ring->fbr[0]->ring_virtaddr,
2494 rx_ring->fbr[0]->ring_physaddr);
2496 rx_ring->fbr[0]->ring_virtaddr = NULL;
2500 /* Now the same for Free Buffer Ring 0 */
2501 if (rx_ring->fbr[1]->ring_virtaddr) {
2502 /* First the packet memory */
2503 for (index = 0; index <
2504 (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) {
2505 if (rx_ring->fbr[1]->mem_virtaddrs[index]) {
2507 (rx_ring->fbr[1]->buffsize *
2508 (FBR_CHUNKS + 1)) - 1;
2510 dma_free_coherent(&adapter->pdev->dev,
2512 rx_ring->fbr[1]->mem_virtaddrs[index],
2513 rx_ring->fbr[1]->mem_physaddrs[index]);
2515 rx_ring->fbr[1]->mem_virtaddrs[index] = NULL;
2519 /* Now the FIFO itself */
2520 rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *)
2521 rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset);
2523 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries)
2526 dma_free_coherent(&adapter->pdev->dev,
2528 rx_ring->fbr[1]->ring_virtaddr,
2529 rx_ring->fbr[1]->ring_physaddr);
2531 rx_ring->fbr[1]->ring_virtaddr = NULL;
2535 /* Free Packet Status Ring */
2536 if (rx_ring->ps_ring_virtaddr) {
2538 sizeof(struct pkt_stat_desc) *
2539 adapter->rx_ring.psr_num_entries;
2541 dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
2542 rx_ring->ps_ring_virtaddr,
2543 rx_ring->ps_ring_physaddr);
2545 rx_ring->ps_ring_virtaddr = NULL;
2548 /* Free area of memory for the writeback of status information */
2549 if (rx_ring->rx_status_block) {
2550 dma_free_coherent(&adapter->pdev->dev,
2551 sizeof(struct rx_status_block),
2552 rx_ring->rx_status_block, rx_ring->rx_status_bus);
2553 rx_ring->rx_status_block = NULL;
2556 /* Destroy the lookaside (RFD) pool */
2557 if (adapter->flags & fMP_ADAPTER_RECV_LOOKASIDE) {
2558 kmem_cache_destroy(rx_ring->recv_lookaside);
2559 adapter->flags &= ~fMP_ADAPTER_RECV_LOOKASIDE;
2562 /* Free the FBR Lookup Table */
2564 kfree(rx_ring->fbr[1]);
2567 kfree(rx_ring->fbr[0]);
2569 /* Reset Counters */
2570 rx_ring->num_ready_recv = 0;
2574 * et131x_init_recv - Initialize receive data structures.
2575 * @adapter: pointer to our private adapter structure
2577 * Returns 0 on success and errno on failure (as defined in errno.h)
2579 int et131x_init_recv(struct et131x_adapter *adapter)
2581 int status = -ENOMEM;
2582 struct rfd *rfd = NULL;
2585 struct rx_ring *rx_ring;
2587 /* Setup some convenience pointers */
2588 rx_ring = &adapter->rx_ring;
2590 /* Setup each RFD */
2591 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2592 rfd = kmem_cache_alloc(rx_ring->recv_lookaside,
2593 GFP_ATOMIC | GFP_DMA);
2596 dev_err(&adapter->pdev->dev,
2597 "Couldn't alloc RFD out of kmem_cache\n");
2604 /* Add this RFD to the recv_list */
2605 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2607 /* Increment both the available RFD's, and the total RFD's. */
2608 rx_ring->num_ready_recv++;
2612 if (numrfd > NIC_MIN_NUM_RFD)
2615 rx_ring->num_rfd = numrfd;
2618 kmem_cache_free(rx_ring->recv_lookaside, rfd);
2619 dev_err(&adapter->pdev->dev,
2620 "Allocation problems in et131x_init_recv\n");
2626 * et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate.
2627 * @adapter: pointer to our adapter structure
2629 void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2631 struct phy_device *phydev = adapter->phydev;
2636 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2637 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2639 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2640 writel(0, &adapter->regs->rxdma.max_pkt_time);
2641 writel(1, &adapter->regs->rxdma.num_pkt_done);
2646 * NICReturnRFD - Recycle a RFD and put it back onto the receive list
2647 * @adapter: pointer to our adapter
2648 * @rfd: pointer to the RFD
2650 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2652 struct rx_ring *rx_local = &adapter->rx_ring;
2653 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2654 u16 buff_index = rfd->bufferindex;
2655 u8 ring_index = rfd->ringindex;
2656 unsigned long flags;
2658 /* We don't use any of the OOB data besides status. Otherwise, we
2659 * need to clean up OOB data
2663 (ring_index == 0 && buff_index < rx_local->fbr[1]->num_entries) ||
2665 (ring_index == 1 && buff_index < rx_local->fbr[0]->num_entries)) {
2666 spin_lock_irqsave(&adapter->fbr_lock, flags);
2668 if (ring_index == 1) {
2669 struct fbr_desc *next =
2670 (struct fbr_desc *) (rx_local->fbr[0]->ring_virtaddr) +
2671 INDEX10(rx_local->fbr[0]->local_full);
2673 /* Handle the Free Buffer Ring advancement here. Write
2674 * the PA / Buffer Index for the returned buffer into
2675 * the oldest (next to be freed)FBR entry
2677 next->addr_hi = rx_local->fbr[0]->bus_high[buff_index];
2678 next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
2679 next->word2 = buff_index;
2681 writel(bump_free_buff_ring(&rx_local->fbr[0]->local_full,
2682 rx_local->fbr[0]->num_entries - 1),
2683 &rx_dma->fbr1_full_offset);
2687 struct fbr_desc *next = (struct fbr_desc *)
2688 rx_local->fbr[1]->ring_virtaddr +
2689 INDEX10(rx_local->fbr[1]->local_full);
2691 /* Handle the Free Buffer Ring advancement here. Write
2692 * the PA / Buffer Index for the returned buffer into
2693 * the oldest (next to be freed) FBR entry
2695 next->addr_hi = rx_local->fbr[1]->bus_high[buff_index];
2696 next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
2697 next->word2 = buff_index;
2699 writel(bump_free_buff_ring(
2700 &rx_local->fbr[1]->local_full,
2701 rx_local->fbr[1]->num_entries - 1),
2702 &rx_dma->fbr0_full_offset);
2705 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2707 dev_err(&adapter->pdev->dev,
2708 "%s illegal Buffer Index returned\n", __func__);
2711 /* The processing on this RFD is done, so put it back on the tail of
2714 spin_lock_irqsave(&adapter->rcv_lock, flags);
2715 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2716 rx_local->num_ready_recv++;
2717 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2719 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2723 * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
2724 * @adapter: pointer to our adapter structure
2726 void et131x_rx_dma_disable(struct et131x_adapter *adapter)
2729 /* Setup the receive dma configuration register */
2730 writel(0x00002001, &adapter->regs->rxdma.csr);
2731 csr = readl(&adapter->regs->rxdma.csr);
2732 if ((csr & 0x00020000) == 0) { /* Check halt status (bit 17) */
2734 csr = readl(&adapter->regs->rxdma.csr);
2735 if ((csr & 0x00020000) == 0)
2736 dev_err(&adapter->pdev->dev,
2737 "RX Dma failed to enter halt state. CSR 0x%08x\n",
2743 * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
2744 * @adapter: pointer to our adapter structure
2746 void et131x_rx_dma_enable(struct et131x_adapter *adapter)
2748 /* Setup the receive dma configuration register for normal operation */
2749 u32 csr = 0x2000; /* FBR1 enable */
2751 if (adapter->rx_ring.fbr[0]->buffsize == 4096)
2753 else if (adapter->rx_ring.fbr[0]->buffsize == 8192)
2755 else if (adapter->rx_ring.fbr[0]->buffsize == 16384)
2758 csr |= 0x0400; /* FBR0 enable */
2759 if (adapter->rx_ring.fbr[1]->buffsize == 256)
2761 else if (adapter->rx_ring.fbr[1]->buffsize == 512)
2763 else if (adapter->rx_ring.fbr[1]->buffsize == 1024)
2766 writel(csr, &adapter->regs->rxdma.csr);
2768 csr = readl(&adapter->regs->rxdma.csr);
2769 if ((csr & 0x00020000) != 0) {
2771 csr = readl(&adapter->regs->rxdma.csr);
2772 if ((csr & 0x00020000) != 0) {
2773 dev_err(&adapter->pdev->dev,
2774 "RX Dma failed to exit halt state. CSR 0x%08x\n",
2781 static inline void add_10bit(u32 *v, int n)
2783 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
2786 static inline void add_12bit(u32 *v, int n)
2788 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
2792 * nic_rx_pkts - Checks the hardware for available packets
2793 * @adapter: pointer to our adapter
2795 * Returns rfd, a pointer to our MPRFD.
2797 * Checks the hardware for available packets, using completion ring
2798 * If packets are available, it gets an RFD from the recv_list, attaches
2799 * the packet to it, puts the RFD in the RecvPendList, and also returns
2800 * the pointer to the RFD.
2802 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2804 struct rx_ring *rx_local = &adapter->rx_ring;
2805 struct rx_status_block *status;
2806 struct pkt_stat_desc *psr;
2810 unsigned long flags;
2811 struct list_head *element;
2818 /* RX Status block is written by the DMA engine prior to every
2819 * interrupt. It contains the next to be used entry in the Packet
2820 * Status Ring, and also the two Free Buffer rings.
2822 status = rx_local->rx_status_block;
2823 word1 = status->word1 >> 16; /* Get the useful bits */
2825 /* Check the PSR and wrap bits do not match */
2826 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2827 /* Looks like this ring is not updated yet */
2830 /* The packet status ring indicates that data is available. */
2831 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2832 (rx_local->local_psr_full & 0xFFF);
2834 /* Grab any information that is required once the PSR is
2835 * advanced, since we can no longer rely on the memory being
2838 len = psr->word1 & 0xFFFF;
2839 ring_index = (psr->word1 >> 26) & 0x03;
2840 buff_index = (psr->word1 >> 16) & 0x3FF;
2843 /* Indicate that we have used this PSR entry. */
2845 add_12bit(&rx_local->local_psr_full, 1);
2847 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2848 /* Clear psr full and toggle the wrap bit */
2849 rx_local->local_psr_full &= ~0xFFF;
2850 rx_local->local_psr_full ^= 0x1000;
2853 writel(rx_local->local_psr_full,
2854 &adapter->regs->rxdma.psr_full_offset);
2857 if (ring_index != 1)
2862 if (ring_index > 1 ||
2864 buff_index > rx_local->fbr[1]->num_entries - 1) ||
2866 buff_index > rx_local->fbr[0]->num_entries - 1))
2868 if (ring_index != 1 || buff_index > rx_local->fbr[0]->num_entries - 1)
2871 /* Illegal buffer or ring index cannot be used by S/W*/
2872 dev_err(&adapter->pdev->dev,
2873 "NICRxPkts PSR Entry %d indicates "
2874 "length of %d and/or bad bi(%d)\n",
2875 rx_local->local_psr_full & 0xFFF,
2880 /* Get and fill the RFD. */
2881 spin_lock_irqsave(&adapter->rcv_lock, flags);
2884 element = rx_local->recv_list.next;
2885 rfd = (struct rfd *) list_entry(element, struct rfd, list_node);
2888 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2892 list_del(&rfd->list_node);
2893 rx_local->num_ready_recv--;
2895 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2897 rfd->bufferindex = buff_index;
2898 rfd->ringindex = ring_index;
2900 /* In V1 silicon, there is a bug which screws up filtering of
2901 * runt packets. Therefore runt packet filtering is disabled
2902 * in the MAC and the packets are dropped here. They are
2903 * also counted here.
2905 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2906 adapter->stats.rx_other_errs++;
2911 /* Determine if this is a multicast packet coming in */
2912 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2913 !(word0 & ALCATEL_BROADCAST_PKT)) {
2914 /* Promiscuous mode and Multicast mode are
2915 * not mutually exclusive as was first
2916 * thought. I guess Promiscuous is just
2917 * considered a super-set of the other
2918 * filters. Generally filter is 0x2b when in
2921 if ((adapter->packet_filter &
2922 ET131X_PACKET_TYPE_MULTICAST)
2923 && !(adapter->packet_filter &
2924 ET131X_PACKET_TYPE_PROMISCUOUS)
2925 && !(adapter->packet_filter &
2926 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2928 * Note - ring_index for fbr[] array is reversed
2931 buf = rx_local->fbr[(ring_index == 0 ? 1 : 0)]->
2934 /* Loop through our list to see if the
2935 * destination address of this packet
2936 * matches one in our list.
2938 for (i = 0; i < adapter->multicast_addr_count;
2941 adapter->multicast_list[i][0]
2943 adapter->multicast_list[i][1]
2945 adapter->multicast_list[i][2]
2947 adapter->multicast_list[i][3]
2949 adapter->multicast_list[i][4]
2951 adapter->multicast_list[i][5]) {
2956 /* If our index is equal to the number
2957 * of Multicast address we have, then
2958 * this means we did not find this
2959 * packet's matching address in our
2960 * list. Set the len to zero,
2961 * so we free our RFD when we return
2962 * from this function.
2964 if (i == adapter->multicast_addr_count)
2969 adapter->stats.multicast_pkts_rcvd++;
2970 } else if (word0 & ALCATEL_BROADCAST_PKT)
2971 adapter->stats.broadcast_pkts_rcvd++;
2973 /* Not sure what this counter measures in
2974 * promiscuous mode. Perhaps we should check
2975 * the MAC address to see if it is directed
2976 * to us in promiscuous mode.
2978 adapter->stats.unicast_pkts_rcvd++;
2982 struct sk_buff *skb = NULL;
2984 /*rfd->len = len - 4; */
2987 skb = dev_alloc_skb(rfd->len + 2);
2989 dev_err(&adapter->pdev->dev,
2990 "Couldn't alloc an SKB for Rx\n");
2994 adapter->net_stats.rx_bytes += rfd->len;
2997 * Note - ring_index for fbr[] array is reversed,
3000 memcpy(skb_put(skb, rfd->len),
3001 rx_local->fbr[(ring_index == 0 ? 1 : 0)]->virt[buff_index],
3004 skb->dev = adapter->netdev;
3005 skb->protocol = eth_type_trans(skb, adapter->netdev);
3006 skb->ip_summed = CHECKSUM_NONE;
3013 nic_return_rfd(adapter, rfd);
3018 * et131x_handle_recv_interrupt - Interrupt handler for receive processing
3019 * @adapter: pointer to our adapter
3021 * Assumption, Rcv spinlock has been acquired.
3023 void et131x_handle_recv_interrupt(struct et131x_adapter *adapter)
3025 struct rfd *rfd = NULL;
3029 /* Process up to available RFD's */
3030 while (count < NUM_PACKETS_HANDLED) {
3031 if (list_empty(&adapter->rx_ring.recv_list)) {
3032 WARN_ON(adapter->rx_ring.num_ready_recv != 0);
3037 rfd = nic_rx_pkts(adapter);
3042 /* Do not receive any packets until a filter has been set.
3043 * Do not receive any packets until we have link.
3044 * If length is zero, return the RFD in order to advance the
3047 if (!adapter->packet_filter ||
3048 !netif_carrier_ok(adapter->netdev) ||
3052 /* Increment the number of packets we received */
3053 adapter->net_stats.rx_packets++;
3055 /* Set the status on the packet, either resources or success */
3056 if (adapter->rx_ring.num_ready_recv < RFD_LOW_WATER_MARK) {
3057 dev_warn(&adapter->pdev->dev,
3058 "RFD's are running out\n");
3063 if (count == NUM_PACKETS_HANDLED || !done) {
3064 adapter->rx_ring.unfinished_receives = true;
3065 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
3066 &adapter->regs->global.watchdog_timer);
3068 /* Watchdog timer will disable itself if appropriate. */
3069 adapter->rx_ring.unfinished_receives = false;
3075 * et131x_tx_dma_memory_alloc
3076 * @adapter: pointer to our private adapter structure
3078 * Returns 0 on success and errno on failure (as defined in errno.h).
3080 * Allocates memory that will be visible both to the device and to the CPU.
3081 * The OS will pass us packets, pointers to which we will insert in the Tx
3082 * Descriptor queue. The device will read this queue to find the packets in
3083 * memory. The device will update the "status" in memory each time it xmits a
3086 int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
3089 struct tx_ring *tx_ring = &adapter->tx_ring;
3091 /* Allocate memory for the TCB's (Transmit Control Block) */
3092 adapter->tx_ring.tcb_ring =
3093 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
3094 if (!adapter->tx_ring.tcb_ring) {
3095 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
3099 /* Allocate enough memory for the Tx descriptor ring, and allocate
3100 * some extra so that the ring can be aligned on a 4k boundary.
3102 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
3103 tx_ring->tx_desc_ring =
3104 (struct tx_desc *) dma_alloc_coherent(&adapter->pdev->dev, desc_size,
3105 &tx_ring->tx_desc_ring_pa, GFP_KERNEL);
3106 if (!adapter->tx_ring.tx_desc_ring) {
3107 dev_err(&adapter->pdev->dev,
3108 "Cannot alloc memory for Tx Ring\n");
3112 /* Save physical address
3114 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
3115 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
3116 * are ever returned, make sure the high part is retrieved here before
3117 * storing the adjusted address.
3119 /* Allocate memory for the Tx status block */
3120 tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
3122 &tx_ring->tx_status_pa,
3124 if (!adapter->tx_ring.tx_status_pa) {
3125 dev_err(&adapter->pdev->dev,
3126 "Cannot alloc memory for Tx status block\n");
3133 * et131x_tx_dma_memory_free - Free all memory allocated within this module
3134 * @adapter: pointer to our private adapter structure
3136 * Returns 0 on success and errno on failure (as defined in errno.h).
3138 void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
3142 if (adapter->tx_ring.tx_desc_ring) {
3143 /* Free memory relating to Tx rings here */
3144 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
3146 dma_free_coherent(&adapter->pdev->dev,
3148 adapter->tx_ring.tx_desc_ring,
3149 adapter->tx_ring.tx_desc_ring_pa);
3150 adapter->tx_ring.tx_desc_ring = NULL;
3153 /* Free memory for the Tx status block */
3154 if (adapter->tx_ring.tx_status) {
3155 dma_free_coherent(&adapter->pdev->dev,
3157 adapter->tx_ring.tx_status,
3158 adapter->tx_ring.tx_status_pa);
3160 adapter->tx_ring.tx_status = NULL;
3162 /* Free the memory for the tcb structures */
3163 kfree(adapter->tx_ring.tcb_ring);
3167 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
3168 * @adapter: pointer to our adapter structure
3170 void et131x_tx_dma_disable(struct et131x_adapter *adapter)
3172 /* Setup the tramsmit dma configuration register */
3173 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
3174 &adapter->regs->txdma.csr);
3178 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
3179 * @adapter: pointer to our adapter structure
3181 * Mainly used after a return to the D0 (full-power) state from a lower state.
3183 void et131x_tx_dma_enable(struct et131x_adapter *adapter)
3185 /* Setup the transmit dma configuration register for normal
3188 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
3189 &adapter->regs->txdma.csr);
3193 * et131x_init_send - Initialize send data structures
3194 * @adapter: pointer to our private adapter structure
3196 void et131x_init_send(struct et131x_adapter *adapter)
3200 struct tx_ring *tx_ring;
3202 /* Setup some convenience pointers */
3203 tx_ring = &adapter->tx_ring;
3204 tcb = adapter->tx_ring.tcb_ring;
3206 tx_ring->tcb_qhead = tcb;
3208 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
3210 /* Go through and set up each TCB */
3211 for (ct = 0; ct++ < NUM_TCB; tcb++)
3212 /* Set the link pointer in HW TCB to the next TCB in the
3215 tcb->next = tcb + 1;
3217 /* Set the tail pointer */
3219 tx_ring->tcb_qtail = tcb;
3221 /* Curr send queue should now be empty */
3222 tx_ring->send_head = NULL;
3223 tx_ring->send_tail = NULL;
3227 * nic_send_packet - NIC specific send handler for version B silicon.
3228 * @adapter: pointer to our adapter
3229 * @tcb: pointer to struct tcb
3231 * Returns 0 or errno.
3233 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
3236 struct tx_desc desc[24]; /* 24 x 16 byte */
3238 u32 thiscopy, remainder;
3239 struct sk_buff *skb = tcb->skb;
3240 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
3241 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
3242 unsigned long flags;
3243 struct phy_device *phydev = adapter->phydev;
3245 /* Part of the optimizations of this send routine restrict us to
3246 * sending 24 fragments at a pass. In practice we should never see
3247 * more than 5 fragments.
3249 * NOTE: The older version of this function (below) can handle any
3250 * number of fragments. If needed, we can call this function,
3251 * although it is less efficient.
3256 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
3258 for (i = 0; i < nr_frags; i++) {
3259 /* If there is something in this element, lets get a
3260 * descriptor from the ring and get the necessary data
3263 /* If the fragments are smaller than a standard MTU,
3264 * then map them to a single descriptor in the Tx
3265 * Desc ring. However, if they're larger, as is
3266 * possible with support for jumbo packets, then
3267 * split them each across 2 descriptors.
3269 * This will work until we determine why the hardware
3270 * doesn't seem to like large fragments.
3272 if ((skb->len - skb->data_len) <= 1514) {
3273 desc[frag].addr_hi = 0;
3274 /* Low 16bits are length, high is vlan and
3275 unused currently so zero */
3276 desc[frag].len_vlan =
3277 skb->len - skb->data_len;
3279 /* NOTE: Here, the dma_addr_t returned from
3280 * dma_map_single() is implicitly cast as a
3281 * u32. Although dma_addr_t can be
3282 * 64-bit, the address returned by
3283 * dma_map_single() is always 32-bit
3284 * addressable (as defined by the pci/dma
3287 desc[frag++].addr_lo =
3288 dma_map_single(&adapter->pdev->dev,
3294 desc[frag].addr_hi = 0;
3295 desc[frag].len_vlan =
3296 (skb->len - skb->data_len) / 2;
3298 /* NOTE: Here, the dma_addr_t returned from
3299 * dma_map_single() is implicitly cast as a
3300 * u32. Although dma_addr_t can be
3301 * 64-bit, the address returned by
3302 * dma_map_single() is always 32-bit
3303 * addressable (as defined by the pci/dma
3306 desc[frag++].addr_lo =
3307 dma_map_single(&adapter->pdev->dev,
3310 skb->data_len) / 2),
3312 desc[frag].addr_hi = 0;
3314 desc[frag].len_vlan =
3315 (skb->len - skb->data_len) / 2;
3317 /* NOTE: Here, the dma_addr_t returned from
3318 * dma_map_single() is implicitly cast as a
3319 * u32. Although dma_addr_t can be
3320 * 64-bit, the address returned by
3321 * dma_map_single() is always 32-bit
3322 * addressable (as defined by the pci/dma
3325 desc[frag++].addr_lo =
3326 dma_map_single(&adapter->pdev->dev,
3329 skb->data_len) / 2),
3331 skb->data_len) / 2),
3335 desc[frag].addr_hi = 0;
3336 desc[frag].len_vlan =
3339 /* NOTE: Here, the dma_addr_t returned from
3340 * dma_map_page() is implicitly cast as a u32.
3341 * Although dma_addr_t can be 64-bit, the address
3342 * returned by dma_map_page() is always 32-bit
3343 * addressable (as defined by the pci/dma subsystem)
3345 desc[frag++].addr_lo =
3346 dma_map_page(&adapter->pdev->dev,
3348 frags[i - 1].page_offset,
3357 if (phydev && phydev->speed == SPEED_1000) {
3358 if (++adapter->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
3359 /* Last element & Interrupt flag */
3360 desc[frag - 1].flags = 0x5;
3361 adapter->tx_ring.since_irq = 0;
3362 } else { /* Last element */
3363 desc[frag - 1].flags = 0x1;
3366 desc[frag - 1].flags = 0x5;
3368 desc[0].flags |= 2; /* First element flag */
3370 tcb->index_start = adapter->tx_ring.send_idx;
3373 spin_lock_irqsave(&adapter->send_hw_lock, flags);
3375 thiscopy = NUM_DESC_PER_RING_TX -
3376 INDEX10(adapter->tx_ring.send_idx);
3378 if (thiscopy >= frag) {
3382 remainder = frag - thiscopy;
3385 memcpy(adapter->tx_ring.tx_desc_ring +
3386 INDEX10(adapter->tx_ring.send_idx), desc,
3387 sizeof(struct tx_desc) * thiscopy);
3389 add_10bit(&adapter->tx_ring.send_idx, thiscopy);
3391 if (INDEX10(adapter->tx_ring.send_idx) == 0 ||
3392 INDEX10(adapter->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
3393 adapter->tx_ring.send_idx &= ~ET_DMA10_MASK;
3394 adapter->tx_ring.send_idx ^= ET_DMA10_WRAP;
3398 memcpy(adapter->tx_ring.tx_desc_ring,
3400 sizeof(struct tx_desc) * remainder);
3402 add_10bit(&adapter->tx_ring.send_idx, remainder);
3405 if (INDEX10(adapter->tx_ring.send_idx) == 0) {
3406 if (adapter->tx_ring.send_idx)
3407 tcb->index = NUM_DESC_PER_RING_TX - 1;
3409 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
3411 tcb->index = adapter->tx_ring.send_idx - 1;
3413 spin_lock(&adapter->tcb_send_qlock);
3415 if (adapter->tx_ring.send_tail)
3416 adapter->tx_ring.send_tail->next = tcb;
3418 adapter->tx_ring.send_head = tcb;
3420 adapter->tx_ring.send_tail = tcb;
3422 WARN_ON(tcb->next != NULL);
3424 adapter->tx_ring.used++;
3426 spin_unlock(&adapter->tcb_send_qlock);
3428 /* Write the new write pointer back to the device. */
3429 writel(adapter->tx_ring.send_idx,
3430 &adapter->regs->txdma.service_request);
3432 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
3433 * timer to wake us up if this packet isn't followed by N more.
3435 if (phydev && phydev->speed == SPEED_1000) {
3436 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
3437 &adapter->regs->global.watchdog_timer);
3439 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
3445 * send_packet - Do the work to send a packet
3446 * @skb: the packet(s) to send
3447 * @adapter: a pointer to the device's private adapter structure
3449 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
3451 * Assumption: Send spinlock has been acquired
3453 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
3456 struct tcb *tcb = NULL;
3458 unsigned long flags;
3460 /* All packets must have at least a MAC address and a protocol type */
3461 if (skb->len < ETH_HLEN)
3464 /* Get a TCB for this packet */
3465 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3467 tcb = adapter->tx_ring.tcb_qhead;
3470 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3474 adapter->tx_ring.tcb_qhead = tcb->next;
3476 if (adapter->tx_ring.tcb_qhead == NULL)
3477 adapter->tx_ring.tcb_qtail = NULL;
3479 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3483 if (skb->data != NULL && skb->len - skb->data_len >= 6) {
3484 shbufva = (u16 *) skb->data;
3486 if ((shbufva[0] == 0xffff) &&
3487 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
3488 tcb->flags |= fMP_DEST_BROAD;
3489 } else if ((shbufva[0] & 0x3) == 0x0001) {
3490 tcb->flags |= fMP_DEST_MULTI;
3496 /* Call the NIC specific send handler. */
3497 status = nic_send_packet(adapter, tcb);
3500 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3502 if (adapter->tx_ring.tcb_qtail)
3503 adapter->tx_ring.tcb_qtail->next = tcb;
3505 /* Apparently ready Q is empty. */
3506 adapter->tx_ring.tcb_qhead = tcb;
3508 adapter->tx_ring.tcb_qtail = tcb;
3509 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3512 WARN_ON(adapter->tx_ring.used > NUM_TCB);
3517 * et131x_send_packets - This function is called by the OS to send packets
3518 * @skb: the packet(s) to send
3519 * @netdev:device on which to TX the above packet(s)
3521 * Return 0 in almost all cases; non-zero value in extreme hard failure only
3523 int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
3526 struct et131x_adapter *adapter = netdev_priv(netdev);
3528 /* Send these packets
3530 * NOTE: The Linux Tx entry point is only given one packet at a time
3531 * to Tx, so the PacketCount and it's array used makes no sense here
3534 /* TCB is not available */
3535 if (adapter->tx_ring.used >= NUM_TCB) {
3536 /* NOTE: If there's an error on send, no need to queue the
3537 * packet under Linux; if we just send an error up to the
3538 * netif layer, it will resend the skb to us.
3542 /* We need to see if the link is up; if it's not, make the
3543 * netif layer think we're good and drop the packet
3545 if ((adapter->flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
3546 !netif_carrier_ok(netdev)) {
3547 dev_kfree_skb_any(skb);
3550 adapter->net_stats.tx_dropped++;
3552 status = send_packet(skb, adapter);
3553 if (status != 0 && status != -ENOMEM) {
3554 /* On any other error, make netif think we're
3555 * OK and drop the packet
3557 dev_kfree_skb_any(skb);
3559 adapter->net_stats.tx_dropped++;
3567 * free_send_packet - Recycle a struct tcb
3568 * @adapter: pointer to our adapter
3569 * @tcb: pointer to struct tcb
3571 * Complete the packet if necessary
3572 * Assumption - Send spinlock has been acquired
3574 static inline void free_send_packet(struct et131x_adapter *adapter,
3577 unsigned long flags;
3578 struct tx_desc *desc = NULL;
3579 struct net_device_stats *stats = &adapter->net_stats;
3581 if (tcb->flags & fMP_DEST_BROAD)
3582 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
3583 else if (tcb->flags & fMP_DEST_MULTI)
3584 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
3586 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
3589 stats->tx_bytes += tcb->skb->len;
3591 /* Iterate through the TX descriptors on the ring
3592 * corresponding to this packet and umap the fragments
3596 desc = (struct tx_desc *)
3597 (adapter->tx_ring.tx_desc_ring +
3598 INDEX10(tcb->index_start));
3600 dma_unmap_single(&adapter->pdev->dev,
3602 desc->len_vlan, DMA_TO_DEVICE);
3604 add_10bit(&tcb->index_start, 1);
3605 if (INDEX10(tcb->index_start) >=
3606 NUM_DESC_PER_RING_TX) {
3607 tcb->index_start &= ~ET_DMA10_MASK;
3608 tcb->index_start ^= ET_DMA10_WRAP;
3610 } while (desc != (adapter->tx_ring.tx_desc_ring +
3611 INDEX10(tcb->index)));
3613 dev_kfree_skb_any(tcb->skb);
3616 memset(tcb, 0, sizeof(struct tcb));
3618 /* Add the TCB to the Ready Q */
3619 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3621 adapter->net_stats.tx_packets++;
3623 if (adapter->tx_ring.tcb_qtail)
3624 adapter->tx_ring.tcb_qtail->next = tcb;
3626 /* Apparently ready Q is empty. */
3627 adapter->tx_ring.tcb_qhead = tcb;
3629 adapter->tx_ring.tcb_qtail = tcb;
3631 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3632 WARN_ON(adapter->tx_ring.used < 0);
3636 * et131x_free_busy_send_packets - Free and complete the stopped active sends
3637 * @adapter: pointer to our adapter
3639 * Assumption - Send spinlock has been acquired
3641 void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3644 unsigned long flags;
3647 /* Any packets being sent? Check the first TCB on the send list */
3648 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3650 tcb = adapter->tx_ring.send_head;
3652 while (tcb != NULL && freed < NUM_TCB) {
3653 struct tcb *next = tcb->next;
3655 adapter->tx_ring.send_head = next;
3658 adapter->tx_ring.send_tail = NULL;
3660 adapter->tx_ring.used--;
3662 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3665 free_send_packet(adapter, tcb);
3667 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3669 tcb = adapter->tx_ring.send_head;
3672 WARN_ON(freed == NUM_TCB);
3674 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3676 adapter->tx_ring.used = 0;
3680 * et131x_handle_send_interrupt - Interrupt handler for sending processing
3681 * @adapter: pointer to our adapter
3683 * Re-claim the send resources, complete sends and get more to send from
3684 * the send wait queue.
3686 * Assumption - Send spinlock has been acquired
3688 void et131x_handle_send_interrupt(struct et131x_adapter *adapter)
3690 unsigned long flags;
3695 serviced = readl(&adapter->regs->txdma.new_service_complete);
3696 index = INDEX10(serviced);
3698 /* Has the ring wrapped? Process any descriptors that do not have
3699 * the same "wrap" indicator as the current completion indicator
3701 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3703 tcb = adapter->tx_ring.send_head;
3706 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3707 index < INDEX10(tcb->index)) {
3708 adapter->tx_ring.used--;
3709 adapter->tx_ring.send_head = tcb->next;
3710 if (tcb->next == NULL)
3711 adapter->tx_ring.send_tail = NULL;
3713 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3714 free_send_packet(adapter, tcb);
3715 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3717 /* Goto the next packet */
3718 tcb = adapter->tx_ring.send_head;
3721 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3722 && index > (tcb->index & ET_DMA10_MASK)) {
3723 adapter->tx_ring.used--;
3724 adapter->tx_ring.send_head = tcb->next;
3725 if (tcb->next == NULL)
3726 adapter->tx_ring.send_tail = NULL;
3728 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3729 free_send_packet(adapter, tcb);
3730 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3732 /* Goto the next packet */
3733 tcb = adapter->tx_ring.send_head;
3736 /* Wake up the queue when we hit a low-water mark */
3737 if (adapter->tx_ring.used <= NUM_TCB / 3)
3738 netif_wake_queue(adapter->netdev);
3740 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3743 /* ETHTOOL functions */
3745 static int et131x_get_settings(struct net_device *netdev,
3746 struct ethtool_cmd *cmd)
3748 struct et131x_adapter *adapter = netdev_priv(netdev);
3750 return phy_ethtool_gset(adapter->phydev, cmd);
3753 static int et131x_set_settings(struct net_device *netdev,
3754 struct ethtool_cmd *cmd)
3756 struct et131x_adapter *adapter = netdev_priv(netdev);
3758 return phy_ethtool_sset(adapter->phydev, cmd);
3761 static int et131x_get_regs_len(struct net_device *netdev)
3763 #define ET131X_REGS_LEN 256
3764 return ET131X_REGS_LEN * sizeof(u32);
3767 static void et131x_get_regs(struct net_device *netdev,
3768 struct ethtool_regs *regs, void *regs_data)
3770 struct et131x_adapter *adapter = netdev_priv(netdev);
3771 struct address_map __iomem *aregs = adapter->regs;
3772 u32 *regs_buff = regs_data;
3775 memset(regs_data, 0, et131x_get_regs_len(netdev));
3777 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3778 adapter->pdev->device;
3781 et131x_mii_read(adapter, MII_BMCR, (u16 *)®s_buff[num++]);
3782 et131x_mii_read(adapter, MII_BMSR, (u16 *)®s_buff[num++]);
3783 et131x_mii_read(adapter, MII_PHYSID1, (u16 *)®s_buff[num++]);
3784 et131x_mii_read(adapter, MII_PHYSID2, (u16 *)®s_buff[num++]);
3785 et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)®s_buff[num++]);
3786 et131x_mii_read(adapter, MII_LPA, (u16 *)®s_buff[num++]);
3787 et131x_mii_read(adapter, MII_EXPANSION, (u16 *)®s_buff[num++]);
3788 /* Autoneg next page transmit reg */
3789 et131x_mii_read(adapter, 0x07, (u16 *)®s_buff[num++]);
3790 /* Link partner next page reg */
3791 et131x_mii_read(adapter, 0x08, (u16 *)®s_buff[num++]);
3792 et131x_mii_read(adapter, MII_CTRL1000, (u16 *)®s_buff[num++]);
3793 et131x_mii_read(adapter, MII_STAT1000, (u16 *)®s_buff[num++]);
3794 et131x_mii_read(adapter, MII_ESTATUS, (u16 *)®s_buff[num++]);
3795 et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)®s_buff[num++]);
3796 et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)®s_buff[num++]);
3797 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3798 (u16 *)®s_buff[num++]);
3799 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL,
3800 (u16 *)®s_buff[num++]);
3801 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1,
3802 (u16 *)®s_buff[num++]);
3803 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL,
3804 (u16 *)®s_buff[num++]);
3805 et131x_mii_read(adapter, PHY_CONFIG, (u16 *)®s_buff[num++]);
3806 et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)®s_buff[num++]);
3807 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)®s_buff[num++]);
3808 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS,
3809 (u16 *)®s_buff[num++]);
3810 et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)®s_buff[num++]);
3811 et131x_mii_read(adapter, PHY_LED_1, (u16 *)®s_buff[num++]);
3812 et131x_mii_read(adapter, PHY_LED_2, (u16 *)®s_buff[num++]);
3815 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3816 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3817 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3818 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3819 regs_buff[num++] = readl(&aregs->global.pm_csr);
3820 regs_buff[num++] = adapter->stats.interrupt_status;
3821 regs_buff[num++] = readl(&aregs->global.int_mask);
3822 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3823 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3824 regs_buff[num++] = readl(&aregs->global.sw_reset);
3825 regs_buff[num++] = readl(&aregs->global.slv_timer);
3826 regs_buff[num++] = readl(&aregs->global.msi_config);
3827 regs_buff[num++] = readl(&aregs->global.loopback);
3828 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3831 regs_buff[num++] = readl(&aregs->txdma.csr);
3832 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3833 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3834 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3835 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3836 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3837 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3838 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3839 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3840 regs_buff[num++] = readl(&aregs->txdma.service_request);
3841 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3842 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3843 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3844 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3845 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3846 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3847 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3848 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3849 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3850 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3851 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3852 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3853 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3854 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3855 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3856 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3859 regs_buff[num++] = readl(&aregs->rxdma.csr);
3860 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3861 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3862 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3863 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3864 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3865 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3866 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3867 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3868 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3869 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3870 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3871 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3872 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3873 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3874 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3875 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3876 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3877 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3878 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3879 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3880 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3881 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3882 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3883 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3884 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3885 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3886 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3887 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3890 #define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */
3891 static void et131x_get_drvinfo(struct net_device *netdev,
3892 struct ethtool_drvinfo *info)
3894 struct et131x_adapter *adapter = netdev_priv(netdev);
3896 strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN);
3897 strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN);
3898 strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN);
3901 static struct ethtool_ops et131x_ethtool_ops = {
3902 .get_settings = et131x_get_settings,
3903 .set_settings = et131x_set_settings,
3904 .get_drvinfo = et131x_get_drvinfo,
3905 .get_regs_len = et131x_get_regs_len,
3906 .get_regs = et131x_get_regs,
3907 .get_link = ethtool_op_get_link,
3910 void et131x_set_ethtool_ops(struct net_device *netdev)
3912 SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops);
3918 * et131x_hwaddr_init - set up the MAC Address on the ET1310
3919 * @adapter: pointer to our private adapter structure
3921 void et131x_hwaddr_init(struct et131x_adapter *adapter)
3923 /* If have our default mac from init and no mac address from
3924 * EEPROM then we need to generate the last octet and set it on the
3927 if (adapter->rom_addr[0] == 0x00 &&
3928 adapter->rom_addr[1] == 0x00 &&
3929 adapter->rom_addr[2] == 0x00 &&
3930 adapter->rom_addr[3] == 0x00 &&
3931 adapter->rom_addr[4] == 0x00 &&
3932 adapter->rom_addr[5] == 0x00) {
3934 * We need to randomly generate the last octet so we
3935 * decrease our chances of setting the mac address to
3936 * same as another one of our cards in the system
3938 get_random_bytes(&adapter->addr[5], 1);
3940 * We have the default value in the register we are
3941 * working with so we need to copy the current
3942 * address into the permanent address
3944 memcpy(adapter->rom_addr,
3945 adapter->addr, ETH_ALEN);
3947 /* We do not have an override address, so set the
3948 * current address to the permanent address and add
3951 memcpy(adapter->addr,
3952 adapter->rom_addr, ETH_ALEN);
3957 * et131x_pci_init - initial PCI setup
3958 * @adapter: pointer to our private adapter structure
3959 * @pdev: our PCI device
3961 * Perform the initial setup of PCI registers and if possible initialise
3962 * the MAC address. At this point the I/O registers have yet to be mapped
3964 static int et131x_pci_init(struct et131x_adapter *adapter,
3965 struct pci_dev *pdev)
3971 if (et131x_init_eeprom(adapter) < 0)
3974 /* Let's set up the PORT LOGIC Register. First we need to know what
3975 * the max_payload_size is
3977 if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) {
3979 "Could not read PCI config space for Max Payload Size\n");
3983 /* Program the Ack/Nak latency and replay timers */
3984 max_payload &= 0x07; /* Only the lower 3 bits are valid */
3986 if (max_payload < 2) {
3987 static const u16 acknak[2] = { 0x76, 0xD0 };
3988 static const u16 replay[2] = { 0x1E0, 0x2ED };
3990 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3991 acknak[max_payload])) {
3993 "Could not write PCI config space for ACK/NAK\n");
3996 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3997 replay[max_payload])) {
3999 "Could not write PCI config space for Replay Timer\n");
4004 /* l0s and l1 latency timers. We are using default values.
4005 * Representing 001 for L0s and 010 for L1
4007 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
4009 "Could not write PCI config space for Latency Timers\n");
4013 /* Change the max read size to 2k */
4014 if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) {
4016 "Could not read PCI config space for Max read size\n");
4020 read_size_reg &= 0x8f;
4021 read_size_reg |= 0x40;
4023 if (pci_write_config_byte(pdev, 0x51, read_size_reg)) {
4025 "Could not write PCI config space for Max read size\n");
4029 /* Get MAC address from config space if an eeprom exists, otherwise
4030 * the MAC address there will not be valid
4032 if (!adapter->has_eeprom) {
4033 et131x_hwaddr_init(adapter);
4037 for (i = 0; i < ETH_ALEN; i++) {
4038 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
4039 adapter->rom_addr + i)) {
4040 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
4044 memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
4049 * et131x_enable_interrupts - enable interrupt
4050 * @adapter: et131x device
4052 * Enable the appropriate interrupts on the ET131x according to our
4055 void et131x_enable_interrupts(struct et131x_adapter *adapter)
4059 /* Enable all global interrupts */
4060 if (adapter->flowcontrol == FLOW_TXONLY ||
4061 adapter->flowcontrol == FLOW_BOTH)
4062 mask = INT_MASK_ENABLE;
4064 mask = INT_MASK_ENABLE_NO_FLOW;
4066 writel(mask, &adapter->regs->global.int_mask);
4070 * et131x_error_timer_handler
4071 * @data: timer-specific variable; here a pointer to our adapter structure
4073 * The routine called when the error timer expires, to track the number of
4076 void et131x_error_timer_handler(unsigned long data)
4078 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
4079 struct phy_device *phydev = adapter->phydev;
4081 if (et1310_in_phy_coma(adapter)) {
4082 /* Bring the device immediately out of coma, to
4083 * prevent it from sleeping indefinitely, this
4084 * mechanism could be improved! */
4085 et1310_disable_phy_coma(adapter);
4086 adapter->boot_coma = 20;
4088 et1310_update_macstat_host_counters(adapter);
4091 if (!phydev->link && adapter->boot_coma < 11)
4092 adapter->boot_coma++;
4094 if (adapter->boot_coma == 10) {
4095 if (!phydev->link) {
4096 if (!et1310_in_phy_coma(adapter)) {
4097 /* NOTE - This was originally a 'sync with
4098 * interrupt'. How to do that under Linux?
4100 et131x_enable_interrupts(adapter);
4101 et1310_enable_phy_coma(adapter);
4106 /* This is a periodic timer, so reschedule */
4107 mod_timer(&adapter->error_timer, jiffies +
4108 TX_ERROR_PERIOD * HZ / 1000);
4112 * et131x_adapter_memory_alloc
4113 * @adapter: pointer to our private adapter structure
4115 * Returns 0 on success, errno on failure (as defined in errno.h).
4117 * Allocate all the memory blocks for send, receive and others.
4119 int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
4123 /* Allocate memory for the Tx Ring */
4124 status = et131x_tx_dma_memory_alloc(adapter);
4126 dev_err(&adapter->pdev->dev,
4127 "et131x_tx_dma_memory_alloc FAILED\n");
4130 /* Receive buffer memory allocation */
4131 status = et131x_rx_dma_memory_alloc(adapter);
4133 dev_err(&adapter->pdev->dev,
4134 "et131x_rx_dma_memory_alloc FAILED\n");
4135 et131x_tx_dma_memory_free(adapter);
4139 /* Init receive data structures */
4140 status = et131x_init_recv(adapter);
4142 dev_err(&adapter->pdev->dev,
4143 "et131x_init_recv FAILED\n");
4144 et131x_tx_dma_memory_free(adapter);
4145 et131x_rx_dma_memory_free(adapter);
4151 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
4152 * @adapter: pointer to our private adapter structure
4154 void et131x_adapter_memory_free(struct et131x_adapter *adapter)
4156 /* Free DMA memory */
4157 et131x_tx_dma_memory_free(adapter);
4158 et131x_rx_dma_memory_free(adapter);
4161 static void et131x_adjust_link(struct net_device *netdev)
4163 struct et131x_adapter *adapter = netdev_priv(netdev);
4164 struct phy_device *phydev = adapter->phydev;
4166 if (netif_carrier_ok(netdev)) {
4167 adapter->boot_coma = 20;
4169 if (phydev && phydev->speed == SPEED_10) {
4171 * NOTE - Is there a way to query this without
4173 * && TRU_QueryCoreType(adapter->hTruePhy, 0)==
4174 * EMI_TRUEPHY_A13O) {
4178 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
4180 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4182 et131x_mii_write(adapter, PHY_INDEX_REG,
4183 register18 | 0x8402);
4184 et131x_mii_write(adapter, PHY_DATA_REG,
4186 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4190 et1310_config_flow_control(adapter);
4192 if (phydev && phydev->speed == SPEED_1000 &&
4193 adapter->registry_jumbo_packet > 2048) {
4196 et131x_mii_read(adapter, PHY_CONFIG, ®);
4197 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
4198 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
4199 et131x_mii_write(adapter, PHY_CONFIG, reg);
4202 et131x_set_rx_dma_timer(adapter);
4203 et1310_config_mac_regs2(adapter);
4206 if (phydev && phydev->link != adapter->link) {
4208 * Check to see if we are in coma mode and if
4209 * so, disable it because we will not be able
4210 * to read PHY values until we are out.
4212 if (et1310_in_phy_coma(adapter))
4213 et1310_disable_phy_coma(adapter);
4216 adapter->boot_coma = 20;
4218 dev_warn(&adapter->pdev->dev,
4219 "Link down - cable problem ?\n");
4220 adapter->boot_coma = 0;
4222 if (phydev->speed == SPEED_10) {
4223 /* NOTE - Is there a way to query this without
4225 * && TRU_QueryCoreType(adapter->hTruePhy, 0) ==
4230 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
4232 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4234 et131x_mii_write(adapter, PHY_INDEX_REG,
4235 register18 | 0x8402);
4236 et131x_mii_write(adapter, PHY_DATA_REG,
4238 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4242 /* Free the packets being actively sent & stopped */
4243 et131x_free_busy_send_packets(adapter);
4245 /* Re-initialize the send structures */
4246 et131x_init_send(adapter);
4249 * Bring the device back to the state it was during
4250 * init prior to autonegotiation being complete. This
4251 * way, when we get the auto-neg complete interrupt,
4252 * we can complete init by calling config_mac_regs2.
4254 et131x_soft_reset(adapter);
4256 /* Setup ET1310 as per the documentation */
4257 et131x_adapter_setup(adapter);
4259 /* perform reset of tx/rx */
4260 et131x_disable_txrx(netdev);
4261 et131x_enable_txrx(netdev);
4264 adapter->link = phydev->link;
4266 phy_print_status(phydev);
4270 static int et131x_mii_probe(struct net_device *netdev)
4272 struct et131x_adapter *adapter = netdev_priv(netdev);
4273 struct phy_device *phydev = NULL;
4275 phydev = phy_find_first(adapter->mii_bus);
4277 dev_err(&adapter->pdev->dev, "no PHY found\n");
4281 phydev = phy_connect(netdev, dev_name(&phydev->dev),
4282 &et131x_adjust_link, 0, PHY_INTERFACE_MODE_MII);
4284 if (IS_ERR(phydev)) {
4285 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
4286 return PTR_ERR(phydev);
4289 phydev->supported &= (SUPPORTED_10baseT_Half
4290 | SUPPORTED_10baseT_Full
4291 | SUPPORTED_100baseT_Half
4292 | SUPPORTED_100baseT_Full
4297 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
4298 phydev->supported |= SUPPORTED_1000baseT_Full;
4300 phydev->advertising = phydev->supported;
4301 adapter->phydev = phydev;
4303 dev_info(&adapter->pdev->dev, "attached PHY driver [%s] "
4304 "(mii_bus:phy_addr=%s)\n",
4305 phydev->drv->name, dev_name(&phydev->dev));
4311 * et131x_adapter_init
4312 * @adapter: pointer to the private adapter struct
4313 * @pdev: pointer to the PCI device
4315 * Initialize the data structures for the et131x_adapter object and link
4316 * them together with the platform provided device structures.
4318 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
4319 struct pci_dev *pdev)
4321 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
4323 struct et131x_adapter *adapter;
4325 /* Allocate private adapter struct and copy in relevant information */
4326 adapter = netdev_priv(netdev);
4327 adapter->pdev = pci_dev_get(pdev);
4328 adapter->netdev = netdev;
4330 /* Do the same for the netdev struct */
4331 netdev->irq = pdev->irq;
4332 netdev->base_addr = pci_resource_start(pdev, 0);
4334 /* Initialize spinlocks here */
4335 spin_lock_init(&adapter->lock);
4336 spin_lock_init(&adapter->tcb_send_qlock);
4337 spin_lock_init(&adapter->tcb_ready_qlock);
4338 spin_lock_init(&adapter->send_hw_lock);
4339 spin_lock_init(&adapter->rcv_lock);
4340 spin_lock_init(&adapter->rcv_pend_lock);
4341 spin_lock_init(&adapter->fbr_lock);
4342 spin_lock_init(&adapter->phy_lock);
4344 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
4346 /* Set the MAC address to a default */
4347 memcpy(adapter->addr, default_mac, ETH_ALEN);
4353 * et131x_disable_interrupts - interrupt disable
4354 * @adapter: et131x device
4356 * Block all interrupts from the et131x device at the device itself
4358 void et131x_disable_interrupts(struct et131x_adapter *adapter)
4360 /* Disable all global interrupts */
4361 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
4366 * @pdev: a pointer to the device's pci_dev structure
4368 * Registered in the pci_driver structure, this function is called when the
4369 * PCI subsystem detects that a PCI device which matches the information
4370 * contained in the pci_device_id table has been removed.
4372 static void __devexit et131x_pci_remove(struct pci_dev *pdev)
4374 struct net_device *netdev = pci_get_drvdata(pdev);
4375 struct et131x_adapter *adapter = netdev_priv(netdev);
4377 unregister_netdev(netdev);
4378 mdiobus_unregister(adapter->mii_bus);
4379 kfree(adapter->mii_bus->irq);
4380 mdiobus_free(adapter->mii_bus);
4382 et131x_adapter_memory_free(adapter);
4383 iounmap(adapter->regs);
4386 free_netdev(netdev);
4387 pci_release_regions(pdev);
4388 pci_disable_device(pdev);
4391 #ifdef CONFIG_PM_SLEEP
4392 static int et131x_suspend(struct device *dev)
4394 struct pci_dev *pdev = to_pci_dev(dev);
4395 struct net_device *netdev = pci_get_drvdata(pdev);
4397 if (netif_running(netdev)) {
4398 netif_device_detach(netdev);
4399 et131x_down(netdev);
4400 pci_save_state(pdev);
4406 static int et131x_resume(struct device *dev)
4408 struct pci_dev *pdev = to_pci_dev(dev);
4409 struct net_device *netdev = pci_get_drvdata(pdev);
4411 if (netif_running(netdev)) {
4412 pci_restore_state(pdev);
4414 netif_device_attach(netdev);
4423 * et131x_isr - The Interrupt Service Routine for the driver.
4424 * @irq: the IRQ on which the interrupt was received.
4425 * @dev_id: device-specific info (here a pointer to a net_device struct)
4427 * Returns a value indicating if the interrupt was handled.
4429 irqreturn_t et131x_isr(int irq, void *dev_id)
4431 bool handled = true;
4432 struct net_device *netdev = (struct net_device *)dev_id;
4433 struct et131x_adapter *adapter = NULL;
4436 if (!netif_device_present(netdev)) {
4441 adapter = netdev_priv(netdev);
4443 /* If the adapter is in low power state, then it should not
4444 * recognize any interrupt
4447 /* Disable Device Interrupts */
4448 et131x_disable_interrupts(adapter);
4450 /* Get a copy of the value in the interrupt status register
4451 * so we can process the interrupting section
4453 status = readl(&adapter->regs->global.int_status);
4455 if (adapter->flowcontrol == FLOW_TXONLY ||
4456 adapter->flowcontrol == FLOW_BOTH) {
4457 status &= ~INT_MASK_ENABLE;
4459 status &= ~INT_MASK_ENABLE_NO_FLOW;
4462 /* Make sure this is our interrupt */
4465 et131x_enable_interrupts(adapter);
4469 /* This is our interrupt, so process accordingly */
4471 if (status & ET_INTR_WATCHDOG) {
4472 struct tcb *tcb = adapter->tx_ring.send_head;
4475 if (++tcb->stale > 1)
4476 status |= ET_INTR_TXDMA_ISR;
4478 if (adapter->rx_ring.unfinished_receives)
4479 status |= ET_INTR_RXDMA_XFR_DONE;
4480 else if (tcb == NULL)
4481 writel(0, &adapter->regs->global.watchdog_timer);
4483 status &= ~ET_INTR_WATCHDOG;
4487 /* This interrupt has in some way been "handled" by
4488 * the ISR. Either it was a spurious Rx interrupt, or
4489 * it was a Tx interrupt that has been filtered by
4492 et131x_enable_interrupts(adapter);
4496 /* We need to save the interrupt status value for use in our
4497 * DPC. We will clear the software copy of that in that
4500 adapter->stats.interrupt_status = status;
4502 /* Schedule the ISR handler as a bottom-half task in the
4503 * kernel's tq_immediate queue, and mark the queue for
4506 schedule_work(&adapter->task);
4508 return IRQ_RETVAL(handled);
4512 * et131x_isr_handler - The ISR handler
4513 * @p_adapter, a pointer to the device's private adapter structure
4515 * scheduled to run in a deferred context by the ISR. This is where the ISR's
4516 * work actually gets done.
4518 void et131x_isr_handler(struct work_struct *work)
4520 struct et131x_adapter *adapter =
4521 container_of(work, struct et131x_adapter, task);
4522 u32 status = adapter->stats.interrupt_status;
4523 struct address_map __iomem *iomem = adapter->regs;
4526 * These first two are by far the most common. Once handled, we clear
4527 * their two bits in the status word. If the word is now zero, we
4530 /* Handle all the completed Transmit interrupts */
4531 if (status & ET_INTR_TXDMA_ISR)
4532 et131x_handle_send_interrupt(adapter);
4534 /* Handle all the completed Receives interrupts */
4535 if (status & ET_INTR_RXDMA_XFR_DONE)
4536 et131x_handle_recv_interrupt(adapter);
4538 status &= 0xffffffd7;
4541 /* Handle the TXDMA Error interrupt */
4542 if (status & ET_INTR_TXDMA_ERR) {
4545 /* Following read also clears the register (COR) */
4546 txdma_err = readl(&iomem->txdma.tx_dma_error);
4548 dev_warn(&adapter->pdev->dev,
4549 "TXDMA_ERR interrupt, error = %d\n",
4553 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
4555 (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
4557 * This indicates the number of unused buffers in
4558 * RXDMA free buffer ring 0 is <= the limit you
4559 * programmed. Free buffer resources need to be
4560 * returned. Free buffers are consumed as packets
4561 * are passed from the network to the host. The host
4562 * becomes aware of the packets from the contents of
4563 * the packet status ring. This ring is queried when
4564 * the packet done interrupt occurs. Packets are then
4565 * passed to the OS. When the OS is done with the
4566 * packets the resources can be returned to the
4567 * ET1310 for re-use. This interrupt is one method of
4568 * returning resources.
4571 /* If the user has flow control on, then we will
4572 * send a pause packet, otherwise just exit
4574 if (adapter->flowcontrol == FLOW_TXONLY ||
4575 adapter->flowcontrol == FLOW_BOTH) {
4578 /* Tell the device to send a pause packet via
4579 * the back pressure register (bp req and
4582 pm_csr = readl(&iomem->global.pm_csr);
4583 if (!et1310_in_phy_coma(adapter))
4584 writel(3, &iomem->txmac.bp_ctrl);
4588 /* Handle Packet Status Ring Low Interrupt */
4589 if (status & ET_INTR_RXDMA_STAT_LOW) {
4592 * Same idea as with the two Free Buffer Rings.
4593 * Packets going from the network to the host each
4594 * consume a free buffer resource and a packet status
4595 * resource. These resoures are passed to the OS.
4596 * When the OS is done with the resources, they need
4597 * to be returned to the ET1310. This is one method
4598 * of returning the resources.
4602 /* Handle RXDMA Error Interrupt */
4603 if (status & ET_INTR_RXDMA_ERR) {
4605 * The rxdma_error interrupt is sent when a time-out
4606 * on a request issued by the JAGCore has occurred or
4607 * a completion is returned with an un-successful
4608 * status. In both cases the request is considered
4609 * complete. The JAGCore will automatically re-try the
4610 * request in question. Normally information on events
4611 * like these are sent to the host using the "Advanced
4612 * Error Reporting" capability. This interrupt is
4613 * another way of getting similar information. The
4614 * only thing required is to clear the interrupt by
4615 * reading the ISR in the global resources. The
4616 * JAGCore will do a re-try on the request. Normally
4617 * you should never see this interrupt. If you start
4618 * to see this interrupt occurring frequently then
4619 * something bad has occurred. A reset might be the
4624 dev_warn(&adapter->pdev->dev,
4625 "RxDMA_ERR interrupt, error %x\n",
4626 readl(&iomem->txmac.tx_test));
4629 /* Handle the Wake on LAN Event */
4630 if (status & ET_INTR_WOL) {
4632 * This is a secondary interrupt for wake on LAN.
4633 * The driver should never see this, if it does,
4634 * something serious is wrong. We will TRAP the
4635 * message when we are in DBG mode, otherwise we
4638 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
4641 /* Let's move on to the TxMac */
4642 if (status & ET_INTR_TXMAC) {
4643 u32 err = readl(&iomem->txmac.err);
4646 * When any of the errors occur and TXMAC generates
4647 * an interrupt to report these errors, it usually
4648 * means that TXMAC has detected an error in the data
4649 * stream retrieved from the on-chip Tx Q. All of
4650 * these errors are catastrophic and TXMAC won't be
4651 * able to recover data when these errors occur. In
4652 * a nutshell, the whole Tx path will have to be reset
4653 * and re-configured afterwards.
4655 dev_warn(&adapter->pdev->dev,
4656 "TXMAC interrupt, error 0x%08x\n",
4659 /* If we are debugging, we want to see this error,
4660 * otherwise we just want the device to be reset and
4665 /* Handle RXMAC Interrupt */
4666 if (status & ET_INTR_RXMAC) {
4668 * These interrupts are catastrophic to the device,
4669 * what we need to do is disable the interrupts and
4670 * set the flag to cause us to reset so we can solve
4673 /* MP_SET_FLAG( adapter,
4674 fMP_ADAPTER_HARDWARE_ERROR); */
4676 dev_warn(&adapter->pdev->dev,
4677 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
4678 readl(&iomem->rxmac.err_reg));
4680 dev_warn(&adapter->pdev->dev,
4681 "Enable 0x%08x, Diag 0x%08x\n",
4682 readl(&iomem->rxmac.ctrl),
4683 readl(&iomem->rxmac.rxq_diag));
4686 * If we are debugging, we want to see this error,
4687 * otherwise we just want the device to be reset and
4692 /* Handle MAC_STAT Interrupt */
4693 if (status & ET_INTR_MAC_STAT) {
4695 * This means at least one of the un-masked counters
4696 * in the MAC_STAT block has rolled over. Use this
4697 * to maintain the top, software managed bits of the
4700 et1310_handle_macstat_interrupt(adapter);
4703 /* Handle SLV Timeout Interrupt */
4704 if (status & ET_INTR_SLV_TIMEOUT) {
4706 * This means a timeout has occurred on a read or
4707 * write request to one of the JAGCore registers. The
4708 * Global Resources block has terminated the request
4709 * and on a read request, returned a "fake" value.
4710 * The most likely reasons are: Bad Address or the
4711 * addressed module is in a power-down state and
4716 et131x_enable_interrupts(adapter);
4719 /* NETDEV functions */
4722 * et131x_stats - Return the current device statistics.
4723 * @netdev: device whose stats are being queried
4725 * Returns 0 on success, errno on failure (as defined in errno.h)
4727 static struct net_device_stats *et131x_stats(struct net_device *netdev)
4729 struct et131x_adapter *adapter = netdev_priv(netdev);
4730 struct net_device_stats *stats = &adapter->net_stats;
4731 struct ce_stats *devstat = &adapter->stats;
4733 stats->rx_errors = devstat->rx_length_errs +
4734 devstat->rx_align_errs +
4735 devstat->rx_crc_errs +
4736 devstat->rx_code_violations +
4737 devstat->rx_other_errs;
4738 stats->tx_errors = devstat->tx_max_pkt_errs;
4739 stats->multicast = devstat->multicast_pkts_rcvd;
4740 stats->collisions = devstat->tx_collisions;
4742 stats->rx_length_errors = devstat->rx_length_errs;
4743 stats->rx_over_errors = devstat->rx_overflows;
4744 stats->rx_crc_errors = devstat->rx_crc_errs;
4746 /* NOTE: These stats don't have corresponding values in CE_STATS,
4747 * so we're going to have to update these directly from within the
4750 /* stats->rx_bytes = 20; devstat->; */
4751 /* stats->tx_bytes = 20; devstat->; */
4752 /* stats->rx_dropped = devstat->; */
4753 /* stats->tx_dropped = devstat->; */
4755 /* NOTE: Not used, can't find analogous statistics */
4756 /* stats->rx_frame_errors = devstat->; */
4757 /* stats->rx_fifo_errors = devstat->; */
4758 /* stats->rx_missed_errors = devstat->; */
4760 /* stats->tx_aborted_errors = devstat->; */
4761 /* stats->tx_carrier_errors = devstat->; */
4762 /* stats->tx_fifo_errors = devstat->; */
4763 /* stats->tx_heartbeat_errors = devstat->; */
4764 /* stats->tx_window_errors = devstat->; */
4769 * et131x_enable_txrx - Enable tx/rx queues
4770 * @netdev: device to be enabled
4772 void et131x_enable_txrx(struct net_device *netdev)
4774 struct et131x_adapter *adapter = netdev_priv(netdev);
4776 /* Enable the Tx and Rx DMA engines (if not already enabled) */
4777 et131x_rx_dma_enable(adapter);
4778 et131x_tx_dma_enable(adapter);
4780 /* Enable device interrupts */
4781 if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)
4782 et131x_enable_interrupts(adapter);
4784 /* We're ready to move some data, so start the queue */
4785 netif_start_queue(netdev);
4789 * et131x_disable_txrx - Disable tx/rx queues
4790 * @netdev: device to be disabled
4792 void et131x_disable_txrx(struct net_device *netdev)
4794 struct et131x_adapter *adapter = netdev_priv(netdev);
4796 /* First thing is to stop the queue */
4797 netif_stop_queue(netdev);
4799 /* Stop the Tx and Rx DMA engines */
4800 et131x_rx_dma_disable(adapter);
4801 et131x_tx_dma_disable(adapter);
4803 /* Disable device interrupts */
4804 et131x_disable_interrupts(adapter);
4808 * et131x_up - Bring up a device for use.
4809 * @netdev: device to be opened
4811 void et131x_up(struct net_device *netdev)
4813 struct et131x_adapter *adapter = netdev_priv(netdev);
4815 et131x_enable_txrx(netdev);
4816 phy_start(adapter->phydev);
4820 * et131x_open - Open the device for use.
4821 * @netdev: device to be opened
4823 * Returns 0 on success, errno on failure (as defined in errno.h)
4825 int et131x_open(struct net_device *netdev)
4828 struct et131x_adapter *adapter = netdev_priv(netdev);
4830 /* Start the timer to track NIC errors */
4831 init_timer(&adapter->error_timer);
4832 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
4833 adapter->error_timer.function = et131x_error_timer_handler;
4834 adapter->error_timer.data = (unsigned long)adapter;
4835 add_timer(&adapter->error_timer);
4837 /* Register our IRQ */
4838 result = request_irq(netdev->irq, et131x_isr, IRQF_SHARED,
4839 netdev->name, netdev);
4841 dev_err(&adapter->pdev->dev, "could not register IRQ %d\n",
4846 adapter->flags |= fMP_ADAPTER_INTERRUPT_IN_USE;
4854 * et131x_down - Bring down the device
4855 * @netdev: device to be broght down
4857 void et131x_down(struct net_device *netdev)
4859 struct et131x_adapter *adapter = netdev_priv(netdev);
4861 /* Save the timestamp for the TX watchdog, prevent a timeout */
4862 netdev->trans_start = jiffies;
4864 phy_stop(adapter->phydev);
4865 et131x_disable_txrx(netdev);
4869 * et131x_close - Close the device
4870 * @netdev: device to be closed
4872 * Returns 0 on success, errno on failure (as defined in errno.h)
4874 int et131x_close(struct net_device *netdev)
4876 struct et131x_adapter *adapter = netdev_priv(netdev);
4878 et131x_down(netdev);
4880 adapter->flags &= ~fMP_ADAPTER_INTERRUPT_IN_USE;
4881 free_irq(netdev->irq, netdev);
4883 /* Stop the error timer */
4884 return del_timer_sync(&adapter->error_timer);
4888 * et131x_ioctl - The I/O Control handler for the driver
4889 * @netdev: device on which the control request is being made
4890 * @reqbuf: a pointer to the IOCTL request buffer
4891 * @cmd: the IOCTL command code
4893 * Returns 0 on success, errno on failure (as defined in errno.h)
4895 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
4897 struct et131x_adapter *adapter = netdev_priv(netdev);
4899 if (!adapter->phydev)
4902 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4906 * et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4907 * @adapter: pointer to our private adapter structure
4909 * FIXME: lot of dups with MAC code
4911 * Returns 0 on success, errno on failure
4913 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4916 uint32_t filter = adapter->packet_filter;
4920 ctrl = readl(&adapter->regs->rxmac.ctrl);
4921 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4923 /* Default to disabled packet filtering. Enable it in the individual
4924 * case statements that require the device to filter something
4928 /* Set us to be in promiscuous mode so we receive everything, this
4929 * is also true when we get a packet filter of 0
4931 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4932 pf_ctrl &= ~7; /* Clear filter bits */
4935 * Set us up with Multicast packet filtering. Three cases are
4936 * possible - (1) we have a multi-cast list, (2) we receive ALL
4937 * multicast entries or (3) we receive none.
4939 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4940 pf_ctrl &= ~2; /* Multicast filter bit */
4942 et1310_setup_device_for_multicast(adapter);
4947 /* Set us up with Unicast packet filtering */
4948 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4949 et1310_setup_device_for_unicast(adapter);
4954 /* Set us up with Broadcast packet filtering */
4955 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4956 pf_ctrl |= 1; /* Broadcast filter bit */
4961 /* Setup the receive mac configuration registers - Packet
4962 * Filter control + the enable / disable for packet filter
4963 * in the control reg.
4965 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4966 writel(ctrl, &adapter->regs->rxmac.ctrl);
4972 * et131x_multicast - The handler to configure multicasting on the interface
4973 * @netdev: a pointer to a net_device struct representing the device
4975 static void et131x_multicast(struct net_device *netdev)
4977 struct et131x_adapter *adapter = netdev_priv(netdev);
4978 uint32_t packet_filter = 0;
4979 unsigned long flags;
4980 struct netdev_hw_addr *ha;
4983 spin_lock_irqsave(&adapter->lock, flags);
4985 /* Before we modify the platform-independent filter flags, store them
4986 * locally. This allows us to determine if anything's changed and if
4987 * we even need to bother the hardware
4989 packet_filter = adapter->packet_filter;
4991 /* Clear the 'multicast' flag locally; because we only have a single
4992 * flag to check multicast, and multiple multicast addresses can be
4993 * set, this is the easiest way to determine if more than one
4994 * multicast address is being set.
4996 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4998 /* Check the net_device flags and set the device independent flags
5002 if (netdev->flags & IFF_PROMISC)
5003 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
5005 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
5007 if (netdev->flags & IFF_ALLMULTI)
5008 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
5010 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
5011 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
5013 if (netdev_mc_count(netdev) < 1) {
5014 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
5015 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
5017 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
5019 /* Set values in the private adapter struct */
5021 netdev_for_each_mc_addr(ha, netdev) {
5022 if (i == NIC_MAX_MCAST_LIST)
5024 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
5026 adapter->multicast_addr_count = i;
5028 /* Are the new flags different from the previous ones? If not, then no
5029 * action is required
5031 * NOTE - This block will always update the multicast_list with the
5032 * hardware, even if the addresses aren't the same.
5034 if (packet_filter != adapter->packet_filter) {
5035 /* Call the device's filter function */
5036 et131x_set_packet_filter(adapter);
5038 spin_unlock_irqrestore(&adapter->lock, flags);
5042 * et131x_tx - The handler to tx a packet on the device
5043 * @skb: data to be Tx'd
5044 * @netdev: device on which data is to be Tx'd
5046 * Returns 0 on success, errno on failure (as defined in errno.h)
5048 static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
5051 struct et131x_adapter *adapter = netdev_priv(netdev);
5053 /* stop the queue if it's getting full */
5054 if(adapter->tx_ring.used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
5055 netif_stop_queue(netdev);
5057 /* Save the timestamp for the TX timeout watchdog */
5058 netdev->trans_start = jiffies;
5060 /* Call the device-specific data Tx routine */
5061 status = et131x_send_packets(skb, netdev);
5063 /* Check status and manage the netif queue if necessary */
5065 if (status == -ENOMEM) {
5066 status = NETDEV_TX_BUSY;
5068 status = NETDEV_TX_OK;
5075 * et131x_tx_timeout - Timeout handler
5076 * @netdev: a pointer to a net_device struct representing the device
5078 * The handler called when a Tx request times out. The timeout period is
5079 * specified by the 'tx_timeo" element in the net_device structure (see
5080 * et131x_alloc_device() to see how this value is set).
5082 static void et131x_tx_timeout(struct net_device *netdev)
5084 struct et131x_adapter *adapter = netdev_priv(netdev);
5086 unsigned long flags;
5088 /* If the device is closed, ignore the timeout */
5089 if (~(adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE))
5092 /* Any nonrecoverable hardware error?
5093 * Checks adapter->flags for any failure in phy reading
5095 if (adapter->flags & fMP_ADAPTER_NON_RECOVER_ERROR)
5098 /* Hardware failure? */
5099 if (adapter->flags & fMP_ADAPTER_HARDWARE_ERROR) {
5100 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
5104 /* Is send stuck? */
5105 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
5107 tcb = adapter->tx_ring.send_head;
5112 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
5113 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
5116 dev_warn(&adapter->pdev->dev,
5117 "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
5121 adapter->net_stats.tx_errors++;
5123 /* perform reset of tx/rx */
5124 et131x_disable_txrx(netdev);
5125 et131x_enable_txrx(netdev);
5130 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
5134 * et131x_change_mtu - The handler called to change the MTU for the device
5135 * @netdev: device whose MTU is to be changed
5136 * @new_mtu: the desired MTU
5138 * Returns 0 on success, errno on failure (as defined in errno.h)
5140 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
5143 struct et131x_adapter *adapter = netdev_priv(netdev);
5145 /* Make sure the requested MTU is valid */
5146 if (new_mtu < 64 || new_mtu > 9216)
5149 et131x_disable_txrx(netdev);
5150 et131x_handle_send_interrupt(adapter);
5151 et131x_handle_recv_interrupt(adapter);
5153 /* Set the new MTU */
5154 netdev->mtu = new_mtu;
5156 /* Free Rx DMA memory */
5157 et131x_adapter_memory_free(adapter);
5159 /* Set the config parameter for Jumbo Packet support */
5160 adapter->registry_jumbo_packet = new_mtu + 14;
5161 et131x_soft_reset(adapter);
5163 /* Alloc and init Rx DMA memory */
5164 result = et131x_adapter_memory_alloc(adapter);
5166 dev_warn(&adapter->pdev->dev,
5167 "Change MTU failed; couldn't re-alloc DMA memory\n");
5171 et131x_init_send(adapter);
5173 et131x_hwaddr_init(adapter);
5174 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
5176 /* Init the device with the new settings */
5177 et131x_adapter_setup(adapter);
5179 et131x_enable_txrx(netdev);
5185 * et131x_set_mac_addr - handler to change the MAC address for the device
5186 * @netdev: device whose MAC is to be changed
5187 * @new_mac: the desired MAC address
5189 * Returns 0 on success, errno on failure (as defined in errno.h)
5191 * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14
5193 static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
5196 struct et131x_adapter *adapter = netdev_priv(netdev);
5197 struct sockaddr *address = new_mac;
5201 if (adapter == NULL)
5204 /* Make sure the requested MAC is valid */
5205 if (!is_valid_ether_addr(address->sa_data))
5208 et131x_disable_txrx(netdev);
5209 et131x_handle_send_interrupt(adapter);
5210 et131x_handle_recv_interrupt(adapter);
5212 /* Set the new MAC */
5213 /* netdev->set_mac_address = &new_mac; */
5215 memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
5217 printk(KERN_INFO "%s: Setting MAC address to %pM\n",
5218 netdev->name, netdev->dev_addr);
5220 /* Free Rx DMA memory */
5221 et131x_adapter_memory_free(adapter);
5223 et131x_soft_reset(adapter);
5225 /* Alloc and init Rx DMA memory */
5226 result = et131x_adapter_memory_alloc(adapter);
5228 dev_err(&adapter->pdev->dev,
5229 "Change MAC failed; couldn't re-alloc DMA memory\n");
5233 et131x_init_send(adapter);
5235 et131x_hwaddr_init(adapter);
5237 /* Init the device with the new settings */
5238 et131x_adapter_setup(adapter);
5240 et131x_enable_txrx(netdev);
5245 static const struct net_device_ops et131x_netdev_ops = {
5246 .ndo_open = et131x_open,
5247 .ndo_stop = et131x_close,
5248 .ndo_start_xmit = et131x_tx,
5249 .ndo_set_multicast_list = et131x_multicast,
5250 .ndo_tx_timeout = et131x_tx_timeout,
5251 .ndo_change_mtu = et131x_change_mtu,
5252 .ndo_set_mac_address = et131x_set_mac_addr,
5253 .ndo_validate_addr = eth_validate_addr,
5254 .ndo_get_stats = et131x_stats,
5255 .ndo_do_ioctl = et131x_ioctl,
5259 * et131x_device_alloc
5261 * Returns pointer to the allocated and initialized net_device struct for
5264 * Create instances of net_device and wl_private for the new adapter and
5265 * register the device's entry points in the net_device structure.
5267 struct net_device *et131x_device_alloc(void)
5269 struct net_device *netdev;
5271 /* Alloc net_device and adapter structs */
5272 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
5275 printk(KERN_ERR "et131x: Alloc of net_device struct failed\n");
5280 * Setup the function registration table (and other data) for a
5283 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
5284 netdev->netdev_ops = &et131x_netdev_ops;
5287 /* netdev->poll = &et131x_poll; */
5288 /* netdev->poll_controller = &et131x_poll_controller; */
5293 * et131x_pci_setup - Perform device initialization
5294 * @pdev: a pointer to the device's pci_dev structure
5295 * @ent: this device's entry in the pci_device_id table
5297 * Returns 0 on success, errno on failure (as defined in errno.h)
5299 * Registered in the pci_driver structure, this function is called when the
5300 * PCI subsystem finds a new PCI device which matches the information
5301 * contained in the pci_device_id table. This routine is the equivalent to
5302 * a device insertion routine.
5304 static int __devinit et131x_pci_setup(struct pci_dev *pdev,
5305 const struct pci_device_id *ent)
5308 struct net_device *netdev;
5309 struct et131x_adapter *adapter;
5312 result = pci_enable_device(pdev);
5314 dev_err(&pdev->dev, "pci_enable_device() failed\n");
5318 /* Perform some basic PCI checks */
5319 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5320 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
5324 if (pci_request_regions(pdev, DRIVER_NAME)) {
5325 dev_err(&pdev->dev, "Can't get PCI resources\n");
5329 pci_set_master(pdev);
5331 /* Check the DMA addressing support of this device */
5332 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
5333 result = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
5336 "Unable to obtain 64 bit DMA for consistent allocations\n");
5337 goto err_release_res;
5339 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
5340 result = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5343 "Unable to obtain 32 bit DMA for consistent allocations\n");
5344 goto err_release_res;
5347 dev_err(&pdev->dev, "No usable DMA addressing method\n");
5349 goto err_release_res;
5352 /* Allocate netdev and private adapter structs */
5353 netdev = et131x_device_alloc();
5355 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
5357 goto err_release_res;
5360 SET_NETDEV_DEV(netdev, &pdev->dev);
5361 et131x_set_ethtool_ops(netdev);
5363 adapter = et131x_adapter_init(netdev, pdev);
5365 /* Initialise the PCI setup for the device */
5366 et131x_pci_init(adapter, pdev);
5368 /* Map the bus-relative registers to system virtual memory */
5369 adapter->regs = pci_ioremap_bar(pdev, 0);
5370 if (!adapter->regs) {
5371 dev_err(&pdev->dev, "Cannot map device registers\n");
5376 /* If Phy COMA mode was enabled when we went down, disable it here. */
5377 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
5379 /* Issue a global reset to the et1310 */
5380 et131x_soft_reset(adapter);
5382 /* Disable all interrupts (paranoid) */
5383 et131x_disable_interrupts(adapter);
5385 /* Allocate DMA memory */
5386 result = et131x_adapter_memory_alloc(adapter);
5388 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
5392 /* Init send data structures */
5393 et131x_init_send(adapter);
5395 /* Set up the task structure for the ISR's deferred handler */
5396 INIT_WORK(&adapter->task, et131x_isr_handler);
5398 /* Copy address into the net_device struct */
5399 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
5401 /* Init variable for counting how long we do not have link status */
5402 adapter->boot_coma = 0;
5403 et1310_disable_phy_coma(adapter);
5405 /* Setup the mii_bus struct */
5406 adapter->mii_bus = mdiobus_alloc();
5407 if (!adapter->mii_bus) {
5408 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
5412 adapter->mii_bus->name = "et131x_eth_mii";
5413 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
5414 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
5415 adapter->mii_bus->priv = netdev;
5416 adapter->mii_bus->read = et131x_mdio_read;
5417 adapter->mii_bus->write = et131x_mdio_write;
5418 adapter->mii_bus->reset = et131x_mdio_reset;
5419 adapter->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
5420 if (!adapter->mii_bus->irq) {
5421 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
5425 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
5426 adapter->mii_bus->irq[ii] = PHY_POLL;
5428 if (mdiobus_register(adapter->mii_bus)) {
5429 dev_err(&pdev->dev, "failed to register MII bus\n");
5430 mdiobus_free(adapter->mii_bus);
5431 goto err_mdio_free_irq;
5434 if (et131x_mii_probe(netdev)) {
5435 dev_err(&pdev->dev, "failed to probe MII bus\n");
5436 goto err_mdio_unregister;
5439 /* Setup et1310 as per the documentation */
5440 et131x_adapter_setup(adapter);
5442 /* We can enable interrupts now
5444 * NOTE - Because registration of interrupt handler is done in the
5445 * device's open(), defer enabling device interrupts to that
5449 /* Register the net_device struct with the Linux network layer */
5450 result = register_netdev(netdev);
5452 dev_err(&pdev->dev, "register_netdev() failed\n");
5453 goto err_mdio_unregister;
5456 /* Register the net_device struct with the PCI subsystem. Save a copy
5457 * of the PCI config space for this device now that the device has
5458 * been initialized, just in case it needs to be quickly restored.
5460 pci_set_drvdata(pdev, netdev);
5461 pci_save_state(adapter->pdev);
5465 err_mdio_unregister:
5466 mdiobus_unregister(adapter->mii_bus);
5468 kfree(adapter->mii_bus->irq);
5470 mdiobus_free(adapter->mii_bus);
5472 et131x_adapter_memory_free(adapter);
5474 iounmap(adapter->regs);
5477 free_netdev(netdev);
5479 pci_release_regions(pdev);
5481 pci_disable_device(pdev);
5486 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
5487 #define ET131X_PM_OPS (&et131x_pm_ops)
5489 #define ET131X_PM_OPS NULL
5492 static DEFINE_PCI_DEVICE_TABLE(et131x_pci_table) = {
5493 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
5494 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
5497 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
5499 static struct pci_driver et131x_driver = {
5500 .name = DRIVER_NAME,
5501 .id_table = et131x_pci_table,
5502 .probe = et131x_pci_setup,
5503 .remove = __devexit_p(et131x_pci_remove),
5504 .driver.pm = ET131X_PM_OPS,
5508 * et131x_init_module - The "main" entry point called on driver initialization
5510 * Returns 0 on success, errno on failure (as defined in errno.h)
5512 static int __init et131x_init_module(void)
5514 return pci_register_driver(&et131x_driver);
5518 * et131x_cleanup_module - The entry point called on driver cleanup
5520 static void __exit et131x_cleanup_module(void)
5522 pci_unregister_driver(&et131x_driver);
5525 module_init(et131x_init_module);
5526 module_exit(et131x_cleanup_module);