3 * 10/100/1000 Base-T Ethernet Driver for the ET1310 and ET131x series MACs
5 * Copyright * 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_phy.c - Routines for configuring and accessing the PHY
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
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22 * Copyright * 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
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30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
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58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/ctype.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
74 #include <linux/delay.h>
76 #include <linux/bitops.h>
77 #include <asm/system.h>
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82 #include <linux/if_arp.h>
83 #include <linux/ioport.h>
84 #include <linux/random.h>
85 #include <linux/phy.h>
87 #include "et1310_phy.h"
89 #include "et131x_adapter.h"
91 #include "et1310_address_map.h"
92 #include "et1310_tx.h"
93 #include "et1310_rx.h"
97 int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
99 struct net_device *netdev = bus->priv;
100 struct et131x_adapter *adapter = netdev_priv(netdev);
104 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
112 int et131x_mdio_write(struct mii_bus *bus, int phy_addr, int reg, u16 value)
114 struct net_device *netdev = bus->priv;
115 struct et131x_adapter *adapter = netdev_priv(netdev);
117 return et131x_mii_write(adapter, reg, value);
120 int et131x_mdio_reset(struct mii_bus *bus)
122 struct net_device *netdev = bus->priv;
123 struct et131x_adapter *adapter = netdev_priv(netdev);
125 et131x_mii_write(adapter, MII_BMCR, 0x8000);
131 int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
133 struct phy_device *phydev = adapter->phydev;
138 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
142 * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
143 * @adapter: pointer to our private adapter structure
144 * @addr: the address of the transceiver
145 * @reg: the register to read
146 * @value: pointer to a 16-bit value in which the value will be stored
148 * Returns 0 on success, errno on failure (as defined in errno.h)
150 int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
153 struct mac_regs __iomem *mac = &adapter->regs->mac;
160 /* Save a local copy of the registers we are dealing with so we can
163 mii_addr = readl(&mac->mii_mgmt_addr);
164 mii_cmd = readl(&mac->mii_mgmt_cmd);
166 /* Stop the current operation */
167 writel(0, &mac->mii_mgmt_cmd);
169 /* Set up the register we need to read from on the correct PHY */
170 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
172 writel(0x1, &mac->mii_mgmt_cmd);
177 mii_indicator = readl(&mac->mii_mgmt_indicator);
178 } while ((mii_indicator & MGMT_WAIT) && delay < 50);
180 /* If we hit the max delay, we could not read the register */
182 dev_warn(&adapter->pdev->dev,
183 "reg 0x%08x could not be read\n", reg);
184 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
190 /* If we hit here we were able to read the register and we need to
191 * return the value to the caller */
192 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
194 /* Stop the read operation */
195 writel(0, &mac->mii_mgmt_cmd);
197 /* set the registers we touched back to the state at which we entered
200 writel(mii_addr, &mac->mii_mgmt_addr);
201 writel(mii_cmd, &mac->mii_mgmt_cmd);
207 * et131x_mii_write - Write to a PHY register through the MII interface of the MAC
208 * @adapter: pointer to our private adapter structure
209 * @reg: the register to read
210 * @value: 16-bit value to write
212 * FIXME: one caller in netdev still
214 * Return 0 on success, errno on failure (as defined in errno.h)
216 int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
218 struct mac_regs __iomem *mac = &adapter->regs->mac;
219 struct phy_device *phydev = adapter->phydev;
232 /* Save a local copy of the registers we are dealing with so we can
235 mii_addr = readl(&mac->mii_mgmt_addr);
236 mii_cmd = readl(&mac->mii_mgmt_cmd);
238 /* Stop the current operation */
239 writel(0, &mac->mii_mgmt_cmd);
241 /* Set up the register we need to write to on the correct PHY */
242 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
244 /* Add the value to write to the registers to the mac */
245 writel(value, &mac->mii_mgmt_ctrl);
250 mii_indicator = readl(&mac->mii_mgmt_indicator);
251 } while ((mii_indicator & MGMT_BUSY) && delay < 100);
253 /* If we hit the max delay, we could not write the register */
257 dev_warn(&adapter->pdev->dev,
258 "reg 0x%08x could not be written", reg);
259 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
261 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
262 readl(&mac->mii_mgmt_cmd));
264 et131x_mii_read(adapter, reg, &tmp);
268 /* Stop the write operation */
269 writel(0, &mac->mii_mgmt_cmd);
272 * set the registers we touched back to the state at which we entered
275 writel(mii_addr, &mac->mii_mgmt_addr);
276 writel(mii_cmd, &mac->mii_mgmt_cmd);
282 * et1310_phy_power_down - PHY power control
283 * @adapter: device to control
284 * @down: true for off/false for back on
286 * one hundred, ten, one thousand megs
287 * How would you like to have your LAN accessed
288 * Can't you see that this code processed
289 * Phy power, phy power..
291 void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
295 et131x_mii_read(adapter, MII_BMCR, &data);
296 data &= ~0x0800; /* Power UP */
297 if (down) /* Power DOWN */
299 et131x_mii_write(adapter, MII_BMCR, data);
303 * et1310_phy_link_status - read link state
304 * @adapter: device to read
305 * @link_status: reported link state
306 * @autoneg: reported autonegotiation state (complete/incomplete/disabled)
307 * @linkspeed: returnedlink speed in use
308 * @duplex_mode: reported half/full duplex state
309 * @mdi_mdix: not yet working
310 * @masterslave: report whether we are master or slave
311 * @polarity: link polarity
313 * I can read your lan like a magazine
315 * I know your link speed
316 * I see all the setting that you'd rather keep
318 static void et1310_phy_link_status(struct et131x_adapter *adapter,
324 u32 *masterslave, u32 *polarity)
328 u16 vmi_phystatus = 0;
331 et131x_mii_read(adapter, MII_BMSR, &mistatus);
332 et131x_mii_read(adapter, MII_STAT1000, &is1000BaseT);
333 et131x_mii_read(adapter, PHY_PHY_STATUS, &vmi_phystatus);
334 et131x_mii_read(adapter, MII_BMCR, &control);
336 *link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
337 *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
338 TRUEPHY_ANEG_COMPLETE :
339 TRUEPHY_ANEG_NOT_COMPLETE) :
340 TRUEPHY_ANEG_DISABLED;
341 *linkspeed = (vmi_phystatus & 0x0300) >> 8;
342 *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
343 /* NOTE: Need to complete this */
346 *masterslave = (is1000BaseT & 0x4000) ?
347 TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
348 *polarity = (vmi_phystatus & 0x0400) ?
349 TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
352 static void et1310_phy_and_or_reg(struct et131x_adapter *adapter,
353 u16 regnum, u16 and_mask, u16 or_mask)
357 et131x_mii_read(adapter, regnum, ®);
360 et131x_mii_write(adapter, regnum, reg);
363 /* Still used from _mac for BIT_READ */
364 void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action,
365 u16 regnum, u16 bitnum, u8 *value)
368 u16 mask = 0x0001 << bitnum;
370 /* Read the requested register */
371 et131x_mii_read(adapter, regnum, ®);
374 case TRUEPHY_BIT_READ:
375 *value = (reg & mask) >> bitnum;
378 case TRUEPHY_BIT_SET:
379 et131x_mii_write(adapter, regnum, reg | mask);
382 case TRUEPHY_BIT_CLEAR:
383 et131x_mii_write(adapter, regnum, reg & ~mask);
392 * et131x_xcvr_init - Init the phy if we are setting it into force mode
393 * @adapter: pointer to our private adapter structure
396 void et131x_xcvr_init(struct et131x_adapter *adapter)
402 /* Zero out the adapter structure variable representing BMSR */
405 et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, isr), &isr);
406 et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, imr), &imr);
408 /* Set the link status interrupt only. Bad behavior when link status
409 * and auto neg are set, we run into a nested interrupt problem
413 et131x_mii_write(adapter, (u8) offsetof(struct mi_regs, imr), imr);
415 /* Set the LED behavior such that LED 1 indicates speed (off =
416 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
417 * link and activity (on for link, blink off for activity).
419 * NOTE: Some customizations have been added here for specific
420 * vendors; The LED behavior is now determined by vendor data in the
421 * EEPROM. However, the above description is the default.
423 if ((adapter->eeprom_data[1] & 0x4) == 0) {
424 et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, lcr2),
428 lcr2 |= 0xA000; /* led link */
430 if ((adapter->eeprom_data[1] & 0x8) == 0)
435 et131x_mii_write(adapter, (u8) offsetof(struct mi_regs, lcr2),
440 void et131x_mii_check(struct et131x_adapter *adapter,
441 u16 bmsr, u16 bmsr_ints)
443 struct phy_device *phydev = adapter->phydev;
452 if (bmsr_ints & BMSR_LSTATUS) {
453 if (bmsr & BMSR_LSTATUS) {
454 adapter->boot_coma = 20;
455 netif_carrier_on(adapter->netdev);
457 dev_warn(&adapter->pdev->dev,
458 "Link down - cable problem ?\n");
460 if (phydev && phydev->speed == SPEED_10) {
461 /* NOTE - Is there a way to query this without
463 * && TRU_QueryCoreType(adapter->hTruePhy, 0) ==
464 * EMI_TRUEPHY_A13O) {
468 et131x_mii_read(adapter, 0x12, ®ister18);
469 et131x_mii_write(adapter, 0x12,
471 et131x_mii_write(adapter, 0x10,
472 register18 | 0x8402);
473 et131x_mii_write(adapter, 0x11,
475 et131x_mii_write(adapter, 0x12, register18);
478 netif_carrier_off(adapter->netdev);
480 /* Free the packets being actively sent & stopped */
481 et131x_free_busy_send_packets(adapter);
483 /* Re-initialize the send structures */
484 et131x_init_send(adapter);
486 /* Reset the RFD list and re-start RU */
487 et131x_reset_recv(adapter);
490 * Bring the device back to the state it was during
491 * init prior to autonegotiation being complete. This
492 * way, when we get the auto-neg complete interrupt,
493 * we can complete init by calling config_mac_regs2.
495 et131x_soft_reset(adapter);
497 /* Setup ET1310 as per the documentation */
498 et131x_adapter_setup(adapter);
502 if ((bmsr_ints & BMSR_ANEGCOMPLETE) ||
503 (adapter->ai_force_duplex == 3 && (bmsr_ints & BMSR_LSTATUS))) {
504 if ((bmsr & BMSR_ANEGCOMPLETE) ||
505 adapter->ai_force_duplex == 3) {
506 et1310_phy_link_status(adapter,
507 &link_status, &autoneg_status,
508 &speed, &duplex, &mdi_mdix,
509 &masterslave, &polarity);
511 adapter->boot_coma = 20;
513 if (phydev && phydev->speed == SPEED_10) {
515 * NOTE - Is there a way to query this without
517 * && TRU_QueryCoreType(adapter->hTruePhy, 0)==
518 * EMI_TRUEPHY_A13O) {
522 et131x_mii_read(adapter, 0x12, ®ister18);
523 et131x_mii_write(adapter, 0x12,
525 et131x_mii_write(adapter, 0x10,
526 register18 | 0x8402);
527 et131x_mii_write(adapter, 0x11,
529 et131x_mii_write(adapter, 0x12, register18);
532 et1310_config_flow_control(adapter);
534 if (phydev && phydev->speed == SPEED_1000 &&
535 adapter->registry_jumbo_packet > 2048)
536 et1310_phy_and_or_reg(adapter, 0x16, 0xcfff,
539 et131x_set_rx_dma_timer(adapter);
540 et1310_config_mac_regs2(adapter);