3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_mac.c - All code and routines pertaining to the MAC
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/init.h>
62 #include <linux/module.h>
63 #include <linux/types.h>
64 #include <linux/kernel.h>
66 #include <linux/sched.h>
67 #include <linux/ptrace.h>
68 #include <linux/slab.h>
69 #include <linux/ctype.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
74 #include <linux/delay.h>
76 #include <linux/bitops.h>
77 #include <linux/pci.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
85 #include <linux/crc32.h>
87 #include "et1310_phy.h"
88 #include "et131x_adapter.h"
92 #define COUNTER_WRAP_28_BIT 0x10000000
93 #define COUNTER_WRAP_22_BIT 0x400000
94 #define COUNTER_WRAP_16_BIT 0x10000
95 #define COUNTER_WRAP_12_BIT 0x1000
97 #define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1)
98 #define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1)
99 #define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
100 #define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
103 * ConfigMacRegs1 - Initialize the first part of MAC regs
104 * @pAdpater: pointer to our adapter structure
106 void ConfigMACRegs1(struct et131x_adapter *etdev)
108 struct _MAC_t __iomem *pMac = &etdev->regs->mac;
109 MAC_STATION_ADDR1_t station1;
110 MAC_STATION_ADDR2_t station2;
113 /* First we need to reset everything. Write to MAC configuration
114 * register 1 to perform reset.
116 writel(0xC00F0000, &pMac->cfg1);
118 /* Next lets configure the MAC Inter-packet gap register */
119 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
120 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
121 writel(ipg, &pMac->ipg);
123 /* Next lets configure the MAC Half Duplex register */
124 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
125 writel(0x00A1F037, &pMac->hfdp);
127 /* Next lets configure the MAC Interface Control register */
128 writel(0, &pMac->if_ctrl);
130 /* Let's move on to setting up the mii management configuration */
131 writel(0x07, &pMac->mii_mgmt_cfg); /* Clock reset 0x7 */
133 /* Next lets configure the MAC Station Address register. These
134 * values are read from the EEPROM during initialization and stored
135 * in the adapter structure. We write what is stored in the adapter
136 * structure to the MAC Station Address registers high and low. This
137 * station address is used for generating and checking pause control
140 station2.bits.Octet1 = etdev->CurrentAddress[0];
141 station2.bits.Octet2 = etdev->CurrentAddress[1];
142 station1.bits.Octet3 = etdev->CurrentAddress[2];
143 station1.bits.Octet4 = etdev->CurrentAddress[3];
144 station1.bits.Octet5 = etdev->CurrentAddress[4];
145 station1.bits.Octet6 = etdev->CurrentAddress[5];
146 writel(station1.value, &pMac->station_addr_1.value);
147 writel(station2.value, &pMac->station_addr_2.value);
149 /* Max ethernet packet in bytes that will passed by the mac without
150 * being truncated. Allow the MAC to pass 4 more than our max packet
151 * size. This is 4 for the Ethernet CRC.
153 * Packets larger than (RegistryJumboPacket) that do not contain a
154 * VLAN ID will be dropped by the Rx function.
156 writel(etdev->RegistryJumboPacket + 4, &pMac->max_fm_len);
158 /* clear out MAC config reset */
159 writel(0, &pMac->cfg1);
163 * ConfigMacRegs2 - Initialize the second part of MAC regs
164 * @pAdpater: pointer to our adapter structure
166 void ConfigMACRegs2(struct et131x_adapter *etdev)
169 struct _MAC_t __iomem *pMac = &etdev->regs->mac;
175 ctl = readl(&etdev->regs->txmac.ctl);
176 cfg1 = readl(&pMac->cfg1);
177 cfg2 = readl(&pMac->cfg2);
178 ifctrl = readl(&pMac->if_ctrl);
180 /* Set up the if mode bits */
182 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
185 ifctrl &= ~(1 << 24);
191 /* We need to enable Rx/Tx */
192 cfg1 |= CFG1_RX_ENABLE|CFG1_TX_ENABLE|CFG1_TX_FLOW;
193 /* Initialize loop back to off */
194 cfg1 &= ~(CFG1_LOOPBACK|CFG1_RX_FLOW);
195 if (etdev->FlowControl == RxOnly || etdev->FlowControl == Both)
196 cfg1 |= CFG1_RX_FLOW;
197 writel(cfg1, &pMac->cfg1);
199 /* Now we need to initialize the MAC Configuration 2 register */
200 /* preamble 7, check length, huge frame off, pad crc, crc enable
205 /* Turn on duplex if needed */
206 if (etdev->duplex_mode)
209 ifctrl &= ~(1 << 26);
210 if (!etdev->duplex_mode)
211 ifctrl |= (1<<26); /* Enable ghd */
213 writel(ifctrl, &pMac->if_ctrl);
214 writel(cfg2, &pMac->cfg2);
219 cfg1 = readl(&pMac->cfg1);
220 } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
223 dev_warn(&etdev->pdev->dev,
224 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
229 ctl |= 0x05; /* TX mac enable, FC disable */
230 writel(ctl, &etdev->regs->txmac.ctl);
232 /* Ready to start the RXDMA/TXDMA engine */
233 if (etdev->Flags & fMP_ADAPTER_LOWER_POWER) {
234 et131x_rx_dma_enable(etdev);
235 et131x_tx_dma_enable(etdev);
239 void ConfigRxMacRegs(struct et131x_adapter *etdev)
241 struct _RXMAC_t __iomem *pRxMac = &etdev->regs->rxmac;
242 RXMAC_WOL_SA_LO_t sa_lo;
243 RXMAC_WOL_SA_HI_t sa_hi;
246 /* Disable the MAC while it is being configured (also disable WOL) */
247 writel(0x8, &pRxMac->ctrl.value);
249 /* Initialize WOL to disabled. */
250 writel(0, &pRxMac->crc0);
251 writel(0, &pRxMac->crc12);
252 writel(0, &pRxMac->crc34);
254 /* We need to set the WOL mask0 - mask4 next. We initialize it to
255 * its default Values of 0x00000000 because there are not WOL masks
258 writel(0, &pRxMac->mask0_word0);
259 writel(0, &pRxMac->mask0_word1);
260 writel(0, &pRxMac->mask0_word2);
261 writel(0, &pRxMac->mask0_word3);
263 writel(0, &pRxMac->mask1_word0);
264 writel(0, &pRxMac->mask1_word1);
265 writel(0, &pRxMac->mask1_word2);
266 writel(0, &pRxMac->mask1_word3);
268 writel(0, &pRxMac->mask2_word0);
269 writel(0, &pRxMac->mask2_word1);
270 writel(0, &pRxMac->mask2_word2);
271 writel(0, &pRxMac->mask2_word3);
273 writel(0, &pRxMac->mask3_word0);
274 writel(0, &pRxMac->mask3_word1);
275 writel(0, &pRxMac->mask3_word2);
276 writel(0, &pRxMac->mask3_word3);
278 writel(0, &pRxMac->mask4_word0);
279 writel(0, &pRxMac->mask4_word1);
280 writel(0, &pRxMac->mask4_word2);
281 writel(0, &pRxMac->mask4_word3);
283 /* Lets setup the WOL Source Address */
284 sa_lo.bits.sa3 = etdev->CurrentAddress[2];
285 sa_lo.bits.sa4 = etdev->CurrentAddress[3];
286 sa_lo.bits.sa5 = etdev->CurrentAddress[4];
287 sa_lo.bits.sa6 = etdev->CurrentAddress[5];
288 writel(sa_lo.value, &pRxMac->sa_lo.value);
290 sa_hi.bits.sa1 = etdev->CurrentAddress[0];
291 sa_hi.bits.sa2 = etdev->CurrentAddress[1];
292 writel(sa_hi.value, &pRxMac->sa_hi.value);
294 /* Disable all Packet Filtering */
295 writel(0, &pRxMac->pf_ctrl);
297 /* Let's initialize the Unicast Packet filtering address */
298 if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
299 SetupDeviceForUnicast(etdev);
300 pf_ctrl |= 4; /* Unicast filter */
302 writel(0, &pRxMac->uni_pf_addr1.value);
303 writel(0, &pRxMac->uni_pf_addr2.value);
304 writel(0, &pRxMac->uni_pf_addr3.value);
307 /* Let's initialize the Multicast hash */
308 if (!(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
309 pf_ctrl |= 2; /* Multicast filter */
310 SetupDeviceForMulticast(etdev);
313 /* Runt packet filtering. Didn't work in version A silicon. */
314 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
315 pf_ctrl |= 8; /* Fragment filter */
317 if (etdev->RegistryJumboPacket > 8192) {
318 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;
320 /* In order to transmit jumbo packets greater than 8k, the
321 * FIFO between RxMAC and RxDMA needs to be reduced in size
322 * to (16k - Jumbo packet size). In order to implement this,
323 * we must use "cut through" mode in the RxMAC, which chops
324 * packets down into segments which are (max_size * 16). In
325 * this case we selected 256 bytes, since this is the size of
326 * the PCI-Express TLP's that the 1310 uses.
328 mcif_ctrl_max_seg.bits.seg_en = 0x1;
329 mcif_ctrl_max_seg.bits.fc_en = 0x0;
330 mcif_ctrl_max_seg.bits.max_size = 0x10;
332 writel(mcif_ctrl_max_seg.value,
333 &pRxMac->mcif_ctrl_max_seg.value);
335 writel(0, &pRxMac->mcif_ctrl_max_seg.value);
338 /* Initialize the MCIF water marks */
339 writel(0, &pRxMac->mcif_water_mark.value);
341 /* Initialize the MIF control */
342 writel(0, &pRxMac->mif_ctrl.value);
344 /* Initialize the Space Available Register */
345 writel(0, &pRxMac->space_avail.value);
347 /* Initialize the the mif_ctrl register
348 * bit 3: Receive code error. One or more nibbles were signaled as
349 * errors during the reception of the packet. Clear this
350 * bit in Gigabit, set it in 100Mbit. This was derived
351 * experimentally at UNH.
352 * bit 4: Receive CRC error. The packet's CRC did not match the
353 * internally generated CRC.
354 * bit 5: Receive length check error. Indicates that frame length
355 * field value in the packet does not match the actual data
356 * byte length and is not a type field.
357 * bit 16: Receive frame truncated.
358 * bit 17: Drop packet enable
360 if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS)
361 writel(0x30038, &pRxMac->mif_ctrl.value);
363 writel(0x30030, &pRxMac->mif_ctrl.value);
365 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
366 * filter is always enabled since it is where the runt packets are
367 * supposed to be dropped. For version A silicon, runt packet
368 * dropping doesn't work, so it is disabled in the pf_ctrl register,
369 * but we still leave the packet filter on.
371 writel(pf_ctrl, &pRxMac->pf_ctrl);
372 writel(0x9, &pRxMac->ctrl.value);
375 void ConfigTxMacRegs(struct et131x_adapter *etdev)
377 struct txmac_regs *txmac = &etdev->regs->txmac;
379 /* We need to update the Control Frame Parameters
380 * cfpt - control frame pause timer set to 64 (0x40)
381 * cfep - control frame extended pause timer set to 0x0
383 if (etdev->FlowControl == None)
384 writel(0, &txmac->cf_param);
386 writel(0x40, &txmac->cf_param);
389 void ConfigMacStatRegs(struct et131x_adapter *etdev)
391 struct macstat_regs __iomem *macstat =
392 &etdev->regs->macstat;
394 /* Next we need to initialize all the MAC_STAT registers to zero on
397 writel(0, &macstat->RFcs);
398 writel(0, &macstat->RAln);
399 writel(0, &macstat->RFlr);
400 writel(0, &macstat->RDrp);
401 writel(0, &macstat->RCde);
402 writel(0, &macstat->ROvr);
403 writel(0, &macstat->RFrg);
405 writel(0, &macstat->TScl);
406 writel(0, &macstat->TDfr);
407 writel(0, &macstat->TMcl);
408 writel(0, &macstat->TLcl);
409 writel(0, &macstat->TNcl);
410 writel(0, &macstat->TOvr);
411 writel(0, &macstat->TUnd);
413 /* Unmask any counters that we want to track the overflow of.
414 * Initially this will be all counters. It may become clear later
415 * that we do not need to track all counters.
417 writel(0xFFFFBE32, &macstat->Carry1M);
418 writel(0xFFFE7E8B, &macstat->Carry2M);
421 void ConfigFlowControl(struct et131x_adapter *etdev)
423 if (etdev->duplex_mode == 0) {
424 etdev->FlowControl = None;
426 char remote_pause, remote_async_pause;
428 ET1310_PhyAccessMiBit(etdev,
429 TRUEPHY_BIT_READ, 5, 10, &remote_pause);
430 ET1310_PhyAccessMiBit(etdev,
431 TRUEPHY_BIT_READ, 5, 11,
432 &remote_async_pause);
434 if ((remote_pause == TRUEPHY_BIT_SET) &&
435 (remote_async_pause == TRUEPHY_BIT_SET)) {
436 etdev->FlowControl = etdev->RegistryFlowControl;
437 } else if ((remote_pause == TRUEPHY_BIT_SET) &&
438 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
439 if (etdev->RegistryFlowControl == Both)
440 etdev->FlowControl = Both;
442 etdev->FlowControl = None;
443 } else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
444 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
445 etdev->FlowControl = None;
446 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
447 remote_async_pause == TRUEPHY_SET_BIT) */
448 if (etdev->RegistryFlowControl == Both)
449 etdev->FlowControl = RxOnly;
451 etdev->FlowControl = None;
457 * UpdateMacStatHostCounters - Update the local copy of the statistics
458 * @etdev: pointer to the adapter structure
460 void UpdateMacStatHostCounters(struct et131x_adapter *etdev)
462 struct _ce_stats_t *stats = &etdev->Stats;
463 struct macstat_regs __iomem *macstat =
464 &etdev->regs->macstat;
466 stats->collisions += readl(&macstat->TNcl);
467 stats->first_collision += readl(&macstat->TScl);
468 stats->tx_deferred += readl(&macstat->TDfr);
469 stats->excessive_collisions += readl(&macstat->TMcl);
470 stats->late_collisions += readl(&macstat->TLcl);
471 stats->tx_uflo += readl(&macstat->TUnd);
472 stats->max_pkt_error += readl(&macstat->TOvr);
474 stats->alignment_err += readl(&macstat->RAln);
475 stats->crc_err += readl(&macstat->RCde);
476 stats->norcvbuf += readl(&macstat->RDrp);
477 stats->rx_ov_flow += readl(&macstat->ROvr);
478 stats->code_violations += readl(&macstat->RFcs);
479 stats->length_err += readl(&macstat->RFlr);
481 stats->other_errors += readl(&macstat->RFrg);
485 * HandleMacStatInterrupt
486 * @etdev: pointer to the adapter structure
488 * One of the MACSTAT counters has wrapped. Update the local copy of
489 * the statistics held in the adapter structure, checking the "wrap"
490 * bit for each counter.
492 void HandleMacStatInterrupt(struct et131x_adapter *etdev)
497 /* Read the interrupt bits from the register(s). These are Clear On
500 Carry1 = readl(&etdev->regs->macstat.Carry1);
501 Carry2 = readl(&etdev->regs->macstat.Carry2);
503 writel(Carry1, &etdev->regs->macstat.Carry1);
504 writel(Carry2, &etdev->regs->macstat.Carry2);
506 /* We need to do update the host copy of all the MAC_STAT counters.
507 * For each counter, check it's overflow bit. If the overflow bit is
508 * set, then increment the host version of the count by one complete
509 * revolution of the counter. This routine is called when the counter
510 * block indicates that one of the counters has wrapped.
512 if (Carry1 & (1 << 14))
513 etdev->Stats.code_violations += COUNTER_WRAP_16_BIT;
514 if (Carry1 & (1 << 8))
515 etdev->Stats.alignment_err += COUNTER_WRAP_12_BIT;
516 if (Carry1 & (1 << 7))
517 etdev->Stats.length_err += COUNTER_WRAP_16_BIT;
518 if (Carry1 & (1 << 2))
519 etdev->Stats.other_errors += COUNTER_WRAP_16_BIT;
520 if (Carry1 & (1 << 6))
521 etdev->Stats.crc_err += COUNTER_WRAP_16_BIT;
522 if (Carry1 & (1 << 3))
523 etdev->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
524 if (Carry1 & (1 << 0))
525 etdev->Stats.norcvbuf += COUNTER_WRAP_16_BIT;
526 if (Carry2 & (1 << 16))
527 etdev->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;
528 if (Carry2 & (1 << 15))
529 etdev->Stats.tx_uflo += COUNTER_WRAP_12_BIT;
530 if (Carry2 & (1 << 6))
531 etdev->Stats.first_collision += COUNTER_WRAP_12_BIT;
532 if (Carry2 & (1 << 8))
533 etdev->Stats.tx_deferred += COUNTER_WRAP_12_BIT;
534 if (Carry2 & (1 << 5))
535 etdev->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;
536 if (Carry2 & (1 << 4))
537 etdev->Stats.late_collisions += COUNTER_WRAP_12_BIT;
538 if (Carry2 & (1 << 2))
539 etdev->Stats.collisions += COUNTER_WRAP_12_BIT;
542 void SetupDeviceForMulticast(struct et131x_adapter *etdev)
544 struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac;
553 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
554 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
555 * specified) then we should pass NO multi-cast addresses to the
558 if (etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {
559 /* Loop through our multicast array and set up the device */
560 for (nIndex = 0; nIndex < etdev->MCAddressCount; nIndex++) {
561 result = ether_crc(6, etdev->MCList[nIndex]);
563 result = (result & 0x3F800000) >> 23;
566 hash1 |= (1 << result);
567 } else if ((31 < result) && (result < 64)) {
569 hash2 |= (1 << result);
570 } else if ((63 < result) && (result < 96)) {
572 hash3 |= (1 << result);
575 hash4 |= (1 << result);
580 /* Write out the new hash to the device */
581 pm_csr = readl(&etdev->regs->global.pm_csr);
582 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
583 writel(hash1, &rxmac->multi_hash1);
584 writel(hash2, &rxmac->multi_hash2);
585 writel(hash3, &rxmac->multi_hash3);
586 writel(hash4, &rxmac->multi_hash4);
590 void SetupDeviceForUnicast(struct et131x_adapter *etdev)
592 struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac;
593 RXMAC_UNI_PF_ADDR1_t uni_pf1;
594 RXMAC_UNI_PF_ADDR2_t uni_pf2;
595 RXMAC_UNI_PF_ADDR3_t uni_pf3;
598 /* Set up unicast packet filter reg 3 to be the first two octets of
599 * the MAC address for both address
601 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
602 * MAC address for second address
604 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
605 * MAC address for first address
607 uni_pf3.bits.addr1_1 = etdev->CurrentAddress[0];
608 uni_pf3.bits.addr1_2 = etdev->CurrentAddress[1];
609 uni_pf3.bits.addr2_1 = etdev->CurrentAddress[0];
610 uni_pf3.bits.addr2_2 = etdev->CurrentAddress[1];
612 uni_pf2.bits.addr2_3 = etdev->CurrentAddress[2];
613 uni_pf2.bits.addr2_4 = etdev->CurrentAddress[3];
614 uni_pf2.bits.addr2_5 = etdev->CurrentAddress[4];
615 uni_pf2.bits.addr2_6 = etdev->CurrentAddress[5];
617 uni_pf1.bits.addr1_3 = etdev->CurrentAddress[2];
618 uni_pf1.bits.addr1_4 = etdev->CurrentAddress[3];
619 uni_pf1.bits.addr1_5 = etdev->CurrentAddress[4];
620 uni_pf1.bits.addr1_6 = etdev->CurrentAddress[5];
622 pm_csr = readl(&etdev->regs->global.pm_csr);
623 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
624 writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);
625 writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);
626 writel(uni_pf3.value, &rxmac->uni_pf_addr3.value);