drivers/staging/dgnc/dgnc_cls.c

   1 /*
   2  * Copyright 2003 Digi International (www.digi.com)
   3  *      Scott H Kilau <Scott_Kilau at digi dot com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2, or (at your option)
   8  * any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
  12  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  13  * PURPOSE.  See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  *
  20  *      NOTE TO LINUX KERNEL HACKERS:  DO NOT REFORMAT THIS CODE!
  21  *
  22  *      This is shared code between Digi's CVS archive and the
  23  *      Linux Kernel sources.
  24  *      Changing the source just for reformatting needlessly breaks
  25  *      our CVS diff history.
  26  *
  27  *      Send any bug fixes/changes to:  Eng.Linux at digi dot com.
  28  *      Thank you.
  29  *
  30  */
  31
  32 #include <linux/kernel.h>
  33 #include <linux/sched.h>        /* For jiffies, task states */
  34 #include <linux/interrupt.h>    /* For tasklet and interrupt structs/defines */
  35 #include <linux/delay.h>        /* For udelay */
  36 #include <linux/io.h>           /* For read[bwl]/write[bwl] */
  37 #include <linux/serial.h>       /* For struct async_serial */
  38 #include <linux/serial_reg.h>   /* For the various UART offsets */
  39 #include <linux/pci.h>
  40
  41 #include "dgnc_driver.h"        /* Driver main header file */
  42 #include "dgnc_cls.h"
  43 #include "dgnc_tty.h"
  44
  45 static inline void cls_parse_isr(struct dgnc_board *brd, uint port);
  46 static inline void cls_clear_break(struct channel_t *ch, int force);
  47 static inline void cls_set_cts_flow_control(struct channel_t *ch);
  48 static inline void cls_set_rts_flow_control(struct channel_t *ch);
  49 static inline void cls_set_ixon_flow_control(struct channel_t *ch);
  50 static inline void cls_set_ixoff_flow_control(struct channel_t *ch);
  51 static inline void cls_set_no_output_flow_control(struct channel_t *ch);
  52 static inline void cls_set_no_input_flow_control(struct channel_t *ch);
  53 static void cls_parse_modem(struct channel_t *ch, unsigned char signals);
  54 static void cls_tasklet(unsigned long data);
  55 static void cls_vpd(struct dgnc_board *brd);
  56 static void cls_uart_init(struct channel_t *ch);
  57 static void cls_uart_off(struct channel_t *ch);
  58 static int cls_drain(struct tty_struct *tty, uint seconds);
  59 static void cls_param(struct tty_struct *tty);
  60 static void cls_assert_modem_signals(struct channel_t *ch);
  61 static void cls_flush_uart_write(struct channel_t *ch);
  62 static void cls_flush_uart_read(struct channel_t *ch);
  63 static void cls_disable_receiver(struct channel_t *ch);
  64 static void cls_enable_receiver(struct channel_t *ch);
  65 static void cls_send_break(struct channel_t *ch, int msecs);
  66 static void cls_send_start_character(struct channel_t *ch);
  67 static void cls_send_stop_character(struct channel_t *ch);
  68 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch);
  69 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch);
  70 static uint cls_get_uart_bytes_left(struct channel_t *ch);
  71 static void cls_send_immediate_char(struct channel_t *ch, unsigned char);
  72 static irqreturn_t cls_intr(int irq, void *voidbrd);
  73
  74 struct board_ops dgnc_cls_ops = {
  75         .tasklet =                      cls_tasklet,
  76         .intr =                         cls_intr,
  77         .uart_init =                    cls_uart_init,
  78         .uart_off =                     cls_uart_off,
  79         .drain =                        cls_drain,
  80         .param =                        cls_param,
  81         .vpd =                          cls_vpd,
  82         .assert_modem_signals =         cls_assert_modem_signals,
  83         .flush_uart_write =             cls_flush_uart_write,
  84         .flush_uart_read =              cls_flush_uart_read,
  85         .disable_receiver =             cls_disable_receiver,
  86         .enable_receiver =              cls_enable_receiver,
  87         .send_break =                   cls_send_break,
  88         .send_start_character =         cls_send_start_character,
  89         .send_stop_character =          cls_send_stop_character,
  90         .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
  91         .get_uart_bytes_left =          cls_get_uart_bytes_left,
  92         .send_immediate_char =          cls_send_immediate_char
  93 };
  94
  95
  96 static inline void cls_set_cts_flow_control(struct channel_t *ch)
  97 {
  98         unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
  99         unsigned char ier = readb(&ch->ch_cls_uart->ier);
 100         unsigned char isr_fcr = 0;
 101
 102
 103         /*
 104          * The Enhanced Register Set may only be accessed when
 105          * the Line Control Register is set to 0xBFh.
 106          */
 107         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 108
 109         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 110
 111         /* Turn on CTS flow control, turn off IXON flow control */
 112         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
 113         isr_fcr &= ~(UART_EXAR654_EFR_IXON);
 114
 115         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 116
 117         /* Write old LCR value back out, which turns enhanced access off */
 118         writeb(lcrb, &ch->ch_cls_uart->lcr);
 119
 120         /*
 121          * Enable interrupts for CTS flow, turn off interrupts for
 122          * received XOFF chars
 123          */
 124         ier |= (UART_EXAR654_IER_CTSDSR);
 125         ier &= ~(UART_EXAR654_IER_XOFF);
 126         writeb(ier, &ch->ch_cls_uart->ier);
 127
 128         /* Set the usual FIFO values */
 129         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 130
 131         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
 132                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 133                 &ch->ch_cls_uart->isr_fcr);
 134
 135         ch->ch_t_tlevel = 16;
 136
 137 }
 138
 139
 140 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
 141 {
 142         unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
 143         unsigned char ier = readb(&ch->ch_cls_uart->ier);
 144         unsigned char isr_fcr = 0;
 145
 146
 147         /*
 148          * The Enhanced Register Set may only be accessed when
 149          * the Line Control Register is set to 0xBFh.
 150          */
 151         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 152
 153         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 154
 155         /* Turn on IXON flow control, turn off CTS flow control */
 156         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
 157         isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
 158
 159         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 160
 161         /* Now set our current start/stop chars while in enhanced mode */
 162         writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
 163         writeb(0, &ch->ch_cls_uart->lsr);
 164         writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
 165         writeb(0, &ch->ch_cls_uart->spr);
 166
 167         /* Write old LCR value back out, which turns enhanced access off */
 168         writeb(lcrb, &ch->ch_cls_uart->lcr);
 169
 170         /*
 171          * Disable interrupts for CTS flow, turn on interrupts for
 172          * received XOFF chars
 173          */
 174         ier &= ~(UART_EXAR654_IER_CTSDSR);
 175         ier |= (UART_EXAR654_IER_XOFF);
 176         writeb(ier, &ch->ch_cls_uart->ier);
 177
 178         /* Set the usual FIFO values */
 179         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 180
 181         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 182                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 183                 &ch->ch_cls_uart->isr_fcr);
 184
 185 }
 186
 187
 188 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
 189 {
 190         unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
 191         unsigned char ier = readb(&ch->ch_cls_uart->ier);
 192         unsigned char isr_fcr = 0;
 193
 194
 195         /*
 196          * The Enhanced Register Set may only be accessed when
 197          * the Line Control Register is set to 0xBFh.
 198          */
 199         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 200
 201         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 202
 203         /* Turn off IXON flow control, turn off CTS flow control */
 204         isr_fcr |= (UART_EXAR654_EFR_ECB);
 205         isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
 206
 207         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 208
 209         /* Write old LCR value back out, which turns enhanced access off */
 210         writeb(lcrb, &ch->ch_cls_uart->lcr);
 211
 212         /*
 213          * Disable interrupts for CTS flow, turn off interrupts for
 214          * received XOFF chars
 215          */
 216         ier &= ~(UART_EXAR654_IER_CTSDSR);
 217         ier &= ~(UART_EXAR654_IER_XOFF);
 218         writeb(ier, &ch->ch_cls_uart->ier);
 219
 220         /* Set the usual FIFO values */
 221         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 222
 223         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 224                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 225                 &ch->ch_cls_uart->isr_fcr);
 226
 227         ch->ch_r_watermark = 0;
 228         ch->ch_t_tlevel = 16;
 229         ch->ch_r_tlevel = 16;
 230
 231 }
 232
 233
 234 static inline void cls_set_rts_flow_control(struct channel_t *ch)
 235 {
 236         unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
 237         unsigned char ier = readb(&ch->ch_cls_uart->ier);
 238         unsigned char isr_fcr = 0;
 239
 240
 241         /*
 242          * The Enhanced Register Set may only be accessed when
 243          * the Line Control Register is set to 0xBFh.
 244          */
 245         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 246
 247         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 248
 249         /* Turn on RTS flow control, turn off IXOFF flow control */
 250         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
 251         isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
 252
 253         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 254
 255         /* Write old LCR value back out, which turns enhanced access off */
 256         writeb(lcrb, &ch->ch_cls_uart->lcr);
 257
 258         /* Enable interrupts for RTS flow */
 259         ier |= (UART_EXAR654_IER_RTSDTR);
 260         writeb(ier, &ch->ch_cls_uart->ier);
 261
 262         /* Set the usual FIFO values */
 263         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 264
 265         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
 266                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 267                 &ch->ch_cls_uart->isr_fcr);
 268
 269
 270         ch->ch_r_watermark = 4;
 271         ch->ch_r_tlevel = 8;
 272
 273 }
 274
 275
 276 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
 277 {
 278         unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
 279         unsigned char ier = readb(&ch->ch_cls_uart->ier);
 280         unsigned char isr_fcr = 0;
 281
 282
 283         /*
 284          * The Enhanced Register Set may only be accessed when
 285          * the Line Control Register is set to 0xBFh.
 286          */
 287         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 288
 289         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 290
 291         /* Turn on IXOFF flow control, turn off RTS flow control */
 292         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
 293         isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
 294
 295         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 296
 297         /* Now set our current start/stop chars while in enhanced mode */
 298         writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
 299         writeb(0, &ch->ch_cls_uart->lsr);
 300         writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
 301         writeb(0, &ch->ch_cls_uart->spr);
 302
 303         /* Write old LCR value back out, which turns enhanced access off */
 304         writeb(lcrb, &ch->ch_cls_uart->lcr);
 305
 306         /* Disable interrupts for RTS flow */
 307         ier &= ~(UART_EXAR654_IER_RTSDTR);
 308         writeb(ier, &ch->ch_cls_uart->ier);
 309
 310         /* Set the usual FIFO values */
 311         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 312
 313         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 314                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 315                 &ch->ch_cls_uart->isr_fcr);
 316
 317 }
 318
 319
 320 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
 321 {
 322         unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
 323         unsigned char ier = readb(&ch->ch_cls_uart->ier);
 324         unsigned char isr_fcr = 0;
 325
 326
 327         /*
 328          * The Enhanced Register Set may only be accessed when
 329          * the Line Control Register is set to 0xBFh.
 330          */
 331         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 332
 333         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 334
 335         /* Turn off IXOFF flow control, turn off RTS flow control */
 336         isr_fcr |= (UART_EXAR654_EFR_ECB);
 337         isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
 338
 339         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 340
 341         /* Write old LCR value back out, which turns enhanced access off */
 342         writeb(lcrb, &ch->ch_cls_uart->lcr);
 343
 344         /* Disable interrupts for RTS flow */
 345         ier &= ~(UART_EXAR654_IER_RTSDTR);
 346         writeb(ier, &ch->ch_cls_uart->ier);
 347
 348         /* Set the usual FIFO values */
 349         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 350
 351         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 352                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 353                 &ch->ch_cls_uart->isr_fcr);
 354
 355         ch->ch_t_tlevel = 16;
 356         ch->ch_r_tlevel = 16;
 357
 358 }
 359
 360
 361 /*
 362  * cls_clear_break.
 363  * Determines whether its time to shut off break condition.
 364  *
 365  * No locks are assumed to be held when calling this function.
 366  * channel lock is held and released in this function.
 367  */
 368 static inline void cls_clear_break(struct channel_t *ch, int force)
 369 {
 370         unsigned long flags;
 371
 372         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 373                 return;
 374
 375         spin_lock_irqsave(&ch->ch_lock, flags);
 376
 377         /* Bail if we aren't currently sending a break. */
 378         if (!ch->ch_stop_sending_break) {
 379                 spin_unlock_irqrestore(&ch->ch_lock, flags);
 380                 return;
 381         }
 382
 383         /* Turn break off, and unset some variables */
 384         if (ch->ch_flags & CH_BREAK_SENDING) {
 385                 if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
 386                         unsigned char temp = readb(&ch->ch_cls_uart->lcr);
 387
 388                         writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
 389                         ch->ch_flags &= ~(CH_BREAK_SENDING);
 390                         ch->ch_stop_sending_break = 0;
 391                 }
 392         }
 393         spin_unlock_irqrestore(&ch->ch_lock, flags);
 394 }
 395
 396
 397 /* Parse the ISR register for the specific port */
 398 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
 399 {
 400         struct channel_t *ch;
 401         unsigned char isr = 0;
 402         unsigned long flags;
 403
 404         /*
 405          * No need to verify board pointer, it was already
 406          * verified in the interrupt routine.
 407          */
 408
 409         if (port > brd->nasync)
 410                 return;
 411
 412         ch = brd->channels[port];
 413         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 414                 return;
 415
 416         /* Here we try to figure out what caused the interrupt to happen */
 417         while (1) {
 418
 419                 isr = readb(&ch->ch_cls_uart->isr_fcr);
 420
 421                 /* Bail if no pending interrupt on port */
 422                 if (isr & UART_IIR_NO_INT)
 423                         break;
 424
 425                 /* Receive Interrupt pending */
 426                 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
 427                         /* Read data from uart -> queue */
 428                         brd->intr_rx++;
 429                         ch->ch_intr_rx++;
 430                         cls_copy_data_from_uart_to_queue(ch);
 431                         dgnc_check_queue_flow_control(ch);
 432                 }
 433
 434                 /* Transmit Hold register empty pending */
 435                 if (isr & UART_IIR_THRI) {
 436                         /* Transfer data (if any) from Write Queue -> UART. */
 437                         spin_lock_irqsave(&ch->ch_lock, flags);
 438                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 439                         brd->intr_tx++;
 440                         ch->ch_intr_tx++;
 441                         spin_unlock_irqrestore(&ch->ch_lock, flags);
 442                         cls_copy_data_from_queue_to_uart(ch);
 443                 }
 444
 445                 /* CTS/RTS change of state */
 446                 if (isr & UART_IIR_CTSRTS) {
 447                         brd->intr_modem++;
 448                         ch->ch_intr_modem++;
 449                         /*
 450                          * Don't need to do anything, the cls_parse_modem
 451                          * below will grab the updated modem signals.
 452                          */
 453                 }
 454
 455                 /* Parse any modem signal changes */
 456                 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
 457         }
 458 }
 459
 460
 461 /*
 462  * cls_param()
 463  * Send any/all changes to the line to the UART.
 464  */
 465 static void cls_param(struct tty_struct *tty)
 466 {
 467         unsigned char lcr = 0;
 468         unsigned char uart_lcr = 0;
 469         unsigned char ier = 0;
 470         unsigned char uart_ier = 0;
 471         uint baud = 9600;
 472         int quot = 0;
 473         struct dgnc_board *bd;
 474         struct channel_t *ch;
 475         struct un_t   *un;
 476
 477         if (!tty || tty->magic != TTY_MAGIC)
 478                 return;
 479
 480         un = (struct un_t *) tty->driver_data;
 481         if (!un || un->magic != DGNC_UNIT_MAGIC)
 482                 return;
 483
 484         ch = un->un_ch;
 485         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 486                 return;
 487
 488         bd = ch->ch_bd;
 489         if (!bd || bd->magic != DGNC_BOARD_MAGIC)
 490                 return;
 491
 492         /*
 493          * If baud rate is zero, flush queues, and set mval to drop DTR.
 494          */
 495         if ((ch->ch_c_cflag & (CBAUD)) == 0) {
 496                 ch->ch_r_head = 0;
 497                 ch->ch_r_tail = 0;
 498                 ch->ch_e_head = 0;
 499                 ch->ch_e_tail = 0;
 500                 ch->ch_w_head = 0;
 501                 ch->ch_w_tail = 0;
 502
 503                 cls_flush_uart_write(ch);
 504                 cls_flush_uart_read(ch);
 505
 506                 /* The baudrate is B0 so all modem lines are to be dropped. */
 507                 ch->ch_flags |= (CH_BAUD0);
 508                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
 509                 cls_assert_modem_signals(ch);
 510                 ch->ch_old_baud = 0;
 511                 return;
 512         } else if (ch->ch_custom_speed) {
 513
 514                 baud = ch->ch_custom_speed;
 515                 /* Handle transition from B0 */
 516                 if (ch->ch_flags & CH_BAUD0) {
 517                         ch->ch_flags &= ~(CH_BAUD0);
 518
 519                         /*
 520                          * Bring back up RTS and DTR...
 521                          * Also handle RTS or DTR toggle if set.
 522                          */
 523                         if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
 524                                 ch->ch_mostat |= (UART_MCR_RTS);
 525                         if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
 526                                 ch->ch_mostat |= (UART_MCR_DTR);
 527                 }
 528
 529         } else {
 530                 int iindex = 0;
 531                 int jindex = 0;
 532
 533                 ulong bauds[4][16] = {
 534                         { /* slowbaud */
 535                                 0,      50,     75,     110,
 536                                 134,    150,    200,    300,
 537                                 600,    1200,   1800,   2400,
 538                                 4800,   9600,   19200,  38400 },
 539                         { /* slowbaud & CBAUDEX */
 540                                 0,      57600,  115200, 230400,
 541                                 460800, 150,    200,    921600,
 542                                 600,    1200,   1800,   2400,
 543                                 4800,   9600,   19200,  38400 },
 544                         { /* fastbaud */
 545                                 0,      57600,   76800, 115200,
 546                                 131657, 153600, 230400, 460800,
 547                                 921600, 1200,   1800,   2400,
 548                                 4800,   9600,   19200,  38400 },
 549                         { /* fastbaud & CBAUDEX */
 550                                 0,      57600,  115200, 230400,
 551                                 460800, 150,    200,    921600,
 552                                 600,    1200,   1800,   2400,
 553                                 4800,   9600,   19200,  38400 }
 554                 };
 555
 556                 /*
 557                  * Only use the TXPrint baud rate if the terminal
 558                  * unit is NOT open
 559                  */
 560                 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
 561                                          (un->un_type == DGNC_PRINT))
 562                         baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
 563                 else
 564                         baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
 565
 566                 if (ch->ch_c_cflag & CBAUDEX)
 567                         iindex = 1;
 568
 569                 if (ch->ch_digi.digi_flags & DIGI_FAST)
 570                         iindex += 2;
 571
 572                 jindex = baud;
 573
 574                 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
 575                                                                 (jindex < 16)) {
 576                         baud = bauds[iindex][jindex];
 577                 } else {
 578                         baud = 0;
 579                 }
 580
 581                 if (baud == 0)
 582                         baud = 9600;
 583
 584                 /* Handle transition from B0 */
 585                 if (ch->ch_flags & CH_BAUD0) {
 586                         ch->ch_flags &= ~(CH_BAUD0);
 587
 588                         /*
 589                          * Bring back up RTS and DTR...
 590                          * Also handle RTS or DTR toggle if set.
 591                          */
 592                         if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
 593                                 ch->ch_mostat |= (UART_MCR_RTS);
 594                         if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
 595                                 ch->ch_mostat |= (UART_MCR_DTR);
 596                 }
 597         }
 598
 599         if (ch->ch_c_cflag & PARENB)
 600                 lcr |= UART_LCR_PARITY;
 601
 602         if (!(ch->ch_c_cflag & PARODD))
 603                 lcr |= UART_LCR_EPAR;
 604
 605         /*
 606          * Not all platforms support mark/space parity,
 607          * so this will hide behind an ifdef.
 608          */
 609 #ifdef CMSPAR
 610         if (ch->ch_c_cflag & CMSPAR)
 611                 lcr |= UART_LCR_SPAR;
 612 #endif
 613
 614         if (ch->ch_c_cflag & CSTOPB)
 615                 lcr |= UART_LCR_STOP;
 616
 617         switch (ch->ch_c_cflag & CSIZE) {
 618         case CS5:
 619                 lcr |= UART_LCR_WLEN5;
 620                 break;
 621         case CS6:
 622                 lcr |= UART_LCR_WLEN6;
 623                 break;
 624         case CS7:
 625                 lcr |= UART_LCR_WLEN7;
 626                 break;
 627         case CS8:
 628         default:
 629                 lcr |= UART_LCR_WLEN8;
 630                 break;
 631         }
 632
 633         uart_ier = readb(&ch->ch_cls_uart->ier);
 634         ier =  uart_ier;
 635         uart_lcr = readb(&ch->ch_cls_uart->lcr);
 636
 637         if (baud == 0)
 638                 baud = 9600;
 639
 640         quot = ch->ch_bd->bd_dividend / baud;
 641
 642         if (quot != 0 && ch->ch_old_baud != baud) {
 643                 ch->ch_old_baud = baud;
 644                 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
 645                 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
 646                 writeb((quot >> 8), &ch->ch_cls_uart->ier);
 647                 writeb(lcr, &ch->ch_cls_uart->lcr);
 648         }
 649
 650         if (uart_lcr != lcr)
 651                 writeb(lcr, &ch->ch_cls_uart->lcr);
 652
 653         if (ch->ch_c_cflag & CREAD)
 654                 ier |= (UART_IER_RDI | UART_IER_RLSI);
 655         else
 656                 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
 657
 658         /*
 659          * Have the UART interrupt on modem signal changes ONLY when
 660          * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
 661          */
 662         if ((ch->ch_digi.digi_flags & CTSPACE) ||
 663                 (ch->ch_digi.digi_flags & RTSPACE) ||
 664                 (ch->ch_c_cflag & CRTSCTS) ||
 665                 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
 666                 !(ch->ch_c_cflag & CLOCAL))
 667                         ier |= UART_IER_MSI;
 668         else
 669                         ier &= ~UART_IER_MSI;
 670
 671         ier |= UART_IER_THRI;
 672
 673         if (ier != uart_ier)
 674                 writeb(ier, &ch->ch_cls_uart->ier);
 675
 676         if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
 677                 cls_set_cts_flow_control(ch);
 678         } else if (ch->ch_c_iflag & IXON) {
 679                 /*
 680                  * If start/stop is set to disable, then we should
 681                  * disable flow control
 682                  */
 683                 if ((ch->ch_startc == _POSIX_VDISABLE) ||
 684                                          (ch->ch_stopc == _POSIX_VDISABLE))
 685                         cls_set_no_output_flow_control(ch);
 686                 else
 687                         cls_set_ixon_flow_control(ch);
 688         } else {
 689                 cls_set_no_output_flow_control(ch);
 690         }
 691
 692         if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
 693                 cls_set_rts_flow_control(ch);
 694         } else if (ch->ch_c_iflag & IXOFF) {
 695                 /*
 696                  * If start/stop is set to disable, then we should disable
 697                  * flow control
 698                  */
 699                 if ((ch->ch_startc == _POSIX_VDISABLE) ||
 700                                 (ch->ch_stopc == _POSIX_VDISABLE))
 701                         cls_set_no_input_flow_control(ch);
 702                 else
 703                         cls_set_ixoff_flow_control(ch);
 704         } else {
 705                 cls_set_no_input_flow_control(ch);
 706         }
 707
 708         cls_assert_modem_signals(ch);
 709
 710         /* Get current status of the modem signals now */
 711         cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
 712 }
 713
 714
 715 /*
 716  * Our board poller function.
 717  */
 718 static void cls_tasklet(unsigned long data)
 719 {
 720         struct dgnc_board *bd = (struct dgnc_board *) data;
 721         struct channel_t *ch;
 722         unsigned long flags;
 723         int i;
 724         int state = 0;
 725         int ports = 0;
 726
 727         if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
 728                 APR(("poll_tasklet() - NULL or bad bd.\n"));
 729                 return;
 730         }
 731
 732         /* Cache a couple board values */
 733         spin_lock_irqsave(&bd->bd_lock, flags);
 734         state = bd->state;
 735         ports = bd->nasync;
 736         spin_unlock_irqrestore(&bd->bd_lock, flags);
 737
 738         /*
 739          * Do NOT allow the interrupt routine to read the intr registers
 740          * Until we release this lock.
 741          */
 742         spin_lock_irqsave(&bd->bd_intr_lock, flags);
 743
 744         /*
 745          * If board is ready, parse deeper to see if there is anything to do.
 746          */
 747         if ((state == BOARD_READY) && (ports > 0)) {
 748
 749                 /* Loop on each port */
 750                 for (i = 0; i < ports; i++) {
 751                         ch = bd->channels[i];
 752                         if (!ch)
 753                                 continue;
 754
 755                         /*
 756                          * NOTE: Remember you CANNOT hold any channel
 757                          * locks when calling input.
 758                          * During input processing, its possible we
 759                          * will call ld, which might do callbacks back
 760                          * into us.
 761                          */
 762                         dgnc_input(ch);
 763
 764                         /*
 765                          * Channel lock is grabbed and then released
 766                          * inside this routine.
 767                          */
 768                         cls_copy_data_from_queue_to_uart(ch);
 769                         dgnc_wakeup_writes(ch);
 770
 771                         /*
 772                          * Check carrier function.
 773                          */
 774                         dgnc_carrier(ch);
 775
 776                         /*
 777                          * The timing check of turning off the break is done
 778                          * inside clear_break()
 779                          */
 780                         if (ch->ch_stop_sending_break)
 781                                 cls_clear_break(ch, 0);
 782                 }
 783         }
 784
 785         spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
 786
 787 }
 788
 789
 790 /*
 791  * cls_intr()
 792  *
 793  * Classic specific interrupt handler.
 794  */
 795 static irqreturn_t cls_intr(int irq, void *voidbrd)
 796 {
 797         struct dgnc_board *brd = (struct dgnc_board *) voidbrd;
 798         uint i = 0;
 799         unsigned char poll_reg;
 800         unsigned long flags;
 801
 802         if (!brd) {
 803                 APR(("Received interrupt (%d) with null board associated\n",
 804                                                                          irq));
 805                 return IRQ_NONE;
 806         }
 807
 808         /*
 809          * Check to make sure its for us.
 810          */
 811         if (brd->magic != DGNC_BOARD_MAGIC) {
 812                 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n",
 813                           irq));
 814                 return IRQ_NONE;
 815         }
 816
 817         spin_lock_irqsave(&brd->bd_intr_lock, flags);
 818
 819         brd->intr_count++;
 820
 821         /*
 822          * Check the board's global interrupt offset to see if we
 823          * we actually do have an interrupt pending for us.
 824          */
 825         poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
 826
 827         /* If 0, no interrupts pending */
 828         if (!poll_reg) {
 829                 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
 830                 return IRQ_NONE;
 831         }
 832
 833         /* Parse each port to find out what caused the interrupt */
 834         for (i = 0; i < brd->nasync; i++)
 835                 cls_parse_isr(brd, i);
 836
 837         /*
 838          * Schedule tasklet to more in-depth servicing at a better time.
 839          */
 840         tasklet_schedule(&brd->helper_tasklet);
 841
 842         spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
 843
 844         return IRQ_HANDLED;
 845 }
 846
 847
 848 static void cls_disable_receiver(struct channel_t *ch)
 849 {
 850         unsigned char tmp = readb(&ch->ch_cls_uart->ier);
 851
 852         tmp &= ~(UART_IER_RDI);
 853         writeb(tmp, &ch->ch_cls_uart->ier);
 854 }
 855
 856
 857 static void cls_enable_receiver(struct channel_t *ch)
 858 {
 859         unsigned char tmp = readb(&ch->ch_cls_uart->ier);
 860
 861         tmp |= (UART_IER_RDI);
 862         writeb(tmp, &ch->ch_cls_uart->ier);
 863 }
 864
 865
 866 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
 867 {
 868         int qleft = 0;
 869         unsigned char linestatus = 0;
 870         unsigned char error_mask = 0;
 871         ushort head;
 872         ushort tail;
 873         unsigned long flags;
 874
 875         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 876                 return;
 877
 878         spin_lock_irqsave(&ch->ch_lock, flags);
 879
 880         /* cache head and tail of queue */
 881         head = ch->ch_r_head;
 882         tail = ch->ch_r_tail;
 883
 884         /* Store how much space we have left in the queue */
 885         qleft = (tail - head - 1);
 886         if (qleft < 0)
 887                 qleft += RQUEUEMASK + 1;
 888
 889         /*
 890          * Create a mask to determine whether we should
 891          * insert the character (if any) into our queue.
 892          */
 893         if (ch->ch_c_iflag & IGNBRK)
 894                 error_mask |= UART_LSR_BI;
 895
 896         while (1) {
 897                 linestatus = readb(&ch->ch_cls_uart->lsr);
 898
 899                 if (!(linestatus & (UART_LSR_DR)))
 900                         break;
 901
 902                 /*
 903                  * Discard character if we are ignoring the error mask.
 904                 */
 905                 if (linestatus & error_mask)  {
 906                         unsigned char discard;
 907
 908                         linestatus = 0;
 909                         discard = readb(&ch->ch_cls_uart->txrx);
 910                         continue;
 911                 }
 912
 913                 /*
 914                  * If our queue is full, we have no choice but to drop some
 915                  * data. The assumption is that HWFLOW or SWFLOW should have
 916                  * stopped things way way before we got to this point.
 917                  *
 918                  * I decided that I wanted to ditch the oldest data first,
 919                  * I hope thats okay with everyone? Yes? Good.
 920                  */
 921                 while (qleft < 1) {
 922                         tail = (tail + 1) & RQUEUEMASK;
 923                         ch->ch_r_tail = tail;
 924                         ch->ch_err_overrun++;
 925                         qleft++;
 926                 }
 927
 928                 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
 929                                                                  | UART_LSR_FE);
 930                 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
 931                 dgnc_sniff_nowait_nolock(ch, "UART READ",
 932                                                  ch->ch_rqueue + head, 1);
 933
 934                 qleft--;
 935
 936                 if (ch->ch_equeue[head] & UART_LSR_PE)
 937                         ch->ch_err_parity++;
 938                 if (ch->ch_equeue[head] & UART_LSR_BI)
 939                         ch->ch_err_break++;
 940                 if (ch->ch_equeue[head] & UART_LSR_FE)
 941                         ch->ch_err_frame++;
 942
 943                 /* Add to, and flip head if needed */
 944                 head = (head + 1) & RQUEUEMASK;
 945                 ch->ch_rxcount++;
 946         }
 947
 948         /*
 949          * Write new final heads to channel structure.
 950          */
 951         ch->ch_r_head = head & RQUEUEMASK;
 952         ch->ch_e_head = head & EQUEUEMASK;
 953
 954         spin_unlock_irqrestore(&ch->ch_lock, flags);
 955 }
 956
 957
 958 /*
 959  * This function basically goes to sleep for secs, or until
 960  * it gets signalled that the port has fully drained.
 961  */
 962 static int cls_drain(struct tty_struct *tty, uint seconds)
 963 {
 964         unsigned long flags;
 965         struct channel_t *ch;
 966         struct un_t *un;
 967         int rc = 0;
 968
 969         if (!tty || tty->magic != TTY_MAGIC)
 970                 return -ENXIO;
 971
 972         un = (struct un_t *) tty->driver_data;
 973         if (!un || un->magic != DGNC_UNIT_MAGIC)
 974                 return -ENXIO;
 975
 976         ch = un->un_ch;
 977         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 978                 return -ENXIO;
 979
 980         spin_lock_irqsave(&ch->ch_lock, flags);
 981         un->un_flags |= UN_EMPTY;
 982         spin_unlock_irqrestore(&ch->ch_lock, flags);
 983
 984         /*
 985          * NOTE: Do something with time passed in.
 986          */
 987         rc = wait_event_interruptible(un->un_flags_wait,
 988                                          ((un->un_flags & UN_EMPTY) == 0));
 989
 990         /* If ret is non-zero, user ctrl-c'ed us */
 991
 992         return rc;
 993 }
 994
 995
 996 /* Channel lock MUST be held before calling this function! */
 997 static void cls_flush_uart_write(struct channel_t *ch)
 998 {
 999         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1000                 return;
1001
1002         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1003                                                 &ch->ch_cls_uart->isr_fcr);
1004         udelay(10);
1005
1006         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1007 }
1008
1009
1010 /* Channel lock MUST be held before calling this function! */
1011 static void cls_flush_uart_read(struct channel_t *ch)
1012 {
1013         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1014                 return;
1015
1016         /*
1017          * For complete POSIX compatibility, we should be purging the
1018          * read FIFO in the UART here.
1019          *
1020          * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
1021          * incorrectly flushes write data as well as just basically trashing the
1022          * FIFO.
1023          *
1024          * Presumably, this is a bug in this UART.
1025          */
1026
1027         udelay(10);
1028 }
1029
1030
1031 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
1032 {
1033         ushort head;
1034         ushort tail;
1035         int n;
1036         int qlen;
1037         uint len_written = 0;
1038         unsigned long flags;
1039
1040         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1041                 return;
1042
1043         spin_lock_irqsave(&ch->ch_lock, flags);
1044
1045         /* No data to write to the UART */
1046         if (ch->ch_w_tail == ch->ch_w_head) {
1047                 spin_unlock_irqrestore(&ch->ch_lock, flags);
1048                 return;
1049         }
1050
1051         /* If port is "stopped", don't send any data to the UART */
1052         if ((ch->ch_flags & CH_FORCED_STOP) ||
1053                                  (ch->ch_flags & CH_BREAK_SENDING)) {
1054                 spin_unlock_irqrestore(&ch->ch_lock, flags);
1055                 return;
1056         }
1057
1058         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1059                 spin_unlock_irqrestore(&ch->ch_lock, flags);
1060                 return;
1061         }
1062
1063         n = 32;
1064
1065         /* cache head and tail of queue */
1066         head = ch->ch_w_head & WQUEUEMASK;
1067         tail = ch->ch_w_tail & WQUEUEMASK;
1068         qlen = (head - tail) & WQUEUEMASK;
1069
1070         /* Find minimum of the FIFO space, versus queue length */
1071         n = min(n, qlen);
1072
1073         while (n > 0) {
1074
1075                 /*
1076                  * If RTS Toggle mode is on, turn on RTS now if not already set,
1077                  * and make sure we get an event when the data transfer has
1078                  * completed.
1079                  */
1080                 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1081                         if (!(ch->ch_mostat & UART_MCR_RTS)) {
1082                                 ch->ch_mostat |= (UART_MCR_RTS);
1083                                 cls_assert_modem_signals(ch);
1084                         }
1085                         ch->ch_tun.un_flags |= (UN_EMPTY);
1086                 }
1087
1088                 /*
1089                  * If DTR Toggle mode is on, turn on DTR now if not already set,
1090                  * and make sure we get an event when the data transfer has
1091                  * completed.
1092                  */
1093                 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1094                         if (!(ch->ch_mostat & UART_MCR_DTR)) {
1095                                 ch->ch_mostat |= (UART_MCR_DTR);
1096                                 cls_assert_modem_signals(ch);
1097                         }
1098                         ch->ch_tun.un_flags |= (UN_EMPTY);
1099                 }
1100                 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
1101                 dgnc_sniff_nowait_nolock(ch, "UART WRITE",
1102                                             ch->ch_wqueue + ch->ch_w_tail, 1);
1103                 ch->ch_w_tail++;
1104                 ch->ch_w_tail &= WQUEUEMASK;
1105                 ch->ch_txcount++;
1106                 len_written++;
1107                 n--;
1108         }
1109
1110         if (len_written > 0)
1111                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1112
1113         spin_unlock_irqrestore(&ch->ch_lock, flags);
1114 }
1115
1116
1117 static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
1118 {
1119         unsigned char msignals = signals;
1120         unsigned long flags;
1121
1122         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1123                 return;
1124
1125         /*
1126          * Do altpin switching. Altpin switches DCD and DSR.
1127          * This prolly breaks DSRPACE, so we should be more clever here.
1128          */
1129         spin_lock_irqsave(&ch->ch_lock, flags);
1130         if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1131                 unsigned char mswap = signals;
1132
1133                 if (mswap & UART_MSR_DDCD) {
1134                         msignals &= ~UART_MSR_DDCD;
1135                         msignals |= UART_MSR_DDSR;
1136                 }
1137                 if (mswap & UART_MSR_DDSR) {
1138                         msignals &= ~UART_MSR_DDSR;
1139                         msignals |= UART_MSR_DDCD;
1140                 }
1141                 if (mswap & UART_MSR_DCD) {
1142                         msignals &= ~UART_MSR_DCD;
1143                         msignals |= UART_MSR_DSR;
1144                 }
1145                 if (mswap & UART_MSR_DSR) {
1146                         msignals &= ~UART_MSR_DSR;
1147                         msignals |= UART_MSR_DCD;
1148                 }
1149         }
1150         spin_unlock_irqrestore(&ch->ch_lock, flags);
1151
1152         /*
1153          * Scrub off lower bits. They signify delta's, which I don't
1154          * care about
1155          */
1156         signals &= 0xf0;
1157
1158         spin_lock_irqsave(&ch->ch_lock, flags);
1159         if (msignals & UART_MSR_DCD)
1160                 ch->ch_mistat |= UART_MSR_DCD;
1161         else
1162                 ch->ch_mistat &= ~UART_MSR_DCD;
1163
1164         if (msignals & UART_MSR_DSR)
1165                 ch->ch_mistat |= UART_MSR_DSR;
1166         else
1167                 ch->ch_mistat &= ~UART_MSR_DSR;
1168
1169         if (msignals & UART_MSR_RI)
1170                 ch->ch_mistat |= UART_MSR_RI;
1171         else
1172                 ch->ch_mistat &= ~UART_MSR_RI;
1173
1174         if (msignals & UART_MSR_CTS)
1175                 ch->ch_mistat |= UART_MSR_CTS;
1176         else
1177                 ch->ch_mistat &= ~UART_MSR_CTS;
1178         spin_unlock_irqrestore(&ch->ch_lock, flags);
1179 }
1180
1181
1182 /* Make the UART raise any of the output signals we want up */
1183 static void cls_assert_modem_signals(struct channel_t *ch)
1184 {
1185         unsigned char out;
1186
1187         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1188                 return;
1189
1190         out = ch->ch_mostat;
1191
1192         if (ch->ch_flags & CH_LOOPBACK)
1193                 out |= UART_MCR_LOOP;
1194
1195         writeb(out, &ch->ch_cls_uart->mcr);
1196
1197         /* Give time for the UART to actually drop the signals */
1198         udelay(10);
1199 }
1200
1201
1202 static void cls_send_start_character(struct channel_t *ch)
1203 {
1204         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1205                 return;
1206
1207         if (ch->ch_startc != _POSIX_VDISABLE) {
1208                 ch->ch_xon_sends++;
1209                 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
1210         }
1211 }
1212
1213
1214 static void cls_send_stop_character(struct channel_t *ch)
1215 {
1216         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1217                 return;
1218
1219         if (ch->ch_stopc != _POSIX_VDISABLE) {
1220                 ch->ch_xoff_sends++;
1221                 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1222         }
1223 }
1224
1225
1226 /* Inits UART */
1227 static void cls_uart_init(struct channel_t *ch)
1228 {
1229         unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
1230         unsigned char isr_fcr = 0;
1231
1232         writeb(0, &ch->ch_cls_uart->ier);
1233
1234         /*
1235          * The Enhanced Register Set may only be accessed when
1236          * the Line Control Register is set to 0xBFh.
1237          */
1238         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1239
1240         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1241
1242         /* Turn on Enhanced/Extended controls */
1243         isr_fcr |= (UART_EXAR654_EFR_ECB);
1244
1245         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1246
1247         /* Write old LCR value back out, which turns enhanced access off */
1248         writeb(lcrb, &ch->ch_cls_uart->lcr);
1249
1250         /* Clear out UART and FIFO */
1251         readb(&ch->ch_cls_uart->txrx);
1252
1253         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT),
1254                                                  &ch->ch_cls_uart->isr_fcr);
1255         udelay(10);
1256
1257         ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1258
1259         readb(&ch->ch_cls_uart->lsr);
1260         readb(&ch->ch_cls_uart->msr);
1261 }
1262
1263
1264 /*
1265  * Turns off UART.
1266  */
1267 static void cls_uart_off(struct channel_t *ch)
1268 {
1269         writeb(0, &ch->ch_cls_uart->ier);
1270 }
1271
1272
1273 /*
1274  * cls_get_uarts_bytes_left.
1275  * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1276  *
1277  * The channel lock MUST be held by the calling function.
1278  */
1279 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1280 {
1281         unsigned char left = 0;
1282         unsigned char lsr = 0;
1283
1284         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1285                 return 0;
1286
1287         lsr = readb(&ch->ch_cls_uart->lsr);
1288
1289         /* Determine whether the Transmitter is empty or not */
1290         if (!(lsr & UART_LSR_TEMT)) {
1291                 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1292                         tasklet_schedule(&ch->ch_bd->helper_tasklet);
1293                 left = 1;
1294         } else {
1295                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1296                 left = 0;
1297         }
1298
1299         return left;
1300 }
1301
1302
1303 /*
1304  * cls_send_break.
1305  * Starts sending a break thru the UART.
1306  *
1307  * The channel lock MUST be held by the calling function.
1308  */
1309 static void cls_send_break(struct channel_t *ch, int msecs)
1310 {
1311         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1312                 return;
1313
1314         /*
1315          * If we receive a time of 0, this means turn off the break.
1316          */
1317         if (msecs == 0) {
1318                 /* Turn break off, and unset some variables */
1319                 if (ch->ch_flags & CH_BREAK_SENDING) {
1320                         unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1321
1322                         writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1323                         ch->ch_flags &= ~(CH_BREAK_SENDING);
1324                         ch->ch_stop_sending_break = 0;
1325                 }
1326                 return;
1327         }
1328
1329         /*
1330          * Set the time we should stop sending the break.
1331          * If we are already sending a break, toss away the existing
1332          * time to stop, and use this new value instead.
1333          */
1334         ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1335
1336         /* Tell the UART to start sending the break */
1337         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1338                 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1339
1340                 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1341                 ch->ch_flags |= (CH_BREAK_SENDING);
1342         }
1343 }
1344
1345
1346 /*
1347  * cls_send_immediate_char.
1348  * Sends a specific character as soon as possible to the UART,
1349  * jumping over any bytes that might be in the write queue.
1350  *
1351  * The channel lock MUST be held by the calling function.
1352  */
1353 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1354 {
1355         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1356                 return;
1357
1358         writeb(c, &ch->ch_cls_uart->txrx);
1359 }
1360
1361 static void cls_vpd(struct dgnc_board *brd)
1362 {
1363         ulong           vpdbase;        /* Start of io base of the card */
1364         u8 __iomem           *re_map_vpdbase;/* Remapped memory of the card */
1365         int i = 0;
1366
1367
1368         vpdbase = pci_resource_start(brd->pdev, 3);
1369
1370         /* No VPD */
1371         if (!vpdbase)
1372                 return;
1373
1374         re_map_vpdbase = ioremap(vpdbase, 0x400);
1375
1376         if (!re_map_vpdbase)
1377                 return;
1378
1379         /* Store the VPD into our buffer */
1380         for (i = 0; i < 0x40; i++) {
1381                 brd->vpd[i] = readb(re_map_vpdbase + i);
1382                 pr_info("%x ", brd->vpd[i]);
1383         }
1384         pr_info("\n");
1385
1386         if (re_map_vpdbase)
1387                 iounmap(re_map_vpdbase);
1388 }
1389