2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include "cx25821-video.h"
24 #include "cx25821-video-upstream.h"
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/syscalls.h>
32 #include <linux/file.h>
33 #include <linux/fcntl.h>
34 #include <linux/slab.h>
35 #include <asm/uaccess.h>
37 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
38 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
39 MODULE_LICENSE("GPL");
41 static int _intr_msk =
42 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
44 int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
45 struct sram_channel *ch,
46 unsigned int bpl, u32 risc)
48 unsigned int i, lines;
51 if (ch->cmds_start == 0) {
52 cx_write(ch->ptr1_reg, 0);
53 cx_write(ch->ptr2_reg, 0);
54 cx_write(ch->cnt2_reg, 0);
55 cx_write(ch->cnt1_reg, 0);
59 bpl = (bpl + 7) & ~7; /* alignment */
61 lines = ch->fifo_size / bpl;
70 for (i = 0; i < lines; i++) {
71 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
72 cx_write(cdt + 16 * i + 4, 0);
73 cx_write(cdt + 16 * i + 8, 0);
74 cx_write(cdt + 16 * i + 12, 0);
78 cx_write(ch->cmds_start + 0, risc);
80 cx_write(ch->cmds_start + 4, 0);
81 cx_write(ch->cmds_start + 8, cdt);
82 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
83 cx_write(ch->cmds_start + 16, ch->ctrl_start);
85 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
87 for (i = 24; i < 80; i += 4)
88 cx_write(ch->cmds_start + i, 0);
91 cx_write(ch->ptr1_reg, ch->fifo_start);
92 cx_write(ch->ptr2_reg, cdt);
93 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
94 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
99 static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
100 __le32 * rp, unsigned int offset,
101 unsigned int bpl, u32 sync_line,
102 unsigned int lines, int fifo_enable,
105 unsigned int line, i;
106 int dist_betwn_starts = bpl * 2;
108 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
110 if (USE_RISC_NOOP_VIDEO) {
111 for (i = 0; i < NUM_NO_OPS; i++) {
112 *(rp++) = cpu_to_le32(RISC_NOOP);
117 for (line = 0; line < lines; line++) {
118 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
119 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
120 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
122 if ((lines <= NTSC_FIELD_HEIGHT)
123 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
124 offset += dist_betwn_starts;
131 static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
132 dma_addr_t databuf_phys_addr,
133 unsigned int offset, u32 sync_line,
134 unsigned int bpl, unsigned int lines,
135 int fifo_enable, int field_type)
137 unsigned int line, i;
138 struct sram_channel *sram_ch =
139 &dev->sram_channels[dev->_channel_upstream_select];
140 int dist_betwn_starts = bpl * 2;
142 /* sync instruction */
143 if (sync_line != NO_SYNC_LINE) {
144 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
147 if (USE_RISC_NOOP_VIDEO) {
148 for (i = 0; i < NUM_NO_OPS; i++) {
149 *(rp++) = cpu_to_le32(RISC_NOOP);
154 for (line = 0; line < lines; line++) {
155 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
156 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
157 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
159 if ((lines <= NTSC_FIELD_HEIGHT)
160 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
161 offset += dist_betwn_starts; //to skip the other field line
164 // check if we need to enable the FIFO after the first 4 lines
165 // For the upstream video channel, the risc engine will enable the FIFO.
166 if (fifo_enable && line == 3) {
167 *(rp++) = RISC_WRITECR;
168 *(rp++) = sram_ch->dma_ctl;
169 *(rp++) = FLD_VID_FIFO_EN;
170 *(rp++) = 0x00000001;
177 int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
179 unsigned int top_offset,
180 unsigned int bpl, unsigned int lines)
184 int singlefield_lines = lines >> 1; //get line count for single field
185 int odd_num_lines = singlefield_lines;
188 int databuf_offset = 0;
189 int risc_program_size = 0;
190 int risc_flag = RISC_CNT_RESET;
191 unsigned int bottom_offset = bpl;
192 dma_addr_t risc_phys_jump_addr;
195 odd_num_lines = singlefield_lines + 1;
196 risc_program_size = FRAME1_VID_PROG_SIZE;
199 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
200 FRAME_SIZE_NTSC_Y422;
202 risc_program_size = PAL_VID_PROG_SIZE;
205 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
208 /* Virtual address of Risc buffer program */
209 rp = dev->_dma_virt_addr;
211 for (frame = 0; frame < NUM_FRAMES; frame++) {
212 databuf_offset = frame_size * frame;
214 if (UNSET != top_offset) {
215 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
216 rp = cx25821_risc_field_upstream(dev, rp,
218 _data_buf_phys_addr +
226 fifo_enable = FIFO_DISABLE;
229 rp = cx25821_risc_field_upstream(dev, rp,
230 dev->_data_buf_phys_addr +
231 databuf_offset, bottom_offset,
232 0x200, bpl, singlefield_lines,
233 fifo_enable, EVEN_FIELD);
236 risc_flag = RISC_CNT_RESET;
237 risc_phys_jump_addr =
238 dev->_dma_phys_start_addr + risc_program_size;
240 risc_phys_jump_addr = dev->_dma_phys_start_addr;
241 risc_flag = RISC_CNT_INC;
244 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
245 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
246 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
247 *(rp++) = cpu_to_le32(0);
253 void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
255 struct sram_channel *sram_ch =
256 &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_I];
259 if (!dev->_is_running) {
261 ("cx25821: No video file is currently running so return!\n");
264 //Disable RISC interrupts
265 tmp = cx_read(sram_ch->int_msk);
266 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
268 //Turn OFF risc and fifo enable
269 tmp = cx_read(sram_ch->dma_ctl);
270 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
272 //Clear data buffer memory
273 if (dev->_data_buf_virt_addr)
274 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
276 dev->_is_running = 0;
277 dev->_is_first_frame = 0;
278 dev->_frame_count = 0;
279 dev->_file_status = END_OF_FILE;
281 if (dev->_irq_queues) {
282 kfree(dev->_irq_queues);
283 dev->_irq_queues = NULL;
286 if (dev->_filename != NULL)
287 kfree(dev->_filename);
289 tmp = cx_read(VID_CH_MODE_SEL);
290 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
293 void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
295 if (dev->_is_running) {
296 cx25821_stop_upstream_video_ch1(dev);
299 if (dev->_dma_virt_addr) {
300 pci_free_consistent(dev->pci, dev->_risc_size,
301 dev->_dma_virt_addr, dev->_dma_phys_addr);
302 dev->_dma_virt_addr = NULL;
305 if (dev->_data_buf_virt_addr) {
306 pci_free_consistent(dev->pci, dev->_data_buf_size,
307 dev->_data_buf_virt_addr,
308 dev->_data_buf_phys_addr);
309 dev->_data_buf_virt_addr = NULL;
313 int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
316 int frame_index_temp = dev->_frame_index;
319 (dev->_pixel_format ==
320 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
322 int frame_offset = 0;
323 ssize_t vfs_read_retval = 0;
324 char mybuf[line_size];
329 if (dev->_file_status == END_OF_FILE)
335 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
336 FRAME_SIZE_NTSC_Y422;
340 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
343 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
344 file_offset = dev->_frame_count * frame_size;
346 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
348 if (IS_ERR(myfile)) {
349 const int open_errno = -PTR_ERR(myfile);
350 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
351 __func__, dev->_filename, open_errno);
352 return PTR_ERR(myfile);
354 if (!(myfile->f_op)) {
355 printk("%s: File has no file operations registered!",
357 filp_close(myfile, NULL);
361 if (!myfile->f_op->read) {
362 printk("%s: File has no READ operations registered!",
364 filp_close(myfile, NULL);
372 for (i = 0; i < dev->_lines_count; i++) {
376 vfs_read(myfile, mybuf, line_size, &pos);
378 if (vfs_read_retval > 0 && vfs_read_retval == line_size
379 && dev->_data_buf_virt_addr != NULL) {
380 memcpy((void *)(dev->_data_buf_virt_addr +
381 frame_offset / 4), mybuf,
385 file_offset += vfs_read_retval;
386 frame_offset += vfs_read_retval;
388 if (vfs_read_retval < line_size) {
390 "Done: exit %s() since no more bytes to read from Video file.\n",
400 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
403 filp_close(myfile, NULL);
409 static void cx25821_vidups_handler(struct work_struct *work)
411 struct cx25821_dev *dev =
412 container_of(work, struct cx25821_dev, _irq_work_entry);
415 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
420 cx25821_get_frame(dev,
421 &dev->sram_channels[dev->_channel_upstream_select]);
424 int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
429 (dev->_pixel_format ==
430 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
431 ssize_t vfs_read_retval = 0;
432 char mybuf[line_size];
434 loff_t offset = (unsigned long)0;
437 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
439 if (IS_ERR(myfile)) {
440 const int open_errno = -PTR_ERR(myfile);
441 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
442 __func__, dev->_filename, open_errno);
443 return PTR_ERR(myfile);
445 if (!(myfile->f_op)) {
446 printk("%s: File has no file operations registered!",
448 filp_close(myfile, NULL);
452 if (!myfile->f_op->read) {
454 ("%s: File has no READ operations registered! Returning.",
456 filp_close(myfile, NULL);
464 for (j = 0; j < NUM_FRAMES; j++) {
465 for (i = 0; i < dev->_lines_count; i++) {
469 vfs_read(myfile, mybuf, line_size, &pos);
471 if (vfs_read_retval > 0
472 && vfs_read_retval == line_size
473 && dev->_data_buf_virt_addr != NULL) {
474 memcpy((void *)(dev->
475 _data_buf_virt_addr +
480 offset += vfs_read_retval;
482 if (vfs_read_retval < line_size) {
484 "Done: exit %s() since no more bytes to read from Video file.\n",
493 if (vfs_read_retval < line_size) {
499 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
503 filp_close(myfile, NULL);
509 int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
510 struct sram_channel *sram_ch, int bpl)
514 dma_addr_t data_dma_addr;
516 if (dev->_dma_virt_addr != NULL) {
517 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
518 dev->_dma_virt_addr, dev->_dma_phys_addr);
521 dev->_dma_virt_addr =
522 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
524 dev->_dma_virt_start_addr = dev->_dma_virt_addr;
525 dev->_dma_phys_start_addr = dma_addr;
526 dev->_dma_phys_addr = dma_addr;
527 dev->_risc_size = dev->upstream_riscbuf_size;
529 if (!dev->_dma_virt_addr) {
531 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
535 //Clear memory at address
536 memset(dev->_dma_virt_addr, 0, dev->_risc_size);
538 if (dev->_data_buf_virt_addr != NULL) {
539 pci_free_consistent(dev->pci, dev->upstream_databuf_size,
540 dev->_data_buf_virt_addr,
541 dev->_data_buf_phys_addr);
543 //For Video Data buffer allocation
544 dev->_data_buf_virt_addr =
545 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
547 dev->_data_buf_phys_addr = data_dma_addr;
548 dev->_data_buf_size = dev->upstream_databuf_size;
550 if (!dev->_data_buf_virt_addr) {
552 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
556 //Clear memory at address
557 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
559 ret = cx25821_openfile(dev, sram_ch);
563 //Create RISC programs
565 cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
569 "cx25821: Failed creating Video Upstream Risc programs! \n");
579 int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
583 struct sram_channel *channel = &dev->sram_channels[chan_num];
584 int singlefield_lines = NTSC_FIELD_HEIGHT;
585 int line_size_in_bytes = Y422_LINE_SZ;
586 int odd_risc_prog_size = 0;
587 dma_addr_t risc_phys_jump_addr;
590 if (status & FLD_VID_SRC_RISC1) {
591 // We should only process one program per call
592 u32 prog_cnt = cx_read(channel->gpcnt);
594 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
595 int_msk_tmp = cx_read(channel->int_msk);
596 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
597 cx_write(channel->int_stat, _intr_msk);
599 spin_lock(&dev->slock);
601 dev->_frame_index = prog_cnt;
603 queue_work(dev->_irq_queues, &dev->_irq_work_entry);
605 if (dev->_is_first_frame) {
606 dev->_is_first_frame = 0;
609 singlefield_lines += 1;
610 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
612 singlefield_lines = PAL_FIELD_HEIGHT;
613 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
616 if (dev->_dma_virt_start_addr != NULL) {
618 (dev->_pixel_format ==
619 PIXEL_FRMT_411) ? Y411_LINE_SZ :
621 risc_phys_jump_addr =
622 dev->_dma_phys_start_addr +
625 rp = cx25821_update_riscprogram(dev,
627 _dma_virt_start_addr,
635 // Jump to Even Risc program of 1st Frame
636 *(rp++) = cpu_to_le32(RISC_JUMP);
637 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
638 *(rp++) = cpu_to_le32(0);
642 spin_unlock(&dev->slock);
644 if (status & FLD_VID_SRC_UF)
646 ("%s: Video Received Underflow Error Interrupt!\n",
649 if (status & FLD_VID_SRC_SYNC)
650 printk("%s: Video Received Sync Error Interrupt!\n",
653 if (status & FLD_VID_SRC_OPC_ERR)
654 printk("%s: Video Received OpCode Error Interrupt!\n",
658 if (dev->_file_status == END_OF_FILE) {
659 printk("cx25821: EOF Channel 1 Framecount = %d\n",
663 //ElSE, set the interrupt mask register, re-enable irq.
664 int_msk_tmp = cx_read(channel->int_msk);
665 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
670 static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
672 struct cx25821_dev *dev = dev_id;
673 u32 msk_stat, vid_status;
676 struct sram_channel *sram_ch;
681 channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
683 sram_ch = &dev->sram_channels[channel_num];
685 msk_stat = cx_read(sram_ch->int_mstat);
686 vid_status = cx_read(sram_ch->int_stat);
688 // Only deal with our interrupt
691 cx25821_video_upstream_irq(dev, channel_num, vid_status);
695 cx25821_stop_upstream_video_ch1(dev);
700 return IRQ_RETVAL(handled);
703 void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
706 int width = WIDTH_D1;
707 int height = dev->_lines_count;
708 int num_lines, odd_num_lines;
710 int vip_mode = OUTPUT_FRMT_656;
712 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
714 value |= dev->_isNTSC ? 0 : 0x10;
715 cx_write(ch->vid_fmt_ctl, value);
717 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
718 cx_write(ch->vid_active_ctl1, width);
720 num_lines = (height / 2) & 0x3FF;
721 odd_num_lines = num_lines;
727 value = (num_lines << 16) | odd_num_lines;
729 // set number of active lines in field 0 (top) and field 1 (bottom)
730 cx_write(ch->vid_active_ctl2, value);
732 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
735 int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
736 struct sram_channel *sram_ch)
741 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
742 tmp = cx_read(VID_CH_MODE_SEL);
743 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
745 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
746 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
747 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
750 cx_write(sram_ch->gpcnt_ctl, 3);
752 // Clear our bits from the interrupt status register.
753 cx_write(sram_ch->int_stat, _intr_msk);
755 //Set the interrupt mask register, enable irq.
756 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
757 tmp = cx_read(sram_ch->int_msk);
758 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
761 request_irq(dev->pci->irq, cx25821_upstream_irq,
762 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
764 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
769 // Start the DMA engine
770 tmp = cx_read(sram_ch->dma_ctl);
771 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
773 dev->_is_running = 1;
774 dev->_is_first_frame = 1;
779 cx25821_dev_unregister(dev);
783 int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
786 struct sram_channel *sram_ch;
790 int data_frame_size = 0;
791 int risc_buffer_size = 0;
794 if (dev->_is_running) {
795 printk("Video Channel is still running so return!\n");
799 dev->_channel_upstream_select = channel_select;
800 sram_ch = &dev->sram_channels[channel_select];
802 INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
803 dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
805 if (!dev->_irq_queues) {
807 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
810 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
811 tmp = cx_read(VID_CH_MODE_SEL);
812 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
814 dev->_is_running = 0;
815 dev->_frame_count = 0;
816 dev->_file_status = RESET_STATUS;
817 dev->_lines_count = dev->_isNTSC ? 480 : 576;
818 dev->_pixel_format = pixel_format;
820 (dev->_pixel_format ==
821 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
822 data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
824 dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
826 if (dev->input_filename) {
827 str_length = strlen(dev->input_filename);
828 dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL);
833 memcpy(dev->_filename, dev->input_filename, str_length + 1);
835 str_length = strlen(dev->_defaultname);
836 dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL);
841 memcpy(dev->_filename, dev->_defaultname, str_length + 1);
844 //Default if filename is empty string
845 if (strcmp(dev->input_filename, "") == 0) {
848 (dev->_pixel_format ==
849 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
853 (dev->_pixel_format ==
854 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
859 dev->_is_running = 0;
860 dev->_frame_count = 0;
861 dev->_file_status = RESET_STATUS;
862 dev->_lines_count = dev->_isNTSC ? 480 : 576;
863 dev->_pixel_format = pixel_format;
865 (dev->_pixel_format ==
866 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
869 cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
872 /* setup fifo + format */
873 cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
875 dev->upstream_riscbuf_size = risc_buffer_size * 2;
876 dev->upstream_databuf_size = data_frame_size * 2;
878 //Allocating buffers and prepare RISC program
879 retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
882 "%s: Failed to set up Video upstream buffers!\n",
887 cx25821_start_video_dma_upstream(dev, sram_ch);
892 cx25821_dev_unregister(dev);