2 comedi/drivers/rtd520.c
3 Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: Real Time Devices PCI4520/DM7520
26 Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
28 Status: Works. Only tested on DM7520-8. Not SMP safe.
30 Configuration options:
31 [0] - PCI bus of device (optional)
32 If bus/slot is not specified, the first available PCI
34 [1] - PCI slot of device (optional)
37 Created by Dan Christian, NASA Ames Research Center.
39 The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
41 8/16 12 bit ADC with FIFO and channel gain table
42 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
43 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
44 2 12 bit DACs with FIFOs
48 timers: ADC sample, pacer, burst, about, delay, DA1, DA2
50 3 user timer/counters (8254)
53 The DM7520 has slightly fewer features (fewer gain steps).
55 These boards can support external multiplexors and multi-board
56 synchronization, but this driver doesn't support that.
58 Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
59 Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
60 Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
61 Call them and ask for the register level manual.
62 PCI chip: http://www.plxtech.com/products/io/pci9080
65 This board is memory mapped. There is some IO stuff, but it isn't needed.
67 I use a pretty loose naming style within the driver (rtd_blah).
68 All externally visible names should be rtd520_blah.
69 I use camelCase for structures (and inside them).
70 I may also use upper CamelCase for function names (old habit).
72 This board is somewhat related to the RTD PCI4400 board.
74 I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
75 das1800, since they have the best documented code. Driver
76 cb_pcidas64.c uses the same DMA controller.
78 As far as I can tell, the About interrupt doesnt work if Sample is
79 also enabled. It turns out that About really isn't needed, since
80 we always count down samples read.
82 There was some timer/counter code, but it didn't follow the right API.
89 Analog-In supports instruction and command mode.
91 With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
92 (single channel, 64K read buffer). I get random system lockups when
93 using DMA with ALI-15xx based systems. I haven't been able to test
94 any other chipsets. The lockups happen soon after the start of an
95 acquistion, not in the middle of a long run.
97 Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
98 (with a 256K read buffer).
100 Digital-IO and Analog-Out only support instruction mode.
104 #include <linux/interrupt.h>
105 #include <linux/delay.h>
107 #include "../comedidev.h"
108 #include "comedi_pci.h"
110 #define DRV_NAME "rtd520"
112 /*======================================================================
113 Driver specific stuff (tunable)
114 ======================================================================*/
115 /* Enable this to test the new DMA support. You may get hard lock ups */
118 /* We really only need 2 buffers. More than that means being much
119 smarter about knowing which ones are full. */
120 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
122 /* Target period for periodic transfers. This sets the user read latency. */
123 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
124 /* If this is too low, efficiency is poor */
125 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
127 /* Set a practical limit on how long a list to support (affects memory use) */
128 /* The board support a channel list up to the FIFO length (1K or 8K) */
129 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
131 /* tuning for ai/ao instruction done polling */
133 #define WAIT_QUIETLY /* as nothing, spin on done bit */
134 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
135 #define RTD_DAC_TIMEOUT 66000
136 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
138 /* by delaying, power and electrical noise are reduced somewhat */
139 #define WAIT_QUIETLY udelay(1)
140 #define RTD_ADC_TIMEOUT 2000 /* in usec */
141 #define RTD_DAC_TIMEOUT 2000 /* in usec */
142 #define RTD_DMA_TIMEOUT 1000 /* in usec */
145 /*======================================================================
147 ======================================================================*/
150 #define PCI_VENDOR_ID_RTD 0x1435
152 The board has three memory windows: las0, las1, and lcfg (the PCI chip)
153 Las1 has the data and can be burst DMAed 32bits at a time.
155 #define LCFG_PCIINDEX 0
156 /* PCI region 1 is a 256 byte IO space mapping. Use??? */
157 #define LAS0_PCIINDEX 2 /* PCI memory resources */
158 #define LAS1_PCIINDEX 3
159 #define LCFG_PCISIZE 0x100
160 #define LAS0_PCISIZE 0x200
161 #define LAS1_PCISIZE 0x10
163 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
164 #define RTD_CLOCK_BASE 125 /* clock period in ns */
166 /* Note: these speed are slower than the spec, but fit the counter resolution*/
167 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
168 /* max speed if we don't have to wait for settling */
169 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
171 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
172 /* min speed when only 1 channel (no burst counter) */
173 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
178 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
179 #define DMA_MODE_BITS (\
180 PLX_LOCAL_BUS_16_WIDE_BITS \
181 | PLX_DMA_EN_READYIN_BIT \
182 | PLX_DMA_LOCAL_BURST_EN_BIT \
184 | PLX_DMA_INTR_PCI_BIT \
185 | PLX_LOCAL_ADDR_CONST_BIT \
186 | PLX_DEMAND_MODE_BIT)
188 #define DMA_TRANSFER_BITS (\
189 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
190 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
191 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
193 /*======================================================================
194 Comedi specific stuff
195 ======================================================================*/
198 The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
200 static const struct comedi_lrange rtd_ai_7520_range = { 18, {
201 /* +-5V input range gain steps */
210 /* +-10V input range gain steps */
222 /* +10V input range gain steps */
238 /* PCI4520 has two more gains (6 more entries) */
239 static const struct comedi_lrange rtd_ai_4520_range = { 24, {
240 /* +-5V input range gain steps */
253 /* +-10V input range gain steps */
269 /* +10V input range gain steps */
288 /* Table order matches range values */
289 static const struct comedi_lrange rtd_ao_range = { 4, {
301 const char *name; /* must be first */
306 int range10Start; /* start of +-10V range */
307 int rangeUniStart; /* start of +10V range */
310 static const struct rtdBoard rtd520Boards[] = {
331 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table) = {
332 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x7520) },
333 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x4520) },
337 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
340 * Useful for shorthand access to the particular board structure
342 #define thisboard ((const struct rtdBoard *)dev->board_ptr)
345 This structure is for data unique to this hardware driver.
346 This is also unique for each board in the system.
349 /* memory mapped board structures */
354 unsigned long intCount; /* interrupt count */
355 long aiCount; /* total transfer size (samples) */
356 int transCount; /* # to tranfer data. 0->1/2FIFO */
357 int flags; /* flag event modes */
359 /* PCI device info */
360 struct pci_dev *pci_dev;
361 int got_regions; /* non-zero if PCI regions owned */
363 /* channel list info */
364 /* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
365 unsigned char chanBipolar[RTD_MAX_CHANLIST / 8]; /* bit array */
368 unsigned int aoValue[2]; /* Used for AO read back */
370 /* timer gate (when enabled) */
371 u8 utcGate[4]; /* 1 extra allows simple range check */
373 /* shadow registers affect other registers, but cant be read back */
374 /* The macros below update these on writes */
375 u16 intMask; /* interrupt mask */
376 u16 intClearMask; /* interrupt clear mask */
377 u8 utcCtrl[4]; /* crtl mode for 3 utc + read back */
378 u8 dioStatus; /* could be read back (dio0Ctrl) */
380 /* Always DMA 1/2 FIFO. Buffer (dmaBuff?) is (at least) twice that size.
381 After transferring, interrupt processes 1/2 FIFO and passes to comedi */
382 s16 dma0Offset; /* current processing offset (0, 1/2) */
383 uint16_t *dma0Buff[DMA_CHAIN_COUNT]; /* DMA buffers (for ADC) */
384 dma_addr_t dma0BuffPhysAddr[DMA_CHAIN_COUNT]; /* physical addresses */
385 struct plx_dma_desc *dma0Chain; /* DMA descriptor ring for dmaBuff */
386 dma_addr_t dma0ChainPhysAddr; /* physical addresses */
387 /* shadow registers */
394 /* bit defines for "flags" */
395 #define SEND_EOS 0x01 /* send End Of Scan events */
396 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
397 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
399 /* Macros for accessing channel list bit array */
400 #define CHAN_ARRAY_TEST(array, index) \
401 (((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
402 #define CHAN_ARRAY_SET(array, index) \
403 (((array)[(index)/8] |= 1 << ((index) & 0x7)))
404 #define CHAN_ARRAY_CLEAR(array, index) \
405 (((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
408 * most drivers define the following macro to make it easy to
409 * access the private structure.
411 #define devpriv ((struct rtdPrivate *)dev->private)
413 /* Macros to access registers */
416 #define RtdResetBoard(dev) \
417 writel(0, devpriv->las0+LAS0_BOARD_RESET)
419 /* Reset channel gain table read pointer */
420 #define RtdResetCGT(dev) \
421 writel(0, devpriv->las0+LAS0_CGT_RESET)
423 /* Reset channel gain table read and write pointers */
424 #define RtdClearCGT(dev) \
425 writel(0, devpriv->las0+LAS0_CGT_CLEAR)
427 /* Reset channel gain table read and write pointers */
428 #define RtdEnableCGT(dev, v) \
429 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_CGT_ENABLE)
431 /* Write channel gain table entry */
432 #define RtdWriteCGTable(dev, v) \
433 writel(v, devpriv->las0+LAS0_CGT_WRITE)
435 /* Write Channel Gain Latch */
436 #define RtdWriteCGLatch(dev, v) \
437 writel(v, devpriv->las0+LAS0_CGL_WRITE)
440 #define RtdAdcClearFifo(dev) \
441 writel(0, devpriv->las0+LAS0_ADC_FIFO_CLEAR)
443 /* Set ADC start conversion source select (write only) */
444 #define RtdAdcConversionSource(dev, v) \
445 writel(v, devpriv->las0+LAS0_ADC_CONVERSION)
447 /* Set burst start source select (write only) */
448 #define RtdBurstStartSource(dev, v) \
449 writel(v, devpriv->las0+LAS0_BURST_START)
451 /* Set Pacer start source select (write only) */
452 #define RtdPacerStartSource(dev, v) \
453 writel(v, devpriv->las0+LAS0_PACER_START)
455 /* Set Pacer stop source select (write only) */
456 #define RtdPacerStopSource(dev, v) \
457 writel(v, devpriv->las0+LAS0_PACER_STOP)
459 /* Set Pacer clock source select (write only) 0=external 1=internal */
460 #define RtdPacerClockSource(dev, v) \
461 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_SELECT)
463 /* Set sample counter source select (write only) */
464 #define RtdAdcSampleCounterSource(dev, v) \
465 writel(v, devpriv->las0+LAS0_ADC_SCNT_SRC)
467 /* Set Pacer trigger mode select (write only) 0=single cycle, 1=repeat */
468 #define RtdPacerTriggerMode(dev, v) \
469 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_REPEAT)
471 /* Set About counter stop enable (write only) */
472 #define RtdAboutStopEnable(dev, v) \
473 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ACNT_STOP_ENABLE)
475 /* Set external trigger polarity (write only) 0=positive edge, 1=negative */
476 #define RtdTriggerPolarity(dev, v) \
477 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ETRG_POLARITY)
479 /* Start single ADC conversion */
480 #define RtdAdcStart(dev) \
481 writew(0, devpriv->las0+LAS0_ADC)
483 /* Read one ADC data value (12bit (with sign extend) as 16bit) */
484 /* Note: matches what DMA would get. Actual value >> 3 */
485 #define RtdAdcFifoGet(dev) \
486 readw(devpriv->las1+LAS1_ADC_FIFO)
488 /* Read two ADC data values (DOESNT WORK) */
489 #define RtdAdcFifoGet2(dev) \
490 readl(devpriv->las1+LAS1_ADC_FIFO)
493 #define RtdFifoStatus(dev) \
494 readl(devpriv->las0+LAS0_ADC)
496 /* pacer start/stop read=start, write=stop*/
497 #define RtdPacerStart(dev) \
498 readl(devpriv->las0+LAS0_PACER)
499 #define RtdPacerStop(dev) \
500 writel(0, devpriv->las0+LAS0_PACER)
502 /* Interrupt status */
503 #define RtdInterruptStatus(dev) \
504 readw(devpriv->las0+LAS0_IT)
507 #define RtdInterruptMask(dev, v) \
508 writew((devpriv->intMask = (v)), devpriv->las0+LAS0_IT)
510 /* Interrupt status clear (only bits set in mask) */
511 #define RtdInterruptClear(dev) \
512 readw(devpriv->las0+LAS0_CLEAR)
514 /* Interrupt clear mask */
515 #define RtdInterruptClearMask(dev, v) \
516 writew((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
518 /* Interrupt overrun status */
519 #define RtdInterruptOverrunStatus(dev) \
520 readl(devpriv->las0+LAS0_OVERRUN)
522 /* Interrupt overrun clear */
523 #define RtdInterruptOverrunClear(dev) \
524 writel(0, devpriv->las0+LAS0_OVERRUN)
526 /* Pacer counter, 24bit */
527 #define RtdPacerCount(dev) \
528 readl(devpriv->las0+LAS0_PCLK)
529 #define RtdPacerCounter(dev, v) \
530 writel((v) & 0xffffff, devpriv->las0+LAS0_PCLK)
532 /* Burst counter, 10bit */
533 #define RtdBurstCount(dev) \
534 readl(devpriv->las0+LAS0_BCLK)
535 #define RtdBurstCounter(dev, v) \
536 writel((v) & 0x3ff, devpriv->las0+LAS0_BCLK)
538 /* Delay counter, 16bit */
539 #define RtdDelayCount(dev) \
540 readl(devpriv->las0+LAS0_DCLK)
541 #define RtdDelayCounter(dev, v) \
542 writel((v) & 0xffff, devpriv->las0+LAS0_DCLK)
544 /* About counter, 16bit */
545 #define RtdAboutCount(dev) \
546 readl(devpriv->las0+LAS0_ACNT)
547 #define RtdAboutCounter(dev, v) \
548 writel((v) & 0xffff, devpriv->las0+LAS0_ACNT)
550 /* ADC sample counter, 10bit */
551 #define RtdAdcSampleCount(dev) \
552 readl(devpriv->las0+LAS0_ADC_SCNT)
553 #define RtdAdcSampleCounter(dev, v) \
554 writel((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT)
556 /* User Timer/Counter (8254) */
557 #define RtdUtcCounterGet(dev, n) \
558 readb(devpriv->las0 \
559 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
561 #define RtdUtcCounterPut(dev, n, v) \
562 writeb((v) & 0xff, devpriv->las0 \
563 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
565 /* Set UTC (8254) control byte */
566 #define RtdUtcCtrlPut(dev, n, v) \
567 writeb(devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \
568 devpriv->las0 + LAS0_UTC_CTRL)
570 /* Set UTCn clock source (write only) */
571 #define RtdUtcClockSource(dev, n, v) \
572 writew(v, devpriv->las0 \
573 + ((n <= 0) ? LAS0_UTC0_CLOCK : \
574 ((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK)))
576 /* Set UTCn gate source (write only) */
577 #define RtdUtcGateSource(dev, n, v) \
578 writew(v, devpriv->las0 \
579 + ((n <= 0) ? LAS0_UTC0_GATE : \
580 ((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE)))
582 /* User output N source select (write only) */
583 #define RtdUsrOutSource(dev, n, v) \
584 writel(v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : LAS0_UOUT1_SELECT))
587 #define RtdDio0Read(dev) \
588 (readw(devpriv->las0+LAS0_DIO0) & 0xff)
589 #define RtdDio0Write(dev, v) \
590 writew((v) & 0xff, devpriv->las0+LAS0_DIO0)
592 #define RtdDio1Read(dev) \
593 (readw(devpriv->las0+LAS0_DIO1) & 0xff)
594 #define RtdDio1Write(dev, v) \
595 writew((v) & 0xff, devpriv->las0+LAS0_DIO1)
597 #define RtdDioStatusRead(dev) \
598 (readw(devpriv->las0+LAS0_DIO_STATUS) & 0xff)
599 #define RtdDioStatusWrite(dev, v) \
600 writew((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
602 #define RtdDio0CtrlRead(dev) \
603 (readw(devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
604 #define RtdDio0CtrlWrite(dev, v) \
605 writew((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
607 /* Digital to Analog converter */
608 /* Write one data value (sign + 12bit + marker bits) */
609 /* Note: matches what DMA would put. Actual value << 3 */
610 #define RtdDacFifoPut(dev, n, v) \
611 writew((v), devpriv->las1 + (((n) == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO))
613 /* Start single DAC conversion */
614 #define RtdDacUpdate(dev, n) \
615 writew(0, devpriv->las0 + (((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
617 /* Start single DAC conversion on both DACs */
618 #define RtdDacBothUpdate(dev) \
619 writew(0, devpriv->las0+LAS0_DAC)
621 /* Set DAC output type and range */
622 #define RtdDacRange(dev, n, v) \
623 writew((v) & 7, devpriv->las0 \
624 +(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
627 #define RtdDacClearFifo(dev, n) \
628 writel(0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : LAS0_DAC2_RESET))
630 /* Set source for DMA 0 (write only, shadow?) */
631 #define RtdDma0Source(dev, n) \
632 writel((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
634 /* Set source for DMA 1 (write only, shadow?) */
635 #define RtdDma1Source(dev, n) \
636 writel((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
638 /* Reset board state for DMA 0 */
639 #define RtdDma0Reset(dev) \
640 writel(0, devpriv->las0+LAS0_DMA0_RESET)
642 /* Reset board state for DMA 1 */
643 #define RtdDma1Reset(dev) \
644 writel(0, devpriv->las0+LAS0_DMA1_SRC)
646 /* PLX9080 interrupt mask and status */
647 #define RtdPlxInterruptRead(dev) \
648 readl(devpriv->lcfg+LCFG_ITCSR)
649 #define RtdPlxInterruptWrite(dev, v) \
650 writel(v, devpriv->lcfg+LCFG_ITCSR)
652 /* Set mode for DMA 0 */
653 #define RtdDma0Mode(dev, m) \
654 writel((m), devpriv->lcfg+LCFG_DMAMODE0)
656 /* Set PCI address for DMA 0 */
657 #define RtdDma0PciAddr(dev, a) \
658 writel((a), devpriv->lcfg+LCFG_DMAPADR0)
660 /* Set local address for DMA 0 */
661 #define RtdDma0LocalAddr(dev, a) \
662 writel((a), devpriv->lcfg+LCFG_DMALADR0)
664 /* Set byte count for DMA 0 */
665 #define RtdDma0Count(dev, c) \
666 writel((c), devpriv->lcfg+LCFG_DMASIZ0)
668 /* Set next descriptor for DMA 0 */
669 #define RtdDma0Next(dev, a) \
670 writel((a), devpriv->lcfg+LCFG_DMADPR0)
672 /* Set mode for DMA 1 */
673 #define RtdDma1Mode(dev, m) \
674 writel((m), devpriv->lcfg+LCFG_DMAMODE1)
676 /* Set PCI address for DMA 1 */
677 #define RtdDma1PciAddr(dev, a) \
678 writel((a), devpriv->lcfg+LCFG_DMAADR1)
680 /* Set local address for DMA 1 */
681 #define RtdDma1LocalAddr(dev, a) \
682 writel((a), devpriv->lcfg+LCFG_DMALADR1)
684 /* Set byte count for DMA 1 */
685 #define RtdDma1Count(dev, c) \
686 writel((c), devpriv->lcfg+LCFG_DMASIZ1)
688 /* Set next descriptor for DMA 1 */
689 #define RtdDma1Next(dev, a) \
690 writel((a), devpriv->lcfg+LCFG_DMADPR1)
692 /* Set control for DMA 0 (write only, shadow?) */
693 #define RtdDma0Control(dev, n) \
694 writeb(devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
696 /* Get status for DMA 0 */
697 #define RtdDma0Status(dev) \
698 readb(devpriv->lcfg+LCFG_DMACSR0)
700 /* Set control for DMA 1 (write only, shadow?) */
701 #define RtdDma1Control(dev, n) \
702 writeb(devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1)
704 /* Get status for DMA 1 */
705 #define RtdDma1Status(dev) \
706 readb(devpriv->lcfg+LCFG_DMACSR1)
709 * The struct comedi_driver structure tells the Comedi core module
710 * which functions to call to configure/deconfigure (attac/detach)
711 * the board, and also about the kernel module that contains
714 static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it);
715 static int rtd_detach(struct comedi_device *dev);
717 static struct comedi_driver rtd520Driver = {
718 .driver_name = DRV_NAME,
719 .module = THIS_MODULE,
720 .attach = rtd_attach,
721 .detach = rtd_detach,
724 static int rtd_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
725 struct comedi_insn *insn, unsigned int *data);
726 static int rtd_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
727 struct comedi_insn *insn, unsigned int *data);
728 static int rtd_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
729 struct comedi_insn *insn, unsigned int *data);
730 static int rtd_dio_insn_bits(struct comedi_device *dev,
731 struct comedi_subdevice *s,
732 struct comedi_insn *insn, unsigned int *data);
733 static int rtd_dio_insn_config(struct comedi_device *dev,
734 struct comedi_subdevice *s,
735 struct comedi_insn *insn, unsigned int *data);
736 static int rtd_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
737 struct comedi_cmd *cmd);
738 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
739 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
740 /* static int rtd_ai_poll (struct comedi_device *dev,struct comedi_subdevice *s); */
741 static int rtd_ns_to_timer(unsigned int *ns, int roundMode);
742 static irqreturn_t rtd_interrupt(int irq, void *d);
743 static int rtd520_probe_fifo_depth(struct comedi_device *dev);
746 * Attach is called by the Comedi core to configure the driver
747 * for a particular board. If you specified a board_name array
748 * in the driver structure, dev->board_ptr contains that
751 static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
752 { /* board name and options flags */
753 struct comedi_subdevice *s;
754 struct pci_dev *pcidev;
756 resource_size_t physLas0; /* configuration */
757 resource_size_t physLas1; /* data area */
758 resource_size_t physLcfg; /* PLX9080 */
763 printk(KERN_INFO "comedi%d: rtd520 attaching.\n", dev->minor);
765 #if defined(CONFIG_COMEDI_DEBUG) && defined(USE_DMA)
766 /* You can set this a load time: modprobe comedi comedi_debug=1 */
767 if (0 == comedi_debug) /* force DMA debug printks */
772 * Allocate the private structure area. alloc_private() is a
773 * convenient macro defined in comedidev.h.
775 if (alloc_private(dev, sizeof(struct rtdPrivate)) < 0)
779 * Probe the device to determine what device in the series it is.
781 for (pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, NULL);
783 pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, pcidev)) {
786 if (it->options[0] || it->options[1]) {
787 if (pcidev->bus->number != it->options[0]
788 || PCI_SLOT(pcidev->devfn) != it->options[1]) {
792 for (i = 0; i < ARRAY_SIZE(rtd520Boards); ++i) {
793 if (pcidev->device == rtd520Boards[i].device_id) {
794 dev->board_ptr = &rtd520Boards[i];
799 break; /* found one */
802 if (it->options[0] && it->options[1]) {
803 printk(KERN_INFO "No RTD card at bus=%d slot=%d.\n",
804 it->options[0], it->options[1]);
806 printk(KERN_INFO "No RTD card found.\n");
810 devpriv->pci_dev = pcidev;
811 dev->board_name = thisboard->name;
813 ret = comedi_pci_enable(pcidev, DRV_NAME);
815 printk(KERN_INFO "Failed to enable PCI device and request regions.\n");
818 devpriv->got_regions = 1;
821 * Initialize base addresses
823 /* Get the physical address from PCI config */
824 physLas0 = pci_resource_start(devpriv->pci_dev, LAS0_PCIINDEX);
825 physLas1 = pci_resource_start(devpriv->pci_dev, LAS1_PCIINDEX);
826 physLcfg = pci_resource_start(devpriv->pci_dev, LCFG_PCIINDEX);
827 /* Now have the kernel map this into memory */
828 /* ASSUME page aligned */
829 devpriv->las0 = ioremap_nocache(physLas0, LAS0_PCISIZE);
830 devpriv->las1 = ioremap_nocache(physLas1, LAS1_PCISIZE);
831 devpriv->lcfg = ioremap_nocache(physLcfg, LCFG_PCISIZE);
833 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
837 DPRINTK("%s: LAS0=%llx, LAS1=%llx, CFG=%llx.\n", dev->board_name,
838 (unsigned long long)physLas0, (unsigned long long)physLas1,
839 (unsigned long long)physLcfg);
840 { /* The RTD driver does this */
841 unsigned char pci_latency;
843 /*uint32_t epld_version; */
845 pci_read_config_word(devpriv->pci_dev, PCI_REVISION_ID,
847 DPRINTK("%s: PCI revision %d.\n", dev->board_name, revision);
849 pci_read_config_byte(devpriv->pci_dev,
850 PCI_LATENCY_TIMER, &pci_latency);
851 if (pci_latency < 32) {
852 printk(KERN_INFO "%s: PCI latency changed from %d to %d\n",
853 dev->board_name, pci_latency, 32);
854 pci_write_config_byte(devpriv->pci_dev,
855 PCI_LATENCY_TIMER, 32);
857 DPRINTK("rtd520: PCI latency = %d\n", pci_latency);
860 /* Undocumented EPLD version (doesnt match RTD driver results) */
861 /*DPRINTK ("rtd520: Reading epld from %p\n",
863 epld_version = readl (devpriv->las0+0);
864 if ((epld_version & 0xF0) >> 4 == 0x0F) {
865 DPRINTK("rtd520: pre-v8 EPLD. (%x)\n", epld_version);
867 DPRINTK("rtd520: EPLD version %x.\n", epld_version >> 4);
871 /* Show board configuration */
872 printk("%s:", dev->board_name);
875 * Allocate the subdevice structures. alloc_subdevice() is a
876 * convenient macro defined in comedidev.h.
878 if (alloc_subdevices(dev, 4) < 0)
882 s = dev->subdevices + 0;
883 dev->read_subdev = s;
884 /* analog input subdevice */
885 s->type = COMEDI_SUBD_AI;
887 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
888 s->n_chan = thisboard->aiChans;
889 s->maxdata = (1 << thisboard->aiBits) - 1;
890 if (thisboard->aiMaxGain <= 32)
891 s->range_table = &rtd_ai_7520_range;
893 s->range_table = &rtd_ai_4520_range;
895 s->len_chanlist = RTD_MAX_CHANLIST; /* devpriv->fifoLen */
896 s->insn_read = rtd_ai_rinsn;
897 s->do_cmd = rtd_ai_cmd;
898 s->do_cmdtest = rtd_ai_cmdtest;
899 s->cancel = rtd_ai_cancel;
900 /* s->poll = rtd_ai_poll; *//* not ready yet */
902 s = dev->subdevices + 1;
903 /* analog output subdevice */
904 s->type = COMEDI_SUBD_AO;
905 s->subdev_flags = SDF_WRITABLE;
907 s->maxdata = (1 << thisboard->aiBits) - 1;
908 s->range_table = &rtd_ao_range;
909 s->insn_write = rtd_ao_winsn;
910 s->insn_read = rtd_ao_rinsn;
912 s = dev->subdevices + 2;
913 /* digital i/o subdevice */
914 s->type = COMEDI_SUBD_DIO;
915 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
916 /* we only support port 0 right now. Ignoring port 1 and user IO */
919 s->range_table = &range_digital;
920 s->insn_bits = rtd_dio_insn_bits;
921 s->insn_config = rtd_dio_insn_config;
923 /* timer/counter subdevices (not currently supported) */
924 s = dev->subdevices + 3;
925 s->type = COMEDI_SUBD_COUNTER;
926 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
930 /* initialize board, per RTD spec */
931 /* also, initialize shadow registers */
933 udelay(100); /* needed? */
934 RtdPlxInterruptWrite(dev, 0);
935 RtdInterruptMask(dev, 0); /* and sets shadow */
936 RtdInterruptClearMask(dev, ~0); /* and sets shadow */
937 RtdInterruptClear(dev); /* clears bits set by mask */
938 RtdInterruptOverrunClear(dev);
940 RtdAdcClearFifo(dev);
941 RtdDacClearFifo(dev, 0);
942 RtdDacClearFifo(dev, 1);
943 /* clear digital IO fifo */
944 RtdDioStatusWrite(dev, 0); /* safe state, set shadow */
945 RtdUtcCtrlPut(dev, 0, 0x30); /* safe state, set shadow */
946 RtdUtcCtrlPut(dev, 1, 0x30); /* safe state, set shadow */
947 RtdUtcCtrlPut(dev, 2, 0x30); /* safe state, set shadow */
948 RtdUtcCtrlPut(dev, 3, 0); /* safe state, set shadow */
949 /* TODO: set user out source ??? */
951 /* check if our interrupt is available and get it */
952 ret = request_irq(devpriv->pci_dev->irq, rtd_interrupt,
953 IRQF_SHARED, DRV_NAME, dev);
956 printk("Could not get interrupt! (%u)\n",
957 devpriv->pci_dev->irq);
960 dev->irq = devpriv->pci_dev->irq;
961 printk("( irq=%u )", dev->irq);
963 ret = rtd520_probe_fifo_depth(dev);
967 devpriv->fifoLen = ret;
968 printk("( fifoLen=%d )", devpriv->fifoLen);
972 printk("( DMA buff=%d )\n", DMA_CHAIN_COUNT);
973 /* The PLX9080 has 2 DMA controllers, but there could be 4 sources:
974 ADC, digital, DAC1, and DAC2. Since only the ADC supports cmd mode
975 right now, this isn't an issue (yet) */
976 devpriv->dma0Offset = 0;
978 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
979 devpriv->dma0Buff[index] =
980 pci_alloc_consistent(devpriv->pci_dev,
982 devpriv->fifoLen / 2,
984 dma0BuffPhysAddr[index]);
985 if (devpriv->dma0Buff[index] == NULL) {
987 goto rtd_attach_die_error;
989 /*DPRINTK ("buff[%d] @ %p virtual, %x PCI\n",
991 devpriv->dma0Buff[index], devpriv->dma0BuffPhysAddr[index]); */
994 /* setup DMA descriptor ring (use cpu_to_le32 for byte ordering?) */
996 pci_alloc_consistent(devpriv->pci_dev,
997 sizeof(struct plx_dma_desc) *
999 &devpriv->dma0ChainPhysAddr);
1000 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
1001 devpriv->dma0Chain[index].pci_start_addr =
1002 devpriv->dma0BuffPhysAddr[index];
1003 devpriv->dma0Chain[index].local_start_addr =
1005 devpriv->dma0Chain[index].transfer_size =
1006 sizeof(u16) * devpriv->fifoLen / 2;
1007 devpriv->dma0Chain[index].next =
1008 (devpriv->dma0ChainPhysAddr + ((index +
1011 * sizeof(devpriv->dma0Chain[0]))
1012 | DMA_TRANSFER_BITS;
1013 /*DPRINTK ("ring[%d] @%lx PCI: %x, local: %x, N: 0x%x, next: %x\n",
1015 ((long)devpriv->dma0ChainPhysAddr
1016 + (index * sizeof(devpriv->dma0Chain[0]))),
1017 devpriv->dma0Chain[index].pci_start_addr,
1018 devpriv->dma0Chain[index].local_start_addr,
1019 devpriv->dma0Chain[index].transfer_size,
1020 devpriv->dma0Chain[index].next); */
1023 if (devpriv->dma0Chain == NULL) {
1025 goto rtd_attach_die_error;
1028 RtdDma0Mode(dev, DMA_MODE_BITS);
1029 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
1031 printk(KERN_INFO "( no IRQ->no DMA )");
1033 #endif /* USE_DMA */
1035 if (dev->irq) { /* enable plx9080 interrupts */
1036 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
1039 printk("\ncomedi%d: rtd520 driver attached.\n", dev->minor);
1044 /* hit an error, clean up memory and return ret */
1045 /* rtd_attach_die_error: */
1047 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
1048 if (NULL != devpriv->dma0Buff[index]) { /* free buffer memory */
1049 pci_free_consistent(devpriv->pci_dev,
1050 sizeof(u16) * devpriv->fifoLen / 2,
1051 devpriv->dma0Buff[index],
1052 devpriv->dma0BuffPhysAddr[index]);
1053 devpriv->dma0Buff[index] = NULL;
1056 if (NULL != devpriv->dma0Chain) {
1057 pci_free_consistent(devpriv->pci_dev,
1058 sizeof(struct plx_dma_desc)
1061 devpriv->dma0ChainPhysAddr);
1062 devpriv->dma0Chain = NULL;
1064 #endif /* USE_DMA */
1065 /* subdevices and priv are freed by the core */
1067 /* disable interrupt controller */
1068 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
1069 & ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E));
1070 free_irq(dev->irq, dev);
1073 /* release all regions that were allocated */
1075 iounmap(devpriv->las0);
1078 iounmap(devpriv->las1);
1081 iounmap(devpriv->lcfg);
1083 if (devpriv->pci_dev)
1084 pci_dev_put(devpriv->pci_dev);
1091 * _detach is called to deconfigure a device. It should deallocate
1093 * This function is also called when _attach() fails, so it should be
1094 * careful not to release resources that were not necessarily
1095 * allocated by _attach(). dev->private and dev->subdevices are
1096 * deallocated automatically by the core.
1098 static int rtd_detach(struct comedi_device *dev)
1104 DPRINTK("comedi%d: rtd520: removing (%ld ints)\n",
1105 dev->minor, (devpriv ? devpriv->intCount : 0L));
1106 if (devpriv && devpriv->lcfg) {
1108 ("(int status 0x%x, overrun status 0x%x, fifo status 0x%x)...\n",
1109 0xffff & RtdInterruptStatus(dev),
1110 0xffff & RtdInterruptOverrunStatus(dev),
1111 (0xffff & RtdFifoStatus(dev)) ^ 0x6666);
1115 /* Shut down any board ops by resetting it */
1117 if (devpriv->lcfg) {
1118 RtdDma0Control(dev, 0); /* disable DMA */
1119 RtdDma1Control(dev, 0); /* disable DMA */
1120 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
1122 #endif /* USE_DMA */
1123 if (devpriv->las0) {
1125 RtdInterruptMask(dev, 0);
1126 RtdInterruptClearMask(dev, ~0);
1127 RtdInterruptClear(dev); /* clears bits set by mask */
1131 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
1132 if (NULL != devpriv->dma0Buff[index]) {
1133 pci_free_consistent(devpriv->pci_dev,
1135 devpriv->fifoLen / 2,
1136 devpriv->dma0Buff[index],
1138 dma0BuffPhysAddr[index]);
1139 devpriv->dma0Buff[index] = NULL;
1142 if (NULL != devpriv->dma0Chain) {
1143 pci_free_consistent(devpriv->pci_dev,
1144 sizeof(struct plx_dma_desc) *
1145 DMA_CHAIN_COUNT, devpriv->dma0Chain,
1146 devpriv->dma0ChainPhysAddr);
1147 devpriv->dma0Chain = NULL;
1149 #endif /* USE_DMA */
1153 /* disable interrupt controller */
1154 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
1155 & ~(ICS_PLIE | ICS_DMA0_E |
1157 free_irq(dev->irq, dev);
1160 /* release all regions that were allocated */
1162 iounmap(devpriv->las0);
1165 iounmap(devpriv->las1);
1168 iounmap(devpriv->lcfg);
1170 if (devpriv->pci_dev) {
1171 if (devpriv->got_regions)
1172 comedi_pci_disable(devpriv->pci_dev);
1174 pci_dev_put(devpriv->pci_dev);
1178 printk(KERN_INFO "comedi%d: rtd520: removed.\n", dev->minor);
1184 Convert a single comedi channel-gain entry to a RTD520 table entry
1186 static unsigned short rtdConvertChanGain(struct comedi_device *dev,
1187 unsigned int comediChan, int chanIndex)
1188 { /* index in channel list */
1189 unsigned int chan, range, aref;
1190 unsigned short r = 0;
1192 chan = CR_CHAN(comediChan);
1193 range = CR_RANGE(comediChan);
1194 aref = CR_AREF(comediChan);
1198 /* Note: we also setup the channel list bipolar flag array */
1199 if (range < thisboard->range10Start) { /* first batch are +-5 */
1200 r |= 0x000; /* +-5 range */
1201 r |= (range & 0x7) << 4; /* gain */
1202 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
1203 } else if (range < thisboard->rangeUniStart) { /* second batch are +-10 */
1204 r |= 0x100; /* +-10 range */
1205 r |= ((range - thisboard->range10Start) & 0x7) << 4; /* gain */
1206 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
1207 } else { /* last batch is +10 */
1208 r |= 0x200; /* +10 range */
1209 r |= ((range - thisboard->rangeUniStart) & 0x7) << 4; /* gain */
1210 CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
1214 case AREF_GROUND: /* on-board ground */
1218 r |= 0x80; /* ref external analog common */
1222 r |= 0x400; /* differential inputs */
1225 case AREF_OTHER: /* ??? */
1228 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
1229 chan, range, aref, r); */
1234 Setup the channel-gain table from a comedi list
1236 static void rtd_load_channelgain_list(struct comedi_device *dev,
1237 unsigned int n_chan, unsigned int *list)
1239 if (n_chan > 1) { /* setup channel gain table */
1242 RtdEnableCGT(dev, 1); /* enable table */
1243 for (ii = 0; ii < n_chan; ii++) {
1244 RtdWriteCGTable(dev, rtdConvertChanGain(dev, list[ii],
1247 } else { /* just use the channel gain latch */
1248 RtdEnableCGT(dev, 0); /* disable table, enable latch */
1249 RtdWriteCGLatch(dev, rtdConvertChanGain(dev, list[0], 0));
1253 /* determine fifo size by doing adc conversions until the fifo half
1254 empty status flag clears */
1255 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
1257 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
1259 static const unsigned limit = 0x2000;
1260 unsigned fifo_size = 0;
1262 RtdAdcClearFifo(dev);
1263 rtd_load_channelgain_list(dev, 1, &chanspec);
1264 RtdAdcConversionSource(dev, 0); /* software */
1265 /* convert samples */
1266 for (i = 0; i < limit; ++i) {
1267 unsigned fifo_status;
1268 /* trigger conversion */
1271 fifo_status = RtdFifoStatus(dev);
1272 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
1278 printk(KERN_INFO "\ncomedi: %s: failed to probe fifo size.\n", DRV_NAME);
1281 RtdAdcClearFifo(dev);
1282 if (fifo_size != 0x400 && fifo_size != 0x2000) {
1284 (KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
1285 DRV_NAME, fifo_size);
1292 "instructions" read/write data in "one-shot" or "software-triggered"
1293 mode (simplest case).
1294 This doesnt use interrupts.
1296 Note, we don't do any settling delays. Use a instruction list to
1297 select, delay, then read.
1299 static int rtd_ai_rinsn(struct comedi_device *dev,
1300 struct comedi_subdevice *s, struct comedi_insn *insn,
1306 /* clear any old fifo data */
1307 RtdAdcClearFifo(dev);
1309 /* write channel to multiplexer and clear channel gain table */
1310 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
1312 /* set conversion source */
1313 RtdAdcConversionSource(dev, 0); /* software */
1315 /* convert n samples */
1316 for (n = 0; n < insn->n; n++) {
1318 /* trigger conversion */
1321 for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
1322 stat = RtdFifoStatus(dev);
1323 if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
1327 if (ii >= RTD_ADC_TIMEOUT) {
1329 ("rtd520: Error: ADC never finished! FifoStatus=0x%x\n",
1335 d = RtdAdcFifoGet(dev); /* get 2s comp value */
1336 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
1337 d = d >> 3; /* low 3 bits are marker lines */
1338 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
1339 data[n] = d + 2048; /* convert to comedi unsigned data */
1344 /* return the number of samples read/written */
1349 Get what we know is there.... Fast!
1350 This uses 1/2 the bus cycles of read_dregs (below).
1352 The manual claims that we can do a lword read, but it doesn't work here.
1354 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
1359 for (ii = 0; ii < count; ii++) {
1363 if (0 == devpriv->aiCount) { /* done */
1364 d = RtdAdcFifoGet(dev); /* Read N and discard */
1368 if (0 == (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY)) { /* DEBUG */
1369 DPRINTK("comedi: READ OOPS on %d of %d\n", ii + 1,
1374 d = RtdAdcFifoGet(dev); /* get 2s comp value */
1376 d = d >> 3; /* low 3 bits are marker lines */
1377 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan))
1378 sample = d + 2048; /* convert to comedi unsigned data */
1382 if (!comedi_buf_put(s->async, sample))
1385 if (devpriv->aiCount > 0) /* < 0, means read forever */
1392 unknown amout of data is waiting in fifo.
1394 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
1396 while (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
1398 s16 d = RtdAdcFifoGet(dev); /* get 2s comp value */
1400 if (0 == devpriv->aiCount) { /* done */
1401 continue; /* read rest */
1404 d = d >> 3; /* low 3 bits are marker lines */
1405 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan))
1406 sample = d + 2048; /* convert to comedi unsigned data */
1410 if (!comedi_buf_put(s->async, sample))
1413 if (devpriv->aiCount > 0) /* < 0, means read forever */
1421 Terminate a DMA transfer and wait for everything to quiet down
1423 void abort_dma(struct comedi_device *dev, unsigned int channel)
1424 { /* DMA channel 0, 1 */
1425 unsigned long dma_cs_addr; /* the control/status register */
1428 /* unsigned long flags; */
1430 dma_cs_addr = (unsigned long)devpriv->lcfg
1431 + ((channel == 0) ? LCFG_DMACSR0 : LCFG_DMACSR1);
1433 /* spinlock for plx dma control/status reg */
1434 /* spin_lock_irqsave( &dev->spinlock, flags ); */
1436 /* abort dma transfer if necessary */
1437 status = readb(dma_cs_addr);
1438 if ((status & PLX_DMA_EN_BIT) == 0) { /* not enabled (Error?) */
1439 DPRINTK("rtd520: AbortDma on non-active channel %d (0x%x)\n",
1444 /* wait to make sure done bit is zero (needed?) */
1445 for (ii = 0; (status & PLX_DMA_DONE_BIT) && ii < RTD_DMA_TIMEOUT; ii++) {
1447 status = readb(dma_cs_addr);
1449 if (status & PLX_DMA_DONE_BIT) {
1450 printk("rtd520: Timeout waiting for dma %i done clear\n",
1455 /* disable channel (required) */
1456 writeb(0, dma_cs_addr);
1457 udelay(1); /* needed?? */
1458 /* set abort bit for channel */
1459 writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
1461 /* wait for dma done bit to be set */
1462 status = readb(dma_cs_addr);
1464 (status & PLX_DMA_DONE_BIT) == 0 && ii < RTD_DMA_TIMEOUT; ii++) {
1465 status = readb(dma_cs_addr);
1468 if ((status & PLX_DMA_DONE_BIT) == 0) {
1469 printk("rtd520: Timeout waiting for dma %i done set\n",
1474 /* spin_unlock_irqrestore( &dev->spinlock, flags ); */
1478 Process what is in the DMA transfer buffer and pass to comedi
1479 Note: this is not re-entrant
1481 static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s)
1486 if (devpriv->aiCount == 0) /* transfer already complete */
1489 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1490 for (ii = 0; ii < devpriv->fifoLen / 2;) { /* convert samples */
1493 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
1494 sample = (*dp >> 3) + 2048; /* convert to comedi unsigned data */
1496 sample = *dp >> 3; /* low 3 bits are marker lines */
1498 *dp++ = sample; /* put processed value back */
1500 if (++s->async->cur_chan >= s->async->cmd.chanlist_len)
1501 s->async->cur_chan = 0;
1503 ++ii; /* number ready to transfer */
1504 if (devpriv->aiCount > 0) { /* < 0, means read forever */
1505 if (--devpriv->aiCount == 0) { /* done */
1506 /*DPRINTK ("rtd520: Final %d samples\n", ii); */
1512 /* now pass the whole array to the comedi buffer */
1513 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1514 n = comedi_buf_write_alloc(s->async, ii * sizeof(s16));
1515 if (n < (ii * sizeof(s16))) { /* any residual is an error */
1516 DPRINTK("rtd520:ai_process_dma buffer overflow %d samples!\n",
1517 ii - (n / sizeof(s16)));
1518 s->async->events |= COMEDI_CB_ERROR;
1521 comedi_buf_memcpy_to(s->async, 0, dp, n);
1522 comedi_buf_write_free(s->async, n);
1524 /* always at least 1 scan -- 1/2 FIFO is larger than our max scan list */
1525 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
1527 if (++devpriv->dma0Offset >= DMA_CHAIN_COUNT) { /* next buffer */
1528 devpriv->dma0Offset = 0;
1532 #endif /* USE_DMA */
1535 Handle all rtd520 interrupts.
1536 Runs atomically and is never re-entered.
1537 This is a "slow handler"; other interrupts may be active.
1538 The data conversion may someday happen in a "bottom half".
1540 static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
1542 { /* our data *//* cpu context (ignored) */
1543 struct comedi_device *dev = d; /* must be called "dev" for devpriv */
1546 struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
1551 devpriv->intCount++; /* DEBUG statistics */
1553 fifoStatus = RtdFifoStatus(dev);
1554 /* check for FIFO full, this automatically halts the ADC! */
1555 if (!(fifoStatus & FS_ADC_NOT_FULL)) { /* 0 -> full */
1556 DPRINTK("rtd520: FIFO full! fifo_status=0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1560 if (devpriv->flags & DMA0_ACTIVE) { /* Check DMA */
1561 u32 istatus = RtdPlxInterruptRead(dev);
1563 if (istatus & ICS_DMA0_A) {
1564 if (ai_process_dma(dev, s) < 0) {
1566 ("rtd520: comedi read buffer overflow (DMA) with %ld to go!\n",
1569 (devpriv->dma0Control &
1571 | PLX_CLEAR_DMA_INTR_BIT);
1575 /*DPRINTK ("rtd520: DMA transfer: %ld to go, istatus %x\n",
1576 devpriv->aiCount, istatus); */
1579 dma0Control & ~PLX_DMA_START_BIT)
1580 | PLX_CLEAR_DMA_INTR_BIT);
1581 if (0 == devpriv->aiCount) { /* counted down */
1582 DPRINTK("rtd520: Samples Done (DMA).\n");
1585 comedi_event(dev, s);
1587 /*DPRINTK ("rtd520: No DMA ready: istatus %x\n", istatus); */
1590 /* Fall through and check for other interrupt sources */
1591 #endif /* USE_DMA */
1593 status = RtdInterruptStatus(dev);
1594 /* if interrupt was not caused by our board, or handled above */
1598 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
1599 /* since the priority interrupt controller may have queued a sample
1600 counter interrupt, even though we have already finished,
1601 we must handle the possibility that there is no data here */
1602 if (!(fifoStatus & FS_ADC_HEMPTY)) { /* 0 -> 1/2 full */
1603 /*DPRINTK("rtd520: Sample int, reading 1/2FIFO. fifo_status 0x%x\n",
1604 (fifoStatus ^ 0x6666) & 0x7777); */
1605 if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0) {
1607 ("rtd520: comedi read buffer overflow (1/2FIFO) with %ld to go!\n",
1611 if (0 == devpriv->aiCount) { /* counted down */
1612 DPRINTK("rtd520: Samples Done (1/2). fifo_status was 0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1615 comedi_event(dev, s);
1616 } else if (devpriv->transCount > 0) { /* read often */
1617 /*DPRINTK("rtd520: Sample int, reading %d fifo_status 0x%x\n",
1618 devpriv->transCount, (fifoStatus ^ 0x6666) & 0x7777); */
1619 if (fifoStatus & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
1620 if (ai_read_n(dev, s, devpriv->transCount) < 0) {
1622 ("rtd520: comedi read buffer overflow (N) with %ld to go!\n",
1626 if (0 == devpriv->aiCount) { /* counted down */
1628 ("rtd520: Samples Done (N). fifo_status was 0x%x\n",
1629 (fifoStatus ^ 0x6666) & 0x7777);
1632 comedi_event(dev, s);
1634 } else { /* wait for 1/2 FIFO (old) */
1636 ("rtd520: Sample int. Wait for 1/2. fifo_status 0x%x\n",
1637 (fifoStatus ^ 0x6666) & 0x7777);
1640 DPRINTK("rtd520: unknown interrupt source!\n");
1643 if (0xffff & RtdInterruptOverrunStatus(dev)) { /* interrupt overrun */
1645 ("rtd520: Interrupt overrun with %ld to go! over_status=0x%x\n",
1646 devpriv->aiCount, 0xffff & RtdInterruptOverrunStatus(dev));
1650 /* clear the interrupt */
1651 RtdInterruptClearMask(dev, status);
1652 RtdInterruptClear(dev);
1656 RtdAdcClearFifo(dev); /* clears full flag */
1657 s->async->events |= COMEDI_CB_ERROR;
1658 devpriv->aiCount = 0; /* stop and don't transfer any more */
1659 /* fall into transferDone */
1662 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
1663 RtdPacerStop(dev); /* Stop PACER */
1664 RtdAdcConversionSource(dev, 0); /* software trigger only */
1665 RtdInterruptMask(dev, 0); /* mask out SAMPLE */
1667 if (devpriv->flags & DMA0_ACTIVE) {
1668 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1669 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1671 devpriv->flags &= ~DMA0_ACTIVE;
1672 /* if Using DMA, then we should have read everything by now */
1673 if (devpriv->aiCount > 0) {
1674 DPRINTK("rtd520: Lost DMA data! %ld remain\n",
1678 #endif /* USE_DMA */
1680 if (devpriv->aiCount > 0) { /* there shouldn't be anything left */
1681 fifoStatus = RtdFifoStatus(dev);
1682 DPRINTK("rtd520: Finishing up. %ld remain, fifoStat=%x\n", devpriv->aiCount, (fifoStatus ^ 0x6666) & 0x7777); /* should read all 0s */
1683 ai_read_dregs(dev, s); /* read anything left in FIFO */
1686 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
1687 comedi_event(dev, s);
1689 /* clear the interrupt */
1690 status = RtdInterruptStatus(dev);
1691 RtdInterruptClearMask(dev, status);
1692 RtdInterruptClear(dev);
1694 fifoStatus = RtdFifoStatus(dev); /* DEBUG */
1696 ("rtd520: Acquisition complete. %ld ints, intStat=%x, overStat=%x\n",
1697 devpriv->intCount, status,
1698 0xffff & RtdInterruptOverrunStatus(dev));
1705 return the number of samples available
1707 static int rtd_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1709 /* TODO: This needs to mask interrupts, read_dregs, and then re-enable */
1710 /* Not sure what to do if DMA is active */
1711 return s->async->buf_write_count - s->async->buf_read_count;
1716 cmdtest tests a particular command to see if it is valid.
1717 Using the cmdtest ioctl, a user can create a valid cmd
1718 and then have it executed by the cmd ioctl (asyncronously).
1720 cmdtest returns 1,2,3,4 or 0, depending on which tests
1724 static int rtd_ai_cmdtest(struct comedi_device *dev,
1725 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1730 /* step 1: make sure trigger sources are trivially valid */
1732 tmp = cmd->start_src;
1733 cmd->start_src &= TRIG_NOW;
1734 if (!cmd->start_src || tmp != cmd->start_src)
1737 tmp = cmd->scan_begin_src;
1738 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
1739 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1743 tmp = cmd->convert_src;
1744 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1745 if (!cmd->convert_src || tmp != cmd->convert_src)
1749 tmp = cmd->scan_end_src;
1750 cmd->scan_end_src &= TRIG_COUNT;
1751 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1755 tmp = cmd->stop_src;
1756 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1757 if (!cmd->stop_src || tmp != cmd->stop_src)
1764 /* step 2: make sure trigger sources are unique
1765 and mutually compatible */
1766 /* note that mutual compatibility is not an issue here */
1767 if (cmd->scan_begin_src != TRIG_TIMER &&
1768 cmd->scan_begin_src != TRIG_EXT) {
1771 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1774 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1780 /* step 3: make sure arguments are trivially compatible */
1782 if (cmd->start_arg != 0) {
1787 if (cmd->scan_begin_src == TRIG_TIMER) {
1788 /* Note: these are time periods, not actual rates */
1789 if (1 == cmd->chanlist_len) { /* no scanning */
1790 if (cmd->scan_begin_arg < RTD_MAX_SPEED_1) {
1791 cmd->scan_begin_arg = RTD_MAX_SPEED_1;
1792 rtd_ns_to_timer(&cmd->scan_begin_arg,
1796 if (cmd->scan_begin_arg > RTD_MIN_SPEED_1) {
1797 cmd->scan_begin_arg = RTD_MIN_SPEED_1;
1798 rtd_ns_to_timer(&cmd->scan_begin_arg,
1803 if (cmd->scan_begin_arg < RTD_MAX_SPEED) {
1804 cmd->scan_begin_arg = RTD_MAX_SPEED;
1805 rtd_ns_to_timer(&cmd->scan_begin_arg,
1809 if (cmd->scan_begin_arg > RTD_MIN_SPEED) {
1810 cmd->scan_begin_arg = RTD_MIN_SPEED;
1811 rtd_ns_to_timer(&cmd->scan_begin_arg,
1817 /* external trigger */
1818 /* should be level/edge, hi/lo specification here */
1819 /* should specify multiple external triggers */
1820 if (cmd->scan_begin_arg > 9) {
1821 cmd->scan_begin_arg = 9;
1825 if (cmd->convert_src == TRIG_TIMER) {
1826 if (1 == cmd->chanlist_len) { /* no scanning */
1827 if (cmd->convert_arg < RTD_MAX_SPEED_1) {
1828 cmd->convert_arg = RTD_MAX_SPEED_1;
1829 rtd_ns_to_timer(&cmd->convert_arg,
1833 if (cmd->convert_arg > RTD_MIN_SPEED_1) {
1834 cmd->convert_arg = RTD_MIN_SPEED_1;
1835 rtd_ns_to_timer(&cmd->convert_arg,
1840 if (cmd->convert_arg < RTD_MAX_SPEED) {
1841 cmd->convert_arg = RTD_MAX_SPEED;
1842 rtd_ns_to_timer(&cmd->convert_arg,
1846 if (cmd->convert_arg > RTD_MIN_SPEED) {
1847 cmd->convert_arg = RTD_MIN_SPEED;
1848 rtd_ns_to_timer(&cmd->convert_arg,
1854 /* external trigger */
1856 if (cmd->convert_arg > 9) {
1857 cmd->convert_arg = 9;
1863 if (cmd->scan_end_arg != cmd->chanlist_len) {
1864 cmd->scan_end_arg = cmd->chanlist_len;
1868 if (cmd->stop_src == TRIG_COUNT) {
1869 /* TODO check for rounding error due to counter wrap */
1873 if (cmd->stop_arg != 0) {
1883 /* step 4: fix up any arguments */
1885 if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
1886 cmd->chanlist_len = RTD_MAX_CHANLIST;
1889 if (cmd->scan_begin_src == TRIG_TIMER) {
1890 tmp = cmd->scan_begin_arg;
1891 rtd_ns_to_timer(&cmd->scan_begin_arg,
1892 cmd->flags & TRIG_ROUND_MASK);
1893 if (tmp != cmd->scan_begin_arg)
1897 if (cmd->convert_src == TRIG_TIMER) {
1898 tmp = cmd->convert_arg;
1899 rtd_ns_to_timer(&cmd->convert_arg,
1900 cmd->flags & TRIG_ROUND_MASK);
1901 if (tmp != cmd->convert_arg)
1904 if (cmd->scan_begin_src == TRIG_TIMER
1905 && (cmd->scan_begin_arg
1906 < (cmd->convert_arg * cmd->scan_end_arg))) {
1907 cmd->scan_begin_arg =
1908 cmd->convert_arg * cmd->scan_end_arg;
1920 Execute a analog in command with many possible triggering options.
1921 The data get stored in the async structure of the subdevice.
1922 This is usually done by an interrupt handler.
1923 Userland gets to the data using read calls.
1925 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1927 struct comedi_cmd *cmd = &s->async->cmd;
1930 /* stop anything currently running */
1931 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
1932 RtdPacerStop(dev); /* make sure PACER is stopped */
1933 RtdAdcConversionSource(dev, 0); /* software trigger only */
1934 RtdInterruptMask(dev, 0);
1936 if (devpriv->flags & DMA0_ACTIVE) { /* cancel anything running */
1937 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1938 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1940 devpriv->flags &= ~DMA0_ACTIVE;
1941 if (RtdPlxInterruptRead(dev) & ICS_DMA0_A) { /*clear pending int */
1942 RtdDma0Control(dev, PLX_CLEAR_DMA_INTR_BIT);
1945 RtdDma0Reset(dev); /* reset onboard state */
1946 #endif /* USE_DMA */
1947 RtdAdcClearFifo(dev); /* clear any old data */
1948 RtdInterruptOverrunClear(dev);
1949 devpriv->intCount = 0;
1951 if (!dev->irq) { /* we need interrupts for this */
1952 DPRINTK("rtd520: ERROR! No interrupt available!\n");
1956 /* start configuration */
1957 /* load channel list and reset CGT */
1958 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
1960 /* setup the common case and override if needed */
1961 if (cmd->chanlist_len > 1) {
1962 /*DPRINTK ("rtd520: Multi channel setup\n"); */
1963 RtdPacerStartSource(dev, 0); /* software triggers pacer */
1964 RtdBurstStartSource(dev, 1); /* PACER triggers burst */
1965 RtdAdcConversionSource(dev, 2); /* BURST triggers ADC */
1966 } else { /* single channel */
1967 /*DPRINTK ("rtd520: single channel setup\n"); */
1968 RtdPacerStartSource(dev, 0); /* software triggers pacer */
1969 RtdAdcConversionSource(dev, 1); /* PACER triggers ADC */
1971 RtdAboutCounter(dev, devpriv->fifoLen / 2 - 1); /* 1/2 FIFO */
1973 if (TRIG_TIMER == cmd->scan_begin_src) {
1974 /* scan_begin_arg is in nanoseconds */
1975 /* find out how many samples to wait before transferring */
1976 if (cmd->flags & TRIG_WAKE_EOS) {
1977 /* this may generate un-sustainable interrupt rates */
1978 /* the application is responsible for doing the right thing */
1979 devpriv->transCount = cmd->chanlist_len;
1980 devpriv->flags |= SEND_EOS;
1982 /* arrange to transfer data periodically */
1985 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
1986 cmd->scan_begin_arg;
1987 if (devpriv->transCount < cmd->chanlist_len) {
1988 /* tranfer after each scan (and avoid 0) */
1989 devpriv->transCount = cmd->chanlist_len;
1990 } else { /* make a multiple of scan length */
1991 devpriv->transCount =
1992 (devpriv->transCount +
1993 cmd->chanlist_len - 1)
1994 / cmd->chanlist_len;
1995 devpriv->transCount *= cmd->chanlist_len;
1997 devpriv->flags |= SEND_EOS;
1999 if (devpriv->transCount >= (devpriv->fifoLen / 2)) {
2000 /* out of counter range, use 1/2 fifo instead */
2001 devpriv->transCount = 0;
2002 devpriv->flags &= ~SEND_EOS;
2004 /* interrupt for each tranfer */
2005 RtdAboutCounter(dev, devpriv->transCount - 1);
2009 ("rtd520: scanLen=%d tranferCount=%d fifoLen=%d\n scanTime(ns)=%d flags=0x%x\n",
2010 cmd->chanlist_len, devpriv->transCount, devpriv->fifoLen,
2011 cmd->scan_begin_arg, devpriv->flags);
2012 } else { /* unknown timing, just use 1/2 FIFO */
2013 devpriv->transCount = 0;
2014 devpriv->flags &= ~SEND_EOS;
2016 RtdPacerClockSource(dev, 1); /* use INTERNAL 8Mhz clock source */
2017 RtdAboutStopEnable(dev, 1); /* just interrupt, dont stop */
2019 /* BUG??? these look like enumerated values, but they are bit fields */
2021 /* First, setup when to stop */
2022 switch (cmd->stop_src) {
2023 case TRIG_COUNT: /* stop after N scans */
2024 devpriv->aiCount = cmd->stop_arg * cmd->chanlist_len;
2025 if ((devpriv->transCount > 0)
2026 && (devpriv->transCount > devpriv->aiCount)) {
2027 devpriv->transCount = devpriv->aiCount;
2031 case TRIG_NONE: /* stop when cancel is called */
2032 devpriv->aiCount = -1; /* read forever */
2036 DPRINTK("rtd520: Warning! ignoring stop_src mode %d\n",
2041 switch (cmd->scan_begin_src) {
2042 case TRIG_TIMER: /* periodic scanning */
2043 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
2044 TRIG_ROUND_NEAREST);
2045 /* set PACER clock */
2046 /*DPRINTK ("rtd520: loading %d into pacer\n", timer); */
2047 RtdPacerCounter(dev, timer);
2052 RtdPacerStartSource(dev, 1); /* EXTERNALy trigger pacer */
2056 DPRINTK("rtd520: Warning! ignoring scan_begin_src mode %d\n",
2057 cmd->scan_begin_src);
2060 /* Sample timing within a scan */
2061 switch (cmd->convert_src) {
2062 case TRIG_TIMER: /* periodic */
2063 if (cmd->chanlist_len > 1) { /* only needed for multi-channel */
2064 timer = rtd_ns_to_timer(&cmd->convert_arg,
2065 TRIG_ROUND_NEAREST);
2066 /* setup BURST clock */
2067 /*DPRINTK ("rtd520: loading %d into burst\n", timer); */
2068 RtdBurstCounter(dev, timer);
2073 case TRIG_EXT: /* external */
2074 RtdBurstStartSource(dev, 2); /* EXTERNALy trigger burst */
2078 DPRINTK("rtd520: Warning! ignoring convert_src mode %d\n",
2081 /* end configuration */
2083 /* This doesn't seem to work. There is no way to clear an interrupt
2084 that the priority controller has queued! */
2085 RtdInterruptClearMask(dev, ~0); /* clear any existing flags */
2086 RtdInterruptClear(dev);
2088 /* TODO: allow multiple interrupt sources */
2089 if (devpriv->transCount > 0) { /* transfer every N samples */
2090 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
2091 DPRINTK("rtd520: Transferring every %d\n", devpriv->transCount);
2092 } else { /* 1/2 FIFO transfers */
2094 devpriv->flags |= DMA0_ACTIVE;
2096 /* point to first transfer in ring */
2097 devpriv->dma0Offset = 0;
2098 RtdDma0Mode(dev, DMA_MODE_BITS);
2099 RtdDma0Next(dev, /* point to first block */
2100 devpriv->dma0Chain[DMA_CHAIN_COUNT - 1].next);
2101 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
2103 RtdPlxInterruptWrite(dev, /* enable interrupt */
2104 RtdPlxInterruptRead(dev) | ICS_DMA0_E);
2105 /* Must be 2 steps. See PLX app note about "Starting a DMA transfer" */
2106 RtdDma0Control(dev, PLX_DMA_EN_BIT); /* enable DMA (clear INTR?) */
2107 RtdDma0Control(dev, PLX_DMA_EN_BIT | PLX_DMA_START_BIT); /*start DMA */
2108 DPRINTK("rtd520: Using DMA0 transfers. plxInt %x RtdInt %x\n",
2109 RtdPlxInterruptRead(dev), devpriv->intMask);
2111 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
2112 DPRINTK("rtd520: Transferring every 1/2 FIFO\n");
2113 #endif /* USE_DMA */
2116 /* BUG: start_src is ASSUMED to be TRIG_NOW */
2117 /* BUG? it seems like things are running before the "start" */
2118 RtdPacerStart(dev); /* Start PACER */
2123 Stop a running data aquisition.
2125 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2129 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
2130 RtdPacerStop(dev); /* Stop PACER */
2131 RtdAdcConversionSource(dev, 0); /* software trigger only */
2132 RtdInterruptMask(dev, 0);
2133 devpriv->aiCount = 0; /* stop and don't transfer any more */
2135 if (devpriv->flags & DMA0_ACTIVE) {
2136 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
2137 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
2139 devpriv->flags &= ~DMA0_ACTIVE;
2141 #endif /* USE_DMA */
2142 status = RtdInterruptStatus(dev);
2144 ("rtd520: Acquisition canceled. %ld ints, intStat=%x, overStat=%x\n",
2145 devpriv->intCount, status,
2146 0xffff & RtdInterruptOverrunStatus(dev));
2151 Given a desired period and the clock period (both in ns),
2152 return the proper counter value (divider-1).
2153 Sets the original period to be the true value.
2154 Note: you have to check if the value is larger than the counter range!
2156 static int rtd_ns_to_timer_base(unsigned int *nanosec, /* desired period (in ns) */
2157 int round_mode, int base)
2158 { /* clock period (in ns) */
2161 switch (round_mode) {
2162 case TRIG_ROUND_NEAREST:
2164 divider = (*nanosec + base / 2) / base;
2166 case TRIG_ROUND_DOWN:
2167 divider = (*nanosec) / base;
2170 divider = (*nanosec + base - 1) / base;
2174 divider = 2; /* min is divide by 2 */
2176 /* Note: we don't check for max, because different timers
2177 have different ranges */
2179 *nanosec = base * divider;
2180 return divider - 1; /* countdown is divisor+1 */
2184 Given a desired period (in ns),
2185 return the proper counter value (divider-1) for the internal clock.
2186 Sets the original period to be the true value.
2188 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
2190 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
2194 Output one (or more) analog values to a single port as fast as possible.
2196 static int rtd_ao_winsn(struct comedi_device *dev,
2197 struct comedi_subdevice *s, struct comedi_insn *insn,
2201 int chan = CR_CHAN(insn->chanspec);
2202 int range = CR_RANGE(insn->chanspec);
2204 /* Configure the output range (table index matches the range values) */
2205 RtdDacRange(dev, chan, range);
2207 /* Writing a list of values to an AO channel is probably not
2208 * very useful, but that's how the interface is defined. */
2209 for (i = 0; i < insn->n; ++i) {
2210 int val = data[i] << 3;
2211 int stat = 0; /* initialize to avoid bogus warning */
2214 /* VERIFY: comedi range and offset conversions */
2216 if ((range > 1) /* bipolar */
2217 && (data[i] < 2048)) {
2218 /* offset and sign extend */
2219 val = (((int)data[i]) - 2048) << 3;
2220 } else { /* unipolor */
2225 ("comedi: rtd520 DAC chan=%d range=%d writing %d as 0x%x\n",
2226 chan, range, data[i], val);
2228 /* a typical programming sequence */
2229 RtdDacFifoPut(dev, chan, val); /* put the value in */
2230 RtdDacUpdate(dev, chan); /* trigger the conversion */
2232 devpriv->aoValue[chan] = data[i]; /* save for read back */
2234 for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
2235 stat = RtdFifoStatus(dev);
2236 /* 1 -> not empty */
2237 if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
2242 if (ii >= RTD_DAC_TIMEOUT) {
2244 ("rtd520: Error: DAC never finished! FifoStatus=0x%x\n",
2250 /* return the number of samples read/written */
2254 /* AO subdevices should have a read insn as well as a write insn.
2255 * Usually this means copying a value stored in devpriv. */
2256 static int rtd_ao_rinsn(struct comedi_device *dev,
2257 struct comedi_subdevice *s, struct comedi_insn *insn,
2261 int chan = CR_CHAN(insn->chanspec);
2263 for (i = 0; i < insn->n; i++)
2264 data[i] = devpriv->aoValue[chan];
2271 Write a masked set of bits and the read back the port.
2272 We track what the bits should be (i.e. we don't read the port first).
2274 DIO devices are slightly special. Although it is possible to
2275 * implement the insn_read/insn_write interface, it is much more
2276 * useful to applications if you implement the insn_bits interface.
2277 * This allows packed reading/writing of the DIO channels. The
2278 * comedi core can convert between insn_bits and insn_read/write
2280 static int rtd_dio_insn_bits(struct comedi_device *dev,
2281 struct comedi_subdevice *s,
2282 struct comedi_insn *insn, unsigned int *data)
2287 /* The insn data is a mask in data[0] and the new data
2288 * in data[1], each channel cooresponding to a bit. */
2290 s->state &= ~data[0];
2291 s->state |= data[0] & data[1];
2293 /* Write out the new digital output lines */
2294 RtdDio0Write(dev, s->state);
2296 /* on return, data[1] contains the value of the digital
2298 data[1] = RtdDio0Read(dev);
2300 /*DPRINTK("rtd520:port_0 wrote: 0x%x read: 0x%x\n", s->state, data[1]); */
2306 Configure one bit on a IO port as Input or Output (hence the name :-).
2308 static int rtd_dio_insn_config(struct comedi_device *dev,
2309 struct comedi_subdevice *s,
2310 struct comedi_insn *insn, unsigned int *data)
2312 int chan = CR_CHAN(insn->chanspec);
2314 /* The input or output configuration of each digital line is
2315 * configured by a special insn_config instruction. chanspec
2316 * contains the channel to be changed, and data[0] contains the
2317 * value COMEDI_INPUT or COMEDI_OUTPUT. */
2319 case INSN_CONFIG_DIO_OUTPUT:
2320 s->io_bits |= 1 << chan; /* 1 means Out */
2322 case INSN_CONFIG_DIO_INPUT:
2323 s->io_bits &= ~(1 << chan);
2325 case INSN_CONFIG_DIO_QUERY:
2327 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
2334 DPRINTK("rtd520: port_0_direction=0x%x (1 means out)\n", s->io_bits);
2335 /* TODO support digital match interrupts and strobes */
2336 RtdDioStatusWrite(dev, 0x01); /* make Dio0Ctrl point to direction */
2337 RtdDio0CtrlWrite(dev, s->io_bits); /* set direction 1 means Out */
2338 RtdDioStatusWrite(dev, 0); /* make Dio0Ctrl clear interrupts */
2340 /* port1 can only be all input or all output */
2342 /* there are also 2 user input lines and 2 user output lines */
2348 * A convenient macro that defines init_module() and cleanup_module(),
2351 static int __devinit rtd520Driver_pci_probe(struct pci_dev *dev,
2352 const struct pci_device_id *ent)
2354 return comedi_pci_auto_config(dev, rtd520Driver.driver_name);
2357 static void __devexit rtd520Driver_pci_remove(struct pci_dev *dev)
2359 comedi_pci_auto_unconfig(dev);
2362 static struct pci_driver rtd520Driver_pci_driver = {
2363 .id_table = rtd520_pci_table,
2364 .probe = &rtd520Driver_pci_probe,
2365 .remove = __devexit_p(&rtd520Driver_pci_remove)
2368 static int __init rtd520Driver_init_module(void)
2372 retval = comedi_driver_register(&rtd520Driver);
2376 rtd520Driver_pci_driver.name = (char *)rtd520Driver.driver_name;
2377 return pci_register_driver(&rtd520Driver_pci_driver);
2380 static void __exit rtd520Driver_cleanup_module(void)
2382 pci_unregister_driver(&rtd520Driver_pci_driver);
2383 comedi_driver_unregister(&rtd520Driver);
2386 module_init(rtd520Driver_init_module);
2387 module_exit(rtd520Driver_cleanup_module);
2389 MODULE_AUTHOR("Comedi http://www.comedi.org");
2390 MODULE_DESCRIPTION("Comedi low-level driver");
2391 MODULE_LICENSE("GPL");