2 comedi/drivers/ni_tiocmd.c
3 Command support for NI general purpose counters
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments general purpose counters command support
26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
27 Herman.Bruyninckx@mech.kuleuven.ac.be,
28 Wim.Meeussen@mech.kuleuven.ac.be,
29 Klaas.Gadeyne@mech.kuleuven.ac.be,
30 Frank Mori Hess <fmhess@users.sourceforge.net>
31 Updated: Fri, 11 Apr 2008 12:32:35 +0100
34 This module is not used directly by end-users. Rather, it
35 is used by other drivers (for example ni_660x and ni_pcimio)
36 to provide command support for NI's general purpose counters.
37 It was originally split out of ni_tio.c to stop the 'ni_tio'
38 module depending on the 'mite' module.
41 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
42 DAQ 6601/6602 User Manual (NI 322137B-01)
43 340934b.pdf DAQ-STC reference manual
48 Support use of both banks X and Y
51 #include "ni_tio_internal.h"
54 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
55 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
56 MODULE_LICENSE("GPL");
58 static void ni_tio_configure_dma(struct ni_gpct *counter, short enable,
61 struct ni_gpct_device *counter_dev = counter->counter_dev;
62 unsigned input_select_bits = 0;
66 input_select_bits |= Gi_Read_Acknowledges_Irq;
68 input_select_bits |= Gi_Write_Acknowledges_Irq;
71 ni_tio_set_bits(counter,
72 NITIO_Gi_Input_Select_Reg(counter->counter_index),
73 Gi_Read_Acknowledges_Irq | Gi_Write_Acknowledges_Irq,
75 switch (counter_dev->variant) {
76 case ni_gpct_variant_e_series:
78 case ni_gpct_variant_m_series:
79 case ni_gpct_variant_660x:
81 unsigned gi_dma_config_bits = 0;
84 gi_dma_config_bits |= Gi_DMA_Enable_Bit;
85 gi_dma_config_bits |= Gi_DMA_Int_Bit;
87 if (read_not_write == 0) {
88 gi_dma_config_bits |= Gi_DMA_Write_Bit;
90 ni_tio_set_bits(counter,
91 NITIO_Gi_DMA_Config_Reg(counter->counter_index),
92 Gi_DMA_Enable_Bit | Gi_DMA_Int_Bit |
93 Gi_DMA_Write_Bit, gi_dma_config_bits);
99 static int ni_tio_input_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
100 unsigned int trignum)
104 struct ni_gpct *counter = s->private;
106 BUG_ON(counter == NULL);
110 spin_lock_irqsave(&counter->lock, flags);
111 if (counter->mite_chan)
112 mite_dma_arm(counter->mite_chan);
115 spin_unlock_irqrestore(&counter->lock, flags);
118 retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
119 s->async->inttrig = NULL;
124 static int ni_tio_input_cmd(struct ni_gpct *counter, struct comedi_async *async)
126 struct ni_gpct_device *counter_dev = counter->counter_dev;
127 struct comedi_cmd *cmd = &async->cmd;
130 /* write alloc the entire buffer */
131 comedi_buf_write_alloc(async, async->prealloc_bufsz);
132 counter->mite_chan->dir = COMEDI_INPUT;
133 switch (counter_dev->variant) {
134 case ni_gpct_variant_m_series:
135 case ni_gpct_variant_660x:
136 mite_prep_dma(counter->mite_chan, 32, 32);
138 case ni_gpct_variant_e_series:
139 mite_prep_dma(counter->mite_chan, 16, 32);
145 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
146 Gi_Save_Trace_Bit, 0);
147 ni_tio_configure_dma(counter, 1, 1);
148 switch (cmd->start_src) {
150 async->inttrig = NULL;
151 mite_dma_arm(counter->mite_chan);
152 retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
155 async->inttrig = &ni_tio_input_inttrig;
158 async->inttrig = NULL;
159 mite_dma_arm(counter->mite_chan);
160 retval = ni_tio_arm(counter, 1, cmd->start_arg);
162 async->inttrig = NULL;
163 mite_dma_arm(counter->mite_chan);
172 static int ni_tio_output_cmd(struct ni_gpct *counter, struct comedi_async *async)
174 printk("ni_tio: output commands not yet implemented.\n");
177 counter->mite_chan->dir = COMEDI_OUTPUT;
178 mite_prep_dma(counter->mite_chan, 32, 32);
179 ni_tio_configure_dma(counter, 1, 0);
180 mite_dma_arm(counter->mite_chan);
181 return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
184 static int ni_tio_cmd_setup(struct ni_gpct *counter, struct comedi_async *async)
186 struct comedi_cmd *cmd = &async->cmd;
187 int set_gate_source = 0;
188 unsigned gate_source;
191 if (cmd->scan_begin_src == TRIG_EXT) {
193 gate_source = cmd->scan_begin_arg;
194 } else if (cmd->convert_src == TRIG_EXT) {
196 gate_source = cmd->convert_arg;
198 if (set_gate_source) {
199 retval = ni_tio_set_gate_src(counter, 0, gate_source);
201 if (cmd->flags & TRIG_WAKE_EOS) {
202 ni_tio_set_bits(counter,
203 NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
204 Gi_Gate_Interrupt_Enable_Bit(counter->counter_index),
205 Gi_Gate_Interrupt_Enable_Bit(counter->counter_index));
210 int ni_tio_cmd(struct ni_gpct *counter, struct comedi_async *async)
212 struct comedi_cmd *cmd = &async->cmd;
216 spin_lock_irqsave(&counter->lock, flags);
217 if (counter->mite_chan == NULL) {
219 ("ni_tio: commands only supported with DMA. Interrupt-driven commands not yet implemented.\n");
222 retval = ni_tio_cmd_setup(counter, async);
224 if (cmd->flags & CMDF_WRITE) {
225 retval = ni_tio_output_cmd(counter, async);
227 retval = ni_tio_input_cmd(counter, async);
231 spin_unlock_irqrestore(&counter->lock, flags);
235 int ni_tio_cmdtest(struct ni_gpct *counter, struct comedi_cmd * cmd)
241 /* step 1: make sure trigger sources are trivially valid */
243 tmp = cmd->start_src;
244 sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
245 if (ni_tio_counting_mode_registers_present(counter->counter_dev))
247 cmd->start_src &= sources;
248 if (!cmd->start_src || tmp != cmd->start_src)
251 tmp = cmd->scan_begin_src;
252 cmd->scan_begin_src &= TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER;
253 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
256 tmp = cmd->convert_src;
257 sources = TRIG_NOW | TRIG_EXT | TRIG_OTHER;
258 cmd->convert_src &= sources;
259 if (!cmd->convert_src || tmp != cmd->convert_src)
262 tmp = cmd->scan_end_src;
263 cmd->scan_end_src &= TRIG_COUNT;
264 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
268 cmd->stop_src &= TRIG_NONE;
269 if (!cmd->stop_src || tmp != cmd->stop_src)
275 /* step 2: make sure trigger sources are unique... */
277 if (cmd->start_src != TRIG_NOW &&
278 cmd->start_src != TRIG_INT &&
279 cmd->start_src != TRIG_EXT && cmd->start_src != TRIG_OTHER)
281 if (cmd->scan_begin_src != TRIG_FOLLOW &&
282 cmd->scan_begin_src != TRIG_EXT &&
283 cmd->scan_begin_src != TRIG_OTHER)
285 if (cmd->convert_src != TRIG_OTHER &&
286 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
288 if (cmd->stop_src != TRIG_NONE)
290 /* ... and mutually compatible */
291 if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
297 /* step 3: make sure arguments are trivially compatible */
298 if (cmd->start_src != TRIG_EXT) {
299 if (cmd->start_arg != 0) {
304 if (cmd->scan_begin_src != TRIG_EXT) {
305 if (cmd->scan_begin_arg) {
306 cmd->scan_begin_arg = 0;
310 if (cmd->convert_src != TRIG_EXT) {
311 if (cmd->convert_arg) {
312 cmd->convert_arg = 0;
317 if (cmd->scan_end_arg != cmd->chanlist_len) {
318 cmd->scan_end_arg = cmd->chanlist_len;
322 if (cmd->stop_src == TRIG_NONE) {
323 if (cmd->stop_arg != 0) {
332 /* step 4: fix up any arguments */
340 int ni_tio_cancel(struct ni_gpct *counter)
344 ni_tio_arm(counter, 0, 0);
345 spin_lock_irqsave(&counter->lock, flags);
346 if (counter->mite_chan) {
347 mite_dma_disarm(counter->mite_chan);
349 spin_unlock_irqrestore(&counter->lock, flags);
350 ni_tio_configure_dma(counter, 0, 0);
352 ni_tio_set_bits(counter,
353 NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
354 Gi_Gate_Interrupt_Enable_Bit(counter->counter_index), 0x0);
358 /* During buffered input counter operation for e-series, the gate interrupt is acked
359 automatically by the dma controller, due to the Gi_Read/Write_Acknowledges_IRQ bits
360 in the input select register. */
361 static int should_ack_gate(struct ni_gpct *counter)
366 switch (counter->counter_dev->variant) {
367 case ni_gpct_variant_m_series:
368 case ni_gpct_variant_660x: /* not sure if 660x really supports gate interrupts (the bits are not listed in register-level manual) */
371 case ni_gpct_variant_e_series:
372 spin_lock_irqsave(&counter->lock, flags);
374 if (counter->mite_chan == NULL ||
375 counter->mite_chan->dir != COMEDI_INPUT ||
376 (mite_done(counter->mite_chan))) {
380 spin_unlock_irqrestore(&counter->lock, flags);
386 void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, int *gate_error,
387 int *tc_error, int *perm_stale_data, int *stale_data)
389 const unsigned short gxx_status = read_register(counter,
390 NITIO_Gxx_Status_Reg(counter->counter_index));
391 const unsigned short gi_status = read_register(counter,
392 NITIO_Gi_Status_Reg(counter->counter_index));
400 *perm_stale_data = 0;
404 if (gxx_status & Gi_Gate_Error_Bit(counter->counter_index)) {
405 ack |= Gi_Gate_Error_Confirm_Bit(counter->counter_index);
407 /*660x don't support automatic acknowledgement of gate interrupt via dma read/write
408 and report bogus gate errors */
409 if (counter->counter_dev->variant !=
410 ni_gpct_variant_660x) {
415 if (gxx_status & Gi_TC_Error_Bit(counter->counter_index)) {
416 ack |= Gi_TC_Error_Confirm_Bit(counter->counter_index);
420 if (gi_status & Gi_TC_Bit) {
421 ack |= Gi_TC_Interrupt_Ack_Bit;
423 if (gi_status & Gi_Gate_Interrupt_Bit) {
424 if (should_ack_gate(counter))
425 ack |= Gi_Gate_Interrupt_Ack_Bit;
428 write_register(counter, ack,
429 NITIO_Gi_Interrupt_Acknowledge_Reg(counter->
431 if (ni_tio_get_soft_copy(counter,
432 NITIO_Gi_Mode_Reg(counter->
433 counter_index)) & Gi_Loading_On_Gate_Bit) {
434 if (gxx_status & Gi_Stale_Data_Bit(counter->counter_index)) {
438 if (read_register(counter,
439 NITIO_Gxx_Joint_Status2_Reg(counter->
441 Gi_Permanent_Stale_Bit(counter->counter_index)) {
442 printk("%s: Gi_Permanent_Stale_Data detected.\n",
445 *perm_stale_data = 1;
450 void ni_tio_handle_interrupt(struct ni_gpct *counter, struct comedi_subdevice * s)
452 unsigned gpct_mite_status;
458 ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
459 &perm_stale_data, NULL);
461 printk("%s: Gi_Gate_Error detected.\n", __FUNCTION__);
462 s->async->events |= COMEDI_CB_OVERFLOW;
464 if (perm_stale_data) {
465 s->async->events |= COMEDI_CB_ERROR;
467 switch (counter->counter_dev->variant) {
468 case ni_gpct_variant_m_series:
469 case ni_gpct_variant_660x:
470 if (read_register(counter,
471 NITIO_Gi_DMA_Status_Reg(counter->
472 counter_index)) & Gi_DRQ_Error_Bit) {
473 printk("%s: Gi_DRQ_Error detected.\n", __FUNCTION__);
474 s->async->events |= COMEDI_CB_OVERFLOW;
477 case ni_gpct_variant_e_series:
480 spin_lock_irqsave(&counter->lock, flags);
481 if (counter->mite_chan == NULL) {
482 spin_unlock_irqrestore(&counter->lock, flags);
485 gpct_mite_status = mite_get_status(counter->mite_chan);
486 if (gpct_mite_status & CHSR_LINKC) {
488 counter->mite_chan->mite->mite_io_addr +
489 MITE_CHOR(counter->mite_chan->channel));
491 mite_sync_input_dma(counter->mite_chan, s->async);
492 spin_unlock_irqrestore(&counter->lock, flags);
495 void ni_tio_set_mite_channel(struct ni_gpct *counter,
496 struct mite_channel *mite_chan)
500 spin_lock_irqsave(&counter->lock, flags);
501 counter->mite_chan = mite_chan;
502 spin_unlock_irqrestore(&counter->lock, flags);
505 static int __init ni_tiocmd_init_module(void)
510 module_init(ni_tiocmd_init_module);
512 static void __exit ni_tiocmd_cleanup_module(void)
516 module_exit(ni_tiocmd_cleanup_module);
518 EXPORT_SYMBOL_GPL(ni_tio_cmd);
519 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
520 EXPORT_SYMBOL_GPL(ni_tio_cancel);
521 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
522 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
523 EXPORT_SYMBOL_GPL(ni_tio_acknowledge_and_confirm);