2 comedi/drivers/ni_tio.c
3 Support for NI general purpose counters
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments general purpose counters
26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
27 Herman.Bruyninckx@mech.kuleuven.ac.be,
28 Wim.Meeussen@mech.kuleuven.ac.be,
29 Klaas.Gadeyne@mech.kuleuven.ac.be,
30 Frank Mori Hess <fmhess@users.sourceforge.net>
31 Updated: Thu Nov 16 09:50:32 EST 2006
34 This module is not used directly by end-users. Rather, it
35 is used by other drivers (for example ni_660x and ni_pcimio)
36 to provide support for NI's general purpose counters. It was
37 originally based on the counter code from ni_660x.c and
41 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
42 DAQ 6601/6602 User Manual (NI 322137B-01)
43 340934b.pdf DAQ-STC reference manual
48 Support use of both banks X and Y
51 #include "ni_tio_internal.h"
53 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
54 unsigned generic_clock_source);
55 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
57 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
58 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
59 MODULE_LICENSE("GPL");
61 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Alternate_Sync_Bit(enum
62 ni_gpct_variant variant)
65 case ni_gpct_variant_e_series:
68 case ni_gpct_variant_m_series:
69 return Gi_M_Series_Alternate_Sync_Bit;
71 case ni_gpct_variant_660x:
72 return Gi_660x_Alternate_Sync_Bit;
80 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X2_Bit(enum
81 ni_gpct_variant variant)
84 case ni_gpct_variant_e_series:
87 case ni_gpct_variant_m_series:
88 return Gi_M_Series_Prescale_X2_Bit;
90 case ni_gpct_variant_660x:
91 return Gi_660x_Prescale_X2_Bit;
99 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X8_Bit(enum
100 ni_gpct_variant variant)
103 case ni_gpct_variant_e_series:
106 case ni_gpct_variant_m_series:
107 return Gi_M_Series_Prescale_X8_Bit;
109 case ni_gpct_variant_660x:
110 return Gi_660x_Prescale_X8_Bit;
118 static inline enum Gi_Counting_Mode_Reg_Bits Gi_HW_Arm_Select_Mask(enum
119 ni_gpct_variant variant)
122 case ni_gpct_variant_e_series:
125 case ni_gpct_variant_m_series:
126 return Gi_M_Series_HW_Arm_Select_Mask;
128 case ni_gpct_variant_660x:
129 return Gi_660x_HW_Arm_Select_Mask;
138 /* clock sources for ni_660x boards, get bits with Gi_Source_Select_Bits() */
139 enum ni_660x_clock_source {
140 NI_660x_Timebase_1_Clock = 0x0, /* 20MHz */
141 NI_660x_Source_Pin_i_Clock = 0x1,
142 NI_660x_Next_Gate_Clock = 0xa,
143 NI_660x_Timebase_2_Clock = 0x12, /* 100KHz */
144 NI_660x_Next_TC_Clock = 0x13,
145 NI_660x_Timebase_3_Clock = 0x1e, /* 80MHz */
146 NI_660x_Logic_Low_Clock = 0x1f,
148 static const unsigned ni_660x_max_rtsi_channel = 6;
149 static inline unsigned NI_660x_RTSI_Clock(unsigned n)
151 BUG_ON(n > ni_660x_max_rtsi_channel);
154 static const unsigned ni_660x_max_source_pin = 7;
155 static inline unsigned NI_660x_Source_Pin_Clock(unsigned n)
157 BUG_ON(n > ni_660x_max_source_pin);
161 /* clock sources for ni e and m series boards, get bits with Gi_Source_Select_Bits() */
162 enum ni_m_series_clock_source {
163 NI_M_Series_Timebase_1_Clock = 0x0, /* 20MHz */
164 NI_M_Series_Timebase_2_Clock = 0x12, /* 100KHz */
165 NI_M_Series_Next_TC_Clock = 0x13,
166 NI_M_Series_Next_Gate_Clock = 0x14, /* when Gi_Src_SubSelect = 0 */
167 NI_M_Series_PXI_Star_Trigger_Clock = 0x14, /* when Gi_Src_SubSelect = 1 */
168 NI_M_Series_PXI10_Clock = 0x1d,
169 NI_M_Series_Timebase_3_Clock = 0x1e, /* 80MHz, when Gi_Src_SubSelect = 0 */
170 NI_M_Series_Analog_Trigger_Out_Clock = 0x1e, /* when Gi_Src_SubSelect = 1 */
171 NI_M_Series_Logic_Low_Clock = 0x1f,
173 static const unsigned ni_m_series_max_pfi_channel = 15;
174 static inline unsigned NI_M_Series_PFI_Clock(unsigned n)
176 BUG_ON(n > ni_m_series_max_pfi_channel);
182 static const unsigned ni_m_series_max_rtsi_channel = 7;
183 static inline unsigned NI_M_Series_RTSI_Clock(unsigned n)
185 BUG_ON(n > ni_m_series_max_rtsi_channel);
192 enum ni_660x_gate_select {
193 NI_660x_Source_Pin_i_Gate_Select = 0x0,
194 NI_660x_Gate_Pin_i_Gate_Select = 0x1,
195 NI_660x_Next_SRC_Gate_Select = 0xa,
196 NI_660x_Next_Out_Gate_Select = 0x14,
197 NI_660x_Logic_Low_Gate_Select = 0x1f,
199 static const unsigned ni_660x_max_gate_pin = 7;
200 static inline unsigned NI_660x_Gate_Pin_Gate_Select(unsigned n)
202 BUG_ON(n > ni_660x_max_gate_pin);
205 static inline unsigned NI_660x_RTSI_Gate_Select(unsigned n)
207 BUG_ON(n > ni_660x_max_rtsi_channel);
211 enum ni_m_series_gate_select {
212 NI_M_Series_Timestamp_Mux_Gate_Select = 0x0,
213 NI_M_Series_AI_START2_Gate_Select = 0x12,
214 NI_M_Series_PXI_Star_Trigger_Gate_Select = 0x13,
215 NI_M_Series_Next_Out_Gate_Select = 0x14,
216 NI_M_Series_AI_START1_Gate_Select = 0x1c,
217 NI_M_Series_Next_SRC_Gate_Select = 0x1d,
218 NI_M_Series_Analog_Trigger_Out_Gate_Select = 0x1e,
219 NI_M_Series_Logic_Low_Gate_Select = 0x1f,
221 static inline unsigned NI_M_Series_RTSI_Gate_Select(unsigned n)
223 BUG_ON(n > ni_m_series_max_rtsi_channel);
228 static inline unsigned NI_M_Series_PFI_Gate_Select(unsigned n)
230 BUG_ON(n > ni_m_series_max_pfi_channel);
236 static inline unsigned Gi_Source_Select_Bits(unsigned source)
238 return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
240 static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
242 return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
245 enum ni_660x_second_gate_select {
246 NI_660x_Source_Pin_i_Second_Gate_Select = 0x0,
247 NI_660x_Up_Down_Pin_i_Second_Gate_Select = 0x1,
248 NI_660x_Next_SRC_Second_Gate_Select = 0xa,
249 NI_660x_Next_Out_Second_Gate_Select = 0x14,
250 NI_660x_Selected_Gate_Second_Gate_Select = 0x1e,
251 NI_660x_Logic_Low_Second_Gate_Select = 0x1f,
253 static const unsigned ni_660x_max_up_down_pin = 7;
254 static inline unsigned NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned n)
256 BUG_ON(n > ni_660x_max_up_down_pin);
259 static inline unsigned NI_660x_RTSI_Second_Gate_Select(unsigned n)
261 BUG_ON(n > ni_660x_max_rtsi_channel);
265 static const unsigned int counter_status_mask =
266 COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
268 static int __init ni_tio_init_module(void)
273 module_init(ni_tio_init_module);
275 static void __exit ni_tio_cleanup_module(void)
279 module_exit(ni_tio_cleanup_module);
281 struct ni_gpct_device *ni_gpct_device_construct(struct comedi_device * dev,
282 void (*write_register) (struct ni_gpct * counter, unsigned bits,
283 enum ni_gpct_register reg),
284 unsigned (*read_register) (struct ni_gpct * counter,
285 enum ni_gpct_register reg), enum ni_gpct_variant variant,
286 unsigned num_counters)
290 struct ni_gpct_device *counter_dev =
291 kzalloc(sizeof(struct ni_gpct_device), GFP_KERNEL);
292 if (counter_dev == NULL)
294 counter_dev->dev = dev;
295 counter_dev->write_register = write_register;
296 counter_dev->read_register = read_register;
297 counter_dev->variant = variant;
298 spin_lock_init(&counter_dev->regs_lock);
299 BUG_ON(num_counters == 0);
300 counter_dev->counters =
301 kzalloc(sizeof(struct ni_gpct) * num_counters, GFP_KERNEL);
302 if (counter_dev->counters == NULL) {
306 for (i = 0; i < num_counters; ++i) {
307 counter_dev->counters[i].counter_dev = counter_dev;
308 spin_lock_init(&counter_dev->counters[i].lock);
310 counter_dev->num_counters = num_counters;
314 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
316 if (counter_dev->counters == NULL)
318 kfree(counter_dev->counters);
322 static int ni_tio_second_gate_registers_present(const struct ni_gpct_device
325 switch (counter_dev->variant) {
326 case ni_gpct_variant_e_series:
329 case ni_gpct_variant_m_series:
330 case ni_gpct_variant_660x:
340 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
342 write_register(counter, Gi_Reset_Bit(counter->counter_index),
343 NITIO_Gxx_Joint_Reset_Reg(counter->counter_index));
346 void ni_tio_init_counter(struct ni_gpct *counter)
348 struct ni_gpct_device *counter_dev = counter->counter_dev;
350 ni_tio_reset_count_and_disarm(counter);
351 /* initialize counter registers */
352 counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] =
354 write_register(counter,
355 counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->
357 NITIO_Gi_Autoincrement_Reg(counter->counter_index));
358 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
359 ~0, Gi_Synchronize_Gate_Bit);
360 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0,
362 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
363 write_register(counter,
364 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)],
365 NITIO_Gi_LoadA_Reg(counter->counter_index));
366 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0;
367 write_register(counter,
368 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)],
369 NITIO_Gi_LoadB_Reg(counter->counter_index));
370 ni_tio_set_bits(counter,
371 NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0, 0);
372 if (ni_tio_counting_mode_registers_present(counter_dev)) {
373 ni_tio_set_bits(counter,
374 NITIO_Gi_Counting_Mode_Reg(counter->counter_index), ~0,
377 if (ni_tio_second_gate_registers_present(counter_dev)) {
378 counter_dev->regs[NITIO_Gi_Second_Gate_Reg(counter->
379 counter_index)] = 0x0;
380 write_register(counter,
381 counter_dev->regs[NITIO_Gi_Second_Gate_Reg(counter->
383 NITIO_Gi_Second_Gate_Reg(counter->counter_index));
385 ni_tio_set_bits(counter,
386 NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0, 0x0);
387 ni_tio_set_bits(counter,
388 NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index), ~0, 0x0);
391 static unsigned int ni_tio_counter_status(struct ni_gpct *counter)
393 unsigned int status = 0;
394 const unsigned bits = read_register(counter,
395 NITIO_Gxx_Status_Reg(counter->counter_index));
396 if (bits & Gi_Armed_Bit(counter->counter_index)) {
397 status |= COMEDI_COUNTER_ARMED;
398 if (bits & Gi_Counting_Bit(counter->counter_index))
399 status |= COMEDI_COUNTER_COUNTING;
404 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
406 struct ni_gpct_device *counter_dev = counter->counter_dev;
407 const unsigned counting_mode_reg =
408 NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
409 static const uint64_t min_normal_sync_period_ps = 25000;
410 const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
411 ni_tio_generic_clock_src_select(counter));
413 if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
416 switch (ni_tio_get_soft_copy(counter,
417 counting_mode_reg) & Gi_Counting_Mode_Mask) {
418 case Gi_Counting_Mode_QuadratureX1_Bits:
419 case Gi_Counting_Mode_QuadratureX2_Bits:
420 case Gi_Counting_Mode_QuadratureX4_Bits:
421 case Gi_Counting_Mode_Sync_Source_Bits:
427 /* It's not clear what we should do if clock_period is unknown, so we are not
428 using the alt sync bit in that case, but allow the caller to decide by using the
429 force_alt_sync parameter. */
430 if (force_alt_sync ||
432 && clock_period_ps < min_normal_sync_period_ps)) {
433 ni_tio_set_bits(counter, counting_mode_reg,
434 Gi_Alternate_Sync_Bit(counter_dev->variant),
435 Gi_Alternate_Sync_Bit(counter_dev->variant));
437 ni_tio_set_bits(counter, counting_mode_reg,
438 Gi_Alternate_Sync_Bit(counter_dev->variant), 0x0);
442 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
444 struct ni_gpct_device *counter_dev = counter->counter_dev;
445 unsigned mode_reg_mask;
446 unsigned mode_reg_values;
447 unsigned input_select_bits = 0;
448 /* these bits map directly on to the mode register */
449 static const unsigned mode_reg_direct_mask =
450 NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
451 NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
452 NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
453 NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
455 mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
456 mode_reg_values = mode & mode_reg_direct_mask;
457 switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
458 case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
460 case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
461 mode_reg_values |= Gi_Reload_Source_Switching_Bit;
463 case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
464 input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
465 mode_reg_mask |= Gi_Gating_Mode_Mask;
466 mode_reg_values |= Gi_Level_Gating_Bits;
471 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
472 mode_reg_mask, mode_reg_values);
474 if (ni_tio_counting_mode_registers_present(counter_dev)) {
475 unsigned counting_mode_bits = 0;
476 counting_mode_bits |=
477 (mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
478 Gi_Counting_Mode_Mask;
479 counting_mode_bits |=
480 ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
481 Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
482 if (mode & NI_GPCT_INDEX_ENABLE_BIT) {
483 counting_mode_bits |= Gi_Index_Mode_Bit;
485 ni_tio_set_bits(counter,
486 NITIO_Gi_Counting_Mode_Reg(counter->counter_index),
487 Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
488 Gi_Index_Mode_Bit, counting_mode_bits);
489 ni_tio_set_sync_mode(counter, 0);
492 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
494 (mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) << Gi_Up_Down_Shift);
496 if (mode & NI_GPCT_OR_GATE_BIT) {
497 input_select_bits |= Gi_Or_Gate_Bit;
499 if (mode & NI_GPCT_INVERT_OUTPUT_BIT) {
500 input_select_bits |= Gi_Output_Polarity_Bit;
502 ni_tio_set_bits(counter,
503 NITIO_Gi_Input_Select_Reg(counter->counter_index),
504 Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
505 Gi_Output_Polarity_Bit, input_select_bits);
510 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
512 struct ni_gpct_device *counter_dev = counter->counter_dev;
514 unsigned command_transient_bits = 0;
517 switch (start_trigger) {
518 case NI_GPCT_ARM_IMMEDIATE:
519 command_transient_bits |= Gi_Arm_Bit;
521 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
522 command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
527 if (ni_tio_counting_mode_registers_present(counter_dev)) {
528 unsigned counting_mode_bits = 0;
530 switch (start_trigger) {
531 case NI_GPCT_ARM_IMMEDIATE:
532 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
535 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
536 /* pass-through the least significant bits so we can figure out what select later */
537 unsigned hw_arm_select_bits =
539 Gi_HW_Arm_Select_Shift) &
540 Gi_HW_Arm_Select_Mask
541 (counter_dev->variant);
543 counting_mode_bits |=
544 Gi_HW_Arm_Enable_Bit |
551 ni_tio_set_bits(counter,
552 NITIO_Gi_Counting_Mode_Reg(counter->
554 Gi_HW_Arm_Select_Mask(counter_dev->
555 variant) | Gi_HW_Arm_Enable_Bit,
559 command_transient_bits |= Gi_Disarm_Bit;
561 ni_tio_set_bits_transient(counter,
562 NITIO_Gi_Command_Reg(counter->counter_index), 0, 0,
563 command_transient_bits);
567 static unsigned ni_660x_source_select_bits(unsigned int clock_source)
569 unsigned ni_660x_clock;
571 const unsigned clock_select_bits =
572 clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
574 switch (clock_select_bits) {
575 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
576 ni_660x_clock = NI_660x_Timebase_1_Clock;
578 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
579 ni_660x_clock = NI_660x_Timebase_2_Clock;
581 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
582 ni_660x_clock = NI_660x_Timebase_3_Clock;
584 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
585 ni_660x_clock = NI_660x_Logic_Low_Clock;
587 case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
588 ni_660x_clock = NI_660x_Source_Pin_i_Clock;
590 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
591 ni_660x_clock = NI_660x_Next_Gate_Clock;
593 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
594 ni_660x_clock = NI_660x_Next_TC_Clock;
597 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
598 if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
599 ni_660x_clock = NI_660x_RTSI_Clock(i);
603 if (i <= ni_660x_max_rtsi_channel)
605 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
606 if (clock_select_bits ==
607 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
608 ni_660x_clock = NI_660x_Source_Pin_Clock(i);
612 if (i <= ni_660x_max_source_pin)
618 return Gi_Source_Select_Bits(ni_660x_clock);
621 static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
623 unsigned ni_m_series_clock;
625 const unsigned clock_select_bits =
626 clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
627 switch (clock_select_bits) {
628 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
629 ni_m_series_clock = NI_M_Series_Timebase_1_Clock;
631 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
632 ni_m_series_clock = NI_M_Series_Timebase_2_Clock;
634 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
635 ni_m_series_clock = NI_M_Series_Timebase_3_Clock;
637 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
638 ni_m_series_clock = NI_M_Series_Logic_Low_Clock;
640 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
641 ni_m_series_clock = NI_M_Series_Next_Gate_Clock;
643 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
644 ni_m_series_clock = NI_M_Series_Next_TC_Clock;
646 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
647 ni_m_series_clock = NI_M_Series_PXI10_Clock;
649 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
650 ni_m_series_clock = NI_M_Series_PXI_Star_Trigger_Clock;
652 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
653 ni_m_series_clock = NI_M_Series_Analog_Trigger_Out_Clock;
656 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
657 if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
658 ni_m_series_clock = NI_M_Series_RTSI_Clock(i);
662 if (i <= ni_m_series_max_rtsi_channel)
664 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
665 if (clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
666 ni_m_series_clock = NI_M_Series_PFI_Clock(i);
670 if (i <= ni_m_series_max_pfi_channel)
672 rt_printk("invalid clock source 0x%lx\n",
673 (unsigned long)clock_source);
675 ni_m_series_clock = 0;
678 return Gi_Source_Select_Bits(ni_m_series_clock);
681 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
682 unsigned int clock_source)
684 struct ni_gpct_device *counter_dev = counter->counter_dev;
685 const unsigned second_gate_reg =
686 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
688 if (counter_dev->variant != ni_gpct_variant_m_series)
690 switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
691 /* Gi_Source_Subselect is zero */
692 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
693 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
694 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
696 /* Gi_Source_Subselect is one */
697 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
698 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
699 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
701 /* Gi_Source_Subselect doesn't matter */
706 write_register(counter, counter_dev->regs[second_gate_reg],
710 static int ni_tio_set_clock_src(struct ni_gpct *counter,
711 unsigned int clock_source, unsigned int period_ns)
713 struct ni_gpct_device *counter_dev = counter->counter_dev;
714 unsigned input_select_bits = 0;
715 static const uint64_t pico_per_nano = 1000;
717 /*FIXME: validate clock source */
718 switch (counter_dev->variant) {
719 case ni_gpct_variant_660x:
720 input_select_bits |= ni_660x_source_select_bits(clock_source);
722 case ni_gpct_variant_e_series:
723 case ni_gpct_variant_m_series:
725 ni_m_series_source_select_bits(clock_source);
731 if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
732 input_select_bits |= Gi_Source_Polarity_Bit;
733 ni_tio_set_bits(counter,
734 NITIO_Gi_Input_Select_Reg(counter->counter_index),
735 Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
737 ni_tio_set_source_subselect(counter, clock_source);
738 if (ni_tio_counting_mode_registers_present(counter_dev)) {
739 const unsigned prescaling_mode =
740 clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
741 unsigned counting_mode_bits = 0;
743 switch (prescaling_mode) {
744 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
746 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
747 counting_mode_bits |=
748 Gi_Prescale_X2_Bit(counter_dev->variant);
750 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
751 counting_mode_bits |=
752 Gi_Prescale_X8_Bit(counter_dev->variant);
758 ni_tio_set_bits(counter,
759 NITIO_Gi_Counting_Mode_Reg(counter->counter_index),
760 Gi_Prescale_X2_Bit(counter_dev->
761 variant) | Gi_Prescale_X8_Bit(counter_dev->
762 variant), counting_mode_bits);
764 counter->clock_period_ps = pico_per_nano * period_ns;
765 ni_tio_set_sync_mode(counter, 0);
769 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
771 struct ni_gpct_device *counter_dev = counter->counter_dev;
772 const unsigned counting_mode_bits = ni_tio_get_soft_copy(counter,
773 NITIO_Gi_Counting_Mode_Reg(counter->counter_index));
776 if (ni_tio_get_soft_copy(counter,
777 NITIO_Gi_Input_Select_Reg(counter->
778 counter_index)) & Gi_Source_Polarity_Bit)
779 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
780 if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
781 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
782 if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
783 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
787 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
789 struct ni_gpct_device *counter_dev = counter->counter_dev;
790 const unsigned second_gate_reg =
791 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
792 unsigned clock_source = 0;
794 const unsigned input_select = (ni_tio_get_soft_copy(counter,
795 NITIO_Gi_Input_Select_Reg(counter->
796 counter_index)) & Gi_Source_Select_Mask) >>
797 Gi_Source_Select_Shift;
799 switch (input_select) {
800 case NI_M_Series_Timebase_1_Clock:
801 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
803 case NI_M_Series_Timebase_2_Clock:
804 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
806 case NI_M_Series_Timebase_3_Clock:
808 regs[second_gate_reg] & Gi_Source_Subselect_Bit)
810 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
812 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
814 case NI_M_Series_Logic_Low_Clock:
815 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
817 case NI_M_Series_Next_Gate_Clock:
819 regs[second_gate_reg] & Gi_Source_Subselect_Bit)
820 clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
822 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
824 case NI_M_Series_PXI10_Clock:
825 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
827 case NI_M_Series_Next_TC_Clock:
828 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
831 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
832 if (input_select == NI_M_Series_RTSI_Clock(i)) {
833 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
837 if (i <= ni_m_series_max_rtsi_channel)
839 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
840 if (input_select == NI_M_Series_PFI_Clock(i)) {
841 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
845 if (i <= ni_m_series_max_pfi_channel)
850 clock_source |= ni_tio_clock_src_modifiers(counter);
854 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
856 unsigned clock_source = 0;
858 const unsigned input_select = (ni_tio_get_soft_copy(counter,
859 NITIO_Gi_Input_Select_Reg(counter->
860 counter_index)) & Gi_Source_Select_Mask) >>
861 Gi_Source_Select_Shift;
863 switch (input_select) {
864 case NI_660x_Timebase_1_Clock:
865 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
867 case NI_660x_Timebase_2_Clock:
868 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
870 case NI_660x_Timebase_3_Clock:
871 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
873 case NI_660x_Logic_Low_Clock:
874 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
876 case NI_660x_Source_Pin_i_Clock:
877 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
879 case NI_660x_Next_Gate_Clock:
880 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
882 case NI_660x_Next_TC_Clock:
883 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
886 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
887 if (input_select == NI_660x_RTSI_Clock(i)) {
888 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
892 if (i <= ni_660x_max_rtsi_channel)
894 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
895 if (input_select == NI_660x_Source_Pin_Clock(i)) {
897 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
901 if (i <= ni_660x_max_source_pin)
906 clock_source |= ni_tio_clock_src_modifiers(counter);
910 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
912 switch (counter->counter_dev->variant) {
913 case ni_gpct_variant_e_series:
914 case ni_gpct_variant_m_series:
915 return ni_m_series_clock_src_select(counter);
917 case ni_gpct_variant_660x:
918 return ni_660x_clock_src_select(counter);
927 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
928 unsigned generic_clock_source)
930 uint64_t clock_period_ps;
932 switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
933 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
934 clock_period_ps = 50000;
936 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
937 clock_period_ps = 10000000;
939 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
940 clock_period_ps = 12500;
942 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
943 clock_period_ps = 100000;
946 /* clock period is specified by user with prescaling already taken into account. */
947 return counter->clock_period_ps;
951 switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
952 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
954 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
955 clock_period_ps *= 2;
957 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
958 clock_period_ps *= 8;
964 return clock_period_ps;
967 static void ni_tio_get_clock_src(struct ni_gpct *counter,
968 unsigned int * clock_source, unsigned int * period_ns)
970 static const unsigned pico_per_nano = 1000;
972 *clock_source = ni_tio_generic_clock_src_select(counter);
973 temp64 = ni_tio_clock_period_ps(counter, *clock_source);
974 do_div(temp64, pico_per_nano);
978 static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
979 unsigned int gate_source)
981 const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
982 unsigned mode_values = 0;
984 if (gate_source & CR_INVERT) {
985 mode_values |= Gi_Gate_Polarity_Bit;
987 if (gate_source & CR_EDGE) {
988 mode_values |= Gi_Rising_Edge_Gating_Bits;
990 mode_values |= Gi_Level_Gating_Bits;
992 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
993 mode_mask, mode_values);
996 static int ni_660x_set_first_gate(struct ni_gpct *counter, unsigned int gate_source)
998 const unsigned selected_gate = CR_CHAN(gate_source);
999 /* bits of selected_gate that may be meaningful to input select register */
1000 const unsigned selected_gate_mask = 0x1f;
1001 unsigned ni_660x_gate_select;
1004 switch (selected_gate) {
1005 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1006 ni_660x_gate_select = NI_660x_Next_SRC_Gate_Select;
1008 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1009 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1010 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1011 case NI_GPCT_GATE_PIN_i_GATE_SELECT:
1012 ni_660x_gate_select = selected_gate & selected_gate_mask;
1015 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1016 if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1017 ni_660x_gate_select =
1018 selected_gate & selected_gate_mask;
1022 if (i <= ni_660x_max_rtsi_channel)
1024 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1025 if (selected_gate == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
1026 ni_660x_gate_select =
1027 selected_gate & selected_gate_mask;
1031 if (i <= ni_660x_max_gate_pin)
1036 ni_tio_set_bits(counter,
1037 NITIO_Gi_Input_Select_Reg(counter->counter_index),
1038 Gi_Gate_Select_Mask, Gi_Gate_Select_Bits(ni_660x_gate_select));
1042 static int ni_m_series_set_first_gate(struct ni_gpct *counter,
1043 unsigned int gate_source)
1045 const unsigned selected_gate = CR_CHAN(gate_source);
1046 /* bits of selected_gate that may be meaningful to input select register */
1047 const unsigned selected_gate_mask = 0x1f;
1048 unsigned ni_m_series_gate_select;
1051 switch (selected_gate) {
1052 case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
1053 case NI_GPCT_AI_START2_GATE_SELECT:
1054 case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
1055 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1056 case NI_GPCT_AI_START1_GATE_SELECT:
1057 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1058 case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
1059 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1060 ni_m_series_gate_select = selected_gate & selected_gate_mask;
1063 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1064 if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1065 ni_m_series_gate_select =
1066 selected_gate & selected_gate_mask;
1070 if (i <= ni_m_series_max_rtsi_channel)
1072 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1073 if (selected_gate == NI_GPCT_PFI_GATE_SELECT(i)) {
1074 ni_m_series_gate_select =
1075 selected_gate & selected_gate_mask;
1079 if (i <= ni_m_series_max_pfi_channel)
1084 ni_tio_set_bits(counter,
1085 NITIO_Gi_Input_Select_Reg(counter->counter_index),
1086 Gi_Gate_Select_Mask,
1087 Gi_Gate_Select_Bits(ni_m_series_gate_select));
1091 static int ni_660x_set_second_gate(struct ni_gpct *counter,
1092 unsigned int gate_source)
1094 struct ni_gpct_device *counter_dev = counter->counter_dev;
1095 const unsigned second_gate_reg =
1096 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1097 const unsigned selected_second_gate = CR_CHAN(gate_source);
1098 /* bits of second_gate that may be meaningful to second gate register */
1099 static const unsigned selected_second_gate_mask = 0x1f;
1100 unsigned ni_660x_second_gate_select;
1103 switch (selected_second_gate) {
1104 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1105 case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
1106 case NI_GPCT_SELECTED_GATE_GATE_SELECT:
1107 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1108 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1109 ni_660x_second_gate_select =
1110 selected_second_gate & selected_second_gate_mask;
1112 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1113 ni_660x_second_gate_select =
1114 NI_660x_Next_SRC_Second_Gate_Select;
1117 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1118 if (selected_second_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1119 ni_660x_second_gate_select =
1120 selected_second_gate &
1121 selected_second_gate_mask;
1125 if (i <= ni_660x_max_rtsi_channel)
1127 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1128 if (selected_second_gate ==
1129 NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
1130 ni_660x_second_gate_select =
1131 selected_second_gate &
1132 selected_second_gate_mask;
1136 if (i <= ni_660x_max_up_down_pin)
1141 counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1142 counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1143 counter_dev->regs[second_gate_reg] |=
1144 Gi_Second_Gate_Select_Bits(ni_660x_second_gate_select);
1145 write_register(counter, counter_dev->regs[second_gate_reg],
1150 static int ni_m_series_set_second_gate(struct ni_gpct *counter,
1151 unsigned int gate_source)
1153 struct ni_gpct_device *counter_dev = counter->counter_dev;
1154 const unsigned second_gate_reg =
1155 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1156 const unsigned selected_second_gate = CR_CHAN(gate_source);
1157 /* bits of second_gate that may be meaningful to second gate register */
1158 static const unsigned selected_second_gate_mask = 0x1f;
1159 unsigned ni_m_series_second_gate_select;
1161 /* FIXME: We don't know what the m-series second gate codes are, so we'll just pass
1162 the bits through for now. */
1163 switch (selected_second_gate) {
1165 ni_m_series_second_gate_select =
1166 selected_second_gate & selected_second_gate_mask;
1169 counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1170 counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1171 counter_dev->regs[second_gate_reg] |=
1172 Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
1173 write_register(counter, counter_dev->regs[second_gate_reg],
1178 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
1179 unsigned int gate_source)
1181 struct ni_gpct_device *counter_dev = counter->counter_dev;
1182 const unsigned second_gate_reg =
1183 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1185 switch (gate_index) {
1187 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1188 ni_tio_set_bits(counter,
1189 NITIO_Gi_Mode_Reg(counter->counter_index),
1190 Gi_Gating_Mode_Mask, Gi_Gating_Disabled_Bits);
1193 ni_tio_set_first_gate_modifiers(counter, gate_source);
1194 switch (counter_dev->variant) {
1195 case ni_gpct_variant_e_series:
1196 case ni_gpct_variant_m_series:
1197 return ni_m_series_set_first_gate(counter, gate_source);
1199 case ni_gpct_variant_660x:
1200 return ni_660x_set_first_gate(counter, gate_source);
1208 if (ni_tio_second_gate_registers_present(counter_dev) == 0)
1210 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1211 counter_dev->regs[second_gate_reg] &=
1212 ~Gi_Second_Gate_Mode_Bit;
1213 write_register(counter,
1214 counter_dev->regs[second_gate_reg],
1218 if (gate_source & CR_INVERT) {
1219 counter_dev->regs[second_gate_reg] |=
1220 Gi_Second_Gate_Polarity_Bit;
1222 counter_dev->regs[second_gate_reg] &=
1223 ~Gi_Second_Gate_Polarity_Bit;
1225 switch (counter_dev->variant) {
1226 case ni_gpct_variant_m_series:
1227 return ni_m_series_set_second_gate(counter,
1230 case ni_gpct_variant_660x:
1231 return ni_660x_set_second_gate(counter, gate_source);
1245 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
1246 unsigned int source)
1248 struct ni_gpct_device *counter_dev = counter->counter_dev;
1250 if (counter_dev->variant == ni_gpct_variant_m_series) {
1251 unsigned int abz_reg, shift, mask;
1253 abz_reg = NITIO_Gi_ABZ_Reg(counter->counter_index);
1255 case NI_GPCT_SOURCE_ENCODER_A:
1258 case NI_GPCT_SOURCE_ENCODER_B:
1261 case NI_GPCT_SOURCE_ENCODER_Z:
1268 mask = 0x1f << shift;
1269 if (source > 0x1f) {
1273 counter_dev->regs[abz_reg] &= ~mask;
1274 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1275 write_register(counter, counter_dev->regs[abz_reg], abz_reg);
1276 // rt_printk("%s %x %d %d\n", __FUNCTION__, counter_dev->regs[abz_reg], index, source);
1282 static unsigned ni_660x_first_gate_to_generic_gate_source(unsigned
1283 ni_660x_gate_select)
1287 switch (ni_660x_gate_select) {
1288 case NI_660x_Source_Pin_i_Gate_Select:
1289 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1291 case NI_660x_Gate_Pin_i_Gate_Select:
1292 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1294 case NI_660x_Next_SRC_Gate_Select:
1295 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1297 case NI_660x_Next_Out_Gate_Select:
1298 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1300 case NI_660x_Logic_Low_Gate_Select:
1301 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1304 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1305 if (ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i)) {
1306 return NI_GPCT_RTSI_GATE_SELECT(i);
1310 if (i <= ni_660x_max_rtsi_channel)
1312 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1313 if (ni_660x_gate_select ==
1314 NI_660x_Gate_Pin_Gate_Select(i)) {
1315 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1319 if (i <= ni_660x_max_gate_pin)
1327 static unsigned ni_m_series_first_gate_to_generic_gate_source(unsigned
1328 ni_m_series_gate_select)
1332 switch (ni_m_series_gate_select) {
1333 case NI_M_Series_Timestamp_Mux_Gate_Select:
1334 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1336 case NI_M_Series_AI_START2_Gate_Select:
1337 return NI_GPCT_AI_START2_GATE_SELECT;
1339 case NI_M_Series_PXI_Star_Trigger_Gate_Select:
1340 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1342 case NI_M_Series_Next_Out_Gate_Select:
1343 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1345 case NI_M_Series_AI_START1_Gate_Select:
1346 return NI_GPCT_AI_START1_GATE_SELECT;
1348 case NI_M_Series_Next_SRC_Gate_Select:
1349 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1351 case NI_M_Series_Analog_Trigger_Out_Gate_Select:
1352 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1354 case NI_M_Series_Logic_Low_Gate_Select:
1355 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1358 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1359 if (ni_m_series_gate_select ==
1360 NI_M_Series_RTSI_Gate_Select(i)) {
1361 return NI_GPCT_RTSI_GATE_SELECT(i);
1365 if (i <= ni_m_series_max_rtsi_channel)
1367 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1368 if (ni_m_series_gate_select ==
1369 NI_M_Series_PFI_Gate_Select(i)) {
1370 return NI_GPCT_PFI_GATE_SELECT(i);
1374 if (i <= ni_m_series_max_pfi_channel)
1382 static unsigned ni_660x_second_gate_to_generic_gate_source(unsigned
1383 ni_660x_gate_select)
1387 switch (ni_660x_gate_select) {
1388 case NI_660x_Source_Pin_i_Second_Gate_Select:
1389 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1391 case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
1392 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1394 case NI_660x_Next_SRC_Second_Gate_Select:
1395 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1397 case NI_660x_Next_Out_Second_Gate_Select:
1398 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1400 case NI_660x_Selected_Gate_Second_Gate_Select:
1401 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1403 case NI_660x_Logic_Low_Second_Gate_Select:
1404 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1407 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1408 if (ni_660x_gate_select ==
1409 NI_660x_RTSI_Second_Gate_Select(i)) {
1410 return NI_GPCT_RTSI_GATE_SELECT(i);
1414 if (i <= ni_660x_max_rtsi_channel)
1416 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1417 if (ni_660x_gate_select ==
1418 NI_660x_Up_Down_Pin_Second_Gate_Select(i)) {
1419 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1423 if (i <= ni_660x_max_up_down_pin)
1431 static unsigned ni_m_series_second_gate_to_generic_gate_source(unsigned
1432 ni_m_series_gate_select)
1434 /*FIXME: the second gate sources for the m series are undocumented, so we just return
1435 * the raw bits for now. */
1436 switch (ni_m_series_gate_select) {
1438 return ni_m_series_gate_select;
1444 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
1445 unsigned int * gate_source)
1447 struct ni_gpct_device *counter_dev = counter->counter_dev;
1448 const unsigned mode_bits = ni_tio_get_soft_copy(counter,
1449 NITIO_Gi_Mode_Reg(counter->counter_index));
1450 const unsigned second_gate_reg =
1451 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1452 unsigned gate_select_bits;
1454 switch (gate_index) {
1456 if ((mode_bits & Gi_Gating_Mode_Mask) ==
1457 Gi_Gating_Disabled_Bits) {
1458 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1462 (ni_tio_get_soft_copy(counter,
1463 NITIO_Gi_Input_Select_Reg(counter->
1465 Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
1467 switch (counter_dev->variant) {
1468 case ni_gpct_variant_e_series:
1469 case ni_gpct_variant_m_series:
1471 ni_m_series_first_gate_to_generic_gate_source
1474 case ni_gpct_variant_660x:
1476 ni_660x_first_gate_to_generic_gate_source
1483 if (mode_bits & Gi_Gate_Polarity_Bit) {
1484 *gate_source |= CR_INVERT;
1486 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits) {
1487 *gate_source |= CR_EDGE;
1491 if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
1493 regs[second_gate_reg] & Gi_Second_Gate_Mode_Bit)
1495 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1500 regs[second_gate_reg] &
1501 Gi_Second_Gate_Select_Mask) >>
1502 Gi_Second_Gate_Select_Shift;
1504 switch (counter_dev->variant) {
1505 case ni_gpct_variant_e_series:
1506 case ni_gpct_variant_m_series:
1508 ni_m_series_second_gate_to_generic_gate_source
1511 case ni_gpct_variant_660x:
1513 ni_660x_second_gate_to_generic_gate_source
1521 regs[second_gate_reg] & Gi_Second_Gate_Polarity_Bit) {
1522 *gate_source |= CR_INVERT;
1524 /* second gate can't have edge/level mode set independently */
1525 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits) {
1526 *gate_source |= CR_EDGE;
1536 int ni_tio_insn_config(struct ni_gpct *counter,
1537 struct comedi_insn * insn, unsigned int * data)
1540 case INSN_CONFIG_SET_COUNTER_MODE:
1541 return ni_tio_set_counter_mode(counter, data[1]);
1543 case INSN_CONFIG_ARM:
1544 return ni_tio_arm(counter, 1, data[1]);
1546 case INSN_CONFIG_DISARM:
1547 ni_tio_arm(counter, 0, 0);
1550 case INSN_CONFIG_GET_COUNTER_STATUS:
1551 data[1] = ni_tio_counter_status(counter);
1552 data[2] = counter_status_mask;
1555 case INSN_CONFIG_SET_CLOCK_SRC:
1556 return ni_tio_set_clock_src(counter, data[1], data[2]);
1558 case INSN_CONFIG_GET_CLOCK_SRC:
1559 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1562 case INSN_CONFIG_SET_GATE_SRC:
1563 return ni_tio_set_gate_src(counter, data[1], data[2]);
1565 case INSN_CONFIG_GET_GATE_SRC:
1566 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1568 case INSN_CONFIG_SET_OTHER_SRC:
1569 return ni_tio_set_other_src(counter, data[1], data[2]);
1571 case INSN_CONFIG_RESET:
1572 ni_tio_reset_count_and_disarm(counter);
1581 int ni_tio_rinsn(struct ni_gpct *counter, struct comedi_insn * insn, unsigned int * data)
1583 struct ni_gpct_device *counter_dev = counter->counter_dev;
1584 const unsigned channel = CR_CHAN(insn->chanspec);
1585 unsigned first_read;
1586 unsigned second_read;
1587 unsigned correct_read;
1593 ni_tio_set_bits(counter,
1594 NITIO_Gi_Command_Reg(counter->counter_index),
1595 Gi_Save_Trace_Bit, 0);
1596 ni_tio_set_bits(counter,
1597 NITIO_Gi_Command_Reg(counter->counter_index),
1598 Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
1599 /* The count doesn't get latched until the next clock edge, so it is possible the count
1600 may change (once) while we are reading. Since the read of the SW_Save_Reg isn't
1601 atomic (apparently even when it's a 32 bit register according to 660x docs),
1602 we need to read twice and make sure the reading hasn't changed. If it has,
1603 a third read will be correct since the count value will definitely have latched by then. */
1605 read_register(counter,
1606 NITIO_Gi_SW_Save_Reg(counter->counter_index));
1608 read_register(counter,
1609 NITIO_Gi_SW_Save_Reg(counter->counter_index));
1610 if (first_read != second_read)
1612 read_register(counter,
1613 NITIO_Gi_SW_Save_Reg(counter->counter_index));
1615 correct_read = first_read;
1616 data[0] = correct_read;
1621 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->
1626 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->
1633 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1635 const unsigned bits = read_register(counter,
1636 NITIO_Gxx_Status_Reg(counter->counter_index));
1638 if (bits & Gi_Next_Load_Source_Bit(counter->counter_index)) {
1639 return NITIO_Gi_LoadB_Reg(counter->counter_index);
1641 return NITIO_Gi_LoadA_Reg(counter->counter_index);
1645 int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn * insn, unsigned int * data)
1647 struct ni_gpct_device *counter_dev = counter->counter_dev;
1648 const unsigned channel = CR_CHAN(insn->chanspec);
1655 /* Unsafe if counter is armed. Should probably check status and return -EBUSY if armed. */
1656 /* Don't disturb load source select, just use whichever load register is already selected. */
1657 load_reg = ni_tio_next_load_register(counter);
1658 write_register(counter, data[0], load_reg);
1659 ni_tio_set_bits_transient(counter,
1660 NITIO_Gi_Command_Reg(counter->counter_index), 0, 0,
1662 /* restore state of load reg to whatever the user set last set it to */
1663 write_register(counter, counter_dev->regs[load_reg], load_reg);
1666 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] =
1668 write_register(counter, data[0],
1669 NITIO_Gi_LoadA_Reg(counter->counter_index));
1672 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] =
1674 write_register(counter, data[0],
1675 NITIO_Gi_LoadB_Reg(counter->counter_index));
1684 EXPORT_SYMBOL_GPL(ni_tio_rinsn);
1685 EXPORT_SYMBOL_GPL(ni_tio_winsn);
1686 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1687 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1688 EXPORT_SYMBOL_GPL(ni_tio_arm);
1689 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1690 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1691 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);