2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments PCI-MIO-E series and M series (all boards)
25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
33 PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
35 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
36 PXI-6071E, PCI-6070E, PXI-6070E,
37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
39 Updated: Wed, 03 Dec 2008 10:51:47 +0000
41 These boards are almost identical to the AT-MIO E series, except that
42 they use the PCI bus instead of ISA (i.e., AT). See the notes for
43 the ni_atmio.o driver for additional information about these boards.
45 Autocalibration is supported on many of the devices, using the
46 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
47 M-Series boards do analog input and analog output calibration entirely
48 in software. The software calibration corrects
49 the analog input for offset, gain and
50 nonlinearity. The analog outputs are corrected for offset and gain.
51 See the comedilib documentation on comedi_get_softcal_converter() for
54 By default, the driver uses DMA to transfer analog input data to
55 memory. When DMA is enabled, not all triggering features are
58 Digital I/O may not work on 673x.
60 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
61 With this board all of the convertors perform one simultaineous sample during
62 a scan interval. The period for a scan is used for the convert time in a
63 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
65 The RTSI trigger bus is supported on these cards on
66 subdevice 10. See the comedilib documentation for details.
68 Information (number of channels, bits, etc.) for some devices may be
69 incorrect. Please check this and submit a bug if there are problems
72 SCXI is probably broken for m-series boards.
75 - When DMA is enabled, COMEDI_EV_CONVERT does
80 The PCI-MIO E series driver was originally written by
81 Tomasz Motylewski <...>, and ported to comedi by ds.
85 341079b.pdf PCI E Series Register-Level Programmer Manual
86 340934b.pdf DAQ-STC reference manual
88 322080b.pdf 6711/6713/6715 User Manual
90 320945c.pdf PCI E Series User Manual
91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
95 need to deal with external reference for DAC, and other DAC
96 properties in board properties
98 deal with at-mio-16de-10 revision D to N changes, etc.
100 need to add other CALDAC type
102 need to slow down DAC loading. I don't trust NI's claim that
103 two writes to the PCI bus slows IO enough. I would prefer to
104 use udelay(). Timing specs: (clock)
112 #include "../comedidev.h"
114 #include <asm/byteorder.h>
115 #include <linux/delay.h>
120 /* #define PCI_DEBUG */
127 #define MAX_N_CALDACS (16+16+2)
129 #define DRV_NAME "ni_pcimio"
131 /* The following two tables must be in the same order */
132 static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = {
133 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0162)},
134 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1170)},
135 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1180)},
136 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1190)},
137 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11b0)},
138 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11c0)},
139 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11d0)},
140 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1270)},
141 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1330)},
142 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1340)},
143 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1350)},
144 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14e0)},
145 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14f0)},
146 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1580)},
147 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x15b0)},
148 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1880)},
149 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1870)},
150 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18b0)},
151 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18c0)},
152 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2410)},
153 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2420)},
154 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2430)},
155 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2890)},
156 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x28c0)},
157 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a60)},
158 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a70)},
159 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a80)},
160 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ab0)},
161 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b80)},
162 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b90)},
163 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c80)},
164 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ca0)},
165 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70aa)},
166 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ab)},
167 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ac)},
168 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70af)},
169 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b0)},
170 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b4)},
171 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b6)},
172 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b7)},
173 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b8)},
174 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bc)},
175 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bd)},
176 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bf)},
177 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c0)},
178 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70f2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x710d)},
180 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716c)},
181 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716d)},
182 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717f)},
183 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71bc)},
184 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717d)},
188 MODULE_DEVICE_TABLE(pci, ni_pci_table);
190 /* These are not all the possible ao ranges for 628x boards.
191 They can do OFFSET +- REFERENCE where OFFSET can be
192 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
193 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
194 63 different possibilities. An AO channel
195 can not act as it's own OFFSET or REFERENCE.
197 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
210 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
217 static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
222 static const struct ni_board_struct ni_boards[] = {
224 .device_id = 0x0162, /* NI also says 0x1620. typo? */
225 .name = "pci-mio-16xe-50",
228 .ai_fifo_depth = 2048,
230 .gainlkup = ai_gain_8,
235 .ao_range_table = &range_bipolar10,
238 .num_p0_dio_channels = 8,
239 .caldac = {dac8800, dac8043},
244 .name = "pci-mio-16xe-10", /* aka pci-6030E */
247 .ai_fifo_depth = 512,
249 .gainlkup = ai_gain_14,
253 .ao_fifo_depth = 2048,
254 .ao_range_table = &range_ni_E_ao_ext,
257 .num_p0_dio_channels = 8,
258 .caldac = {dac8800, dac8043, ad8522},
266 .ai_fifo_depth = 512,
268 .gainlkup = ai_gain_4,
273 .ao_range_table = &range_bipolar10,
276 .num_p0_dio_channels = 8,
277 .caldac = {ad8804_debug},
285 .ai_fifo_depth = 512,
287 .gainlkup = ai_gain_14,
291 .ao_fifo_depth = 2048,
292 .ao_range_table = &range_ni_E_ao_ext,
295 .num_p0_dio_channels = 8,
296 .caldac = {dac8800, dac8043, ad8522},
301 .name = "pci-mio-16e-1", /* aka pci-6070e */
304 .ai_fifo_depth = 512,
306 .gainlkup = ai_gain_16,
310 .ao_fifo_depth = 2048,
311 .ao_range_table = &range_ni_E_ao_ext,
314 .num_p0_dio_channels = 8,
320 .name = "pci-mio-16e-4", /* aka pci-6040e */
323 .ai_fifo_depth = 512,
325 .gainlkup = ai_gain_16,
326 /* .Note = there have been reported problems with full speed
331 .ao_fifo_depth = 512,
332 .ao_range_table = &range_ni_E_ao_ext,
335 .num_p0_dio_channels = 8,
336 .caldac = {ad8804_debug}, /* doc says mb88341 */
344 .ai_fifo_depth = 512,
346 .gainlkup = ai_gain_16,
350 .ao_fifo_depth = 512,
351 .ao_range_table = &range_ni_E_ao_ext,
354 .num_p0_dio_channels = 8,
364 .ai_fifo_depth = 512,
366 .gainlkup = ai_gain_14,
370 .ao_fifo_depth = 2048,
371 .ao_range_table = &range_ni_E_ao_ext,
374 .num_p0_dio_channels = 8,
375 .caldac = {dac8800, dac8043, ad8522},
383 .ai_fifo_depth = 512,
385 .gainlkup = ai_gain_14,
391 .num_p0_dio_channels = 8,
392 .caldac = {dac8800, dac8043, ad8522},
400 .ai_fifo_depth = 512,
402 .gainlkup = ai_gain_14,
408 .num_p0_dio_channels = 8,
409 .caldac = {dac8800, dac8043, ad8522},
417 .ai_fifo_depth = 512,
419 .gainlkup = ai_gain_16,
423 .ao_fifo_depth = 2048,
424 .ao_range_table = &range_ni_E_ao_ext,
427 .num_p0_dio_channels = 8,
428 .caldac = {ad8804_debug},
436 .ai_fifo_depth = 512,
438 .gainlkup = ai_gain_4,
443 .num_p0_dio_channels = 8,
444 .caldac = {ad8804_debug}, /* manual is wrong */
452 .ai_fifo_depth = 512,
454 .gainlkup = ai_gain_4,
459 .ao_range_table = &range_bipolar10,
462 .num_p0_dio_channels = 8,
463 .caldac = {ad8804_debug}, /* manual is wrong */
471 .ai_fifo_depth = 512,
473 .gainlkup = ai_gain_4,
478 .ao_range_table = &range_bipolar10,
481 .num_p0_dio_channels = 8,
482 .caldac = {ad8804_debug}, /* manual is wrong */
490 .ai_fifo_depth = 512,
492 .gainlkup = ai_gain_4,
497 .ao_range_table = &range_ni_E_ao_ext,
500 .num_p0_dio_channels = 8,
501 .caldac = {ad8804_debug}, /* manual is wrong */
510 .ai_fifo_depth = 512,
512 .gainlkup = ai_gain_4,
518 .num_p0_dio_channels = 8,
519 .caldac = {ad8804_debug},
527 .ai_fifo_depth = 512,
529 .gainlkup = ai_gain_4,
534 .ao_range_table = &range_bipolar10,
537 .num_p0_dio_channels = 8,
538 .caldac = {ad8804_debug},
546 .ai_fifo_depth = 512,
548 .gainlkup = ai_gain_16,
553 .ao_fifo_depth = 2048,
554 .ao_range_table = &range_ni_E_ao_ext,
556 .num_p0_dio_channels = 8,
557 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */
559 {.device_id = 0x14e0,
563 .ai_fifo_depth = 8192,
565 .gainlkup = ai_gain_611x,
569 .reg_type = ni_reg_611x,
570 .ao_range_table = &range_bipolar10,
572 .ao_fifo_depth = 2048,
574 .num_p0_dio_channels = 8,
575 .caldac = {ad8804, ad8804},
582 .ai_fifo_depth = 8192,
584 .gainlkup = ai_gain_611x,
588 .reg_type = ni_reg_611x,
589 .ao_range_table = &range_bipolar10,
591 .ao_fifo_depth = 2048,
593 .num_p0_dio_channels = 8,
594 .caldac = {ad8804, ad8804},
597 /* The 6115 boards probably need their own driver */
603 .ai_fifo_depth = 8192,
605 .gainlkup = ai_gain_611x,
611 .ao_fifo_depth = 2048,
613 .num_p0_dio_channels = 8,
615 .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
624 .ai_fifo_depth = 8192,
626 .gainlkup = ai_gain_611x,
632 .ao_fifo_depth = 2048,
635 .num_p0_dio_channels = 8,
636 caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
642 .n_adchan = 0, /* no analog input */
646 .ao_fifo_depth = 16384,
647 /* data sheet says 8192, but fifo really holds 16384 samples */
648 .ao_range_table = &range_bipolar10,
650 .num_p0_dio_channels = 8,
651 .reg_type = ni_reg_6711,
652 .caldac = {ad8804_debug},
657 .n_adchan = 0, /* no analog input */
661 .ao_fifo_depth = 16384,
662 .ao_range_table = &range_bipolar10,
664 .num_p0_dio_channels = 8,
665 .reg_type = ni_reg_6711,
666 .caldac = {ad8804_debug},
671 .n_adchan = 0, /* no analog input */
675 .ao_fifo_depth = 16384,
676 .ao_range_table = &range_bipolar10,
678 .num_p0_dio_channels = 8,
679 .reg_type = ni_reg_6713,
680 .caldac = {ad8804_debug, ad8804_debug},
685 .n_adchan = 0, /* no analog input */
689 .ao_fifo_depth = 16384,
690 .ao_range_table = &range_bipolar10,
692 .num_p0_dio_channels = 8,
693 .reg_type = ni_reg_6713,
694 .caldac = {ad8804_debug, ad8804_debug},
699 .n_adchan = 0, /* no analog input */
703 .ao_fifo_depth = 8192,
704 .ao_range_table = &range_bipolar10,
706 .num_p0_dio_channels = 8,
707 .reg_type = ni_reg_6711,
708 .caldac = {ad8804_debug},
710 #if 0 /* need device ids */
714 .n_adchan = 0, /* no analog input */
718 .ao_fifo_depth = 8192,
719 .ao_range_table = &range_bipolar10,
720 .num_p0_dio_channels = 8,
721 .reg_type = ni_reg_6711,
722 .caldac = {ad8804_debug},
728 .n_adchan = 0, /* no analog input */
732 .ao_fifo_depth = 16384,
733 .ao_range_table = &range_bipolar10,
735 .num_p0_dio_channels = 8,
736 .reg_type = ni_reg_6713,
737 .caldac = {ad8804_debug, ad8804_debug},
742 .n_adchan = 0, /* no analog input */
746 .ao_fifo_depth = 16384,
747 .ao_range_table = &range_bipolar10,
749 .num_p0_dio_channels = 8,
750 .reg_type = ni_reg_6713,
751 .caldac = {ad8804_debug, ad8804_debug},
758 .ai_fifo_depth = 512,
760 .gainlkup = ai_gain_16,
764 .ao_fifo_depth = 2048,
765 .ao_range_table = &range_ni_E_ao_ext,
768 .num_p0_dio_channels = 8,
769 .caldac = {ad8804_debug},
777 .ai_fifo_depth = 512,
779 .gainlkup = ai_gain_16,
783 .ao_fifo_depth = 2048,
784 .ao_range_table = &range_ni_E_ao_ext,
787 .num_p0_dio_channels = 8,
788 .caldac = {ad8804_debug},
796 .ai_fifo_depth = 512,
798 .gainlkup = ai_gain_16,
803 .ao_fifo_depth = 2048,
804 .ao_range_table = &range_ni_E_ao_ext,
806 .num_p0_dio_channels = 8,
807 .caldac = {mb88341, mb88341, ad8522},
814 .ai_fifo_depth = 512,
816 .gainlkup = ai_gain_14,
820 .ao_fifo_depth = 2048,
821 .ao_range_table = &range_ni_E_ao_ext,
824 .num_p0_dio_channels = 8,
825 .caldac = {dac8800, dac8043, ad8522},
832 .ai_fifo_depth = 512,
834 .gainlkup = ai_gain_4,
839 .ao_range_table = &range_bipolar10,
842 .num_p0_dio_channels = 8,
843 .caldac = {ad8804_debug},
851 .ai_fifo_depth = 512,
853 .gainlkup = ai_gain_622x,
858 .num_p0_dio_channels = 8,
859 .reg_type = ni_reg_622x,
861 .caldac = {caldac_none},
869 .ai_fifo_depth = 4095,
870 .gainlkup = ai_gain_622x,
874 .ao_fifo_depth = 8191,
875 .ao_range_table = &range_ni_M_622x_ao,
876 .reg_type = ni_reg_622x,
879 .num_p0_dio_channels = 8,
880 .caldac = {caldac_none},
885 .name = "pci-6221_37pin",
888 .ai_fifo_depth = 4095,
889 .gainlkup = ai_gain_622x,
893 .ao_fifo_depth = 8191,
894 .ao_range_table = &range_ni_M_622x_ao,
895 .reg_type = ni_reg_622x,
898 .num_p0_dio_channels = 8,
899 .caldac = {caldac_none},
907 .ai_fifo_depth = 4095,
908 .gainlkup = ai_gain_622x,
913 .reg_type = ni_reg_622x,
915 .num_p0_dio_channels = 32,
916 .caldac = {caldac_none},
924 .ai_fifo_depth = 4095,
925 .gainlkup = ai_gain_622x,
930 .reg_type = ni_reg_622x,
932 .num_p0_dio_channels = 32,
933 .caldac = {caldac_none},
941 .ai_fifo_depth = 4095,
942 .gainlkup = ai_gain_622x,
946 .ao_fifo_depth = 8191,
947 .ao_range_table = &range_ni_M_622x_ao,
948 .reg_type = ni_reg_622x,
951 .num_p0_dio_channels = 32,
952 .caldac = {caldac_none},
960 .ai_fifo_depth = 4095,
961 .gainlkup = ai_gain_622x,
965 .ao_fifo_depth = 8191,
966 .ao_range_table = &range_ni_M_622x_ao,
967 .reg_type = ni_reg_622x,
970 .num_p0_dio_channels = 32,
971 .caldac = {caldac_none},
979 .ai_fifo_depth = 4095,
980 .gainlkup = ai_gain_622x,
984 .ao_fifo_depth = 8191,
985 .ao_range_table = &range_ni_M_622x_ao,
986 .reg_type = ni_reg_622x,
989 .num_p0_dio_channels = 32,
990 .caldac = {caldac_none},
998 .ai_fifo_depth = 4095,
999 .gainlkup = ai_gain_628x,
1004 .reg_type = ni_reg_625x,
1006 .num_p0_dio_channels = 8,
1007 .caldac = {caldac_none},
1011 .device_id = 0x70b8,
1015 .ai_fifo_depth = 4095,
1016 .gainlkup = ai_gain_628x,
1020 .ao_fifo_depth = 8191,
1021 .ao_range_table = &range_ni_M_625x_ao,
1022 .reg_type = ni_reg_625x,
1025 .num_p0_dio_channels = 8,
1026 .caldac = {caldac_none},
1030 .device_id = 0x717d,
1031 .name = "pcie-6251",
1034 .ai_fifo_depth = 4095,
1035 .gainlkup = ai_gain_628x,
1039 .ao_fifo_depth = 8191,
1040 .ao_range_table = &range_ni_M_625x_ao,
1041 .reg_type = ni_reg_625x,
1044 .num_p0_dio_channels = 8,
1045 .caldac = {caldac_none},
1049 .device_id = 0x70b7,
1053 .ai_fifo_depth = 4095,
1054 .gainlkup = ai_gain_628x,
1059 .reg_type = ni_reg_625x,
1061 .num_p0_dio_channels = 32,
1062 .caldac = {caldac_none},
1066 .device_id = 0x70ab,
1070 .ai_fifo_depth = 4095,
1071 .gainlkup = ai_gain_628x,
1075 .ao_fifo_depth = 8191,
1076 .ao_range_table = &range_ni_M_625x_ao,
1077 .reg_type = ni_reg_625x,
1080 .num_p0_dio_channels = 32,
1081 .caldac = {caldac_none},
1085 .device_id = 0x717f,
1086 .name = "pcie-6259",
1089 .ai_fifo_depth = 4095,
1090 .gainlkup = ai_gain_628x,
1094 .ao_fifo_depth = 8191,
1095 .ao_range_table = &range_ni_M_625x_ao,
1096 .reg_type = ni_reg_625x,
1099 .num_p0_dio_channels = 32,
1100 .caldac = {caldac_none},
1104 .device_id = 0x70b6,
1108 .ai_fifo_depth = 2047,
1109 .gainlkup = ai_gain_628x,
1113 .ao_fifo_depth = 8191,
1114 .reg_type = ni_reg_628x,
1116 .num_p0_dio_channels = 8,
1117 .caldac = {caldac_none},
1121 .device_id = 0x70bd,
1125 .ai_fifo_depth = 2047,
1126 .gainlkup = ai_gain_628x,
1130 .ao_fifo_depth = 8191,
1131 .ao_range_table = &range_ni_M_628x_ao,
1132 .reg_type = ni_reg_628x,
1135 .num_p0_dio_channels = 8,
1136 .caldac = {caldac_none},
1140 .device_id = 0x70bf,
1144 .ai_fifo_depth = 2047,
1145 .gainlkup = ai_gain_628x,
1149 .ao_fifo_depth = 8191,
1150 .ao_range_table = &range_ni_M_628x_ao,
1151 .reg_type = ni_reg_628x,
1154 .num_p0_dio_channels = 8,
1155 .caldac = {caldac_none},
1159 .device_id = 0x70bc,
1163 .ai_fifo_depth = 2047,
1164 .gainlkup = ai_gain_628x,
1169 .reg_type = ni_reg_628x,
1171 .num_p0_dio_channels = 32,
1172 .caldac = {caldac_none},
1176 .device_id = 0x70ac,
1180 .ai_fifo_depth = 2047,
1181 .gainlkup = ai_gain_628x,
1185 .ao_fifo_depth = 8191,
1186 .ao_range_table = &range_ni_M_628x_ao,
1187 .reg_type = ni_reg_628x,
1190 .num_p0_dio_channels = 32,
1191 .caldac = {caldac_none},
1195 .device_id = 0x70C0,
1199 .ai_fifo_depth = 1024,
1201 .gainlkup = ai_gain_6143,
1205 .reg_type = ni_reg_6143,
1208 .num_p0_dio_channels = 8,
1209 .caldac = {ad8804_debug, ad8804_debug},
1212 .device_id = 0x710D,
1216 .ai_fifo_depth = 1024,
1218 .gainlkup = ai_gain_6143,
1222 .reg_type = ni_reg_6143,
1225 .num_p0_dio_channels = 8,
1226 .caldac = {ad8804_debug, ad8804_debug},
1230 #define n_pcimio_boards ARRAY_SIZE(ni_boards)
1232 static int pcimio_attach(struct comedi_device *dev,
1233 struct comedi_devconfig *it);
1234 static int pcimio_detach(struct comedi_device *dev);
1235 static struct comedi_driver driver_pcimio = {
1236 .driver_name = DRV_NAME,
1237 .module = THIS_MODULE,
1238 .attach = pcimio_attach,
1239 .detach = pcimio_detach,
1242 COMEDI_PCI_INITCLEANUP(driver_pcimio, ni_pci_table)
1246 #define devpriv ((struct ni_private *)dev->private)
1248 /* How we access registers */
1250 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1251 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1252 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1253 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1254 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1255 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1257 /* How we access STC registers */
1259 /* We automatically take advantage of STC registers that can be
1260 * read/written directly in the I/O space of the board. Most
1261 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1262 * The 611x devices map the write registers to iobase+addr*2, and
1263 * the read registers to iobase+(addr-1)*2. */
1264 /* However, the 611x boards still aren't working, so I'm disabling
1265 * non-windowed STC access temporarily */
1267 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1269 unsigned long flags;
1271 spin_lock_irqsave(&devpriv->window_lock, flags);
1272 ni_writew(reg, Window_Address);
1273 ni_writew(data, Window_Data);
1274 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1277 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1279 unsigned long flags;
1282 spin_lock_irqsave(&devpriv->window_lock, flags);
1283 ni_writew(reg, Window_Address);
1284 ret = ni_readw(Window_Data);
1285 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1290 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1295 case ADC_FIFO_Clear:
1296 offset = M_Offset_AI_FIFO_Clear;
1298 case AI_Command_1_Register:
1299 offset = M_Offset_AI_Command_1;
1301 case AI_Command_2_Register:
1302 offset = M_Offset_AI_Command_2;
1304 case AI_Mode_1_Register:
1305 offset = M_Offset_AI_Mode_1;
1307 case AI_Mode_2_Register:
1308 offset = M_Offset_AI_Mode_2;
1310 case AI_Mode_3_Register:
1311 offset = M_Offset_AI_Mode_3;
1313 case AI_Output_Control_Register:
1314 offset = M_Offset_AI_Output_Control;
1316 case AI_Personal_Register:
1317 offset = M_Offset_AI_Personal;
1319 case AI_SI2_Load_A_Register:
1320 /* this is actually a 32 bit register on m series boards */
1321 ni_writel(data, M_Offset_AI_SI2_Load_A);
1324 case AI_SI2_Load_B_Register:
1325 /* this is actually a 32 bit register on m series boards */
1326 ni_writel(data, M_Offset_AI_SI2_Load_B);
1329 case AI_START_STOP_Select_Register:
1330 offset = M_Offset_AI_START_STOP_Select;
1332 case AI_Trigger_Select_Register:
1333 offset = M_Offset_AI_Trigger_Select;
1335 case Analog_Trigger_Etc_Register:
1336 offset = M_Offset_Analog_Trigger_Etc;
1338 case AO_Command_1_Register:
1339 offset = M_Offset_AO_Command_1;
1341 case AO_Command_2_Register:
1342 offset = M_Offset_AO_Command_2;
1344 case AO_Mode_1_Register:
1345 offset = M_Offset_AO_Mode_1;
1347 case AO_Mode_2_Register:
1348 offset = M_Offset_AO_Mode_2;
1350 case AO_Mode_3_Register:
1351 offset = M_Offset_AO_Mode_3;
1353 case AO_Output_Control_Register:
1354 offset = M_Offset_AO_Output_Control;
1356 case AO_Personal_Register:
1357 offset = M_Offset_AO_Personal;
1359 case AO_Start_Select_Register:
1360 offset = M_Offset_AO_Start_Select;
1362 case AO_Trigger_Select_Register:
1363 offset = M_Offset_AO_Trigger_Select;
1365 case Clock_and_FOUT_Register:
1366 offset = M_Offset_Clock_and_FOUT;
1368 case Configuration_Memory_Clear:
1369 offset = M_Offset_Configuration_Memory_Clear;
1371 case DAC_FIFO_Clear:
1372 offset = M_Offset_AO_FIFO_Clear;
1374 case DIO_Control_Register:
1376 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1380 case G_Autoincrement_Register(0):
1381 offset = M_Offset_G0_Autoincrement;
1383 case G_Autoincrement_Register(1):
1384 offset = M_Offset_G1_Autoincrement;
1386 case G_Command_Register(0):
1387 offset = M_Offset_G0_Command;
1389 case G_Command_Register(1):
1390 offset = M_Offset_G1_Command;
1392 case G_Input_Select_Register(0):
1393 offset = M_Offset_G0_Input_Select;
1395 case G_Input_Select_Register(1):
1396 offset = M_Offset_G1_Input_Select;
1398 case G_Mode_Register(0):
1399 offset = M_Offset_G0_Mode;
1401 case G_Mode_Register(1):
1402 offset = M_Offset_G1_Mode;
1404 case Interrupt_A_Ack_Register:
1405 offset = M_Offset_Interrupt_A_Ack;
1407 case Interrupt_A_Enable_Register:
1408 offset = M_Offset_Interrupt_A_Enable;
1410 case Interrupt_B_Ack_Register:
1411 offset = M_Offset_Interrupt_B_Ack;
1413 case Interrupt_B_Enable_Register:
1414 offset = M_Offset_Interrupt_B_Enable;
1416 case Interrupt_Control_Register:
1417 offset = M_Offset_Interrupt_Control;
1419 case IO_Bidirection_Pin_Register:
1420 offset = M_Offset_IO_Bidirection_Pin;
1422 case Joint_Reset_Register:
1423 offset = M_Offset_Joint_Reset;
1425 case RTSI_Trig_A_Output_Register:
1426 offset = M_Offset_RTSI_Trig_A_Output;
1428 case RTSI_Trig_B_Output_Register:
1429 offset = M_Offset_RTSI_Trig_B_Output;
1431 case RTSI_Trig_Direction_Register:
1432 offset = M_Offset_RTSI_Trig_Direction;
1434 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1435 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1437 printk("%s: bug! unhandled register=0x%x in switch.\n",
1443 ni_writew(data, offset);
1446 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1450 case AI_Status_1_Register:
1451 offset = M_Offset_AI_Status_1;
1453 case AO_Status_1_Register:
1454 offset = M_Offset_AO_Status_1;
1456 case AO_Status_2_Register:
1457 offset = M_Offset_AO_Status_2;
1459 case DIO_Serial_Input_Register:
1460 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1462 case Joint_Status_1_Register:
1463 offset = M_Offset_Joint_Status_1;
1465 case Joint_Status_2_Register:
1466 offset = M_Offset_Joint_Status_2;
1468 case G_Status_Register:
1469 offset = M_Offset_G01_Status;
1472 printk("%s: bug! unhandled register=0x%x in switch.\n",
1478 return ni_readw(offset);
1481 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1486 case AI_SC_Load_A_Registers:
1487 offset = M_Offset_AI_SC_Load_A;
1489 case AI_SI_Load_A_Registers:
1490 offset = M_Offset_AI_SI_Load_A;
1492 case AO_BC_Load_A_Register:
1493 offset = M_Offset_AO_BC_Load_A;
1495 case AO_UC_Load_A_Register:
1496 offset = M_Offset_AO_UC_Load_A;
1498 case AO_UI_Load_A_Register:
1499 offset = M_Offset_AO_UI_Load_A;
1501 case G_Load_A_Register(0):
1502 offset = M_Offset_G0_Load_A;
1504 case G_Load_A_Register(1):
1505 offset = M_Offset_G1_Load_A;
1507 case G_Load_B_Register(0):
1508 offset = M_Offset_G0_Load_B;
1510 case G_Load_B_Register(1):
1511 offset = M_Offset_G1_Load_B;
1514 printk("%s: bug! unhandled register=0x%x in switch.\n",
1520 ni_writel(data, offset);
1523 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1527 case G_HW_Save_Register(0):
1528 offset = M_Offset_G0_HW_Save;
1530 case G_HW_Save_Register(1):
1531 offset = M_Offset_G1_HW_Save;
1533 case G_Save_Register(0):
1534 offset = M_Offset_G0_Save;
1536 case G_Save_Register(1):
1537 offset = M_Offset_G1_Save;
1540 printk("%s: bug! unhandled register=0x%x in switch.\n",
1546 return ni_readl(offset);
1549 #define interrupt_pin(a) 0
1550 #define IRQ_POLARITY 1
1552 #define NI_E_IRQ_FLAGS IRQF_SHARED
1554 #include "ni_mio_common.c"
1556 static int pcimio_find_device(struct comedi_device *dev, int bus, int slot);
1557 static int pcimio_ai_change(struct comedi_device *dev,
1558 struct comedi_subdevice *s, unsigned long new_size);
1559 static int pcimio_ao_change(struct comedi_device *dev,
1560 struct comedi_subdevice *s, unsigned long new_size);
1561 static int pcimio_gpct0_change(struct comedi_device *dev,
1562 struct comedi_subdevice *s,
1563 unsigned long new_size);
1564 static int pcimio_gpct1_change(struct comedi_device *dev,
1565 struct comedi_subdevice *s,
1566 unsigned long new_size);
1567 static int pcimio_dio_change(struct comedi_device *dev,
1568 struct comedi_subdevice *s,
1569 unsigned long new_size);
1571 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1573 static const int Start_Cal_EEPROM = 0x400;
1574 static const unsigned window_size = 10;
1575 static const int serial_number_eeprom_offset = 0x4;
1576 static const int serial_number_eeprom_length = 0x4;
1577 unsigned old_iodwbsr_bits;
1578 unsigned old_iodwbsr1_bits;
1579 unsigned old_iodwcr1_bits;
1582 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1583 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1584 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1585 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1586 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1587 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1588 writel(0x1 | old_iodwcr1_bits,
1589 devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1590 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1592 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1593 for (i = 0; i < serial_number_eeprom_length; ++i) {
1594 char *byte_ptr = (char *)&devpriv->serial_number + i;
1595 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1597 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1599 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) {
1600 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1603 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1604 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1605 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1606 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1609 static void init_6143(struct comedi_device *dev)
1611 /* Disable interrupts */
1612 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1614 /* Initialise 6143 AI specific bits */
1615 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */
1616 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */
1617 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */
1619 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Set the FIFO half full level */
1621 /* Strobe Relay disable bit */
1622 devpriv->ai_calib_source_enabled = 0;
1623 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1624 Calibration_Channel_6143);
1625 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1628 /* cleans up allocated resources */
1629 static int pcimio_detach(struct comedi_device *dev)
1631 mio_common_detach(dev);
1633 free_irq(dev->irq, dev);
1636 mite_free_ring(devpriv->ai_mite_ring);
1637 mite_free_ring(devpriv->ao_mite_ring);
1638 mite_free_ring(devpriv->cdo_mite_ring);
1639 mite_free_ring(devpriv->gpct_mite_ring[0]);
1640 mite_free_ring(devpriv->gpct_mite_ring[1]);
1642 mite_unsetup(devpriv->mite);
1648 static int pcimio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1652 printk("comedi%d: ni_pcimio:", dev->minor);
1654 ret = ni_alloc_private(dev);
1658 ret = pcimio_find_device(dev, it->options[0], it->options[1]);
1662 printk(" %s", boardtype.name);
1663 dev->board_name = boardtype.name;
1665 if (boardtype.reg_type & ni_reg_m_series_mask) {
1666 devpriv->stc_writew = &m_series_stc_writew;
1667 devpriv->stc_readw = &m_series_stc_readw;
1668 devpriv->stc_writel = &m_series_stc_writel;
1669 devpriv->stc_readl = &m_series_stc_readl;
1671 devpriv->stc_writew = &e_series_win_out;
1672 devpriv->stc_readw = &e_series_win_in;
1673 devpriv->stc_writel = &win_out2;
1674 devpriv->stc_readl = &win_in2;
1677 ret = mite_setup(devpriv->mite);
1679 printk(" error setting up mite\n");
1682 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1683 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1684 if (devpriv->ai_mite_ring == NULL)
1686 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1687 if (devpriv->ao_mite_ring == NULL)
1689 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1690 if (devpriv->cdo_mite_ring == NULL)
1692 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1693 if (devpriv->gpct_mite_ring[0] == NULL)
1695 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1696 if (devpriv->gpct_mite_ring[1] == NULL)
1699 if (boardtype.reg_type & ni_reg_m_series_mask)
1700 m_series_init_eeprom_buffer(dev);
1701 if (boardtype.reg_type == ni_reg_6143)
1704 dev->irq = mite_irq(devpriv->mite);
1706 if (dev->irq == 0) {
1707 printk(" unknown irq (bad)\n");
1709 printk(" ( irq = %u )", dev->irq);
1710 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1713 printk(" irq not available\n");
1718 ret = ni_E_init(dev, it);
1722 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1723 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1724 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1725 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1726 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1731 static int pcimio_find_device(struct comedi_device *dev, int bus, int slot)
1733 struct mite_struct *mite;
1736 for (mite = mite_devices; mite; mite = mite->next) {
1740 if (bus != mite->pcidev->bus->number ||
1741 slot != PCI_SLOT(mite->pcidev->devfn))
1745 for (i = 0; i < n_pcimio_boards; i++) {
1746 if (mite_device_id(mite) == ni_boards[i].device_id) {
1747 dev->board_ptr = ni_boards + i;
1748 devpriv->mite = mite;
1754 printk("no device found\n");
1755 mite_list_devices();
1759 static int pcimio_ai_change(struct comedi_device *dev,
1760 struct comedi_subdevice *s, unsigned long new_size)
1764 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1771 static int pcimio_ao_change(struct comedi_device *dev,
1772 struct comedi_subdevice *s, unsigned long new_size)
1776 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1783 static int pcimio_gpct0_change(struct comedi_device *dev,
1784 struct comedi_subdevice *s,
1785 unsigned long new_size)
1789 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1796 static int pcimio_gpct1_change(struct comedi_device *dev,
1797 struct comedi_subdevice *s,
1798 unsigned long new_size)
1802 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1809 static int pcimio_dio_change(struct comedi_device *dev,
1810 struct comedi_subdevice *s, unsigned long new_size)
1814 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);