2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments PCI-MIO-E series and M series (all boards)
25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225,
33 PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
35 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
36 PXI-6071E, PCI-6070E, PXI-6070E,
37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
39 Updated: Wed, 03 Dec 2008 10:51:47 +0000
41 These boards are almost identical to the AT-MIO E series, except that
42 they use the PCI bus instead of ISA (i.e., AT). See the notes for
43 the ni_atmio.o driver for additional information about these boards.
45 Autocalibration is supported on many of the devices, using the
46 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
47 M-Series boards do analog input and analog output calibration entirely
48 in software. The software calibration corrects
49 the analog input for offset, gain and
50 nonlinearity. The analog outputs are corrected for offset and gain.
51 See the comedilib documentation on comedi_get_softcal_converter() for
54 By default, the driver uses DMA to transfer analog input data to
55 memory. When DMA is enabled, not all triggering features are
58 Digital I/O may not work on 673x.
60 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
61 With this board all of the convertors perform one simultaineous sample during
62 a scan interval. The period for a scan is used for the convert time in a
63 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
65 The RTSI trigger bus is supported on these cards on
66 subdevice 10. See the comedilib documentation for details.
68 Information (number of channels, bits, etc.) for some devices may be
69 incorrect. Please check this and submit a bug if there are problems
72 SCXI is probably broken for m-series boards.
75 - When DMA is enabled, COMEDI_EV_CONVERT does
80 The PCI-MIO E series driver was originally written by
81 Tomasz Motylewski <...>, and ported to comedi by ds.
85 341079b.pdf PCI E Series Register-Level Programmer Manual
86 340934b.pdf DAQ-STC reference manual
88 322080b.pdf 6711/6713/6715 User Manual
90 320945c.pdf PCI E Series User Manual
91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
95 need to deal with external reference for DAC, and other DAC
96 properties in board properties
98 deal with at-mio-16de-10 revision D to N changes, etc.
100 need to add other CALDAC type
102 need to slow down DAC loading. I don't trust NI's claim that
103 two writes to the PCI bus slows IO enough. I would prefer to
104 use comedi_udelay(). Timing specs: (clock)
112 #include "../comedidev.h"
114 #include <asm/byteorder.h>
115 #include <linux/delay.h>
120 /* #define PCI_DEBUG */
127 #define MAX_N_CALDACS (16+16+2)
129 #define DRV_NAME "ni_pcimio"
131 /* The following two tables must be in the same order */
132 static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = {
133 {PCI_VENDOR_ID_NATINST, 0x0162, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
134 {PCI_VENDOR_ID_NATINST, 0x1170, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NATINST, 0x1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
136 {PCI_VENDOR_ID_NATINST, 0x1190, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NATINST, 0x11b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
138 {PCI_VENDOR_ID_NATINST, 0x11c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NATINST, 0x11d0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
140 {PCI_VENDOR_ID_NATINST, 0x1270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NATINST, 0x1330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
142 {PCI_VENDOR_ID_NATINST, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NATINST, 0x1350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
144 {PCI_VENDOR_ID_NATINST, 0x14e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NATINST, 0x14f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
146 {PCI_VENDOR_ID_NATINST, 0x1580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NATINST, 0x15b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
148 {PCI_VENDOR_ID_NATINST, 0x1880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NATINST, 0x1870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
150 {PCI_VENDOR_ID_NATINST, 0x18b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NATINST, 0x18c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
152 {PCI_VENDOR_ID_NATINST, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NATINST, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
154 {PCI_VENDOR_ID_NATINST, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NATINST, 0x2890, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
156 {PCI_VENDOR_ID_NATINST, 0x28c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NATINST, 0x2a60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
158 {PCI_VENDOR_ID_NATINST, 0x2a70, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NATINST, 0x2a80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
160 {PCI_VENDOR_ID_NATINST, 0x2ab0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NATINST, 0x2b80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
162 {PCI_VENDOR_ID_NATINST, 0x2b90, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NATINST, 0x2c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
164 {PCI_VENDOR_ID_NATINST, 0x2ca0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NATINST, 0x70aa, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
166 {PCI_VENDOR_ID_NATINST, 0x70ab, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NATINST, 0x70ac, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
168 {PCI_VENDOR_ID_NATINST, 0x70af, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NATINST, 0x70b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
170 {PCI_VENDOR_ID_NATINST, 0x70b4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NATINST, 0x70b6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
172 {PCI_VENDOR_ID_NATINST, 0x70b7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NATINST, 0x70b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
174 {PCI_VENDOR_ID_NATINST, 0x70bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NATINST, 0x70bd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
176 {PCI_VENDOR_ID_NATINST, 0x70bf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NATINST, 0x70c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
178 {PCI_VENDOR_ID_NATINST, 0x70f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NATINST, 0x710d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
180 {PCI_VENDOR_ID_NATINST, 0x716c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NATINST, 0x717f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
182 {PCI_VENDOR_ID_NATINST, 0x71bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NATINST, 0x717d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
187 MODULE_DEVICE_TABLE(pci, ni_pci_table);
189 /* These are not all the possible ao ranges for 628x boards.
190 They can do OFFSET +- REFERENCE where OFFSET can be
191 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
192 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
193 63 different possibilities. An AO channel
194 can not act as it's own OFFSET or REFERENCE.
196 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
208 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
214 static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
219 static const struct ni_board_struct ni_boards[] = {
221 .device_id = 0x0162, /* NI also says 0x1620. typo? */
222 .name = "pci-mio-16xe-50",
225 .ai_fifo_depth = 2048,
227 .gainlkup = ai_gain_8,
232 .ao_range_table = &range_bipolar10,
235 .num_p0_dio_channels = 8,
236 .caldac = {dac8800, dac8043},
241 .name = "pci-mio-16xe-10", /* aka pci-6030E */
244 .ai_fifo_depth = 512,
246 .gainlkup = ai_gain_14,
250 .ao_fifo_depth = 2048,
251 .ao_range_table = &range_ni_E_ao_ext,
254 .num_p0_dio_channels = 8,
255 .caldac = {dac8800, dac8043, ad8522},
263 .ai_fifo_depth = 512,
265 .gainlkup = ai_gain_4,
270 .ao_range_table = &range_bipolar10,
273 .num_p0_dio_channels = 8,
274 .caldac = {ad8804_debug},
282 .ai_fifo_depth = 512,
284 .gainlkup = ai_gain_14,
288 .ao_fifo_depth = 2048,
289 .ao_range_table = &range_ni_E_ao_ext,
292 .num_p0_dio_channels = 8,
293 .caldac = {dac8800, dac8043, ad8522},
298 .name = "pci-mio-16e-1", /* aka pci-6070e */
301 .ai_fifo_depth = 512,
303 .gainlkup = ai_gain_16,
307 .ao_fifo_depth = 2048,
308 .ao_range_table = &range_ni_E_ao_ext,
311 .num_p0_dio_channels = 8,
317 .name = "pci-mio-16e-4", /* aka pci-6040e */
320 .ai_fifo_depth = 512,
322 .gainlkup = ai_gain_16,
323 /* Note: there have been reported problems with full speed
328 .ao_fifo_depth = 512,
329 .ao_range_table = &range_ni_E_ao_ext,
332 .num_p0_dio_channels = 8,
333 .caldac = {ad8804_debug}, /* doc says mb88341 */
341 .ai_fifo_depth = 512,
343 .gainlkup = ai_gain_16,
347 .ao_fifo_depth = 512,
348 .ao_range_table = &range_ni_E_ao_ext,
351 .num_p0_dio_channels = 8,
361 .ai_fifo_depth = 512,
363 .gainlkup = ai_gain_14,
367 .ao_fifo_depth = 2048,
368 .ao_range_table = &range_ni_E_ao_ext,
371 .num_p0_dio_channels = 8,
372 .caldac = {dac8800, dac8043, ad8522},
380 .ai_fifo_depth = 512,
382 .gainlkup = ai_gain_14,
388 .num_p0_dio_channels = 8,
389 .caldac = {dac8800, dac8043, ad8522},
397 .ai_fifo_depth = 512,
399 .gainlkup = ai_gain_14,
405 .num_p0_dio_channels = 8,
406 .caldac = {dac8800, dac8043, ad8522},
414 .ai_fifo_depth = 512,
416 .gainlkup = ai_gain_16,
420 .ao_fifo_depth = 2048,
421 .ao_range_table = &range_ni_E_ao_ext,
424 .num_p0_dio_channels = 8,
425 .caldac = {ad8804_debug},
433 .ai_fifo_depth = 512,
435 .gainlkup = ai_gain_4,
440 .num_p0_dio_channels = 8,
441 .caldac = {ad8804_debug}, /* manual is wrong */
449 .ai_fifo_depth = 512,
451 .gainlkup = ai_gain_4,
456 .ao_range_table = &range_bipolar10,
459 .num_p0_dio_channels = 8,
460 .caldac = {ad8804_debug}, /* manual is wrong */
468 .ai_fifo_depth = 512,
470 .gainlkup = ai_gain_4,
475 .ao_range_table = &range_bipolar10,
478 .num_p0_dio_channels = 8,
479 .caldac = {ad8804_debug}, /* manual is wrong */
487 .ai_fifo_depth = 512,
489 .gainlkup = ai_gain_4,
494 .ao_range_table = &range_ni_E_ao_ext,
497 .num_p0_dio_channels = 8,
498 .caldac = {ad8804_debug}, /* manual is wrong */
507 .ai_fifo_depth = 512,
509 .gainlkup = ai_gain_4,
515 .num_p0_dio_channels = 8,
516 .caldac = {ad8804_debug},
524 .ai_fifo_depth = 512,
526 .gainlkup = ai_gain_4,
531 .ao_range_table = &range_bipolar10,
534 .num_p0_dio_channels = 8,
535 .caldac = {ad8804_debug},
543 .ai_fifo_depth = 512,
545 .gainlkup = ai_gain_16,
550 .ao_fifo_depth = 2048,
551 .ao_range_table = &range_ni_E_ao_ext,
553 .num_p0_dio_channels = 8,
554 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */
556 {.device_id = 0x14e0,
560 .ai_fifo_depth = 8192,
562 .gainlkup = ai_gain_611x,
566 .reg_type = ni_reg_611x,
567 .ao_range_table = &range_bipolar10,
569 .ao_fifo_depth = 2048,
571 .num_p0_dio_channels = 8,
572 .caldac = {ad8804, ad8804},
579 .ai_fifo_depth = 8192,
581 .gainlkup = ai_gain_611x,
585 .reg_type = ni_reg_611x,
586 .ao_range_table = &range_bipolar10,
588 .ao_fifo_depth = 2048,
590 .num_p0_dio_channels = 8,
591 .caldac = {ad8804, ad8804},
594 /* The 6115 boards probably need their own driver */
600 .ai_fifo_depth = 8192,
602 .gainlkup = ai_gain_611x,
608 .ao_fifo_depth = 2048,
610 .num_p0_dio_channels = 8,
612 .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
621 .ai_fifo_depth = 8192,
623 .gainlkup = ai_gain_611x,
629 .ao_fifo_depth = 2048,
632 .num_p0_dio_channels = 8,
633 caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
639 .n_adchan = 0, /* no analog input */
643 .ao_fifo_depth = 16384,
644 /* data sheet says 8192, but fifo really holds 16384 samples */
645 .ao_range_table = &range_bipolar10,
647 .num_p0_dio_channels = 8,
648 .reg_type = ni_reg_6711,
649 .caldac = {ad8804_debug},
654 .n_adchan = 0, /* no analog input */
658 .ao_fifo_depth = 16384,
659 .ao_range_table = &range_bipolar10,
661 .num_p0_dio_channels = 8,
662 .reg_type = ni_reg_6711,
663 .caldac = {ad8804_debug},
668 .n_adchan = 0, /* no analog input */
672 .ao_fifo_depth = 16384,
673 .ao_range_table = &range_bipolar10,
675 .num_p0_dio_channels = 8,
676 .reg_type = ni_reg_6713,
677 .caldac = {ad8804_debug, ad8804_debug},
682 .n_adchan = 0, /* no analog input */
686 .ao_fifo_depth = 16384,
687 .ao_range_table = &range_bipolar10,
689 .num_p0_dio_channels = 8,
690 .reg_type = ni_reg_6713,
691 .caldac = {ad8804_debug, ad8804_debug},
696 .n_adchan = 0, /* no analog input */
700 .ao_fifo_depth = 8192,
701 .ao_range_table = &range_bipolar10,
703 .num_p0_dio_channels = 8,
704 .reg_type = ni_reg_6711,
705 .caldac = {ad8804_debug},
707 #if 0 /* need device ids */
711 .n_adchan = 0, /* no analog input */
715 .ao_fifo_depth = 8192,
716 .ao_range_table = &range_bipolar10,
717 .num_p0_dio_channels = 8,
718 .reg_type = ni_reg_6711,
719 .caldac = {ad8804_debug},
725 .n_adchan = 0, /* no analog input */
729 .ao_fifo_depth = 16384,
730 .ao_range_table = &range_bipolar10,
732 .num_p0_dio_channels = 8,
733 .reg_type = ni_reg_6713,
734 .caldac = {ad8804_debug, ad8804_debug},
739 .n_adchan = 0, /* no analog input */
743 .ao_fifo_depth = 16384,
744 .ao_range_table = &range_bipolar10,
746 .num_p0_dio_channels = 8,
747 .reg_type = ni_reg_6713,
748 .caldac = {ad8804_debug, ad8804_debug},
755 .ai_fifo_depth = 512,
757 .gainlkup = ai_gain_16,
761 .ao_fifo_depth = 2048,
762 .ao_range_table = &range_ni_E_ao_ext,
765 .num_p0_dio_channels = 8,
766 .caldac = {ad8804_debug},
774 .ai_fifo_depth = 512,
776 .gainlkup = ai_gain_16,
780 .ao_fifo_depth = 2048,
781 .ao_range_table = &range_ni_E_ao_ext,
784 .num_p0_dio_channels = 8,
785 .caldac = {ad8804_debug},
793 .ai_fifo_depth = 512,
795 .gainlkup = ai_gain_16,
800 .ao_fifo_depth = 2048,
801 .ao_range_table = &range_ni_E_ao_ext,
803 .num_p0_dio_channels = 8,
804 .caldac = {mb88341, mb88341, ad8522},
811 .ai_fifo_depth = 512,
813 .gainlkup = ai_gain_14,
817 .ao_fifo_depth = 2048,
818 .ao_range_table = &range_ni_E_ao_ext,
821 .num_p0_dio_channels = 8,
822 .caldac = {dac8800, dac8043, ad8522},
829 .ai_fifo_depth = 512,
831 .gainlkup = ai_gain_4,
836 .ao_range_table = &range_bipolar10,
839 .num_p0_dio_channels = 8,
840 .caldac = {ad8804_debug},
848 .ai_fifo_depth = 512,
850 .gainlkup = ai_gain_622x,
855 .num_p0_dio_channels = 8,
856 .reg_type = ni_reg_622x,
858 .caldac = {caldac_none},
866 .ai_fifo_depth = 4095,
867 .gainlkup = ai_gain_622x,
871 .ao_fifo_depth = 8191,
872 .ao_range_table = &range_ni_M_622x_ao,
873 .reg_type = ni_reg_622x,
876 .num_p0_dio_channels = 8,
877 .caldac = {caldac_none},
882 .name = "pci-6221_37pin",
885 .ai_fifo_depth = 4095,
886 .gainlkup = ai_gain_622x,
890 .ao_fifo_depth = 8191,
891 .ao_range_table = &range_ni_M_622x_ao,
892 .reg_type = ni_reg_622x,
895 .num_p0_dio_channels = 8,
896 .caldac = {caldac_none},
904 .ai_fifo_depth = 4095,
905 .gainlkup = ai_gain_622x,
910 .reg_type = ni_reg_622x,
912 .num_p0_dio_channels = 32,
913 .caldac = {caldac_none},
921 .ai_fifo_depth = 4095,
922 .gainlkup = ai_gain_622x,
927 .reg_type = ni_reg_622x,
929 .num_p0_dio_channels = 32,
930 .caldac = {caldac_none},
938 .ai_fifo_depth = 4095,
939 .gainlkup = ai_gain_622x,
943 .ao_fifo_depth = 8191,
944 .ao_range_table = &range_ni_M_622x_ao,
945 .reg_type = ni_reg_622x,
948 .num_p0_dio_channels = 32,
949 .caldac = {caldac_none},
957 .ai_fifo_depth = 4095,
958 .gainlkup = ai_gain_622x,
962 .ao_fifo_depth = 8191,
963 .ao_range_table = &range_ni_M_622x_ao,
964 .reg_type = ni_reg_622x,
967 .num_p0_dio_channels = 32,
968 .caldac = {caldac_none},
976 .ai_fifo_depth = 4095,
977 .gainlkup = ai_gain_628x,
982 .reg_type = ni_reg_625x,
984 .num_p0_dio_channels = 8,
985 .caldac = {caldac_none},
993 .ai_fifo_depth = 4095,
994 .gainlkup = ai_gain_628x,
998 .ao_fifo_depth = 8191,
999 .ao_range_table = &range_ni_M_625x_ao,
1000 .reg_type = ni_reg_625x,
1003 .num_p0_dio_channels = 8,
1004 .caldac = {caldac_none},
1008 .device_id = 0x717d,
1009 .name = "pcie-6251",
1012 .ai_fifo_depth = 4095,
1013 .gainlkup = ai_gain_628x,
1017 .ao_fifo_depth = 8191,
1018 .ao_range_table = &range_ni_M_625x_ao,
1019 .reg_type = ni_reg_625x,
1022 .num_p0_dio_channels = 8,
1023 .caldac = {caldac_none},
1027 .device_id = 0x70b7,
1031 .ai_fifo_depth = 4095,
1032 .gainlkup = ai_gain_628x,
1037 .reg_type = ni_reg_625x,
1039 .num_p0_dio_channels = 32,
1040 .caldac = {caldac_none},
1044 .device_id = 0x70ab,
1048 .ai_fifo_depth = 4095,
1049 .gainlkup = ai_gain_628x,
1053 .ao_fifo_depth = 8191,
1054 .ao_range_table = &range_ni_M_625x_ao,
1055 .reg_type = ni_reg_625x,
1058 .num_p0_dio_channels = 32,
1059 .caldac = {caldac_none},
1063 .device_id = 0x717f,
1064 .name = "pcie-6259",
1067 .ai_fifo_depth = 4095,
1068 .gainlkup = ai_gain_628x,
1072 .ao_fifo_depth = 8191,
1073 .ao_range_table = &range_ni_M_625x_ao,
1074 .reg_type = ni_reg_625x,
1077 .num_p0_dio_channels = 32,
1078 .caldac = {caldac_none},
1082 .device_id = 0x70b6,
1086 .ai_fifo_depth = 2047,
1087 .gainlkup = ai_gain_628x,
1091 .ao_fifo_depth = 8191,
1092 .reg_type = ni_reg_628x,
1094 .num_p0_dio_channels = 8,
1095 .caldac = {caldac_none},
1099 .device_id = 0x70bd,
1103 .ai_fifo_depth = 2047,
1104 .gainlkup = ai_gain_628x,
1108 .ao_fifo_depth = 8191,
1109 .ao_range_table = &range_ni_M_628x_ao,
1110 .reg_type = ni_reg_628x,
1113 .num_p0_dio_channels = 8,
1114 .caldac = {caldac_none},
1118 .device_id = 0x70bf,
1122 .ai_fifo_depth = 2047,
1123 .gainlkup = ai_gain_628x,
1127 .ao_fifo_depth = 8191,
1128 .ao_range_table = &range_ni_M_628x_ao,
1129 .reg_type = ni_reg_628x,
1132 .num_p0_dio_channels = 8,
1133 .caldac = {caldac_none},
1137 .device_id = 0x70bc,
1141 .ai_fifo_depth = 2047,
1142 .gainlkup = ai_gain_628x,
1147 .reg_type = ni_reg_628x,
1149 .num_p0_dio_channels = 32,
1150 .caldac = {caldac_none},
1154 .device_id = 0x70ac,
1158 .ai_fifo_depth = 2047,
1159 .gainlkup = ai_gain_628x,
1163 .ao_fifo_depth = 8191,
1164 .ao_range_table = &range_ni_M_628x_ao,
1165 .reg_type = ni_reg_628x,
1168 .num_p0_dio_channels = 32,
1169 .caldac = {caldac_none},
1173 .device_id = 0x70C0,
1177 .ai_fifo_depth = 1024,
1179 .gainlkup = ai_gain_6143,
1183 .reg_type = ni_reg_6143,
1186 .num_p0_dio_channels = 8,
1187 .caldac = {ad8804_debug, ad8804_debug},
1190 .device_id = 0x710D,
1194 .ai_fifo_depth = 1024,
1196 .gainlkup = ai_gain_6143,
1200 .reg_type = ni_reg_6143,
1203 .num_p0_dio_channels = 8,
1204 .caldac = {ad8804_debug, ad8804_debug},
1208 #define n_pcimio_boards ((sizeof(ni_boards)/sizeof(ni_boards[0])))
1210 static int pcimio_attach(struct comedi_device * dev, struct comedi_devconfig * it);
1211 static int pcimio_detach(struct comedi_device * dev);
1212 static struct comedi_driver driver_pcimio = {
1213 driver_name: DRV_NAME,
1215 attach:pcimio_attach,
1216 detach:pcimio_detach,
1219 COMEDI_PCI_INITCLEANUP(driver_pcimio, ni_pci_table)
1225 #define devpriv ((struct ni_private *)dev->private)
1227 /* How we access registers */
1229 #define ni_writel(a,b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1230 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1231 #define ni_writew(a,b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1232 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1233 #define ni_writeb(a,b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1234 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1236 /* How we access STC registers */
1238 /* We automatically take advantage of STC registers that can be
1239 * read/written directly in the I/O space of the board. Most
1240 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1241 * The 611x devices map the write registers to iobase+addr*2, and
1242 * the read registers to iobase+(addr-1)*2. */
1243 /* However, the 611x boards still aren't working, so I'm disabling
1244 * non-windowed STC access temporarily */
1246 static void e_series_win_out(struct comedi_device * dev, uint16_t data, int reg)
1248 unsigned long flags;
1250 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
1251 ni_writew(reg, Window_Address);
1252 ni_writew(data, Window_Data);
1253 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
1256 static uint16_t e_series_win_in(struct comedi_device * dev, int reg)
1258 unsigned long flags;
1261 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
1262 ni_writew(reg, Window_Address);
1263 ret = ni_readw(Window_Data);
1264 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
1269 static void m_series_stc_writew(struct comedi_device * dev, uint16_t data, int reg)
1273 case ADC_FIFO_Clear:
1274 offset = M_Offset_AI_FIFO_Clear;
1276 case AI_Command_1_Register:
1277 offset = M_Offset_AI_Command_1;
1279 case AI_Command_2_Register:
1280 offset = M_Offset_AI_Command_2;
1282 case AI_Mode_1_Register:
1283 offset = M_Offset_AI_Mode_1;
1285 case AI_Mode_2_Register:
1286 offset = M_Offset_AI_Mode_2;
1288 case AI_Mode_3_Register:
1289 offset = M_Offset_AI_Mode_3;
1291 case AI_Output_Control_Register:
1292 offset = M_Offset_AI_Output_Control;
1294 case AI_Personal_Register:
1295 offset = M_Offset_AI_Personal;
1297 case AI_SI2_Load_A_Register:
1298 /* this is actually a 32 bit register on m series boards */
1299 ni_writel(data, M_Offset_AI_SI2_Load_A);
1302 case AI_SI2_Load_B_Register:
1303 /* this is actually a 32 bit register on m series boards */
1304 ni_writel(data, M_Offset_AI_SI2_Load_B);
1307 case AI_START_STOP_Select_Register:
1308 offset = M_Offset_AI_START_STOP_Select;
1310 case AI_Trigger_Select_Register:
1311 offset = M_Offset_AI_Trigger_Select;
1313 case Analog_Trigger_Etc_Register:
1314 offset = M_Offset_Analog_Trigger_Etc;
1316 case AO_Command_1_Register:
1317 offset = M_Offset_AO_Command_1;
1319 case AO_Command_2_Register:
1320 offset = M_Offset_AO_Command_2;
1322 case AO_Mode_1_Register:
1323 offset = M_Offset_AO_Mode_1;
1325 case AO_Mode_2_Register:
1326 offset = M_Offset_AO_Mode_2;
1328 case AO_Mode_3_Register:
1329 offset = M_Offset_AO_Mode_3;
1331 case AO_Output_Control_Register:
1332 offset = M_Offset_AO_Output_Control;
1334 case AO_Personal_Register:
1335 offset = M_Offset_AO_Personal;
1337 case AO_Start_Select_Register:
1338 offset = M_Offset_AO_Start_Select;
1340 case AO_Trigger_Select_Register:
1341 offset = M_Offset_AO_Trigger_Select;
1343 case Clock_and_FOUT_Register:
1344 offset = M_Offset_Clock_and_FOUT;
1346 case Configuration_Memory_Clear:
1347 offset = M_Offset_Configuration_Memory_Clear;
1349 case DAC_FIFO_Clear:
1350 offset = M_Offset_AO_FIFO_Clear;
1352 case DIO_Control_Register:
1354 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1358 case G_Autoincrement_Register(0):
1359 offset = M_Offset_G0_Autoincrement;
1361 case G_Autoincrement_Register(1):
1362 offset = M_Offset_G1_Autoincrement;
1364 case G_Command_Register(0):
1365 offset = M_Offset_G0_Command;
1367 case G_Command_Register(1):
1368 offset = M_Offset_G1_Command;
1370 case G_Input_Select_Register(0):
1371 offset = M_Offset_G0_Input_Select;
1373 case G_Input_Select_Register(1):
1374 offset = M_Offset_G1_Input_Select;
1376 case G_Mode_Register(0):
1377 offset = M_Offset_G0_Mode;
1379 case G_Mode_Register(1):
1380 offset = M_Offset_G1_Mode;
1382 case Interrupt_A_Ack_Register:
1383 offset = M_Offset_Interrupt_A_Ack;
1385 case Interrupt_A_Enable_Register:
1386 offset = M_Offset_Interrupt_A_Enable;
1388 case Interrupt_B_Ack_Register:
1389 offset = M_Offset_Interrupt_B_Ack;
1391 case Interrupt_B_Enable_Register:
1392 offset = M_Offset_Interrupt_B_Enable;
1394 case Interrupt_Control_Register:
1395 offset = M_Offset_Interrupt_Control;
1397 case IO_Bidirection_Pin_Register:
1398 offset = M_Offset_IO_Bidirection_Pin;
1400 case Joint_Reset_Register:
1401 offset = M_Offset_Joint_Reset;
1403 case RTSI_Trig_A_Output_Register:
1404 offset = M_Offset_RTSI_Trig_A_Output;
1406 case RTSI_Trig_B_Output_Register:
1407 offset = M_Offset_RTSI_Trig_B_Output;
1409 case RTSI_Trig_Direction_Register:
1410 offset = M_Offset_RTSI_Trig_Direction;
1412 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1413 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1415 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1421 ni_writew(data, offset);
1424 static uint16_t m_series_stc_readw(struct comedi_device * dev, int reg)
1428 case AI_Status_1_Register:
1429 offset = M_Offset_AI_Status_1;
1431 case AO_Status_1_Register:
1432 offset = M_Offset_AO_Status_1;
1434 case AO_Status_2_Register:
1435 offset = M_Offset_AO_Status_2;
1437 case DIO_Serial_Input_Register:
1438 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1440 case Joint_Status_1_Register:
1441 offset = M_Offset_Joint_Status_1;
1443 case Joint_Status_2_Register:
1444 offset = M_Offset_Joint_Status_2;
1446 case G_Status_Register:
1447 offset = M_Offset_G01_Status;
1450 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1456 return ni_readw(offset);
1459 static void m_series_stc_writel(struct comedi_device * dev, uint32_t data, int reg)
1463 case AI_SC_Load_A_Registers:
1464 offset = M_Offset_AI_SC_Load_A;
1466 case AI_SI_Load_A_Registers:
1467 offset = M_Offset_AI_SI_Load_A;
1469 case AO_BC_Load_A_Register:
1470 offset = M_Offset_AO_BC_Load_A;
1472 case AO_UC_Load_A_Register:
1473 offset = M_Offset_AO_UC_Load_A;
1475 case AO_UI_Load_A_Register:
1476 offset = M_Offset_AO_UI_Load_A;
1478 case G_Load_A_Register(0):
1479 offset = M_Offset_G0_Load_A;
1481 case G_Load_A_Register(1):
1482 offset = M_Offset_G1_Load_A;
1484 case G_Load_B_Register(0):
1485 offset = M_Offset_G0_Load_B;
1487 case G_Load_B_Register(1):
1488 offset = M_Offset_G1_Load_B;
1491 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1497 ni_writel(data, offset);
1500 static uint32_t m_series_stc_readl(struct comedi_device * dev, int reg)
1504 case G_HW_Save_Register(0):
1505 offset = M_Offset_G0_HW_Save;
1507 case G_HW_Save_Register(1):
1508 offset = M_Offset_G1_HW_Save;
1510 case G_Save_Register(0):
1511 offset = M_Offset_G0_Save;
1513 case G_Save_Register(1):
1514 offset = M_Offset_G1_Save;
1517 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1523 return ni_readl(offset);
1526 #define interrupt_pin(a) 0
1527 #define IRQ_POLARITY 1
1529 #define NI_E_IRQ_FLAGS IRQF_SHARED
1531 #include "ni_mio_common.c"
1533 static int pcimio_find_device(struct comedi_device * dev, int bus, int slot);
1534 static int pcimio_ai_change(struct comedi_device * dev, struct comedi_subdevice * s,
1535 unsigned long new_size);
1536 static int pcimio_ao_change(struct comedi_device * dev, struct comedi_subdevice * s,
1537 unsigned long new_size);
1538 static int pcimio_gpct0_change(struct comedi_device * dev, struct comedi_subdevice * s,
1539 unsigned long new_size);
1540 static int pcimio_gpct1_change(struct comedi_device * dev, struct comedi_subdevice * s,
1541 unsigned long new_size);
1542 static int pcimio_dio_change(struct comedi_device * dev, struct comedi_subdevice * s,
1543 unsigned long new_size);
1545 static void m_series_init_eeprom_buffer(struct comedi_device * dev)
1547 static const int Start_Cal_EEPROM = 0x400;
1548 static const unsigned window_size = 10;
1549 static const int serial_number_eeprom_offset = 0x4;
1550 static const int serial_number_eeprom_length = 0x4;
1551 unsigned old_iodwbsr_bits;
1552 unsigned old_iodwbsr1_bits;
1553 unsigned old_iodwcr1_bits;
1556 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1557 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1558 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1559 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1560 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1561 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1562 writel(0x1 | old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1563 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1565 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1566 for (i = 0; i < serial_number_eeprom_length; ++i) {
1567 char *byte_ptr = (char*)&devpriv->serial_number + i;
1568 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1570 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1572 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) {
1573 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1576 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1577 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1578 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1579 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1582 static void init_6143(struct comedi_device * dev)
1584 /* Disable interrupts */
1585 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1587 /* Initialise 6143 AI specific bits */
1588 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */
1589 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */
1590 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */
1592 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Set the FIFO half full level */
1594 /* Strobe Relay disable bit */
1595 devpriv->ai_calib_source_enabled = 0;
1596 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1597 Calibration_Channel_6143);
1598 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1601 /* cleans up allocated resources */
1602 static int pcimio_detach(struct comedi_device * dev)
1604 mio_common_detach(dev);
1606 comedi_free_irq(dev->irq, dev);
1609 mite_free_ring(devpriv->ai_mite_ring);
1610 mite_free_ring(devpriv->ao_mite_ring);
1611 mite_free_ring(devpriv->cdo_mite_ring);
1612 mite_free_ring(devpriv->gpct_mite_ring[0]);
1613 mite_free_ring(devpriv->gpct_mite_ring[1]);
1615 mite_unsetup(devpriv->mite);
1621 static int pcimio_attach(struct comedi_device * dev, struct comedi_devconfig * it)
1625 printk("comedi%d: ni_pcimio:", dev->minor);
1627 ret = ni_alloc_private(dev);
1631 ret = pcimio_find_device(dev, it->options[0], it->options[1]);
1635 printk(" %s", boardtype.name);
1636 dev->board_name = boardtype.name;
1638 if (boardtype.reg_type & ni_reg_m_series_mask) {
1639 devpriv->stc_writew = &m_series_stc_writew;
1640 devpriv->stc_readw = &m_series_stc_readw;
1641 devpriv->stc_writel = &m_series_stc_writel;
1642 devpriv->stc_readl = &m_series_stc_readl;
1644 devpriv->stc_writew = &e_series_win_out;
1645 devpriv->stc_readw = &e_series_win_in;
1646 devpriv->stc_writel = &win_out2;
1647 devpriv->stc_readl = &win_in2;
1650 ret = mite_setup(devpriv->mite);
1652 printk(" error setting up mite\n");
1655 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1656 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1657 if (devpriv->ai_mite_ring == NULL)
1659 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1660 if (devpriv->ao_mite_ring == NULL)
1662 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1663 if (devpriv->cdo_mite_ring == NULL)
1665 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1666 if (devpriv->gpct_mite_ring[0] == NULL)
1668 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1669 if (devpriv->gpct_mite_ring[1] == NULL)
1672 if (boardtype.reg_type & ni_reg_m_series_mask)
1673 m_series_init_eeprom_buffer(dev);
1674 if (boardtype.reg_type == ni_reg_6143)
1677 dev->irq = mite_irq(devpriv->mite);
1679 if (dev->irq == 0) {
1680 printk(" unknown irq (bad)\n");
1682 printk(" ( irq = %u )", dev->irq);
1683 if ((ret = comedi_request_irq(dev->irq, ni_E_interrupt,
1684 NI_E_IRQ_FLAGS, DRV_NAME,
1686 printk(" irq not available\n");
1691 ret = ni_E_init(dev, it);
1695 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1696 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1697 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1698 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1699 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1704 static int pcimio_find_device(struct comedi_device * dev, int bus, int slot)
1706 struct mite_struct *mite;
1709 for (mite = mite_devices; mite; mite = mite->next) {
1713 if (bus != mite->pcidev->bus->number ||
1714 slot != PCI_SLOT(mite->pcidev->devfn))
1718 for (i = 0; i < n_pcimio_boards; i++) {
1719 if (mite_device_id(mite) == ni_boards[i].device_id) {
1720 dev->board_ptr = ni_boards + i;
1721 devpriv->mite = mite;
1727 printk("no device found\n");
1728 mite_list_devices();
1732 static int pcimio_ai_change(struct comedi_device * dev, struct comedi_subdevice * s,
1733 unsigned long new_size)
1737 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1744 static int pcimio_ao_change(struct comedi_device * dev, struct comedi_subdevice * s,
1745 unsigned long new_size)
1749 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1756 static int pcimio_gpct0_change(struct comedi_device * dev, struct comedi_subdevice * s,
1757 unsigned long new_size)
1761 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1768 static int pcimio_gpct1_change(struct comedi_device * dev, struct comedi_subdevice * s,
1769 unsigned long new_size)
1773 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1780 static int pcimio_dio_change(struct comedi_device * dev, struct comedi_subdevice * s,
1781 unsigned long new_size)
1785 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);