2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
29 Interrupt support originally added by Truxton Fulton
32 References (from ftp://ftp.natinst.com/support/manuals):
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
40 Other possibly relevant info:
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
45 320906c.pdf maximum signal ratings
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
54 - the interrupt routine needs to be cleaned up
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
68 #include "comedi_fc.h"
71 #define MDPRINTK(format, args...)
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85 [ai_gain_4] = {0, 1, 4, 7},
86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87 0x003, 0x004, 0x005, 0x006},
88 [ai_gain_622x] = {0, 1, 4, 5},
89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
192 static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
197 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
205 static const struct comedi_lrange *const ni_range_lkup[] = {
206 [ai_gain_16] = &range_ni_E_ai,
207 [ai_gain_8] = &range_ni_E_ai_limited,
208 [ai_gain_14] = &range_ni_E_ai_limited14,
209 [ai_gain_4] = &range_ni_E_ai_bipolar4,
210 [ai_gain_611x] = &range_ni_E_ai_611x,
211 [ai_gain_622x] = &range_ni_M_ai_622x,
212 [ai_gain_628x] = &range_ni_M_ai_628x,
213 [ai_gain_6143] = &range_ni_S_ai_6143
216 static int ni_dio_insn_config(struct comedi_device *dev,
217 struct comedi_subdevice *s,
218 struct comedi_insn *insn, unsigned int *data);
219 static int ni_dio_insn_bits(struct comedi_device *dev,
220 struct comedi_subdevice *s,
221 struct comedi_insn *insn, unsigned int *data);
222 static int ni_cdio_cmdtest(struct comedi_device *dev,
223 struct comedi_subdevice *s, struct comedi_cmd *cmd);
224 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
225 static int ni_cdio_cancel(struct comedi_device *dev,
226 struct comedi_subdevice *s);
227 static void handle_cdio_interrupt(struct comedi_device *dev);
228 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
229 unsigned int trignum);
231 static int ni_serial_insn_config(struct comedi_device *dev,
232 struct comedi_subdevice *s,
233 struct comedi_insn *insn, unsigned int *data);
234 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
235 struct comedi_subdevice *s,
236 unsigned char data_out,
237 unsigned char *data_in);
238 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 unsigned char data_out,
241 unsigned char *data_in);
243 static int ni_calib_insn_read(struct comedi_device *dev,
244 struct comedi_subdevice *s,
245 struct comedi_insn *insn, unsigned int *data);
246 static int ni_calib_insn_write(struct comedi_device *dev,
247 struct comedi_subdevice *s,
248 struct comedi_insn *insn, unsigned int *data);
250 static int ni_eeprom_insn_read(struct comedi_device *dev,
251 struct comedi_subdevice *s,
252 struct comedi_insn *insn, unsigned int *data);
253 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
254 struct comedi_subdevice *s,
255 struct comedi_insn *insn,
258 static int ni_pfi_insn_bits(struct comedi_device *dev,
259 struct comedi_subdevice *s,
260 struct comedi_insn *insn, unsigned int *data);
261 static int ni_pfi_insn_config(struct comedi_device *dev,
262 struct comedi_subdevice *s,
263 struct comedi_insn *insn, unsigned int *data);
264 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
267 static void ni_rtsi_init(struct comedi_device *dev);
268 static int ni_rtsi_insn_bits(struct comedi_device *dev,
269 struct comedi_subdevice *s,
270 struct comedi_insn *insn, unsigned int *data);
271 static int ni_rtsi_insn_config(struct comedi_device *dev,
272 struct comedi_subdevice *s,
273 struct comedi_insn *insn, unsigned int *data);
275 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
276 static int ni_read_eeprom(struct comedi_device *dev, int addr);
278 #ifdef DEBUG_STATUS_A
279 static void ni_mio_print_status_a(int status);
281 #define ni_mio_print_status_a(a)
283 #ifdef DEBUG_STATUS_B
284 static void ni_mio_print_status_b(int status);
286 #define ni_mio_print_status_b(a)
289 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
291 static void ni_handle_fifo_half_full(struct comedi_device *dev);
292 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
293 struct comedi_subdevice *s);
295 static void ni_handle_fifo_dregs(struct comedi_device *dev);
296 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
297 unsigned int trignum);
298 static void ni_load_channelgain_list(struct comedi_device *dev,
299 unsigned int n_chan, unsigned int *list);
300 static void shutdown_ai_command(struct comedi_device *dev);
302 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
303 unsigned int trignum);
305 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
307 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
309 static int ni_gpct_insn_write(struct comedi_device *dev,
310 struct comedi_subdevice *s,
311 struct comedi_insn *insn, unsigned int *data);
312 static int ni_gpct_insn_read(struct comedi_device *dev,
313 struct comedi_subdevice *s,
314 struct comedi_insn *insn, unsigned int *data);
315 static int ni_gpct_insn_config(struct comedi_device *dev,
316 struct comedi_subdevice *s,
317 struct comedi_insn *insn, unsigned int *data);
318 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
319 static int ni_gpct_cmdtest(struct comedi_device *dev,
320 struct comedi_subdevice *s, struct comedi_cmd *cmd);
321 static int ni_gpct_cancel(struct comedi_device *dev,
322 struct comedi_subdevice *s);
323 static void handle_gpct_interrupt(struct comedi_device *dev,
324 unsigned short counter_index);
326 static int init_cs5529(struct comedi_device *dev);
327 static int cs5529_do_conversion(struct comedi_device *dev,
328 unsigned short *data);
329 static int cs5529_ai_insn_read(struct comedi_device *dev,
330 struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data);
332 #ifdef NI_CS5529_DEBUG
333 static unsigned int cs5529_config_read(struct comedi_device *dev,
334 unsigned int reg_select_bits);
336 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
337 unsigned int reg_select_bits);
339 static int ni_m_series_pwm_config(struct comedi_device *dev,
340 struct comedi_subdevice *s,
341 struct comedi_insn *insn, unsigned int *data);
342 static int ni_6143_pwm_config(struct comedi_device *dev,
343 struct comedi_subdevice *s,
344 struct comedi_insn *insn, unsigned int *data);
346 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
348 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
349 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
353 AIMODE_HALF_FULL = 1,
358 enum ni_common_subdevices {
364 NI_CALIBRATION_SUBDEV,
367 NI_CS5529_CALIBRATION_SUBDEV,
375 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
377 switch (counter_index) {
379 return NI_GPCT0_SUBDEV;
382 return NI_GPCT1_SUBDEV;
388 return NI_GPCT0_SUBDEV;
391 enum timebase_nanoseconds {
393 TIMEBASE_2_NS = 10000
396 #define SERIAL_DISABLED 0
397 #define SERIAL_600NS 600
398 #define SERIAL_1_2US 1200
399 #define SERIAL_10US 10000
401 static const int num_adc_stages_611x = 3;
403 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
404 unsigned ai_mite_status);
405 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
406 unsigned ao_mite_status);
407 static void get_last_sample_611x(struct comedi_device *dev);
408 static void get_last_sample_6143(struct comedi_device *dev);
410 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
411 unsigned bit_mask, unsigned bit_values)
415 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
417 case Interrupt_A_Enable_Register:
418 devpriv->int_a_enable_reg &= ~bit_mask;
419 devpriv->int_a_enable_reg |= bit_values & bit_mask;
420 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
421 Interrupt_A_Enable_Register);
423 case Interrupt_B_Enable_Register:
424 devpriv->int_b_enable_reg &= ~bit_mask;
425 devpriv->int_b_enable_reg |= bit_values & bit_mask;
426 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
427 Interrupt_B_Enable_Register);
429 case IO_Bidirection_Pin_Register:
430 devpriv->io_bidirection_pin_reg &= ~bit_mask;
431 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
432 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
433 IO_Bidirection_Pin_Register);
436 devpriv->ai_ao_select_reg &= ~bit_mask;
437 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
438 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
441 devpriv->g0_g1_select_reg &= ~bit_mask;
442 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
443 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
446 printk("Warning %s() called with invalid register\n", __func__);
447 printk("reg is %d\n", reg);
451 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
455 static int ni_ai_drain_dma(struct comedi_device *dev);
457 /* DMA channel setup */
459 /* negative channel means no channel */
460 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
466 (ni_stc_dma_channel_select_bitfield(channel) <<
467 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
471 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
474 /* negative channel means no channel */
475 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
481 (ni_stc_dma_channel_select_bitfield(channel) <<
482 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
486 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
489 /* negative mite_channel means no channel */
490 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
496 if (mite_channel >= 0) {
497 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
501 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
505 /* negative mite_channel means no channel */
506 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
511 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
512 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
513 if (mite_channel >= 0) {
514 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
515 under the assumption the cdio dma selection works just like ai/ao/gpct.
516 Definitely works for dma channels 0 and 1. */
517 devpriv->cdio_dma_select_reg |=
518 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
519 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
521 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
523 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
526 static int ni_request_ai_mite_channel(struct comedi_device *dev)
530 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
531 BUG_ON(devpriv->ai_mite_chan);
532 devpriv->ai_mite_chan =
533 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
534 if (devpriv->ai_mite_chan == NULL) {
535 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
537 "failed to reserve mite dma channel for analog input.");
540 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
541 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
542 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
546 static int ni_request_ao_mite_channel(struct comedi_device *dev)
550 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
551 BUG_ON(devpriv->ao_mite_chan);
552 devpriv->ao_mite_chan =
553 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
554 if (devpriv->ao_mite_chan == NULL) {
555 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
557 "failed to reserve mite dma channel for analog outut.");
560 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
561 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
562 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
566 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
568 enum comedi_io_direction direction)
571 struct mite_channel *mite_chan;
573 BUG_ON(gpct_index >= NUM_GPCT);
574 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
575 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
577 mite_request_channel(devpriv->mite,
578 devpriv->gpct_mite_ring[gpct_index]);
579 if (mite_chan == NULL) {
580 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
582 "failed to reserve mite dma channel for counter.");
585 mite_chan->dir = direction;
586 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
588 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
589 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
595 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
600 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
601 BUG_ON(devpriv->cdo_mite_chan);
602 devpriv->cdo_mite_chan =
603 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
604 if (devpriv->cdo_mite_chan == NULL) {
605 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
607 "failed to reserve mite dma channel for correlated digital outut.");
610 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
611 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
612 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
617 static void ni_release_ai_mite_channel(struct comedi_device *dev)
622 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
623 if (devpriv->ai_mite_chan) {
624 ni_set_ai_dma_channel(dev, -1);
625 mite_release_channel(devpriv->ai_mite_chan);
626 devpriv->ai_mite_chan = NULL;
628 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
632 static void ni_release_ao_mite_channel(struct comedi_device *dev)
637 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
638 if (devpriv->ao_mite_chan) {
639 ni_set_ao_dma_channel(dev, -1);
640 mite_release_channel(devpriv->ao_mite_chan);
641 devpriv->ao_mite_chan = NULL;
643 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
647 void ni_release_gpct_mite_channel(struct comedi_device *dev,
653 BUG_ON(gpct_index >= NUM_GPCT);
654 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
655 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
656 struct mite_channel *mite_chan =
657 devpriv->counter_dev->counters[gpct_index].mite_chan;
659 ni_set_gpct_dma_channel(dev, gpct_index, -1);
660 ni_tio_set_mite_channel(&devpriv->
661 counter_dev->counters[gpct_index],
663 mite_release_channel(mite_chan);
665 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
669 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
674 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
675 if (devpriv->cdo_mite_chan) {
676 ni_set_cdo_dma_channel(dev, -1);
677 mite_release_channel(devpriv->cdo_mite_chan);
678 devpriv->cdo_mite_chan = NULL;
680 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
684 /* e-series boards use the second irq signals to generate dma requests for their counters */
686 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
687 unsigned gpct_index, short enable)
689 if (boardtype.reg_type & ni_reg_m_series_mask)
691 switch (gpct_index) {
694 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
695 Second_IRQ_A_Enable_Register);
697 devpriv->stc_writew(dev, 0,
698 Second_IRQ_A_Enable_Register);
703 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
704 Second_IRQ_B_Enable_Register);
706 devpriv->stc_writew(dev, 0,
707 Second_IRQ_B_Enable_Register);
717 static void ni_clear_ai_fifo(struct comedi_device *dev)
719 if (boardtype.reg_type == ni_reg_6143) {
720 /* Flush the 6143 data FIFO */
721 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
722 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
723 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
725 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
726 if (boardtype.reg_type == ni_reg_625x) {
727 ni_writeb(0, M_Offset_Static_AI_Control(0));
728 ni_writeb(1, M_Offset_Static_AI_Control(0));
730 /* the NI example code does 3 convert pulses for 625x boards,
731 but that appears to be wrong in practice. */
732 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
733 AI_Command_1_Register);
734 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
735 AI_Command_1_Register);
736 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
737 AI_Command_1_Register);
743 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
745 devpriv->stc_writew(dev, data >> 16, reg);
746 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
749 static uint32_t win_in2(struct comedi_device *dev, int reg)
752 bits = devpriv->stc_readw(dev, reg) << 16;
753 bits |= devpriv->stc_readw(dev, reg + 1);
757 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
758 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
763 spin_lock_irqsave(&devpriv->window_lock, flags);
764 ni_writew(addr, AO_Window_Address_611x);
765 ni_writew(data, AO_Window_Data_611x);
766 spin_unlock_irqrestore(&devpriv->window_lock, flags);
769 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
774 spin_lock_irqsave(&devpriv->window_lock, flags);
775 ni_writew(addr, AO_Window_Address_611x);
776 ni_writel(data, AO_Window_Data_611x);
777 spin_unlock_irqrestore(&devpriv->window_lock, flags);
780 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
785 spin_lock_irqsave(&devpriv->window_lock, flags);
786 ni_writew(addr, AO_Window_Address_611x);
787 data = ni_readw(AO_Window_Data_611x);
788 spin_unlock_irqrestore(&devpriv->window_lock, flags);
792 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
793 * share registers (such as Interrupt_A_Register) without interfering with
796 * NOTE: the switch/case statements are optimized out for a constant argument
797 * so this is actually quite fast--- If you must wrap another function around this
798 * make it inline to avoid a large speed penalty.
800 * value should only be 1 or 0.
802 static inline void ni_set_bits(struct comedi_device *dev, int reg,
803 unsigned bits, unsigned value)
811 ni_set_bitfield(dev, reg, bits, bit_values);
814 static irqreturn_t ni_E_interrupt(int irq, void *d)
816 struct comedi_device *dev = d;
817 unsigned short a_status;
818 unsigned short b_status;
819 unsigned int ai_mite_status = 0;
820 unsigned int ao_mite_status = 0;
823 struct mite_struct *mite = devpriv->mite;
826 if (dev->attached == 0)
828 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
830 /* lock to avoid race with comedi_poll */
831 spin_lock_irqsave(&dev->spinlock, flags);
832 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
833 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
836 unsigned long flags_too;
838 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
839 if (devpriv->ai_mite_chan) {
840 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
841 if (ai_mite_status & CHSR_LINKC)
843 devpriv->mite->mite_io_addr +
845 ai_mite_chan->channel));
847 if (devpriv->ao_mite_chan) {
848 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
849 if (ao_mite_status & CHSR_LINKC)
853 ao_mite_chan->channel));
855 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
858 ack_a_interrupt(dev, a_status);
859 ack_b_interrupt(dev, b_status);
860 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
861 handle_a_interrupt(dev, a_status, ai_mite_status);
862 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
863 handle_b_interrupt(dev, b_status, ao_mite_status);
864 handle_gpct_interrupt(dev, 0);
865 handle_gpct_interrupt(dev, 1);
866 handle_cdio_interrupt(dev);
868 spin_unlock_irqrestore(&dev->spinlock, flags);
873 static void ni_sync_ai_dma(struct comedi_device *dev)
875 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
878 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
879 if (devpriv->ai_mite_chan)
880 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
881 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
884 static void mite_handle_b_linkc(struct mite_struct *mite,
885 struct comedi_device *dev)
887 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
890 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
891 if (devpriv->ao_mite_chan) {
892 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
894 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
897 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
899 static const int timeout = 10000;
901 for (i = 0; i < timeout; i++) {
902 unsigned short b_status;
904 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
905 if (b_status & AO_FIFO_Half_Full_St)
907 /* if we poll too often, the pci bus activity seems
908 to slow the dma transfer down */
912 comedi_error(dev, "timed out waiting for dma load");
919 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
921 if (devpriv->aimode == AIMODE_SCAN) {
923 static const int timeout = 10;
926 for (i = 0; i < timeout; i++) {
928 if ((s->async->events & COMEDI_CB_EOS))
933 ni_handle_fifo_dregs(dev);
934 s->async->events |= COMEDI_CB_EOS;
937 /* handle special case of single scan using AI_End_On_End_Of_Scan */
938 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
939 shutdown_ai_command(dev);
943 static void shutdown_ai_command(struct comedi_device *dev)
945 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
948 ni_ai_drain_dma(dev);
950 ni_handle_fifo_dregs(dev);
951 get_last_sample_611x(dev);
952 get_last_sample_6143(dev);
954 s->async->events |= COMEDI_CB_EOA;
957 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
960 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
962 switch (s - dev->subdevices) {
969 case NI_GPCT0_SUBDEV:
970 case NI_GPCT1_SUBDEV:
971 ni_gpct_cancel(dev, s);
974 ni_cdio_cancel(dev, s);
980 comedi_event(dev, s);
983 static void handle_gpct_interrupt(struct comedi_device *dev,
984 unsigned short counter_index)
987 struct comedi_subdevice *s =
988 dev->subdevices + NI_GPCT_SUBDEV(counter_index);
990 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
992 if (s->async->events)
997 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
999 unsigned short ack = 0;
1001 if (a_status & AI_SC_TC_St) {
1002 ack |= AI_SC_TC_Interrupt_Ack;
1004 if (a_status & AI_START1_St) {
1005 ack |= AI_START1_Interrupt_Ack;
1007 if (a_status & AI_START_St) {
1008 ack |= AI_START_Interrupt_Ack;
1010 if (a_status & AI_STOP_St) {
1011 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1012 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1015 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1018 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1019 unsigned ai_mite_status)
1021 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1023 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1024 if (s->type == COMEDI_SUBD_UNUSED)
1027 #ifdef DEBUG_INTERRUPT
1029 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1030 status, ai_mite_status);
1031 ni_mio_print_status_a(status);
1034 if (ai_mite_status & CHSR_LINKC) {
1035 ni_sync_ai_dma(dev);
1038 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1039 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1040 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1042 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1044 /* mite_print_chsr(ai_mite_status); */
1045 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1046 /* disable_irq(dev->irq); */
1050 /* test for all uncommon interrupt events at the same time */
1051 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1052 AI_SC_TC_St | AI_START1_St)) {
1053 if (status == 0xffff) {
1055 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1056 /* we probably aren't even running a command now,
1057 * so it's a good idea to be careful. */
1058 if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1060 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1065 if (status & (AI_Overrun_St | AI_Overflow_St |
1066 AI_SC_TC_Error_St)) {
1067 printk("ni_mio_common: ai error a_status=%04x\n",
1069 ni_mio_print_status_a(status);
1071 shutdown_ai_command(dev);
1073 s->async->events |= COMEDI_CB_ERROR;
1074 if (status & (AI_Overrun_St | AI_Overflow_St))
1075 s->async->events |= COMEDI_CB_OVERFLOW;
1081 if (status & AI_SC_TC_St) {
1082 #ifdef DEBUG_INTERRUPT
1083 printk("ni_mio_common: SC_TC interrupt\n");
1085 if (!devpriv->ai_continuous) {
1086 shutdown_ai_command(dev);
1091 if (status & AI_FIFO_Half_Full_St) {
1093 static const int timeout = 10;
1094 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1095 *fail to get the fifo less than half full, so loop to be sure.*/
1096 for (i = 0; i < timeout; ++i) {
1097 ni_handle_fifo_half_full(dev);
1098 if ((devpriv->stc_readw(dev,
1099 AI_Status_1_Register) &
1100 AI_FIFO_Half_Full_St) == 0)
1104 #endif /* !PCIDMA */
1106 if ((status & AI_STOP_St)) {
1107 ni_handle_eos(dev, s);
1112 #ifdef DEBUG_INTERRUPT
1113 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1114 if (status & Interrupt_A_St) {
1116 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1122 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1124 unsigned short ack = 0;
1125 if (b_status & AO_BC_TC_St) {
1126 ack |= AO_BC_TC_Interrupt_Ack;
1128 if (b_status & AO_Overrun_St) {
1129 ack |= AO_Error_Interrupt_Ack;
1131 if (b_status & AO_START_St) {
1132 ack |= AO_START_Interrupt_Ack;
1134 if (b_status & AO_START1_St) {
1135 ack |= AO_START1_Interrupt_Ack;
1137 if (b_status & AO_UC_TC_St) {
1138 ack |= AO_UC_TC_Interrupt_Ack;
1140 if (b_status & AO_UI2_TC_St) {
1141 ack |= AO_UI2_TC_Interrupt_Ack;
1143 if (b_status & AO_UPDATE_St) {
1144 ack |= AO_UPDATE_Interrupt_Ack;
1147 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1150 static void handle_b_interrupt(struct comedi_device *dev,
1151 unsigned short b_status, unsigned ao_mite_status)
1153 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1154 /* unsigned short ack=0; */
1155 #ifdef DEBUG_INTERRUPT
1156 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1157 b_status, ao_mite_status);
1158 ni_mio_print_status_b(b_status);
1162 /* Currently, mite.c requires us to handle LINKC */
1163 if (ao_mite_status & CHSR_LINKC) {
1164 mite_handle_b_linkc(devpriv->mite, dev);
1167 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1168 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1169 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1171 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1173 /* mite_print_chsr(ao_mite_status); */
1174 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1178 if (b_status == 0xffff)
1180 if (b_status & AO_Overrun_St) {
1182 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1183 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1184 s->async->events |= COMEDI_CB_OVERFLOW;
1187 if (b_status & AO_BC_TC_St) {
1189 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1190 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1191 s->async->events |= COMEDI_CB_EOA;
1194 if (b_status & AO_FIFO_Request_St) {
1197 ret = ni_ao_fifo_half_empty(dev, s);
1199 printk("ni_mio_common: AO buffer underrun\n");
1200 ni_set_bits(dev, Interrupt_B_Enable_Register,
1201 AO_FIFO_Interrupt_Enable |
1202 AO_Error_Interrupt_Enable, 0);
1203 s->async->events |= COMEDI_CB_OVERFLOW;
1211 #ifdef DEBUG_STATUS_A
1212 static const char *const status_a_strings[] = {
1213 "passthru0", "fifo", "G0_gate", "G0_TC",
1214 "stop", "start", "sc_tc", "start1",
1215 "start2", "sc_tc_error", "overflow", "overrun",
1216 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1219 static void ni_mio_print_status_a(int status)
1223 printk("A status:");
1224 for (i = 15; i >= 0; i--) {
1225 if (status & (1 << i)) {
1226 printk(" %s", status_a_strings[i]);
1233 #ifdef DEBUG_STATUS_B
1234 static const char *const status_b_strings[] = {
1235 "passthru1", "fifo", "G1_gate", "G1_TC",
1236 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1237 "start1", "overrun", "start", "bc_tc_error",
1238 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1241 static void ni_mio_print_status_b(int status)
1245 printk("B status:");
1246 for (i = 15; i >= 0; i--) {
1247 if (status & (1 << i)) {
1248 printk(" %s", status_b_strings[i]);
1257 static void ni_ao_fifo_load(struct comedi_device *dev,
1258 struct comedi_subdevice *s, int n)
1260 struct comedi_async *async = s->async;
1261 struct comedi_cmd *cmd = &async->cmd;
1269 chan = async->cur_chan;
1270 for (i = 0; i < n; i++) {
1271 err &= comedi_buf_get(async, &d);
1275 range = CR_RANGE(cmd->chanlist[chan]);
1277 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1278 packed_data = d & 0xffff;
1279 /* 6711 only has 16 bit wide ao fifo */
1280 if (boardtype.reg_type != ni_reg_6711) {
1281 err &= comedi_buf_get(async, &d);
1286 packed_data |= (d << 16) & 0xffff0000;
1288 ni_writel(packed_data, DAC_FIFO_Data_611x);
1290 ni_writew(d, DAC_FIFO_Data);
1293 chan %= cmd->chanlist_len;
1295 async->cur_chan = chan;
1297 async->events |= COMEDI_CB_OVERFLOW;
1302 * There's a small problem if the FIFO gets really low and we
1303 * don't have the data to fill it. Basically, if after we fill
1304 * the FIFO with all the data available, the FIFO is _still_
1305 * less than half full, we never clear the interrupt. If the
1306 * IRQ is in edge mode, we never get another interrupt, because
1307 * this one wasn't cleared. If in level mode, we get flooded
1308 * with interrupts that we can't fulfill, because nothing ever
1309 * gets put into the buffer.
1311 * This kind of situation is recoverable, but it is easier to
1312 * just pretend we had a FIFO underrun, since there is a good
1313 * chance it will happen anyway. This is _not_ the case for
1314 * RT code, as RT code might purposely be running close to the
1315 * metal. Needs to be fixed eventually.
1317 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1318 struct comedi_subdevice *s)
1322 n = comedi_buf_read_n_available(s->async);
1324 s->async->events |= COMEDI_CB_OVERFLOW;
1329 if (n > boardtype.ao_fifo_depth / 2)
1330 n = boardtype.ao_fifo_depth / 2;
1332 ni_ao_fifo_load(dev, s, n);
1334 s->async->events |= COMEDI_CB_BLOCK;
1339 static int ni_ao_prep_fifo(struct comedi_device *dev,
1340 struct comedi_subdevice *s)
1345 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1346 if (boardtype.reg_type & ni_reg_6xxx_mask)
1347 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1349 /* load some data */
1350 n = comedi_buf_read_n_available(s->async);
1355 if (n > boardtype.ao_fifo_depth)
1356 n = boardtype.ao_fifo_depth;
1358 ni_ao_fifo_load(dev, s, n);
1363 static void ni_ai_fifo_read(struct comedi_device *dev,
1364 struct comedi_subdevice *s, int n)
1366 struct comedi_async *async = s->async;
1369 if (boardtype.reg_type == ni_reg_611x) {
1373 for (i = 0; i < n / 2; i++) {
1374 dl = ni_readl(ADC_FIFO_Data_611x);
1375 /* This may get the hi/lo data in the wrong order */
1376 data[0] = (dl >> 16) & 0xffff;
1377 data[1] = dl & 0xffff;
1378 cfc_write_array_to_buffer(s, data, sizeof(data));
1380 /* Check if there's a single sample stuck in the FIFO */
1382 dl = ni_readl(ADC_FIFO_Data_611x);
1383 data[0] = dl & 0xffff;
1384 cfc_write_to_buffer(s, data[0]);
1386 } else if (boardtype.reg_type == ni_reg_6143) {
1390 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1391 for (i = 0; i < n / 2; i++) {
1392 dl = ni_readl(AIFIFO_Data_6143);
1394 data[0] = (dl >> 16) & 0xffff;
1395 data[1] = dl & 0xffff;
1396 cfc_write_array_to_buffer(s, data, sizeof(data));
1399 /* Assume there is a single sample stuck in the FIFO */
1400 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1401 dl = ni_readl(AIFIFO_Data_6143);
1402 data[0] = (dl >> 16) & 0xffff;
1403 cfc_write_to_buffer(s, data[0]);
1406 if (n > sizeof(devpriv->ai_fifo_buffer) /
1407 sizeof(devpriv->ai_fifo_buffer[0])) {
1408 comedi_error(dev, "bug! ai_fifo_buffer too small");
1409 async->events |= COMEDI_CB_ERROR;
1412 for (i = 0; i < n; i++) {
1413 devpriv->ai_fifo_buffer[i] =
1414 ni_readw(ADC_FIFO_Data_Register);
1416 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1418 sizeof(devpriv->ai_fifo_buffer[0]));
1422 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1425 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1427 n = boardtype.ai_fifo_depth / 2;
1429 ni_ai_fifo_read(dev, s, n);
1434 static int ni_ai_drain_dma(struct comedi_device *dev)
1437 static const int timeout = 10000;
1438 unsigned long flags;
1441 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1442 if (devpriv->ai_mite_chan) {
1443 for (i = 0; i < timeout; i++) {
1444 if ((devpriv->stc_readw(dev,
1445 AI_Status_1_Register) &
1447 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1453 printk("ni_mio_common: wait for dma drain timed out\n");
1455 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1456 mite_bytes_in_transit(devpriv->ai_mite_chan),
1457 devpriv->stc_readw(dev, AI_Status_1_Register));
1461 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1463 ni_sync_ai_dma(dev);
1471 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1473 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1479 if (boardtype.reg_type == ni_reg_611x) {
1480 while ((devpriv->stc_readw(dev,
1481 AI_Status_1_Register) &
1482 AI_FIFO_Empty_St) == 0) {
1483 dl = ni_readl(ADC_FIFO_Data_611x);
1485 /* This may get the hi/lo data in the wrong order */
1486 data[0] = (dl >> 16);
1487 data[1] = (dl & 0xffff);
1488 cfc_write_array_to_buffer(s, data, sizeof(data));
1490 } else if (boardtype.reg_type == ni_reg_6143) {
1492 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1493 dl = ni_readl(AIFIFO_Data_6143);
1495 /* This may get the hi/lo data in the wrong order */
1496 data[0] = (dl >> 16);
1497 data[1] = (dl & 0xffff);
1498 cfc_write_array_to_buffer(s, data, sizeof(data));
1501 /* Check if stranded sample is present */
1502 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1503 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1504 dl = ni_readl(AIFIFO_Data_6143);
1505 data[0] = (dl >> 16) & 0xffff;
1506 cfc_write_to_buffer(s, data[0]);
1511 devpriv->stc_readw(dev,
1512 AI_Status_1_Register) & AI_FIFO_Empty_St;
1513 while (fifo_empty == 0) {
1516 sizeof(devpriv->ai_fifo_buffer) /
1517 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1519 devpriv->stc_readw(dev,
1520 AI_Status_1_Register) &
1524 devpriv->ai_fifo_buffer[i] =
1525 ni_readw(ADC_FIFO_Data_Register);
1527 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1530 ai_fifo_buffer[0]));
1535 static void get_last_sample_611x(struct comedi_device *dev)
1537 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1541 if (boardtype.reg_type != ni_reg_611x)
1544 /* Check if there's a single sample stuck in the FIFO */
1545 if (ni_readb(XXX_Status) & 0x80) {
1546 dl = ni_readl(ADC_FIFO_Data_611x);
1547 data = (dl & 0xffff);
1548 cfc_write_to_buffer(s, data);
1552 static void get_last_sample_6143(struct comedi_device *dev)
1554 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1558 if (boardtype.reg_type != ni_reg_6143)
1561 /* Check if there's a single sample stuck in the FIFO */
1562 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1563 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1564 dl = ni_readl(AIFIFO_Data_6143);
1566 /* This may get the hi/lo data in the wrong order */
1567 data = (dl >> 16) & 0xffff;
1568 cfc_write_to_buffer(s, data);
1572 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1573 void *data, unsigned int num_bytes,
1574 unsigned int chan_index)
1576 struct comedi_async *async = s->async;
1578 unsigned int length = num_bytes / bytes_per_sample(s);
1579 short *array = data;
1580 unsigned int *larray = data;
1581 for (i = 0; i < length; i++) {
1583 if (s->subdev_flags & SDF_LSAMPL)
1584 larray[i] = le32_to_cpu(larray[i]);
1586 array[i] = le16_to_cpu(array[i]);
1588 if (s->subdev_flags & SDF_LSAMPL)
1589 larray[i] += devpriv->ai_offset[chan_index];
1591 array[i] += devpriv->ai_offset[chan_index];
1593 chan_index %= async->cmd.chanlist_len;
1599 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1601 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1603 unsigned long flags;
1605 retval = ni_request_ai_mite_channel(dev);
1608 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1610 /* write alloc the entire buffer */
1611 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1613 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1614 if (devpriv->ai_mite_chan == NULL) {
1615 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1619 switch (boardtype.reg_type) {
1622 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1625 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1628 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1632 mite_dma_arm(devpriv->ai_mite_chan);
1633 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1638 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1640 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1642 unsigned long flags;
1644 retval = ni_request_ao_mite_channel(dev);
1648 /* read alloc the entire buffer */
1649 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1651 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1652 if (devpriv->ao_mite_chan) {
1653 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1654 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1656 /* doing 32 instead of 16 bit wide transfers from memory
1657 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1658 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1660 mite_dma_arm(devpriv->ao_mite_chan);
1663 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1671 used for both cancel ioctl and board initialization
1673 this is pretty harsh for a cancel, but it works...
1676 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1678 ni_release_ai_mite_channel(dev);
1679 /* ai configuration */
1680 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1681 Joint_Reset_Register);
1683 ni_set_bits(dev, Interrupt_A_Enable_Register,
1684 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1685 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1686 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1687 AI_FIFO_Interrupt_Enable, 0);
1689 ni_clear_ai_fifo(dev);
1691 if (boardtype.reg_type != ni_reg_6143)
1692 ni_writeb(0, Misc_Command);
1694 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1695 devpriv->stc_writew(dev,
1696 AI_Start_Stop | AI_Mode_1_Reserved
1697 /*| AI_Trigger_Once */ ,
1698 AI_Mode_1_Register);
1699 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1700 /* generate FIFO interrupts on non-empty */
1701 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1702 if (boardtype.reg_type == ni_reg_611x) {
1703 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1705 AI_LOCALMUX_CLK_Pulse_Width,
1706 AI_Personal_Register);
1707 devpriv->stc_writew(dev,
1708 AI_SCAN_IN_PROG_Output_Select(3) |
1709 AI_EXTMUX_CLK_Output_Select(0) |
1710 AI_LOCALMUX_CLK_Output_Select(2) |
1711 AI_SC_TC_Output_Select(3) |
1712 AI_CONVERT_Output_Select
1713 (AI_CONVERT_Output_Enable_High),
1714 AI_Output_Control_Register);
1715 } else if (boardtype.reg_type == ni_reg_6143) {
1716 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1718 AI_LOCALMUX_CLK_Pulse_Width,
1719 AI_Personal_Register);
1720 devpriv->stc_writew(dev,
1721 AI_SCAN_IN_PROG_Output_Select(3) |
1722 AI_EXTMUX_CLK_Output_Select(0) |
1723 AI_LOCALMUX_CLK_Output_Select(2) |
1724 AI_SC_TC_Output_Select(3) |
1725 AI_CONVERT_Output_Select
1726 (AI_CONVERT_Output_Enable_Low),
1727 AI_Output_Control_Register);
1729 unsigned ai_output_control_bits;
1730 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1732 AI_CONVERT_Pulse_Width |
1733 AI_LOCALMUX_CLK_Pulse_Width,
1734 AI_Personal_Register);
1735 ai_output_control_bits =
1736 AI_SCAN_IN_PROG_Output_Select(3) |
1737 AI_EXTMUX_CLK_Output_Select(0) |
1738 AI_LOCALMUX_CLK_Output_Select(2) |
1739 AI_SC_TC_Output_Select(3);
1740 if (boardtype.reg_type == ni_reg_622x)
1741 ai_output_control_bits |=
1742 AI_CONVERT_Output_Select
1743 (AI_CONVERT_Output_Enable_High);
1745 ai_output_control_bits |=
1746 AI_CONVERT_Output_Select
1747 (AI_CONVERT_Output_Enable_Low);
1748 devpriv->stc_writew(dev, ai_output_control_bits,
1749 AI_Output_Control_Register);
1751 /* the following registers should not be changed, because there
1752 * are no backup registers in devpriv. If you want to change
1753 * any of these, add a backup register and other appropriate code:
1754 * AI_Mode_1_Register
1755 * AI_Mode_3_Register
1756 * AI_Personal_Register
1757 * AI_Output_Control_Register
1759 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1761 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1766 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1768 unsigned long flags = 0;
1771 /* lock to avoid race with interrupt handler */
1772 if (in_interrupt() == 0)
1773 spin_lock_irqsave(&dev->spinlock, flags);
1775 ni_handle_fifo_dregs(dev);
1777 ni_sync_ai_dma(dev);
1779 count = s->async->buf_write_count - s->async->buf_read_count;
1780 if (in_interrupt() == 0)
1781 spin_unlock_irqrestore(&dev->spinlock, flags);
1786 static int ni_ai_insn_read(struct comedi_device *dev,
1787 struct comedi_subdevice *s, struct comedi_insn *insn,
1791 const unsigned int mask = (1 << boardtype.adbits) - 1;
1796 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1798 ni_clear_ai_fifo(dev);
1800 signbits = devpriv->ai_offset[0];
1801 if (boardtype.reg_type == ni_reg_611x) {
1802 for (n = 0; n < num_adc_stages_611x; n++) {
1803 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1804 AI_Command_1_Register);
1807 for (n = 0; n < insn->n; n++) {
1808 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1809 AI_Command_1_Register);
1810 /* The 611x has screwy 32-bit FIFOs. */
1812 for (i = 0; i < NI_TIMEOUT; i++) {
1813 if (ni_readb(XXX_Status) & 0x80) {
1814 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1818 if (!(devpriv->stc_readw(dev,
1819 AI_Status_1_Register) &
1820 AI_FIFO_Empty_St)) {
1821 d = ni_readl(ADC_FIFO_Data_611x) &
1826 if (i == NI_TIMEOUT) {
1828 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1834 } else if (boardtype.reg_type == ni_reg_6143) {
1835 for (n = 0; n < insn->n; n++) {
1836 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1837 AI_Command_1_Register);
1839 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1841 for (i = 0; i < NI_TIMEOUT; i++) {
1842 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1843 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1844 dl = ni_readl(AIFIFO_Data_6143);
1848 if (i == NI_TIMEOUT) {
1850 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1853 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1856 for (n = 0; n < insn->n; n++) {
1857 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1858 AI_Command_1_Register);
1859 for (i = 0; i < NI_TIMEOUT; i++) {
1860 if (!(devpriv->stc_readw(dev,
1861 AI_Status_1_Register) &
1865 if (i == NI_TIMEOUT) {
1867 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1870 if (boardtype.reg_type & ni_reg_m_series_mask) {
1872 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1874 d = ni_readw(ADC_FIFO_Data_Register);
1875 d += signbits; /* subtle: needs to be short addition */
1883 void ni_prime_channelgain_list(struct comedi_device *dev)
1886 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1887 for (i = 0; i < NI_TIMEOUT; ++i) {
1888 if (!(devpriv->stc_readw(dev,
1889 AI_Status_1_Register) &
1890 AI_FIFO_Empty_St)) {
1891 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1896 printk("ni_mio_common: timeout loading channel/gain list\n");
1899 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1900 unsigned int n_chan,
1903 unsigned int chan, range, aref;
1906 unsigned int dither;
1907 unsigned range_code;
1909 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1911 /* offset = 1 << (boardtype.adbits - 1); */
1912 if ((list[0] & CR_ALT_SOURCE)) {
1913 unsigned bypass_bits;
1914 chan = CR_CHAN(list[0]);
1915 range = CR_RANGE(list[0]);
1916 range_code = ni_gainlkup[boardtype.gainlkup][range];
1917 dither = ((list[0] & CR_ALT_FILTER) != 0);
1918 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1919 bypass_bits |= chan;
1921 (devpriv->ai_calib_source) &
1922 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1923 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1924 MSeries_AI_Bypass_Mode_Mux_Mask |
1925 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1926 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1928 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1929 /* don't use 2's complement encoding */
1930 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1931 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1933 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1936 for (i = 0; i < n_chan; i++) {
1937 unsigned config_bits = 0;
1938 chan = CR_CHAN(list[i]);
1939 aref = CR_AREF(list[i]);
1940 range = CR_RANGE(list[i]);
1941 dither = ((list[i] & CR_ALT_FILTER) != 0);
1943 range_code = ni_gainlkup[boardtype.gainlkup][range];
1944 devpriv->ai_offset[i] = offset;
1948 MSeries_AI_Config_Channel_Type_Differential_Bits;
1952 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1956 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1961 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1963 MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
1964 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1965 if (i == n_chan - 1)
1966 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1968 config_bits |= MSeries_AI_Config_Dither_Bit;
1969 /* don't use 2's complement encoding */
1970 config_bits |= MSeries_AI_Config_Polarity_Bit;
1971 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1973 ni_prime_channelgain_list(dev);
1977 * Notes on the 6110 and 6111:
1978 * These boards a slightly different than the rest of the series, since
1979 * they have multiple A/D converters.
1980 * From the driver side, the configuration memory is a
1982 * Configuration Memory Low:
1984 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1985 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1986 * 1001 gain=0.1 (+/- 50)
1995 * Configuration Memory High:
1996 * bits 12-14: Channel Type
1997 * 001 for differential
1998 * 000 for calibration
1999 * bit 11: coupling (this is not currently handled)
2003 * valid channels are 0-3
2005 static void ni_load_channelgain_list(struct comedi_device *dev,
2006 unsigned int n_chan, unsigned int *list)
2008 unsigned int chan, range, aref;
2010 unsigned int hi, lo;
2012 unsigned int dither;
2014 if (boardtype.reg_type & ni_reg_m_series_mask) {
2015 ni_m_series_load_channelgain_list(dev, n_chan, list);
2018 if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
2019 && (boardtype.reg_type != ni_reg_6143)) {
2020 if (devpriv->changain_state
2021 && devpriv->changain_spec == list[0]) {
2025 devpriv->changain_state = 1;
2026 devpriv->changain_spec = list[0];
2028 devpriv->changain_state = 0;
2031 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2033 /* Set up Calibration mode if required */
2034 if (boardtype.reg_type == ni_reg_6143) {
2035 if ((list[0] & CR_ALT_SOURCE)
2036 && !devpriv->ai_calib_source_enabled) {
2037 /* Strobe Relay enable bit */
2038 ni_writew(devpriv->ai_calib_source |
2039 Calibration_Channel_6143_RelayOn,
2040 Calibration_Channel_6143);
2041 ni_writew(devpriv->ai_calib_source,
2042 Calibration_Channel_6143);
2043 devpriv->ai_calib_source_enabled = 1;
2044 msleep_interruptible(100); /* Allow relays to change */
2045 } else if (!(list[0] & CR_ALT_SOURCE)
2046 && devpriv->ai_calib_source_enabled) {
2047 /* Strobe Relay disable bit */
2048 ni_writew(devpriv->ai_calib_source |
2049 Calibration_Channel_6143_RelayOff,
2050 Calibration_Channel_6143);
2051 ni_writew(devpriv->ai_calib_source,
2052 Calibration_Channel_6143);
2053 devpriv->ai_calib_source_enabled = 0;
2054 msleep_interruptible(100); /* Allow relays to change */
2058 offset = 1 << (boardtype.adbits - 1);
2059 for (i = 0; i < n_chan; i++) {
2060 if ((boardtype.reg_type != ni_reg_6143)
2061 && (list[i] & CR_ALT_SOURCE)) {
2062 chan = devpriv->ai_calib_source;
2064 chan = CR_CHAN(list[i]);
2066 aref = CR_AREF(list[i]);
2067 range = CR_RANGE(list[i]);
2068 dither = ((list[i] & CR_ALT_FILTER) != 0);
2070 /* fix the external/internal range differences */
2071 range = ni_gainlkup[boardtype.gainlkup][range];
2072 if (boardtype.reg_type == ni_reg_611x)
2073 devpriv->ai_offset[i] = offset;
2075 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2078 if ((list[i] & CR_ALT_SOURCE)) {
2079 if (boardtype.reg_type == ni_reg_611x)
2080 ni_writew(CR_CHAN(list[i]) & 0x0003,
2081 Calibration_Channel_Select_611x);
2083 if (boardtype.reg_type == ni_reg_611x)
2085 else if (boardtype.reg_type == ni_reg_6143)
2089 hi |= AI_DIFFERENTIAL;
2101 hi |= AI_CONFIG_CHANNEL(chan);
2103 ni_writew(hi, Configuration_Memory_High);
2105 if (boardtype.reg_type != ni_reg_6143) {
2107 if (i == n_chan - 1)
2108 lo |= AI_LAST_CHANNEL;
2112 ni_writew(lo, Configuration_Memory_Low);
2116 /* prime the channel/gain list */
2117 if ((boardtype.reg_type != ni_reg_611x)
2118 && (boardtype.reg_type != ni_reg_6143)) {
2119 ni_prime_channelgain_list(dev);
2123 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2127 switch (round_mode) {
2128 case TRIG_ROUND_NEAREST:
2130 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2132 case TRIG_ROUND_DOWN:
2133 divider = (nanosec) / devpriv->clock_ns;
2136 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2142 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2144 return devpriv->clock_ns * (timer + 1);
2147 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2148 unsigned num_channels)
2150 switch (boardtype.reg_type) {
2153 /* simultaneously-sampled inputs */
2154 return boardtype.ai_speed;
2157 /* multiplexed inputs */
2160 return boardtype.ai_speed * num_channels;
2163 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2164 struct comedi_cmd *cmd)
2170 /* step 1: make sure trigger sources are trivially valid */
2172 if ((cmd->flags & CMDF_WRITE)) {
2173 cmd->flags &= ~CMDF_WRITE;
2176 tmp = cmd->start_src;
2177 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
2178 if (!cmd->start_src || tmp != cmd->start_src)
2181 tmp = cmd->scan_begin_src;
2182 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
2183 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2186 tmp = cmd->convert_src;
2187 sources = TRIG_TIMER | TRIG_EXT;
2188 if ((boardtype.reg_type == ni_reg_611x)
2189 || (boardtype.reg_type == ni_reg_6143))
2190 sources |= TRIG_NOW;
2191 cmd->convert_src &= sources;
2192 if (!cmd->convert_src || tmp != cmd->convert_src)
2195 tmp = cmd->scan_end_src;
2196 cmd->scan_end_src &= TRIG_COUNT;
2197 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2200 tmp = cmd->stop_src;
2201 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
2202 if (!cmd->stop_src || tmp != cmd->stop_src)
2208 /* step 2: make sure trigger sources are unique and mutually compatible */
2210 /* note that mutual compatibility is not an issue here */
2211 if (cmd->start_src != TRIG_NOW &&
2212 cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
2214 if (cmd->scan_begin_src != TRIG_TIMER &&
2215 cmd->scan_begin_src != TRIG_EXT &&
2216 cmd->scan_begin_src != TRIG_OTHER)
2218 if (cmd->convert_src != TRIG_TIMER &&
2219 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2221 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
2227 /* step 3: make sure arguments are trivially compatible */
2229 if (cmd->start_src == TRIG_EXT) {
2230 /* external trigger */
2231 unsigned int tmp = CR_CHAN(cmd->start_arg);
2235 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2236 if (cmd->start_arg != tmp) {
2237 cmd->start_arg = tmp;
2241 if (cmd->start_arg != 0) {
2242 /* true for both TRIG_NOW and TRIG_INT */
2247 if (cmd->scan_begin_src == TRIG_TIMER) {
2248 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev,
2252 cmd->scan_begin_arg =
2253 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
2256 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {
2257 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2260 } else if (cmd->scan_begin_src == TRIG_EXT) {
2261 /* external trigger */
2262 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2266 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2267 if (cmd->scan_begin_arg != tmp) {
2268 cmd->scan_begin_arg = tmp;
2271 } else { /* TRIG_OTHER */
2272 if (cmd->scan_begin_arg) {
2273 cmd->scan_begin_arg = 0;
2277 if (cmd->convert_src == TRIG_TIMER) {
2278 if ((boardtype.reg_type == ni_reg_611x)
2279 || (boardtype.reg_type == ni_reg_6143)) {
2280 if (cmd->convert_arg != 0) {
2281 cmd->convert_arg = 0;
2285 if (cmd->convert_arg < boardtype.ai_speed) {
2286 cmd->convert_arg = boardtype.ai_speed;
2289 if (cmd->convert_arg > devpriv->clock_ns * 0xffff) {
2290 cmd->convert_arg = devpriv->clock_ns * 0xffff;
2294 } else if (cmd->convert_src == TRIG_EXT) {
2295 /* external trigger */
2296 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2300 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2301 if (cmd->convert_arg != tmp) {
2302 cmd->convert_arg = tmp;
2305 } else if (cmd->convert_src == TRIG_NOW) {
2306 if (cmd->convert_arg != 0) {
2307 cmd->convert_arg = 0;
2312 if (cmd->scan_end_arg != cmd->chanlist_len) {
2313 cmd->scan_end_arg = cmd->chanlist_len;
2316 if (cmd->stop_src == TRIG_COUNT) {
2317 unsigned int max_count = 0x01000000;
2319 if (boardtype.reg_type == ni_reg_611x)
2320 max_count -= num_adc_stages_611x;
2321 if (cmd->stop_arg > max_count) {
2322 cmd->stop_arg = max_count;
2325 if (cmd->stop_arg < 1) {
2331 if (cmd->stop_arg != 0) {
2340 /* step 4: fix up any arguments */
2342 if (cmd->scan_begin_src == TRIG_TIMER) {
2343 tmp = cmd->scan_begin_arg;
2344 cmd->scan_begin_arg =
2345 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2346 cmd->scan_begin_arg,
2350 if (tmp != cmd->scan_begin_arg)
2353 if (cmd->convert_src == TRIG_TIMER) {
2354 if ((boardtype.reg_type != ni_reg_611x)
2355 && (boardtype.reg_type != ni_reg_6143)) {
2356 tmp = cmd->convert_arg;
2358 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2363 if (tmp != cmd->convert_arg)
2365 if (cmd->scan_begin_src == TRIG_TIMER &&
2366 cmd->scan_begin_arg <
2367 cmd->convert_arg * cmd->scan_end_arg) {
2368 cmd->scan_begin_arg =
2369 cmd->convert_arg * cmd->scan_end_arg;
2381 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2383 const struct comedi_cmd *cmd = &s->async->cmd;
2385 int mode1 = 0; /* mode1 is needed for both stop and convert */
2387 int start_stop_select = 0;
2388 unsigned int stop_count;
2389 int interrupt_a_enable = 0;
2391 MDPRINTK("ni_ai_cmd\n");
2392 if (dev->irq == 0) {
2393 comedi_error(dev, "cannot run command without an irq");
2396 ni_clear_ai_fifo(dev);
2398 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2400 /* start configuration */
2401 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2403 /* disable analog triggering for now, since it
2404 * interferes with the use of pfi0 */
2405 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2406 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2407 Analog_Trigger_Etc_Register);
2409 switch (cmd->start_src) {
2412 devpriv->stc_writew(dev, AI_START2_Select(0) |
2413 AI_START1_Sync | AI_START1_Edge |
2414 AI_START1_Select(0),
2415 AI_Trigger_Select_Register);
2419 int chan = CR_CHAN(cmd->start_arg);
2420 unsigned int bits = AI_START2_Select(0) |
2421 AI_START1_Sync | AI_START1_Select(chan + 1);
2423 if (cmd->start_arg & CR_INVERT)
2424 bits |= AI_START1_Polarity;
2425 if (cmd->start_arg & CR_EDGE)
2426 bits |= AI_START1_Edge;
2427 devpriv->stc_writew(dev, bits,
2428 AI_Trigger_Select_Register);
2433 mode2 &= ~AI_Pre_Trigger;
2434 mode2 &= ~AI_SC_Initial_Load_Source;
2435 mode2 &= ~AI_SC_Reload_Mode;
2436 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2438 if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2439 || (boardtype.reg_type == ni_reg_6143)) {
2440 start_stop_select |= AI_STOP_Polarity;
2441 start_stop_select |= AI_STOP_Select(31); /* logic low */
2442 start_stop_select |= AI_STOP_Sync;
2444 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2446 devpriv->stc_writew(dev, start_stop_select,
2447 AI_START_STOP_Select_Register);
2449 devpriv->ai_cmd2 = 0;
2450 switch (cmd->stop_src) {
2452 stop_count = cmd->stop_arg - 1;
2454 if (boardtype.reg_type == ni_reg_611x) {
2455 /* have to take 3 stage adc pipeline into account */
2456 stop_count += num_adc_stages_611x;
2458 /* stage number of scans */
2459 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2461 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2462 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2463 /* load SC (Scan Count) */
2464 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2466 devpriv->ai_continuous = 0;
2467 if (stop_count == 0) {
2468 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2469 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2470 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2471 if (cmd->chanlist_len > 1)
2472 start_stop_select |=
2473 AI_STOP_Polarity | AI_STOP_Edge;
2477 /* stage number of scans */
2478 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2480 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2481 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2483 /* load SC (Scan Count) */
2484 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2486 devpriv->ai_continuous = 1;
2491 switch (cmd->scan_begin_src) {
2494 stop bits for non 611x boards
2495 AI_SI_Special_Trigger_Delay=0
2497 AI_START_STOP_Select_Register:
2498 AI_START_Polarity=0 (?) rising edge
2499 AI_START_Edge=1 edge triggered
2501 AI_START_Select=0 SI_TC
2502 AI_STOP_Polarity=0 rising edge
2503 AI_STOP_Edge=0 level
2505 AI_STOP_Select=19 external pin (configuration mem)
2507 start_stop_select |= AI_START_Edge | AI_START_Sync;
2508 devpriv->stc_writew(dev, start_stop_select,
2509 AI_START_STOP_Select_Register);
2511 mode2 |= AI_SI_Reload_Mode(0);
2512 /* AI_SI_Initial_Load_Source=A */
2513 mode2 &= ~AI_SI_Initial_Load_Source;
2514 /* mode2 |= AI_SC_Reload_Mode; */
2515 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2518 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2519 TRIG_ROUND_NEAREST);
2520 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2521 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2524 if (cmd->scan_begin_arg & CR_EDGE)
2525 start_stop_select |= AI_START_Edge;
2526 /* AI_START_Polarity==1 is falling edge */
2527 if (cmd->scan_begin_arg & CR_INVERT)
2528 start_stop_select |= AI_START_Polarity;
2529 if (cmd->scan_begin_src != cmd->convert_src ||
2530 (cmd->scan_begin_arg & ~CR_EDGE) !=
2531 (cmd->convert_arg & ~CR_EDGE))
2532 start_stop_select |= AI_START_Sync;
2533 start_stop_select |=
2534 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2535 devpriv->stc_writew(dev, start_stop_select,
2536 AI_START_STOP_Select_Register);
2540 switch (cmd->convert_src) {
2543 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2546 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2547 TRIG_ROUND_NEAREST);
2548 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2549 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2551 /* AI_SI2_Reload_Mode = alternate */
2552 /* AI_SI2_Initial_Load_Source = A */
2553 mode2 &= ~AI_SI2_Initial_Load_Source;
2554 mode2 |= AI_SI2_Reload_Mode;
2555 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2558 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2560 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2561 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2563 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2566 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2567 if ((cmd->convert_arg & CR_INVERT) == 0)
2568 mode1 |= AI_CONVERT_Source_Polarity;
2569 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2571 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2572 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2579 /* interrupt on FIFO, errors, SC_TC */
2580 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2581 AI_SC_TC_Interrupt_Enable;
2584 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2587 if (cmd->flags & TRIG_WAKE_EOS
2588 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2589 /* wake on end-of-scan */
2590 devpriv->aimode = AIMODE_SCAN;
2592 devpriv->aimode = AIMODE_HALF_FULL;
2595 switch (devpriv->aimode) {
2596 case AIMODE_HALF_FULL:
2597 /*generate FIFO interrupts and DMA requests on half-full */
2599 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2600 AI_Mode_3_Register);
2602 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2603 AI_Mode_3_Register);
2607 /*generate FIFO interrupts on non-empty */
2608 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2609 AI_Mode_3_Register);
2613 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2614 AI_Mode_3_Register);
2616 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2617 AI_Mode_3_Register);
2619 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2625 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2627 ni_set_bits(dev, Interrupt_A_Enable_Register,
2628 interrupt_a_enable, 1);
2630 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2631 devpriv->int_a_enable_reg);
2633 /* interrupt on nothing */
2634 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2636 /* XXX start polling if necessary */
2637 MDPRINTK("interrupting on nothing\n");
2640 /* end configuration */
2641 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2643 switch (cmd->scan_begin_src) {
2645 devpriv->stc_writew(dev,
2646 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2647 AI_SC_Arm, AI_Command_1_Register);
2650 /* XXX AI_SI_Arm? */
2651 devpriv->stc_writew(dev,
2652 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2653 AI_SC_Arm, AI_Command_1_Register);
2659 int retval = ni_ai_setup_MITE_dma(dev);
2663 /* mite_dump_regs(devpriv->mite); */
2666 switch (cmd->start_src) {
2668 /* AI_START1_Pulse */
2669 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2670 AI_Command_2_Register);
2671 s->async->inttrig = NULL;
2674 s->async->inttrig = NULL;
2677 s->async->inttrig = &ni_ai_inttrig;
2681 MDPRINTK("exit ni_ai_cmd\n");
2686 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2687 unsigned int trignum)
2692 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2693 AI_Command_2_Register);
2694 s->async->inttrig = NULL;
2699 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2700 struct comedi_subdevice *s,
2701 struct comedi_insn *insn,
2702 unsigned int *data);
2704 static int ni_ai_insn_config(struct comedi_device *dev,
2705 struct comedi_subdevice *s,
2706 struct comedi_insn *insn, unsigned int *data)
2712 case INSN_CONFIG_ANALOG_TRIG:
2713 return ni_ai_config_analog_trig(dev, s, insn, data);
2714 case INSN_CONFIG_ALT_SOURCE:
2715 if (boardtype.reg_type & ni_reg_m_series_mask) {
2716 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2717 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2718 MSeries_AI_Bypass_Mode_Mux_Mask |
2719 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2722 devpriv->ai_calib_source = data[1];
2723 } else if (boardtype.reg_type == ni_reg_6143) {
2724 unsigned int calib_source;
2726 calib_source = data[1] & 0xf;
2728 if (calib_source > 0xF)
2731 devpriv->ai_calib_source = calib_source;
2732 ni_writew(calib_source, Calibration_Channel_6143);
2734 unsigned int calib_source;
2735 unsigned int calib_source_adjust;
2737 calib_source = data[1] & 0xf;
2738 calib_source_adjust = (data[1] >> 4) & 0xff;
2740 if (calib_source >= 8)
2742 devpriv->ai_calib_source = calib_source;
2743 if (boardtype.reg_type == ni_reg_611x) {
2744 ni_writeb(calib_source_adjust,
2745 Cal_Gain_Select_611x);
2756 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2757 struct comedi_subdevice *s,
2758 struct comedi_insn *insn,
2761 unsigned int a, b, modebits;
2765 * data[2] is analog line
2766 * data[3] is set level
2767 * data[4] is reset level */
2768 if (!boardtype.has_analog_trig)
2770 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2771 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2774 if (data[2] >= boardtype.n_adchan) {
2775 data[2] = boardtype.n_adchan - 1;
2778 if (data[3] > 255) { /* a */
2782 if (data[4] > 255) { /* b */
2793 * high mode 00 00 01 10
2794 * low mode 00 00 10 01
2796 * hysteresis low mode 10 00 00 01
2797 * hysteresis high mode 01 00 00 10
2798 * middle mode 10 01 01 10
2803 modebits = data[1] & 0xff;
2804 if (modebits & 0xf0) {
2805 /* two level mode */
2811 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2813 devpriv->atrig_low = a;
2814 devpriv->atrig_high = b;
2816 case 0x81: /* low hysteresis mode */
2817 devpriv->atrig_mode = 6;
2819 case 0x42: /* high hysteresis mode */
2820 devpriv->atrig_mode = 3;
2822 case 0x96: /* middle window mode */
2823 devpriv->atrig_mode = 2;
2830 /* one level mode */
2836 case 0x06: /* high window mode */
2837 devpriv->atrig_high = a;
2838 devpriv->atrig_mode = 0;
2840 case 0x09: /* low window mode */
2841 devpriv->atrig_low = a;
2842 devpriv->atrig_mode = 1;
2854 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2855 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2856 void *data, unsigned int num_bytes,
2857 unsigned int chan_index)
2859 struct comedi_async *async = s->async;
2862 unsigned int offset;
2863 unsigned int length = num_bytes / sizeof(short);
2864 short *array = data;
2866 offset = 1 << (boardtype.aobits - 1);
2867 for (i = 0; i < length; i++) {
2868 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2869 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2872 array[i] = cpu_to_le16(array[i]);
2875 chan_index %= async->cmd.chanlist_len;
2879 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2880 struct comedi_subdevice *s,
2881 unsigned int chanspec[],
2882 unsigned int n_chans, int timed)
2891 for (i = 0; i < boardtype.n_aochan; ++i) {
2892 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2893 ni_writeb(devpriv->ao_conf[i],
2894 M_Offset_AO_Config_Bank(i));
2895 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2898 for (i = 0; i < n_chans; i++) {
2899 const struct comedi_krange *krange;
2900 chan = CR_CHAN(chanspec[i]);
2901 range = CR_RANGE(chanspec[i]);
2902 krange = s->range_table->range + range;
2905 switch (krange->max - krange->min) {
2907 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2908 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2911 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2912 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2915 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2916 ni_writeb(MSeries_Attenuate_x5_Bit,
2917 M_Offset_AO_Reference_Attenuation(chan));
2920 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2921 ni_writeb(MSeries_Attenuate_x5_Bit,
2922 M_Offset_AO_Reference_Attenuation(chan));
2925 printk("%s: bug! unhandled ao reference voltage\n",
2929 switch (krange->max + krange->min) {
2931 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2934 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2937 printk("%s: bug! unhandled ao offset voltage\n",
2942 conf |= MSeries_AO_Update_Timed_Bit;
2943 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2944 devpriv->ao_conf[chan] = conf;
2945 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2950 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2951 struct comedi_subdevice *s,
2952 unsigned int chanspec[],
2953 unsigned int n_chans)
2961 for (i = 0; i < n_chans; i++) {
2962 chan = CR_CHAN(chanspec[i]);
2963 range = CR_RANGE(chanspec[i]);
2964 conf = AO_Channel(chan);
2966 if (boardtype.ao_unipolar) {
2967 if ((range & 1) == 0) {
2969 invert = (1 << (boardtype.aobits - 1));
2977 invert = (1 << (boardtype.aobits - 1));
2980 /* not all boards can deglitch, but this shouldn't hurt */
2981 if (chanspec[i] & CR_DEGLITCH)
2982 conf |= AO_Deglitch;
2984 /* analog reference */
2985 /* AREF_OTHER connects AO ground to AI ground, i think */
2986 conf |= (CR_AREF(chanspec[i]) ==
2987 AREF_OTHER) ? AO_Ground_Ref : 0;
2989 ni_writew(conf, AO_Configuration);
2990 devpriv->ao_conf[chan] = conf;
2995 static int ni_ao_config_chanlist(struct comedi_device *dev,
2996 struct comedi_subdevice *s,
2997 unsigned int chanspec[], unsigned int n_chans,
3000 if (boardtype.reg_type & ni_reg_m_series_mask)
3001 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3004 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3007 static int ni_ao_insn_read(struct comedi_device *dev,
3008 struct comedi_subdevice *s, struct comedi_insn *insn,
3011 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3016 static int ni_ao_insn_write(struct comedi_device *dev,
3017 struct comedi_subdevice *s,
3018 struct comedi_insn *insn, unsigned int *data)
3020 unsigned int chan = CR_CHAN(insn->chanspec);
3021 unsigned int invert;
3023 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3025 devpriv->ao[chan] = data[0];
3027 if (boardtype.reg_type & ni_reg_m_series_mask) {
3028 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3030 ni_writew(data[0] ^ invert,
3031 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3036 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3037 struct comedi_subdevice *s,
3038 struct comedi_insn *insn, unsigned int *data)
3040 unsigned int chan = CR_CHAN(insn->chanspec);
3041 unsigned int invert;
3043 ao_win_out(1 << chan, AO_Immediate_671x);
3044 invert = 1 << (boardtype.aobits - 1);
3046 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3048 devpriv->ao[chan] = data[0];
3049 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3054 static int ni_ao_insn_config(struct comedi_device *dev,
3055 struct comedi_subdevice *s,
3056 struct comedi_insn *insn, unsigned int *data)
3059 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3062 data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short);
3064 data[2] += devpriv->mite->fifo_size;
3081 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3082 unsigned int trignum)
3085 int interrupt_b_bits;
3087 static const int timeout = 1000;
3092 /* Null trig at beginning prevent ao start trigger from executing more than
3093 once per command (and doing things like trying to allocate the ao dma channel
3095 s->async->inttrig = NULL;
3097 ni_set_bits(dev, Interrupt_B_Enable_Register,
3098 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3099 interrupt_b_bits = AO_Error_Interrupt_Enable;
3101 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3102 if (boardtype.reg_type & ni_reg_6xxx_mask)
3103 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3104 ret = ni_ao_setup_MITE_dma(dev);
3107 ret = ni_ao_wait_for_dma_load(dev);
3111 ret = ni_ao_prep_fifo(dev, s);
3115 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3118 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3119 AO_Mode_3_Register);
3120 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3121 /* wait for DACs to be loaded */
3122 for (i = 0; i < timeout; i++) {
3124 if ((devpriv->stc_readw(dev,
3125 Joint_Status_2_Register) &
3126 AO_TMRDACWRs_In_Progress_St) == 0)
3131 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3134 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3135 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3136 Interrupt_B_Ack_Register);
3138 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3140 devpriv->stc_writew(dev,
3141 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3142 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3143 AO_Command_1_Register);
3145 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3146 AO_Command_2_Register);
3151 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3153 const struct comedi_cmd *cmd = &s->async->cmd;
3158 if (dev->irq == 0) {
3159 comedi_error(dev, "cannot run command without an irq");
3163 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3165 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3167 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3168 ao_win_out(CLEAR_WG, AO_Misc_611x);
3171 for (i = 0; i < cmd->chanlist_len; i++) {
3174 chan = CR_CHAN(cmd->chanlist[i]);
3176 ao_win_out(chan, AO_Waveform_Generation_611x);
3178 ao_win_out(bits, AO_Timed_611x);
3181 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3183 if (cmd->stop_src == TRIG_NONE) {
3184 devpriv->ao_mode1 |= AO_Continuous;
3185 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3187 devpriv->ao_mode1 &= ~AO_Continuous;
3188 devpriv->ao_mode1 |= AO_Trigger_Once;
3190 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3191 switch (cmd->start_src) {
3194 devpriv->ao_trigger_select &=
3195 ~(AO_START1_Polarity | AO_START1_Select(-1));
3196 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3197 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3198 AO_Trigger_Select_Register);
3201 devpriv->ao_trigger_select =
3202 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3203 if (cmd->start_arg & CR_INVERT)
3204 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3205 if (cmd->start_arg & CR_EDGE)
3206 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3207 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3208 AO_Trigger_Select_Register);
3214 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3215 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3217 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3218 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3219 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3220 if (cmd->stop_src == TRIG_NONE) {
3221 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3223 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3225 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3226 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3227 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3228 switch (cmd->stop_src) {
3230 if (boardtype.reg_type & ni_reg_m_series_mask) {
3231 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3232 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3233 AO_UC_Load_A_Register);
3234 devpriv->stc_writew(dev, AO_UC_Load,
3235 AO_Command_1_Register);
3237 devpriv->stc_writel(dev, cmd->stop_arg,
3238 AO_UC_Load_A_Register);
3239 devpriv->stc_writew(dev, AO_UC_Load,
3240 AO_Command_1_Register);
3241 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3242 AO_UC_Load_A_Register);
3246 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3247 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3248 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3251 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3252 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3253 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3256 devpriv->ao_mode1 &=
3257 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3258 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3259 switch (cmd->scan_begin_src) {
3261 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3263 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3264 TRIG_ROUND_NEAREST);
3265 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3266 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3267 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3270 devpriv->ao_mode1 |=
3271 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3272 if (cmd->scan_begin_arg & CR_INVERT)
3273 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3274 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3280 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3281 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3282 devpriv->ao_mode2 &=
3283 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3284 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3286 if (cmd->scan_end_arg > 1) {
3287 devpriv->ao_mode1 |= AO_Multiple_Channels;
3288 devpriv->stc_writew(dev,
3289 AO_Number_Of_Channels(cmd->scan_end_arg -
3291 AO_UPDATE_Output_Select
3292 (AO_Update_Output_High_Z),
3293 AO_Output_Control_Register);
3296 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3297 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3299 reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3300 bits |= AO_Number_Of_Channels(0);
3303 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3305 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3307 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3309 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3310 AO_Command_1_Register);
3312 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3313 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3315 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3317 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3319 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3321 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3322 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3324 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3325 AO_TMRDACWR_Pulse_Width;
3326 if (boardtype.ao_fifo_depth)
3327 bits |= AO_FIFO_Enable;
3329 bits |= AO_DMA_PIO_Control;
3331 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3332 verified with bus analyzer. */
3333 if (boardtype.reg_type & ni_reg_m_series_mask)
3334 bits |= AO_Number_Of_DAC_Packages;
3336 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3337 /* enable sending of ao dma requests */
3338 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3340 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3342 if (cmd->stop_src == TRIG_COUNT) {
3343 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3344 Interrupt_B_Ack_Register);
3345 ni_set_bits(dev, Interrupt_B_Enable_Register,
3346 AO_BC_TC_Interrupt_Enable, 1);
3349 s->async->inttrig = &ni_ao_inttrig;
3354 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3355 struct comedi_cmd *cmd)
3360 /* step 1: make sure trigger sources are trivially valid */
3362 if ((cmd->flags & CMDF_WRITE) == 0) {
3363 cmd->flags |= CMDF_WRITE;
3366 tmp = cmd->start_src;
3367 cmd->start_src &= TRIG_INT | TRIG_EXT;
3368 if (!cmd->start_src || tmp != cmd->start_src)
3371 tmp = cmd->scan_begin_src;
3372 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3373 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3376 tmp = cmd->convert_src;
3377 cmd->convert_src &= TRIG_NOW;
3378 if (!cmd->convert_src || tmp != cmd->convert_src)
3381 tmp = cmd->scan_end_src;
3382 cmd->scan_end_src &= TRIG_COUNT;
3383 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3386 tmp = cmd->stop_src;
3387 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
3388 if (!cmd->stop_src || tmp != cmd->stop_src)
3394 /* step 2: make sure trigger sources are unique and mutually compatible */
3396 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
3402 /* step 3: make sure arguments are trivially compatible */
3404 if (cmd->start_src == TRIG_EXT) {
3405 /* external trigger */
3406 unsigned int tmp = CR_CHAN(cmd->start_arg);
3410 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3411 if (cmd->start_arg != tmp) {
3412 cmd->start_arg = tmp;
3416 if (cmd->start_arg != 0) {
3417 /* true for both TRIG_NOW and TRIG_INT */
3422 if (cmd->scan_begin_src == TRIG_TIMER) {
3423 if (cmd->scan_begin_arg < boardtype.ao_speed) {
3424 cmd->scan_begin_arg = boardtype.ao_speed;
3427 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { /* XXX check */
3428 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3432 if (cmd->convert_arg != 0) {
3433 cmd->convert_arg = 0;
3436 if (cmd->scan_end_arg != cmd->chanlist_len) {
3437 cmd->scan_end_arg = cmd->chanlist_len;
3440 if (cmd->stop_src == TRIG_COUNT) { /* XXX check */
3441 if (cmd->stop_arg > 0x00ffffff) {
3442 cmd->stop_arg = 0x00ffffff;
3447 if (cmd->stop_arg != 0) {
3456 /* step 4: fix up any arguments */
3457 if (cmd->scan_begin_src == TRIG_TIMER) {
3458 tmp = cmd->scan_begin_arg;
3459 cmd->scan_begin_arg =
3460 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3461 cmd->scan_begin_arg,
3465 if (tmp != cmd->scan_begin_arg)
3471 /* step 5: fix up chanlist */
3479 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3481 /* devpriv->ao0p=0x0000; */
3482 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3484 /* devpriv->ao1p=AO_Channel(1); */
3485 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3487 ni_release_ao_mite_channel(dev);
3489 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3490 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3491 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3492 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3493 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3494 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3495 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3496 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3497 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3498 devpriv->ao_cmd1 = 0;
3499 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3500 devpriv->ao_cmd2 = 0;
3501 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3502 devpriv->ao_mode1 = 0;
3503 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3504 devpriv->ao_mode2 = 0;
3505 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3506 if (boardtype.reg_type & ni_reg_m_series_mask)
3507 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3509 devpriv->ao_mode3 = 0;
3510 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3511 devpriv->ao_trigger_select = 0;
3512 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3513 AO_Trigger_Select_Register);
3514 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3515 unsigned immediate_bits = 0;
3517 for (i = 0; i < s->n_chan; ++i) {
3518 immediate_bits |= 1 << i;
3520 ao_win_out(immediate_bits, AO_Immediate_671x);
3521 ao_win_out(CLEAR_WG, AO_Misc_611x);
3523 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3530 static int ni_dio_insn_config(struct comedi_device *dev,
3531 struct comedi_subdevice *s,
3532 struct comedi_insn *insn, unsigned int *data)
3535 printk("ni_dio_insn_config() chan=%d io=%d\n",
3536 CR_CHAN(insn->chanspec), data[0]);
3539 case INSN_CONFIG_DIO_OUTPUT:
3540 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3542 case INSN_CONFIG_DIO_INPUT:
3543 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3545 case INSN_CONFIG_DIO_QUERY:
3548 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3556 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3557 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3558 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3563 static int ni_dio_insn_bits(struct comedi_device *dev,
3564 struct comedi_subdevice *s,
3565 struct comedi_insn *insn, unsigned int *data)
3568 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3573 /* Perform check to make sure we're not using the
3574 serial part of the dio */
3575 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3576 && devpriv->serial_interval_ns)
3579 s->state &= ~data[0];
3580 s->state |= (data[0] & data[1]);
3581 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3582 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3583 devpriv->stc_writew(dev, devpriv->dio_output,
3584 DIO_Output_Register);
3586 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3591 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3592 struct comedi_subdevice *s,
3593 struct comedi_insn *insn,
3597 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3598 CR_CHAN(insn->chanspec), data[0]);
3601 case INSN_CONFIG_DIO_OUTPUT:
3602 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3604 case INSN_CONFIG_DIO_INPUT:
3605 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3607 case INSN_CONFIG_DIO_QUERY:
3610 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3618 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3623 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3624 struct comedi_subdevice *s,
3625 struct comedi_insn *insn,
3629 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3635 s->state &= ~data[0];
3636 s->state |= (data[0] & data[1]);
3637 ni_writel(s->state, M_Offset_Static_Digital_Output);
3639 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3644 static int ni_cdio_cmdtest(struct comedi_device *dev,
3645 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3652 /* step 1: make sure trigger sources are trivially valid */
3654 tmp = cmd->start_src;
3656 cmd->start_src &= sources;
3657 if (!cmd->start_src || tmp != cmd->start_src)
3660 tmp = cmd->scan_begin_src;
3661 cmd->scan_begin_src &= TRIG_EXT;
3662 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3665 tmp = cmd->convert_src;
3666 cmd->convert_src &= TRIG_NOW;
3667 if (!cmd->convert_src || tmp != cmd->convert_src)
3670 tmp = cmd->scan_end_src;
3671 cmd->scan_end_src &= TRIG_COUNT;
3672 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3675 tmp = cmd->stop_src;
3676 cmd->stop_src &= TRIG_NONE;
3677 if (!cmd->stop_src || tmp != cmd->stop_src)
3683 /* step 2: make sure trigger sources are unique... */
3685 if (cmd->start_src != TRIG_INT)
3687 if (cmd->scan_begin_src != TRIG_EXT)
3689 if (cmd->convert_src != TRIG_NOW)
3691 if (cmd->stop_src != TRIG_NONE)
3693 /* ... and mutually compatible */
3698 /* step 3: make sure arguments are trivially compatible */
3699 if (cmd->start_src == TRIG_INT) {
3700 if (cmd->start_arg != 0) {
3705 if (cmd->scan_begin_src == TRIG_EXT) {
3706 tmp = cmd->scan_begin_arg;
3707 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0,
3709 if (tmp != cmd->scan_begin_arg) {
3713 if (cmd->convert_src == TRIG_NOW) {
3714 if (cmd->convert_arg) {
3715 cmd->convert_arg = 0;
3720 if (cmd->scan_end_arg != cmd->chanlist_len) {
3721 cmd->scan_end_arg = cmd->chanlist_len;
3725 if (cmd->stop_src == TRIG_NONE) {
3726 if (cmd->stop_arg != 0) {
3735 /* step 4: fix up any arguments */
3740 /* step 5: check chanlist */
3742 for (i = 0; i < cmd->chanlist_len; ++i) {
3743 if (cmd->chanlist[i] != i)
3753 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3755 const struct comedi_cmd *cmd = &s->async->cmd;
3756 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3759 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3760 switch (cmd->scan_begin_src) {
3763 CR_CHAN(cmd->scan_begin_arg) &
3764 CDO_Sample_Source_Select_Mask;
3770 if (cmd->scan_begin_arg & CR_INVERT)
3771 cdo_mode_bits |= CDO_Polarity_Bit;
3772 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3774 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3775 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3776 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3779 "attempted to run digital output command with no lines configured as outputs");
3782 retval = ni_request_cdo_mite_channel(dev);
3786 s->async->inttrig = &ni_cdo_inttrig;
3790 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3791 unsigned int trignum)
3794 unsigned long flags;
3798 const unsigned timeout = 1000;
3800 s->async->inttrig = NULL;
3802 /* read alloc the entire buffer */
3803 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3806 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3807 if (devpriv->cdo_mite_chan) {
3808 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3809 mite_dma_arm(devpriv->cdo_mite_chan);
3811 comedi_error(dev, "BUG: no cdo mite channel?");
3814 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3819 * XXX not sure what interrupt C group does
3820 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3821 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3823 for (i = 0; i < timeout; ++i) {
3824 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3829 comedi_error(dev, "dma failed to fill cdo fifo!");
3830 ni_cdio_cancel(dev, s);
3833 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3834 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3835 M_Offset_CDIO_Command);
3839 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3841 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3842 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3843 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3844 M_Offset_CDIO_Command);
3846 * XXX not sure what interrupt C group does ni_writeb(0,
3847 * M_Offset_Interrupt_C_Enable);
3849 ni_writel(0, M_Offset_CDO_Mask_Enable);
3850 ni_release_cdo_mite_channel(dev);
3854 static void handle_cdio_interrupt(struct comedi_device *dev)
3856 unsigned cdio_status;
3857 struct comedi_subdevice *s = dev->subdevices + NI_DIO_SUBDEV;
3859 unsigned long flags;
3862 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3866 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3867 if (devpriv->cdo_mite_chan) {
3868 unsigned cdo_mite_status =
3869 mite_get_status(devpriv->cdo_mite_chan);
3870 if (cdo_mite_status & CHSR_LINKC) {
3872 devpriv->mite->mite_io_addr +
3873 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3875 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3877 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3880 cdio_status = ni_readl(M_Offset_CDIO_Status);
3881 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3882 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3883 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3884 s->async->events |= COMEDI_CB_OVERFLOW;
3886 if (cdio_status & CDO_FIFO_Empty_Bit) {
3887 /* printk("cdio fifo empty\n"); */
3888 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3889 M_Offset_CDIO_Command);
3890 /* s->async->events |= COMEDI_CB_EOA; */
3895 static int ni_serial_insn_config(struct comedi_device *dev,
3896 struct comedi_subdevice *s,
3897 struct comedi_insn *insn, unsigned int *data)
3900 unsigned char byte_out, byte_in = 0;
3906 case INSN_CONFIG_SERIAL_CLOCK:
3909 printk("SPI serial clock Config cd\n", data[1]);
3911 devpriv->serial_hw_mode = 1;
3912 devpriv->dio_control |= DIO_HW_Serial_Enable;
3914 if (data[1] == SERIAL_DISABLED) {
3915 devpriv->serial_hw_mode = 0;
3916 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3917 DIO_Software_Serial_Control);
3918 data[1] = SERIAL_DISABLED;
3919 devpriv->serial_interval_ns = data[1];
3920 } else if (data[1] <= SERIAL_600NS) {
3921 /* Warning: this clock speed is too fast to reliably
3923 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3924 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3925 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3926 data[1] = SERIAL_600NS;
3927 devpriv->serial_interval_ns = data[1];
3928 } else if (data[1] <= SERIAL_1_2US) {
3929 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3930 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3931 DIO_Serial_Out_Divide_By_2;
3932 data[1] = SERIAL_1_2US;
3933 devpriv->serial_interval_ns = data[1];
3934 } else if (data[1] <= SERIAL_10US) {
3935 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3936 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3937 DIO_Serial_Out_Divide_By_2;
3938 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3939 600ns/1.2us. If you turn divide_by_2 off with the
3940 slow clock, you will still get 10us, except then
3941 all your delays are wrong. */
3942 data[1] = SERIAL_10US;
3943 devpriv->serial_interval_ns = data[1];
3945 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3946 DIO_Software_Serial_Control);
3947 devpriv->serial_hw_mode = 0;
3948 data[1] = (data[1] / 1000) * 1000;
3949 devpriv->serial_interval_ns = data[1];
3952 devpriv->stc_writew(dev, devpriv->dio_control,
3953 DIO_Control_Register);
3954 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3955 Clock_and_FOUT_Register);
3960 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3962 if (devpriv->serial_interval_ns == 0) {
3966 byte_out = data[1] & 0xFF;
3968 if (devpriv->serial_hw_mode) {
3969 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3971 } else if (devpriv->serial_interval_ns > 0) {
3972 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3975 printk("ni_serial_insn_config: serial disabled!\n");
3980 data[1] = byte_in & 0xFF;
3990 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3991 struct comedi_subdevice *s,
3992 unsigned char data_out,
3993 unsigned char *data_in)
3995 unsigned int status1;
3996 int err = 0, count = 20;
3999 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
4002 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
4003 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
4004 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
4006 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
4007 if (status1 & DIO_Serial_IO_In_Progress_St) {
4012 devpriv->dio_control |= DIO_HW_Serial_Start;
4013 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4014 devpriv->dio_control &= ~DIO_HW_Serial_Start;
4016 /* Wait until STC says we're done, but don't loop infinitely. */
4018 devpriv->stc_readw(dev,
4019 Joint_Status_1_Register)) &
4020 DIO_Serial_IO_In_Progress_St) {
4021 /* Delay one bit per loop */
4022 udelay((devpriv->serial_interval_ns + 999) / 1000);
4025 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
4031 /* Delay for last bit. This delay is absolutely necessary, because
4032 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
4033 udelay((devpriv->serial_interval_ns + 999) / 1000);
4035 if (data_in != NULL) {
4036 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4038 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4043 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4048 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4049 struct comedi_subdevice *s,
4050 unsigned char data_out,
4051 unsigned char *data_in)
4053 unsigned char mask, input = 0;
4056 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4059 /* Wait for one bit before transfer */
4060 udelay((devpriv->serial_interval_ns + 999) / 1000);
4062 for (mask = 0x80; mask; mask >>= 1) {
4063 /* Output current bit; note that we cannot touch s->state
4064 because it is a per-subdevice field, and serial is
4065 a separate subdevice from DIO. */
4066 devpriv->dio_output &= ~DIO_SDOUT;
4067 if (data_out & mask) {
4068 devpriv->dio_output |= DIO_SDOUT;
4070 devpriv->stc_writew(dev, devpriv->dio_output,
4071 DIO_Output_Register);
4073 /* Assert SDCLK (active low, inverted), wait for half of
4074 the delay, deassert SDCLK, and wait for the other half. */
4075 devpriv->dio_control |= DIO_Software_Serial_Control;
4076 devpriv->stc_writew(dev, devpriv->dio_control,
4077 DIO_Control_Register);
4079 udelay((devpriv->serial_interval_ns + 999) / 2000);
4081 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4082 devpriv->stc_writew(dev, devpriv->dio_control,
4083 DIO_Control_Register);
4085 udelay((devpriv->serial_interval_ns + 999) / 2000);
4087 /* Input current bit */
4088 if (devpriv->stc_readw(dev,
4089 DIO_Parallel_Input_Register) & DIO_SDIN)
4091 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4096 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4104 static void mio_common_detach(struct comedi_device *dev)
4107 if (devpriv->counter_dev) {
4108 ni_gpct_device_destroy(devpriv->counter_dev);
4111 if (dev->subdevices && boardtype.has_8255)
4112 subdev_8255_cleanup(dev, dev->subdevices + NI_8255_DIO_SUBDEV);
4115 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4119 for (i = 0; i < s->n_chan; i++) {
4120 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4121 AO_Configuration_2_67xx);
4123 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4126 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4128 unsigned stc_register;
4130 case NITIO_G0_Autoincrement_Reg:
4131 stc_register = G_Autoincrement_Register(0);
4133 case NITIO_G1_Autoincrement_Reg:
4134 stc_register = G_Autoincrement_Register(1);
4136 case NITIO_G0_Command_Reg:
4137 stc_register = G_Command_Register(0);
4139 case NITIO_G1_Command_Reg:
4140 stc_register = G_Command_Register(1);
4142 case NITIO_G0_HW_Save_Reg:
4143 stc_register = G_HW_Save_Register(0);
4145 case NITIO_G1_HW_Save_Reg:
4146 stc_register = G_HW_Save_Register(1);
4148 case NITIO_G0_SW_Save_Reg:
4149 stc_register = G_Save_Register(0);
4151 case NITIO_G1_SW_Save_Reg:
4152 stc_register = G_Save_Register(1);
4154 case NITIO_G0_Mode_Reg:
4155 stc_register = G_Mode_Register(0);
4157 case NITIO_G1_Mode_Reg:
4158 stc_register = G_Mode_Register(1);
4160 case NITIO_G0_LoadA_Reg:
4161 stc_register = G_Load_A_Register(0);
4163 case NITIO_G1_LoadA_Reg:
4164 stc_register = G_Load_A_Register(1);
4166 case NITIO_G0_LoadB_Reg:
4167 stc_register = G_Load_B_Register(0);
4169 case NITIO_G1_LoadB_Reg:
4170 stc_register = G_Load_B_Register(1);
4172 case NITIO_G0_Input_Select_Reg:
4173 stc_register = G_Input_Select_Register(0);
4175 case NITIO_G1_Input_Select_Reg:
4176 stc_register = G_Input_Select_Register(1);
4178 case NITIO_G01_Status_Reg:
4179 stc_register = G_Status_Register;
4181 case NITIO_G01_Joint_Reset_Reg:
4182 stc_register = Joint_Reset_Register;
4184 case NITIO_G01_Joint_Status1_Reg:
4185 stc_register = Joint_Status_1_Register;
4187 case NITIO_G01_Joint_Status2_Reg:
4188 stc_register = Joint_Status_2_Register;
4190 case NITIO_G0_Interrupt_Acknowledge_Reg:
4191 stc_register = Interrupt_A_Ack_Register;
4193 case NITIO_G1_Interrupt_Acknowledge_Reg:
4194 stc_register = Interrupt_B_Ack_Register;
4196 case NITIO_G0_Status_Reg:
4197 stc_register = AI_Status_1_Register;
4199 case NITIO_G1_Status_Reg:
4200 stc_register = AO_Status_1_Register;
4202 case NITIO_G0_Interrupt_Enable_Reg:
4203 stc_register = Interrupt_A_Enable_Register;
4205 case NITIO_G1_Interrupt_Enable_Reg:
4206 stc_register = Interrupt_B_Enable_Register;
4209 printk("%s: unhandled register 0x%x in switch.\n",
4215 return stc_register;
4218 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4219 enum ni_gpct_register reg)
4221 struct comedi_device *dev = counter->counter_dev->dev;
4222 unsigned stc_register;
4223 /* bits in the join reset register which are relevant to counters */
4224 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4225 static const unsigned gpct_interrupt_a_enable_mask =
4226 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4227 static const unsigned gpct_interrupt_b_enable_mask =
4228 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4231 /* m-series-only registers */
4232 case NITIO_G0_Counting_Mode_Reg:
4233 ni_writew(bits, M_Offset_G0_Counting_Mode);
4235 case NITIO_G1_Counting_Mode_Reg:
4236 ni_writew(bits, M_Offset_G1_Counting_Mode);
4238 case NITIO_G0_Second_Gate_Reg:
4239 ni_writew(bits, M_Offset_G0_Second_Gate);
4241 case NITIO_G1_Second_Gate_Reg:
4242 ni_writew(bits, M_Offset_G1_Second_Gate);
4244 case NITIO_G0_DMA_Config_Reg:
4245 ni_writew(bits, M_Offset_G0_DMA_Config);
4247 case NITIO_G1_DMA_Config_Reg:
4248 ni_writew(bits, M_Offset_G1_DMA_Config);
4250 case NITIO_G0_ABZ_Reg:
4251 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4253 case NITIO_G1_ABZ_Reg:
4254 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4257 /* 32 bit registers */
4258 case NITIO_G0_LoadA_Reg:
4259 case NITIO_G1_LoadA_Reg:
4260 case NITIO_G0_LoadB_Reg:
4261 case NITIO_G1_LoadB_Reg:
4262 stc_register = ni_gpct_to_stc_register(reg);
4263 devpriv->stc_writel(dev, bits, stc_register);
4266 /* 16 bit registers */
4267 case NITIO_G0_Interrupt_Enable_Reg:
4268 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4269 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4270 gpct_interrupt_a_enable_mask, bits);
4272 case NITIO_G1_Interrupt_Enable_Reg:
4273 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4274 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4275 gpct_interrupt_b_enable_mask, bits);
4277 case NITIO_G01_Joint_Reset_Reg:
4278 BUG_ON(bits & ~gpct_joint_reset_mask);
4281 stc_register = ni_gpct_to_stc_register(reg);
4282 devpriv->stc_writew(dev, bits, stc_register);
4286 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4287 enum ni_gpct_register reg)
4289 struct comedi_device *dev = counter->counter_dev->dev;
4290 unsigned stc_register;
4292 /* m-series only registers */
4293 case NITIO_G0_DMA_Status_Reg:
4294 return ni_readw(M_Offset_G0_DMA_Status);
4296 case NITIO_G1_DMA_Status_Reg:
4297 return ni_readw(M_Offset_G1_DMA_Status);
4300 /* 32 bit registers */
4301 case NITIO_G0_HW_Save_Reg:
4302 case NITIO_G1_HW_Save_Reg:
4303 case NITIO_G0_SW_Save_Reg:
4304 case NITIO_G1_SW_Save_Reg:
4305 stc_register = ni_gpct_to_stc_register(reg);
4306 return devpriv->stc_readl(dev, stc_register);
4309 /* 16 bit registers */
4311 stc_register = ni_gpct_to_stc_register(reg);
4312 return devpriv->stc_readw(dev, stc_register);
4318 static int ni_freq_out_insn_read(struct comedi_device *dev,
4319 struct comedi_subdevice *s,
4320 struct comedi_insn *insn, unsigned int *data)
4322 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4326 static int ni_freq_out_insn_write(struct comedi_device *dev,
4327 struct comedi_subdevice *s,
4328 struct comedi_insn *insn, unsigned int *data)
4330 devpriv->clock_and_fout &= ~FOUT_Enable;
4331 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4332 Clock_and_FOUT_Register);
4333 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4334 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4335 devpriv->clock_and_fout |= FOUT_Enable;
4336 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4337 Clock_and_FOUT_Register);
4341 static int ni_set_freq_out_clock(struct comedi_device *dev,
4342 unsigned int clock_source)
4344 switch (clock_source) {
4345 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4346 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4348 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4349 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4354 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4355 Clock_and_FOUT_Register);
4359 static void ni_get_freq_out_clock(struct comedi_device *dev,
4360 unsigned int *clock_source,
4361 unsigned int *clock_period_ns)
4363 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4364 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4365 *clock_period_ns = TIMEBASE_2_NS;
4367 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4368 *clock_period_ns = TIMEBASE_1_NS * 2;
4372 static int ni_freq_out_insn_config(struct comedi_device *dev,
4373 struct comedi_subdevice *s,
4374 struct comedi_insn *insn, unsigned int *data)
4377 case INSN_CONFIG_SET_CLOCK_SRC:
4378 return ni_set_freq_out_clock(dev, data[1]);
4380 case INSN_CONFIG_GET_CLOCK_SRC:
4381 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4389 static int ni_alloc_private(struct comedi_device *dev)
4393 ret = alloc_private(dev, sizeof(struct ni_private));
4397 spin_lock_init(&devpriv->window_lock);
4398 spin_lock_init(&devpriv->soft_reg_copy_lock);
4399 spin_lock_init(&devpriv->mite_channel_lock);
4404 static int ni_E_init(struct comedi_device *dev, struct comedi_devconfig *it)
4406 struct comedi_subdevice *s;
4408 enum ni_gpct_variant counter_variant;
4410 if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4411 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4415 if (alloc_subdevices(dev, NI_NUM_SUBDEVICES) < 0)
4418 /* analog input subdevice */
4420 s = dev->subdevices + NI_AI_SUBDEV;
4421 dev->read_subdev = s;
4422 if (boardtype.n_adchan) {
4423 s->type = COMEDI_SUBD_AI;
4425 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4426 if (boardtype.reg_type != ni_reg_611x)
4427 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4428 if (boardtype.adbits > 16)
4429 s->subdev_flags |= SDF_LSAMPL;
4430 if (boardtype.reg_type & ni_reg_m_series_mask)
4431 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4432 s->n_chan = boardtype.n_adchan;
4433 s->len_chanlist = 512;
4434 s->maxdata = (1 << boardtype.adbits) - 1;
4435 s->range_table = ni_range_lkup[boardtype.gainlkup];
4436 s->insn_read = &ni_ai_insn_read;
4437 s->insn_config = &ni_ai_insn_config;
4438 s->do_cmdtest = &ni_ai_cmdtest;
4439 s->do_cmd = &ni_ai_cmd;
4440 s->cancel = &ni_ai_reset;
4441 s->poll = &ni_ai_poll;
4442 s->munge = &ni_ai_munge;
4444 s->async_dma_dir = DMA_FROM_DEVICE;
4447 s->type = COMEDI_SUBD_UNUSED;
4450 /* analog output subdevice */
4452 s = dev->subdevices + NI_AO_SUBDEV;
4453 if (boardtype.n_aochan) {
4454 s->type = COMEDI_SUBD_AO;
4455 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4456 if (boardtype.reg_type & ni_reg_m_series_mask)
4457 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4458 s->n_chan = boardtype.n_aochan;
4459 s->maxdata = (1 << boardtype.aobits) - 1;
4460 s->range_table = boardtype.ao_range_table;
4461 s->insn_read = &ni_ao_insn_read;
4462 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4463 s->insn_write = &ni_ao_insn_write_671x;
4465 s->insn_write = &ni_ao_insn_write;
4467 s->insn_config = &ni_ao_insn_config;
4469 if (boardtype.n_aochan) {
4470 s->async_dma_dir = DMA_TO_DEVICE;
4472 if (boardtype.ao_fifo_depth) {
4474 dev->write_subdev = s;
4475 s->subdev_flags |= SDF_CMD_WRITE;
4476 s->do_cmd = &ni_ao_cmd;
4477 s->do_cmdtest = &ni_ao_cmdtest;
4478 s->len_chanlist = boardtype.n_aochan;
4479 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4480 s->munge = ni_ao_munge;
4482 s->cancel = &ni_ao_reset;
4484 s->type = COMEDI_SUBD_UNUSED;
4486 if ((boardtype.reg_type & ni_reg_67xx_mask))
4487 init_ao_67xx(dev, s);
4489 /* digital i/o subdevice */
4491 s = dev->subdevices + NI_DIO_SUBDEV;
4492 s->type = COMEDI_SUBD_DIO;
4493 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4495 s->io_bits = 0; /* all bits input */
4496 s->range_table = &range_digital;
4497 s->n_chan = boardtype.num_p0_dio_channels;
4498 if (boardtype.reg_type & ni_reg_m_series_mask) {
4500 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4501 s->insn_bits = &ni_m_series_dio_insn_bits;
4502 s->insn_config = &ni_m_series_dio_insn_config;
4503 s->do_cmd = &ni_cdio_cmd;
4504 s->do_cmdtest = &ni_cdio_cmdtest;
4505 s->cancel = &ni_cdio_cancel;
4506 s->async_dma_dir = DMA_BIDIRECTIONAL;
4507 s->len_chanlist = s->n_chan;
4509 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4510 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4512 s->insn_bits = &ni_dio_insn_bits;
4513 s->insn_config = &ni_dio_insn_config;
4514 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4515 ni_writew(devpriv->dio_control, DIO_Control_Register);
4519 s = dev->subdevices + NI_8255_DIO_SUBDEV;
4520 if (boardtype.has_8255) {
4521 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4523 s->type = COMEDI_SUBD_UNUSED;
4526 /* formerly general purpose counter/timer device, but no longer used */
4527 s = dev->subdevices + NI_UNUSED_SUBDEV;
4528 s->type = COMEDI_SUBD_UNUSED;
4530 /* calibration subdevice -- ai and ao */
4531 s = dev->subdevices + NI_CALIBRATION_SUBDEV;
4532 s->type = COMEDI_SUBD_CALIB;
4533 if (boardtype.reg_type & ni_reg_m_series_mask) {
4534 /* internal PWM analog output used for AI nonlinearity calibration */
4535 s->subdev_flags = SDF_INTERNAL;
4536 s->insn_config = &ni_m_series_pwm_config;
4539 ni_writel(0x0, M_Offset_Cal_PWM);
4540 } else if (boardtype.reg_type == ni_reg_6143) {
4541 /* internal PWM analog output used for AI nonlinearity calibration */
4542 s->subdev_flags = SDF_INTERNAL;
4543 s->insn_config = &ni_6143_pwm_config;
4547 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4548 s->insn_read = &ni_calib_insn_read;
4549 s->insn_write = &ni_calib_insn_write;
4550 caldac_setup(dev, s);
4554 s = dev->subdevices + NI_EEPROM_SUBDEV;
4555 s->type = COMEDI_SUBD_MEMORY;
4556 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4558 if (boardtype.reg_type & ni_reg_m_series_mask) {
4559 s->n_chan = M_SERIES_EEPROM_SIZE;
4560 s->insn_read = &ni_m_series_eeprom_insn_read;
4563 s->insn_read = &ni_eeprom_insn_read;
4567 s = dev->subdevices + NI_PFI_DIO_SUBDEV;
4568 s->type = COMEDI_SUBD_DIO;
4569 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4570 if (boardtype.reg_type & ni_reg_m_series_mask) {
4573 ni_writew(s->state, M_Offset_PFI_DO);
4574 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4575 ni_writew(devpriv->pfi_output_select_reg[i],
4576 M_Offset_PFI_Output_Select(i + 1));
4582 if (boardtype.reg_type & ni_reg_m_series_mask) {
4583 s->insn_bits = &ni_pfi_insn_bits;
4585 s->insn_config = &ni_pfi_insn_config;
4586 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4588 /* cs5529 calibration adc */
4589 s = dev->subdevices + NI_CS5529_CALIBRATION_SUBDEV;
4590 if (boardtype.reg_type & ni_reg_67xx_mask) {
4591 s->type = COMEDI_SUBD_AI;
4592 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4593 /* one channel for each analog output channel */
4594 s->n_chan = boardtype.n_aochan;
4595 s->maxdata = (1 << 16) - 1;
4596 s->range_table = &range_unknown; /* XXX */
4597 s->insn_read = cs5529_ai_insn_read;
4598 s->insn_config = NULL;
4601 s->type = COMEDI_SUBD_UNUSED;
4605 s = dev->subdevices + NI_SERIAL_SUBDEV;
4606 s->type = COMEDI_SUBD_SERIAL;
4607 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4610 s->insn_config = ni_serial_insn_config;
4611 devpriv->serial_interval_ns = 0;
4612 devpriv->serial_hw_mode = 0;
4615 s = dev->subdevices + NI_RTSI_SUBDEV;
4616 s->type = COMEDI_SUBD_DIO;
4617 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4620 s->insn_bits = ni_rtsi_insn_bits;
4621 s->insn_config = ni_rtsi_insn_config;
4624 if (boardtype.reg_type & ni_reg_m_series_mask) {
4625 counter_variant = ni_gpct_variant_m_series;
4627 counter_variant = ni_gpct_variant_e_series;
4629 devpriv->counter_dev = ni_gpct_device_construct(dev,
4630 &ni_gpct_write_register,
4631 &ni_gpct_read_register,
4634 /* General purpose counters */
4635 for (j = 0; j < NUM_GPCT; ++j) {
4636 s = dev->subdevices + NI_GPCT_SUBDEV(j);
4637 s->type = COMEDI_SUBD_COUNTER;
4639 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4640 /* | SDF_CMD_WRITE */ ;
4642 if (boardtype.reg_type & ni_reg_m_series_mask)
4643 s->maxdata = 0xffffffff;
4645 s->maxdata = 0xffffff;
4646 s->insn_read = &ni_gpct_insn_read;
4647 s->insn_write = &ni_gpct_insn_write;
4648 s->insn_config = &ni_gpct_insn_config;
4649 s->do_cmd = &ni_gpct_cmd;
4650 s->len_chanlist = 1;
4651 s->do_cmdtest = &ni_gpct_cmdtest;
4652 s->cancel = &ni_gpct_cancel;
4653 s->async_dma_dir = DMA_BIDIRECTIONAL;
4654 s->private = &devpriv->counter_dev->counters[j];
4656 devpriv->counter_dev->counters[j].chip_index = 0;
4657 devpriv->counter_dev->counters[j].counter_index = j;
4658 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4661 /* Frequency output */
4662 s = dev->subdevices + NI_FREQ_OUT_SUBDEV;
4663 s->type = COMEDI_SUBD_COUNTER;
4664 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4667 s->insn_read = &ni_freq_out_insn_read;
4668 s->insn_write = &ni_freq_out_insn_write;
4669 s->insn_config = &ni_freq_out_insn_config;
4671 /* ai configuration */
4672 ni_ai_reset(dev, dev->subdevices + NI_AI_SUBDEV);
4673 if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4674 /* BEAM is this needed for PCI-6143 ?? */
4675 devpriv->clock_and_fout =
4676 Slow_Internal_Time_Divide_By_2 |
4677 Slow_Internal_Timebase |
4678 Clock_To_Board_Divide_By_2 |
4680 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4682 devpriv->clock_and_fout =
4683 Slow_Internal_Time_Divide_By_2 |
4684 Slow_Internal_Timebase |
4685 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4687 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4688 Clock_and_FOUT_Register);
4690 /* analog output configuration */
4691 ni_ao_reset(dev, dev->subdevices + NI_AO_SUBDEV);
4694 devpriv->stc_writew(dev,
4695 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4696 0) | (Interrupt_Output_On_3_Pins & 0) |
4697 Interrupt_A_Enable | Interrupt_B_Enable |
4698 Interrupt_A_Output_Select(interrupt_pin
4700 Interrupt_B_Output_Select(interrupt_pin
4702 Interrupt_Control_Register);
4706 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4707 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4709 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4710 ni_writeb(0, Magic_611x);
4711 } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4713 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4714 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4716 M_Offset_AO_Reference_Attenuation(channel));
4718 ni_writeb(0x0, M_Offset_AO_Calibration);
4725 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4727 struct comedi_device *dev = (struct comedi_device *)arg;
4730 ni_writeb(data, Port_A + 2 * port);
4733 return ni_readb(Port_A + 2 * port);
4738 presents the EEPROM as a subdevice
4741 static int ni_eeprom_insn_read(struct comedi_device *dev,
4742 struct comedi_subdevice *s,
4743 struct comedi_insn *insn, unsigned int *data)
4745 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4751 reads bytes out of eeprom
4754 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4759 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4760 ni_writeb(0x04, Serial_Command);
4761 for (bit = 0x8000; bit; bit >>= 1) {
4762 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4764 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4768 for (bit = 0x80; bit; bit >>= 1) {
4769 ni_writeb(0x04, Serial_Command);
4770 ni_writeb(0x05, Serial_Command);
4771 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4773 ni_writeb(0x00, Serial_Command);
4778 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4779 struct comedi_subdevice *s,
4780 struct comedi_insn *insn,
4783 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4788 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4790 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4791 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4795 static int ni_m_series_pwm_config(struct comedi_device *dev,
4796 struct comedi_subdevice *s,
4797 struct comedi_insn *insn, unsigned int *data)
4799 unsigned up_count, down_count;
4801 case INSN_CONFIG_PWM_OUTPUT:
4803 case TRIG_ROUND_NEAREST:
4806 devpriv->clock_ns / 2) / devpriv->clock_ns;
4808 case TRIG_ROUND_DOWN:
4809 up_count = data[2] / devpriv->clock_ns;
4813 (data[2] + devpriv->clock_ns -
4814 1) / devpriv->clock_ns;
4821 case TRIG_ROUND_NEAREST:
4824 devpriv->clock_ns / 2) / devpriv->clock_ns;
4826 case TRIG_ROUND_DOWN:
4827 down_count = data[4] / devpriv->clock_ns;
4831 (data[4] + devpriv->clock_ns -
4832 1) / devpriv->clock_ns;
4838 if (up_count * devpriv->clock_ns != data[2] ||
4839 down_count * devpriv->clock_ns != data[4]) {
4840 data[2] = up_count * devpriv->clock_ns;
4841 data[4] = down_count * devpriv->clock_ns;
4844 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4845 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4847 devpriv->pwm_up_count = up_count;
4848 devpriv->pwm_down_count = down_count;
4851 case INSN_CONFIG_GET_PWM_OUTPUT:
4852 return ni_get_pwm_config(dev, data);
4861 static int ni_6143_pwm_config(struct comedi_device *dev,
4862 struct comedi_subdevice *s,
4863 struct comedi_insn *insn, unsigned int *data)
4865 unsigned up_count, down_count;
4867 case INSN_CONFIG_PWM_OUTPUT:
4869 case TRIG_ROUND_NEAREST:
4872 devpriv->clock_ns / 2) / devpriv->clock_ns;
4874 case TRIG_ROUND_DOWN:
4875 up_count = data[2] / devpriv->clock_ns;
4879 (data[2] + devpriv->clock_ns -
4880 1) / devpriv->clock_ns;
4887 case TRIG_ROUND_NEAREST:
4890 devpriv->clock_ns / 2) / devpriv->clock_ns;
4892 case TRIG_ROUND_DOWN:
4893 down_count = data[4] / devpriv->clock_ns;
4897 (data[4] + devpriv->clock_ns -
4898 1) / devpriv->clock_ns;
4904 if (up_count * devpriv->clock_ns != data[2] ||
4905 down_count * devpriv->clock_ns != data[4]) {
4906 data[2] = up_count * devpriv->clock_ns;
4907 data[4] = down_count * devpriv->clock_ns;
4910 ni_writel(up_count, Calibration_HighTime_6143);
4911 devpriv->pwm_up_count = up_count;
4912 ni_writel(down_count, Calibration_LowTime_6143);
4913 devpriv->pwm_down_count = down_count;
4916 case INSN_CONFIG_GET_PWM_OUTPUT:
4917 return ni_get_pwm_config(dev, data);
4925 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4927 calibration subdevice
4929 static int ni_calib_insn_write(struct comedi_device *dev,
4930 struct comedi_subdevice *s,
4931 struct comedi_insn *insn, unsigned int *data)
4933 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4938 static int ni_calib_insn_read(struct comedi_device *dev,
4939 struct comedi_subdevice *s,
4940 struct comedi_insn *insn, unsigned int *data)
4942 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4947 static int pack_mb88341(int addr, int val, int *bitstring);
4948 static int pack_dac8800(int addr, int val, int *bitstring);
4949 static int pack_dac8043(int addr, int val, int *bitstring);
4950 static int pack_ad8522(int addr, int val, int *bitstring);
4951 static int pack_ad8804(int addr, int val, int *bitstring);
4952 static int pack_ad8842(int addr, int val, int *bitstring);
4954 struct caldac_struct {
4957 int (*packbits) (int, int, int *);
4960 static struct caldac_struct caldacs[] = {
4961 [mb88341] = {12, 8, pack_mb88341},
4962 [dac8800] = {8, 8, pack_dac8800},
4963 [dac8043] = {1, 12, pack_dac8043},
4964 [ad8522] = {2, 12, pack_ad8522},
4965 [ad8804] = {12, 8, pack_ad8804},
4966 [ad8842] = {8, 8, pack_ad8842},
4967 [ad8804_debug] = {16, 8, pack_ad8804},
4970 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4980 type = boardtype.caldac[0];
4981 if (type == caldac_none)
4983 n_bits = caldacs[type].n_bits;
4984 for (i = 0; i < 3; i++) {
4985 type = boardtype.caldac[i];
4986 if (type == caldac_none)
4988 if (caldacs[type].n_bits != n_bits)
4990 n_chans += caldacs[type].n_chans;
4993 s->n_chan = n_chans;
4996 unsigned int *maxdata_list;
4998 if (n_chans > MAX_N_CALDACS) {
4999 printk("BUG! MAX_N_CALDACS too small\n");
5001 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5003 for (i = 0; i < n_dacs; i++) {
5004 type = boardtype.caldac[i];
5005 for (j = 0; j < caldacs[type].n_chans; j++) {
5006 maxdata_list[chan] =
5007 (1 << caldacs[type].n_bits) - 1;
5012 for (chan = 0; chan < s->n_chan; chan++)
5013 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5015 type = boardtype.caldac[0];
5016 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5018 for (chan = 0; chan < s->n_chan; chan++)
5019 ni_write_caldac(dev, i, s->maxdata / 2);
5023 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5025 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5029 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5030 if (devpriv->caldacs[addr] == val)
5032 devpriv->caldacs[addr] = val;
5034 for (i = 0; i < 3; i++) {
5035 type = boardtype.caldac[i];
5036 if (type == caldac_none)
5038 if (addr < caldacs[type].n_chans) {
5039 bits = caldacs[type].packbits(addr, val, &bitstring);
5040 loadbit = SerDacLd(i);
5041 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5044 addr -= caldacs[type].n_chans;
5047 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5048 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5050 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5053 ni_writeb(loadbit, Serial_Command);
5055 ni_writeb(0, Serial_Command);
5058 static int pack_mb88341(int addr, int val, int *bitstring)
5062 Note that address bits are reversed. Thanks to
5063 Ingo Keen for noticing this.
5065 Note also that the 88341 expects address values from
5066 1-12, whereas we use channel numbers 0-11. The NI
5067 docs use 1-12, also, so be careful here.
5070 *bitstring = ((addr & 0x1) << 11) |
5071 ((addr & 0x2) << 9) |
5072 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5076 static int pack_dac8800(int addr, int val, int *bitstring)
5078 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5082 static int pack_dac8043(int addr, int val, int *bitstring)
5084 *bitstring = val & 0xfff;
5088 static int pack_ad8522(int addr, int val, int *bitstring)
5090 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5094 static int pack_ad8804(int addr, int val, int *bitstring)
5096 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5100 static int pack_ad8842(int addr, int val, int *bitstring)
5102 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5108 * Read the GPCTs current value.
5110 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5112 unsigned int hi1, hi2, lo;
5114 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5115 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5116 G_Command_Register(chan));
5118 devpriv->gpct_command[chan] |= G_Save_Trace;
5119 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5120 G_Command_Register(chan));
5122 /* This procedure is used because the two registers cannot
5123 * be read atomically. */
5125 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5126 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5127 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5128 } while (hi1 != hi2);
5130 return (hi1 << 16) | lo;
5133 static void GPCT_Reset(struct comedi_device *dev, int chan)
5135 int temp_ack_reg = 0;
5137 /* printk("GPCT_Reset..."); */
5138 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5142 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5143 ni_set_bits(dev, Interrupt_A_Enable_Register,
5144 G0_TC_Interrupt_Enable, 0);
5145 ni_set_bits(dev, Interrupt_A_Enable_Register,
5146 G0_Gate_Interrupt_Enable, 0);
5147 temp_ack_reg |= G0_Gate_Error_Confirm;
5148 temp_ack_reg |= G0_TC_Error_Confirm;
5149 temp_ack_reg |= G0_TC_Interrupt_Ack;
5150 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5151 devpriv->stc_writew(dev, temp_ack_reg,
5152 Interrupt_A_Ack_Register);
5154 /* problem...this interferes with the other ctr... */
5155 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5156 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5157 Analog_Trigger_Etc_Register);
5160 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5161 ni_set_bits(dev, Interrupt_B_Enable_Register,
5162 G1_TC_Interrupt_Enable, 0);
5163 ni_set_bits(dev, Interrupt_B_Enable_Register,
5164 G0_Gate_Interrupt_Enable, 0);
5165 temp_ack_reg |= G1_Gate_Error_Confirm;
5166 temp_ack_reg |= G1_TC_Error_Confirm;
5167 temp_ack_reg |= G1_TC_Interrupt_Ack;
5168 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5169 devpriv->stc_writew(dev, temp_ack_reg,
5170 Interrupt_B_Ack_Register);
5172 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5173 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5174 Analog_Trigger_Etc_Register);
5178 devpriv->gpct_mode[chan] = 0;
5179 devpriv->gpct_input_select[chan] = 0;
5180 devpriv->gpct_command[chan] = 0;
5182 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5184 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5185 G_Mode_Register(chan));
5186 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5187 G_Input_Select_Register(chan));
5188 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5190 /* printk("exit GPCT_Reset\n"); */
5195 static int ni_gpct_insn_config(struct comedi_device *dev,
5196 struct comedi_subdevice *s,
5197 struct comedi_insn *insn, unsigned int *data)
5199 struct ni_gpct *counter = s->private;
5200 return ni_tio_insn_config(counter, insn, data);
5203 static int ni_gpct_insn_read(struct comedi_device *dev,
5204 struct comedi_subdevice *s,
5205 struct comedi_insn *insn, unsigned int *data)
5207 struct ni_gpct *counter = s->private;
5208 return ni_tio_rinsn(counter, insn, data);
5211 static int ni_gpct_insn_write(struct comedi_device *dev,
5212 struct comedi_subdevice *s,
5213 struct comedi_insn *insn, unsigned int *data)
5215 struct ni_gpct *counter = s->private;
5216 return ni_tio_winsn(counter, insn, data);
5219 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5223 struct ni_gpct *counter = s->private;
5224 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5226 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5230 "no dma channel available for use by counter");
5233 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5234 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5235 retval = ni_tio_cmd(counter, s->async);
5242 static int ni_gpct_cmdtest(struct comedi_device *dev,
5243 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5246 struct ni_gpct *counter = s->private;
5248 return ni_tio_cmdtest(counter, cmd);
5254 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5257 struct ni_gpct *counter = s->private;
5260 retval = ni_tio_cancel(counter);
5261 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5262 ni_release_gpct_mite_channel(dev, counter->counter_index);
5271 * Programmable Function Inputs
5275 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5278 unsigned pfi_reg_index;
5279 unsigned array_offset;
5280 if ((source & 0x1f) != source)
5282 pfi_reg_index = 1 + chan / 3;
5283 array_offset = pfi_reg_index - 1;
5284 devpriv->pfi_output_select_reg[array_offset] &=
5285 ~MSeries_PFI_Output_Select_Mask(chan);
5286 devpriv->pfi_output_select_reg[array_offset] |=
5287 MSeries_PFI_Output_Select_Bits(chan, source);
5288 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5289 M_Offset_PFI_Output_Select(pfi_reg_index));
5293 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5296 /* pre-m-series boards have fixed signals on pfi pins */
5297 if (source != ni_old_get_pfi_routing(dev, chan))
5302 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5305 if (boardtype.reg_type & ni_reg_m_series_mask)
5306 return ni_m_series_set_pfi_routing(dev, chan, source);
5308 return ni_old_set_pfi_routing(dev, chan, source);
5311 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5314 const unsigned array_offset = chan / 3;
5315 return MSeries_PFI_Output_Select_Source(chan,
5317 pfi_output_select_reg
5321 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5323 /* pre-m-series boards have fixed signals on pfi pins */
5326 return NI_PFI_OUTPUT_AI_START1;
5329 return NI_PFI_OUTPUT_AI_START2;
5332 return NI_PFI_OUTPUT_AI_CONVERT;
5335 return NI_PFI_OUTPUT_G_SRC1;
5338 return NI_PFI_OUTPUT_G_GATE1;
5341 return NI_PFI_OUTPUT_AO_UPDATE_N;
5344 return NI_PFI_OUTPUT_AO_START1;
5347 return NI_PFI_OUTPUT_AI_START_PULSE;
5350 return NI_PFI_OUTPUT_G_SRC0;
5353 return NI_PFI_OUTPUT_G_GATE0;
5356 printk("%s: bug, unhandled case in switch.\n", __func__);
5362 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5364 if (boardtype.reg_type & ni_reg_m_series_mask)
5365 return ni_m_series_get_pfi_routing(dev, chan);
5367 return ni_old_get_pfi_routing(dev, chan);
5370 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5371 enum ni_pfi_filter_select filter)
5374 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5377 bits = ni_readl(M_Offset_PFI_Filter);
5378 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5379 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5380 ni_writel(bits, M_Offset_PFI_Filter);
5384 static int ni_pfi_insn_bits(struct comedi_device *dev,
5385 struct comedi_subdevice *s,
5386 struct comedi_insn *insn, unsigned int *data)
5388 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5392 s->state &= ~data[0];
5393 s->state |= (data[0] & data[1]);
5394 ni_writew(s->state, M_Offset_PFI_DO);
5396 data[1] = ni_readw(M_Offset_PFI_DI);
5400 static int ni_pfi_insn_config(struct comedi_device *dev,
5401 struct comedi_subdevice *s,
5402 struct comedi_insn *insn, unsigned int *data)
5409 chan = CR_CHAN(insn->chanspec);
5413 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5416 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5418 case INSN_CONFIG_DIO_QUERY:
5420 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5421 COMEDI_OUTPUT : COMEDI_INPUT;
5424 case INSN_CONFIG_SET_ROUTING:
5425 return ni_set_pfi_routing(dev, chan, data[1]);
5427 case INSN_CONFIG_GET_ROUTING:
5428 data[1] = ni_get_pfi_routing(dev, chan);
5430 case INSN_CONFIG_FILTER:
5431 return ni_config_filter(dev, chan, data[1]);
5441 * NI RTSI Bus Functions
5444 static void ni_rtsi_init(struct comedi_device *dev)
5446 /* Initialises the RTSI bus signal switch to a default state */
5448 /* Set clock mode to internal */
5449 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5450 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5451 printk("ni_set_master_clock failed, bug?");
5453 /* default internal lines routing to RTSI bus lines */
5454 devpriv->rtsi_trig_a_output_reg =
5455 RTSI_Trig_Output_Bits(0,
5456 NI_RTSI_OUTPUT_ADR_START1) |
5457 RTSI_Trig_Output_Bits(1,
5458 NI_RTSI_OUTPUT_ADR_START2) |
5459 RTSI_Trig_Output_Bits(2,
5460 NI_RTSI_OUTPUT_SCLKG) |
5461 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5462 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5463 RTSI_Trig_A_Output_Register);
5464 devpriv->rtsi_trig_b_output_reg =
5465 RTSI_Trig_Output_Bits(4,
5466 NI_RTSI_OUTPUT_DA_START1) |
5467 RTSI_Trig_Output_Bits(5,
5468 NI_RTSI_OUTPUT_G_SRC0) |
5469 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5470 if (boardtype.reg_type & ni_reg_m_series_mask)
5471 devpriv->rtsi_trig_b_output_reg |=
5472 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5473 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5474 RTSI_Trig_B_Output_Register);
5477 * Sets the source and direction of the 4 on board lines
5478 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5482 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5483 struct comedi_subdevice *s,
5484 struct comedi_insn *insn, unsigned int *data)
5494 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5495 * given an arbitrary frequency input clock */
5496 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5497 unsigned *freq_divider,
5498 unsigned *freq_multiplier,
5499 unsigned *actual_period_ns)
5502 unsigned best_div = 1;
5503 static const unsigned max_div = 0x10;
5505 unsigned best_mult = 1;
5506 static const unsigned max_mult = 0x100;
5507 static const unsigned pico_per_nano = 1000;
5509 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5510 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5511 * 20 MHz for most timing clocks */
5512 static const unsigned target_picosec = 12500;
5513 static const unsigned fudge_factor_80_to_20Mhz = 4;
5514 int best_period_picosec = 0;
5515 for (div = 1; div <= max_div; ++div) {
5516 for (mult = 1; mult <= max_mult; ++mult) {
5517 unsigned new_period_ps =
5518 (reference_picosec * div) / mult;
5519 if (abs(new_period_ps - target_picosec) <
5520 abs(best_period_picosec - target_picosec)) {
5521 best_period_picosec = new_period_ps;
5527 if (best_period_picosec == 0) {
5528 printk("%s: bug, failed to find pll parameters\n", __func__);
5531 *freq_divider = best_div;
5532 *freq_multiplier = best_mult;
5534 (best_period_picosec * fudge_factor_80_to_20Mhz +
5535 (pico_per_nano / 2)) / pico_per_nano;
5539 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5541 if (boardtype.reg_type & ni_reg_m_series_mask)
5547 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5548 unsigned source, unsigned period_ns)
5550 static const unsigned min_period_ns = 50;
5551 static const unsigned max_period_ns = 1000;
5552 static const unsigned timeout = 1000;
5553 unsigned pll_control_bits;
5554 unsigned freq_divider;
5555 unsigned freq_multiplier;
5558 if (source == NI_MIO_PLL_PXI10_CLOCK)
5560 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5561 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5563 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5564 "for the phased-lock loop.\n", __func__,
5565 min_period_ns, max_period_ns);
5568 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5569 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5570 RTSI_Trig_Direction_Register);
5572 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5573 devpriv->clock_and_fout2 |=
5574 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5575 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5577 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5578 devpriv->clock_and_fout2 |=
5579 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5580 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5582 &devpriv->clock_ns);
5586 case NI_MIO_PLL_PXI10_CLOCK:
5587 /* pxi clock is 10MHz */
5588 devpriv->clock_and_fout2 |=
5589 MSeries_PLL_In_Source_Select_PXI_Clock10;
5590 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5592 &devpriv->clock_ns);
5598 unsigned rtsi_channel;
5599 static const unsigned max_rtsi_channel = 7;
5600 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5603 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5604 devpriv->clock_and_fout2 |=
5605 MSeries_PLL_In_Source_Select_RTSI_Bits
5610 if (rtsi_channel > max_rtsi_channel)
5612 retval = ni_mseries_get_pll_parameters(period_ns,
5622 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5624 MSeries_PLL_Divisor_Bits(freq_divider) |
5625 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5627 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5628 * freq_divider, freq_multiplier, pll_control_bits); */
5629 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5630 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5631 devpriv->clock_source = source;
5632 /* it seems to typically take a few hundred microseconds for PLL to lock */
5633 for (i = 0; i < timeout; ++i) {
5634 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5641 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5642 __func__, source, period_ns);
5648 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5651 if (source == NI_MIO_INTERNAL_CLOCK) {
5652 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5653 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5654 RTSI_Trig_Direction_Register);
5655 devpriv->clock_ns = TIMEBASE_1_NS;
5656 if (boardtype.reg_type & ni_reg_m_series_mask) {
5657 devpriv->clock_and_fout2 &=
5658 ~(MSeries_Timebase1_Select_Bit |
5659 MSeries_Timebase3_Select_Bit);
5660 ni_writew(devpriv->clock_and_fout2,
5661 M_Offset_Clock_and_Fout2);
5662 ni_writew(0, M_Offset_PLL_Control);
5664 devpriv->clock_source = source;
5666 if (boardtype.reg_type & ni_reg_m_series_mask) {
5667 return ni_mseries_set_pll_master_clock(dev, source,
5670 if (source == NI_MIO_RTSI_CLOCK) {
5671 devpriv->rtsi_trig_direction_reg |=
5673 devpriv->stc_writew(dev,
5675 rtsi_trig_direction_reg,
5676 RTSI_Trig_Direction_Register);
5677 if (period_ns == 0) {
5679 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5683 devpriv->clock_ns = period_ns;
5685 devpriv->clock_source = source;
5693 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5696 if (chan >= num_configurable_rtsi_channels(dev)) {
5697 if (chan == old_RTSI_clock_channel) {
5698 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5702 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5703 __func__, chan, old_RTSI_clock_channel);
5710 case NI_RTSI_OUTPUT_ADR_START1:
5711 case NI_RTSI_OUTPUT_ADR_START2:
5712 case NI_RTSI_OUTPUT_SCLKG:
5713 case NI_RTSI_OUTPUT_DACUPDN:
5714 case NI_RTSI_OUTPUT_DA_START1:
5715 case NI_RTSI_OUTPUT_G_SRC0:
5716 case NI_RTSI_OUTPUT_G_GATE0:
5717 case NI_RTSI_OUTPUT_RGOUT0:
5718 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5721 case NI_RTSI_OUTPUT_RTSI_OSC:
5722 if (boardtype.reg_type & ni_reg_m_series_mask)
5733 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5736 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5739 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5740 devpriv->rtsi_trig_a_output_reg |=
5741 RTSI_Trig_Output_Bits(chan, source);
5742 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5743 RTSI_Trig_A_Output_Register);
5744 } else if (chan < 8) {
5745 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5746 devpriv->rtsi_trig_b_output_reg |=
5747 RTSI_Trig_Output_Bits(chan, source);
5748 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5749 RTSI_Trig_B_Output_Register);
5754 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5757 return RTSI_Trig_Output_Source(chan,
5758 devpriv->rtsi_trig_a_output_reg);
5759 } else if (chan < num_configurable_rtsi_channels(dev)) {
5760 return RTSI_Trig_Output_Source(chan,
5761 devpriv->rtsi_trig_b_output_reg);
5763 if (chan == old_RTSI_clock_channel)
5764 return NI_RTSI_OUTPUT_RTSI_OSC;
5765 printk("%s: bug! should never get here?\n", __func__);
5770 static int ni_rtsi_insn_config(struct comedi_device *dev,
5771 struct comedi_subdevice *s,
5772 struct comedi_insn *insn, unsigned int *data)
5774 unsigned int chan = CR_CHAN(insn->chanspec);
5776 case INSN_CONFIG_DIO_OUTPUT:
5777 if (chan < num_configurable_rtsi_channels(dev)) {
5778 devpriv->rtsi_trig_direction_reg |=
5779 RTSI_Output_Bit(chan,
5781 reg_type & ni_reg_m_series_mask) !=
5783 } else if (chan == old_RTSI_clock_channel) {
5784 devpriv->rtsi_trig_direction_reg |=
5785 Drive_RTSI_Clock_Bit;
5787 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5788 RTSI_Trig_Direction_Register);
5790 case INSN_CONFIG_DIO_INPUT:
5791 if (chan < num_configurable_rtsi_channels(dev)) {
5792 devpriv->rtsi_trig_direction_reg &=
5793 ~RTSI_Output_Bit(chan,
5795 reg_type & ni_reg_m_series_mask)
5797 } else if (chan == old_RTSI_clock_channel) {
5798 devpriv->rtsi_trig_direction_reg &=
5799 ~Drive_RTSI_Clock_Bit;
5801 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5802 RTSI_Trig_Direction_Register);
5804 case INSN_CONFIG_DIO_QUERY:
5805 if (chan < num_configurable_rtsi_channels(dev)) {
5807 (devpriv->rtsi_trig_direction_reg &
5808 RTSI_Output_Bit(chan,
5809 (boardtype.reg_type &
5810 ni_reg_m_series_mask)
5811 != 0)) ? INSN_CONFIG_DIO_OUTPUT :
5812 INSN_CONFIG_DIO_INPUT;
5813 } else if (chan == old_RTSI_clock_channel) {
5815 (devpriv->rtsi_trig_direction_reg &
5816 Drive_RTSI_Clock_Bit)
5817 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5821 case INSN_CONFIG_SET_CLOCK_SRC:
5822 return ni_set_master_clock(dev, data[1], data[2]);
5824 case INSN_CONFIG_GET_CLOCK_SRC:
5825 data[1] = devpriv->clock_source;
5826 data[2] = devpriv->clock_ns;
5829 case INSN_CONFIG_SET_ROUTING:
5830 return ni_set_rtsi_routing(dev, chan, data[1]);
5832 case INSN_CONFIG_GET_ROUTING:
5833 data[1] = ni_get_rtsi_routing(dev, chan);
5843 static int cs5529_wait_for_idle(struct comedi_device *dev)
5845 unsigned short status;
5846 const int timeout = HZ;
5849 for (i = 0; i < timeout; i++) {
5850 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5851 if ((status & CSS_ADC_BUSY) == 0) {
5854 set_current_state(TASK_INTERRUPTIBLE);
5855 if (schedule_timeout(1)) {
5859 /* printk("looped %i times waiting for idle\n", i); */
5861 printk("%s: %s: timeout\n", __FILE__, __func__);
5867 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5869 static const int timeout = 100;
5872 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5873 /* give time for command to start being serially clocked into cs5529.
5874 * this insures that the CSS_ADC_BUSY bit will get properly
5875 * set before we exit this function.
5877 for (i = 0; i < timeout; i++) {
5878 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5882 /* printk("looped %i times writing command to cs5529\n", i); */
5884 comedi_error(dev, "possible problem - never saw adc go busy?");
5888 /* write to cs5529 register */
5889 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5890 unsigned int reg_select_bits)
5892 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5893 CAL_ADC_Config_Data_High_Word_67xx);
5894 ni_ao_win_outw(dev, (value & 0xffff),
5895 CAL_ADC_Config_Data_Low_Word_67xx);
5896 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5897 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5898 if (cs5529_wait_for_idle(dev))
5899 comedi_error(dev, "time or signal in cs5529_config_write()");
5902 #ifdef NI_CS5529_DEBUG
5903 /* read from cs5529 register */
5904 static unsigned int cs5529_config_read(struct comedi_device *dev,
5905 unsigned int reg_select_bits)
5909 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5910 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5911 if (cs5529_wait_for_idle(dev))
5912 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5913 value = (ni_ao_win_inw(dev,
5914 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5916 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5921 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5924 unsigned short status;
5926 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5927 retval = cs5529_wait_for_idle(dev);
5930 "timeout or signal in cs5529_do_conversion()");
5933 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5934 if (status & CSS_OSC_DETECT) {
5936 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5939 if (status & CSS_OVERRANGE) {
5941 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5944 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5945 /* cs5529 returns 16 bit signed data in bipolar mode */
5951 static int cs5529_ai_insn_read(struct comedi_device *dev,
5952 struct comedi_subdevice *s,
5953 struct comedi_insn *insn, unsigned int *data)
5956 unsigned short sample;
5957 unsigned int channel_select;
5958 const unsigned int INTERNAL_REF = 0x1000;
5960 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5961 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5962 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5963 if (insn->chanspec & CR_ALT_SOURCE)
5964 channel_select = INTERNAL_REF;
5966 channel_select = CR_CHAN(insn->chanspec);
5967 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5969 for (n = 0; n < insn->n; n++) {
5970 retval = cs5529_do_conversion(dev, &sample);
5978 static int init_cs5529(struct comedi_device *dev)
5980 unsigned int config_bits =
5981 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5984 /* do self-calibration */
5985 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5986 CSCMD_CONFIG_REGISTER);
5987 /* need to force a conversion for calibration to run */
5988 cs5529_do_conversion(dev, NULL);
5990 /* force gain calibration to 1 */
5991 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5992 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5993 CSCMD_CONFIG_REGISTER);
5994 if (cs5529_wait_for_idle(dev))
5995 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5997 #ifdef NI_CS5529_DEBUG
5998 printk("config: 0x%x\n", cs5529_config_read(dev,
5999 CSCMD_CONFIG_REGISTER));
6000 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6001 printk("offset: 0x%x\n", cs5529_config_read(dev,
6002 CSCMD_OFFSET_REGISTER));