2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 ************************************************************************
24 Description: National Instruments Lab-PC (& compatibles)
25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
30 Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31 and analog references will work, the available ranges/arefs will
32 depend on how you have configured the jumpers on your board
33 (see your owner's manual).
35 Kernel-level ISA plug-and-play support for the lab-pc-1200
37 yet been added to the driver, mainly due to the fact that
38 I don't know the device id numbers. If you have one
40 please file a bug report at https://bugs.comedi.org/
41 so I can get the necessary information from you.
43 The 1200 series boards have onboard calibration dacs for correcting
44 analog input/output offsets and gains. The proper settings for these
45 caldacs are stored on the board's eeprom. To read the caldac values
46 from the eeprom and store them into a file that can be then be used by
47 comedilib, use the comedi_calibrate program.
49 Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
54 Configuration options - PCI boards:
58 The Lab-pc+ has quirky chanlist requirements
59 when scanning multiple channels. Multiple channel scan
60 sequence must start at highest channel, then decrement down to
61 channel 0. The rest of the cards can scan down like lab-pc+ or scan
62 up from channel zero. Chanlists consisting of all one channel
63 are also legal, and allow you to pace conversions in bursts.
70 341309a (labpc-1200 register manual)
77 //#define LABPC_DEBUG // enable debugging messages
79 #include "../comedidev.h"
81 #include <linux/delay.h>
87 #include "comedi_fc.h"
90 #define DRV_NAME "ni_labpc"
92 #define LABPC_SIZE 32 // size of io region used by board
93 #define LABPC_TIMER_BASE 500 // 2 MHz master clock
95 /* Registers for the lab-pc+ */
97 //write-only registers
98 #define COMMAND1_REG 0x0
99 #define ADC_GAIN_MASK (0x7 << 4)
100 #define ADC_CHAN_BITS(x) ((x) & 0x7)
101 #define ADC_SCAN_EN_BIT 0x80 // enables multi channel scans
102 #define COMMAND2_REG 0x1
103 #define PRETRIG_BIT 0x1 // enable pretriggering (used in conjunction with SWTRIG)
104 #define HWTRIG_BIT 0x2 // enable paced conversions on external trigger
105 #define SWTRIG_BIT 0x4 // enable paced conversions
106 #define CASCADE_BIT 0x8 // use two cascaded counters for pacing
107 #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
108 #define COMMAND3_REG 0x2
109 #define DMA_EN_BIT 0x1 // enable dma transfers
110 #define DIO_INTR_EN_BIT 0x2 // enable interrupts for 8255
111 #define DMATC_INTR_EN_BIT 0x4 // enable dma terminal count interrupt
112 #define TIMER_INTR_EN_BIT 0x8 // enable timer interrupt
113 #define ERR_INTR_EN_BIT 0x10 // enable error interrupt
114 #define ADC_FNE_INTR_EN_BIT 0x20 // enable fifo not empty interrupt
115 #define ADC_CONVERT_REG 0x3
116 #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
117 #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
118 #define ADC_CLEAR_REG 0x8
119 #define DMATC_CLEAR_REG 0xa
120 #define TIMER_CLEAR_REG 0xc
121 #define COMMAND6_REG 0xe // 1200 boards only
122 #define ADC_COMMON_BIT 0x1 // select ground or common-mode reference
123 #define ADC_UNIP_BIT 0x2 // adc unipolar
124 #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) // dac unipolar
125 #define ADC_FHF_INTR_EN_BIT 0x20 // enable fifo half full interrupt
126 #define A1_INTR_EN_BIT 0x40 // enable interrupt on end of hardware count
127 #define ADC_SCAN_UP_BIT 0x80 // scan up from channel zero instead of down to zero
128 #define COMMAND4_REG 0xf
129 #define INTERVAL_SCAN_EN_BIT 0x1 // enables 'interval' scanning
130 #define EXT_SCAN_EN_BIT 0x2 // enables external signal on counter b1 output to trigger scan
131 #define EXT_CONVERT_OUT_BIT 0x4 // chooses direction (output or input) for EXTCONV* line
132 #define ADC_DIFF_BIT 0x8 // chooses differential inputs for adc (in conjunction with board jumper)
133 #define EXT_CONVERT_DISABLE_BIT 0x10
134 #define COMMAND5_REG 0x1c // 1200 boards only, calibration stuff
135 #define EEPROM_WRITE_UNPROTECT_BIT 0x4 // enable eeprom for write
136 #define DITHER_EN_BIT 0x8 // enable dithering
137 #define CALDAC_LOAD_BIT 0x10 // load calibration dac
138 #define SCLOCK_BIT 0x20 // serial clock - rising edge writes, falling edge reads
139 #define SDATA_BIT 0x40 // serial data bit for writing to eeprom or calibration dacs
140 #define EEPROM_EN_BIT 0x80 // enable eeprom for read/write
141 #define INTERVAL_COUNT_REG 0x1e
142 #define INTERVAL_LOAD_REG 0x1f
143 #define INTERVAL_LOAD_BITS 0x1
145 // read-only registers
146 #define STATUS1_REG 0x0
147 #define DATA_AVAIL_BIT 0x1 // data is available in fifo
148 #define OVERRUN_BIT 0x2 // overrun has occurred
149 #define OVERFLOW_BIT 0x4 // fifo overflow
150 #define TIMER_BIT 0x8 // timer interrupt has occured
151 #define DMATC_BIT 0x10 // dma terminal count has occured
152 #define EXT_TRIG_BIT 0x40 // external trigger has occured
153 #define STATUS2_REG 0x1d // 1200 boards only
154 #define EEPROM_OUT_BIT 0x1 // programmable eeprom serial output
155 #define A1_TC_BIT 0x2 // counter A1 terminal count
156 #define FNHF_BIT 0x4 // fifo not half full
157 #define ADC_FIFO_REG 0xa
159 #define DIO_BASE_REG 0x10
160 #define COUNTER_A_BASE_REG 0x14
161 #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
162 #define INIT_A0_BITS 0x14 // check modes put conversion pacer output in harmless state (a0 mode 2)
163 #define INIT_A1_BITS 0x70 // put hardware conversion counter output in harmless state (a1 mode 0)
164 #define COUNTER_B_BASE_REG 0x18
166 static int labpc_attach(comedi_device * dev, comedi_devconfig * it);
167 static int labpc_cancel(comedi_device * dev, comedi_subdevice * s);
168 static irqreturn_t labpc_interrupt(int irq, void *d PT_REGS_ARG);
169 static int labpc_drain_fifo(comedi_device * dev);
170 static void labpc_drain_dma(comedi_device * dev);
171 static void handle_isa_dma(comedi_device * dev);
172 static void labpc_drain_dregs(comedi_device * dev);
173 static int labpc_ai_cmdtest(comedi_device * dev, comedi_subdevice * s,
175 static int labpc_ai_cmd(comedi_device * dev, comedi_subdevice * s);
176 static int labpc_ai_rinsn(comedi_device * dev, comedi_subdevice * s,
177 comedi_insn * insn, unsigned int * data);
178 static int labpc_ao_winsn(comedi_device * dev, comedi_subdevice * s,
179 comedi_insn * insn, unsigned int * data);
180 static int labpc_ao_rinsn(comedi_device * dev, comedi_subdevice * s,
181 comedi_insn * insn, unsigned int * data);
182 static int labpc_calib_read_insn(comedi_device * dev, comedi_subdevice * s,
183 comedi_insn * insn, unsigned int * data);
184 static int labpc_calib_write_insn(comedi_device * dev, comedi_subdevice * s,
185 comedi_insn * insn, unsigned int * data);
186 static int labpc_eeprom_read_insn(comedi_device * dev, comedi_subdevice * s,
187 comedi_insn * insn, unsigned int * data);
188 static int labpc_eeprom_write_insn(comedi_device * dev, comedi_subdevice * s,
189 comedi_insn * insn, unsigned int * data);
190 static unsigned int labpc_suggest_transfer_size(comedi_cmd cmd);
191 static void labpc_adc_timing(comedi_device * dev, comedi_cmd * cmd);
192 #ifdef CONFIG_COMEDI_PCI
193 static int labpc_find_device(comedi_device *dev, int bus, int slot);
195 static int labpc_dio_mem_callback(int dir, int port, int data,
197 static void labpc_serial_out(comedi_device * dev, unsigned int value,
198 unsigned int num_bits);
199 static unsigned int labpc_serial_in(comedi_device * dev);
200 static unsigned int labpc_eeprom_read(comedi_device * dev,
201 unsigned int address);
202 static unsigned int labpc_eeprom_read_status(comedi_device * dev);
203 static unsigned int labpc_eeprom_write(comedi_device * dev,
204 unsigned int address, unsigned int value);
205 static void write_caldac(comedi_device * dev, unsigned int channel,
210 MODE_SINGLE_CHAN_INTERVAL,
215 //analog input ranges
216 #define NUM_LABPC_PLUS_AI_RANGES 16
217 // indicates unipolar ranges
218 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
237 // map range index to gain bits
238 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
256 static const comedi_lrange range_labpc_plus_ai = {
257 NUM_LABPC_PLUS_AI_RANGES,
278 #define NUM_LABPC_1200_AI_RANGES 14
279 // indicates unipolar ranges
280 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
297 // map range index to gain bits
298 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
314 const comedi_lrange range_labpc_1200_ai = {
315 NUM_LABPC_1200_AI_RANGES,
334 //analog output ranges
335 #define AO_RANGE_IS_UNIPOLAR 0x1
336 static const comedi_lrange range_labpc_ao = {
344 /* functions that do inb/outb and readb/writeb so we can use
345 * function pointers to decide which to use */
346 static inline unsigned int labpc_inb(unsigned long address)
350 static inline void labpc_outb(unsigned int byte, unsigned long address)
354 static inline unsigned int labpc_readb(unsigned long address)
356 return readb((void *)address);
358 static inline void labpc_writeb(unsigned int byte, unsigned long address)
360 writeb(byte, (void *)address);
363 static const labpc_board labpc_boards[] = {
367 bustype: isa_bustype,
368 register_layout:labpc_1200_layout,
370 ai_range_table:&range_labpc_1200_ai,
371 ai_range_code:labpc_1200_ai_gain_bits,
372 ai_range_is_unipolar:labpc_1200_is_unipolar,
377 name: "lab-pc-1200ai",
379 bustype: isa_bustype,
380 register_layout:labpc_1200_layout,
382 ai_range_table:&range_labpc_1200_ai,
383 ai_range_code:labpc_1200_ai_gain_bits,
384 ai_range_is_unipolar:labpc_1200_is_unipolar,
391 bustype: isa_bustype,
392 register_layout:labpc_plus_layout,
394 ai_range_table:&range_labpc_plus_ai,
395 ai_range_code:labpc_plus_ai_gain_bits,
396 ai_range_is_unipolar:labpc_plus_is_unipolar,
400 #ifdef CONFIG_COMEDI_PCI
405 bustype: pci_bustype,
406 register_layout:labpc_1200_layout,
408 ai_range_table:&range_labpc_1200_ai,
409 ai_range_code:labpc_1200_ai_gain_bits,
410 ai_range_is_unipolar:labpc_1200_is_unipolar,
414 // dummy entry so pci board works when comedi_config is passed driver name
417 .bustype = pci_bustype,
423 * Useful for shorthand access to the particular board structure
425 #define thisboard ((labpc_board *)dev->board_ptr)
427 static const int dma_buffer_size = 0xff00; // size in bytes of dma buffer
428 static const int sample_size = 2; // 2 bytes per sample
430 #define devpriv ((labpc_private *)dev->private)
432 static comedi_driver driver_labpc = {
433 .driver_name = DRV_NAME,
434 .module = THIS_MODULE,
435 .attach = labpc_attach,
436 .detach = labpc_common_detach,
437 .num_names = sizeof(labpc_boards) / sizeof(labpc_board),
438 .board_name = &labpc_boards[0].name,
439 .offset = sizeof(labpc_board),
442 #ifdef CONFIG_COMEDI_PCI
443 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
444 {PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
448 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
449 #endif /* CONFIG_COMEDI_PCI */
451 static inline int labpc_counter_load(comedi_device * dev,
452 unsigned long base_address, unsigned int counter_number,
453 unsigned int count, unsigned int mode)
455 if (thisboard->memory_mapped_io)
456 return i8254_mm_load((void *)base_address, 0, counter_number,
459 return i8254_load(base_address, 0, counter_number, count, mode);
462 int labpc_common_attach(comedi_device * dev, unsigned long iobase,
463 unsigned int irq, unsigned int dma_chan)
467 unsigned long dma_flags, isr_flags;
470 printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name,
473 printk(", irq %u", irq);
476 printk(", dma %u", dma_chan);
481 printk("io base address is zero!\n");
484 // request io regions for isa boards
485 if (thisboard->bustype == isa_bustype) {
486 /* check if io addresses are available */
487 if (!request_region(iobase, LABPC_SIZE,
488 driver_labpc.driver_name)) {
489 printk("I/O port conflict\n");
493 dev->iobase = iobase;
495 if (thisboard->memory_mapped_io) {
496 devpriv->read_byte = labpc_readb;
497 devpriv->write_byte = labpc_writeb;
499 devpriv->read_byte = labpc_inb;
500 devpriv->write_byte = labpc_outb;
502 // initialize board's command registers
503 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
504 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
505 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
506 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
507 if (thisboard->register_layout == labpc_1200_layout) {
508 devpriv->write_byte(devpriv->command5_bits,
509 dev->iobase + COMMAND5_REG);
510 devpriv->write_byte(devpriv->command6_bits,
511 dev->iobase + COMMAND6_REG);
517 if (thisboard->bustype == pci_bustype)
518 isr_flags |= IRQF_SHARED;
519 if (comedi_request_irq(irq, labpc_interrupt, isr_flags,
520 driver_labpc.driver_name, dev)) {
521 printk("unable to allocate irq %u\n", irq);
529 printk(" invalid dma channel %u\n", dma_chan);
531 } else if (dma_chan) {
532 // allocate dma buffer
533 devpriv->dma_buffer =
534 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
535 if (devpriv->dma_buffer == NULL) {
536 printk(" failed to allocate dma buffer\n");
539 if (request_dma(dma_chan, driver_labpc.driver_name)) {
540 printk(" failed to allocate dma channel %u\n",
544 devpriv->dma_chan = dma_chan;
545 dma_flags = claim_dma_lock();
546 disable_dma(devpriv->dma_chan);
547 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
548 release_dma_lock(dma_flags);
551 dev->board_name = thisboard->name;
553 if (alloc_subdevices(dev, 5) < 0)
556 /* analog input subdevice */
557 s = dev->subdevices + 0;
558 dev->read_subdev = s;
559 s->type = COMEDI_SUBD_AI;
561 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF |
565 s->maxdata = (1 << 12) - 1; // 12 bit resolution
566 s->range_table = thisboard->ai_range_table;
567 s->do_cmd = labpc_ai_cmd;
568 s->do_cmdtest = labpc_ai_cmdtest;
569 s->insn_read = labpc_ai_rinsn;
570 s->cancel = labpc_cancel;
573 s = dev->subdevices + 1;
574 if (thisboard->has_ao) {
575 /* Could provide command support, except it only has a one sample
576 * hardware buffer for analog output and no underrun flag. */
577 s->type = COMEDI_SUBD_AO;
578 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
579 s->n_chan = NUM_AO_CHAN;
580 s->maxdata = (1 << 12) - 1; // 12 bit resolution
581 s->range_table = &range_labpc_ao;
582 s->insn_read = labpc_ao_rinsn;
583 s->insn_write = labpc_ao_winsn;
584 /* initialize analog outputs to a known value */
585 for (i = 0; i < s->n_chan; i++) {
586 devpriv->ao_value[i] = s->maxdata / 2;
587 lsb = devpriv->ao_value[i] & 0xff;
588 msb = (devpriv->ao_value[i] >> 8) & 0xff;
589 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
590 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
593 s->type = COMEDI_SUBD_UNUSED;
597 s = dev->subdevices + 2;
598 // if board uses io memory we have to give a custom callback function to the 8255 driver
599 if (thisboard->memory_mapped_io)
600 subdev_8255_init(dev, s, labpc_dio_mem_callback,
601 (unsigned long)(dev->iobase + DIO_BASE_REG));
603 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
605 // calibration subdevices for boards that have one
606 s = dev->subdevices + 3;
607 if (thisboard->register_layout == labpc_1200_layout) {
608 s->type = COMEDI_SUBD_CALIB;
609 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
612 s->insn_read = labpc_calib_read_insn;
613 s->insn_write = labpc_calib_write_insn;
615 for (i = 0; i < s->n_chan; i++)
616 write_caldac(dev, i, s->maxdata / 2);
618 s->type = COMEDI_SUBD_UNUSED;
621 s = dev->subdevices + 4;
622 if (thisboard->register_layout == labpc_1200_layout) {
623 s->type = COMEDI_SUBD_MEMORY;
624 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
625 s->n_chan = EEPROM_SIZE;
627 s->insn_read = labpc_eeprom_read_insn;
628 s->insn_write = labpc_eeprom_write_insn;
630 for (i = 0; i < EEPROM_SIZE; i++) {
631 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
635 for (i = 0; i < EEPROM_SIZE; i++) {
636 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]);
641 s->type = COMEDI_SUBD_UNUSED;
646 static int labpc_attach(comedi_device * dev, comedi_devconfig * it)
648 unsigned long iobase = 0;
649 unsigned int irq = 0;
650 unsigned int dma_chan = 0;
651 #ifdef CONFIG_COMEDI_PCI
655 /* allocate and initialize dev->private */
656 if (alloc_private(dev, sizeof(labpc_private)) < 0)
659 // get base address, irq etc. based on bustype
660 switch (thisboard->bustype) {
662 iobase = it->options[0];
663 irq = it->options[1];
664 dma_chan = it->options[2];
667 #ifdef CONFIG_COMEDI_PCI
668 retval = labpc_find_device(dev, it->options[0], it->options[1]);
672 retval = mite_setup(devpriv->mite);
675 iobase = (unsigned long)devpriv->mite->daq_io_addr;
676 irq = mite_irq(devpriv->mite);
678 printk(" this driver has not been built with PCI support.\n");
683 printk(" this driver does not support pcmcia cards, use ni_labpc_cs.o\n");
687 printk("bug! couldn't determine board type\n");
692 return labpc_common_attach(dev, iobase, irq, dma_chan);
695 // adapted from ni_pcimio for finding mite based boards (pc-1200)
696 #ifdef CONFIG_COMEDI_PCI
697 static int labpc_find_device(comedi_device *dev, int bus, int slot)
699 struct mite_struct *mite;
701 for (mite = mite_devices; mite; mite = mite->next) {
704 // if bus/slot are specified then make sure we have the right bus/slot
706 if (bus != mite->pcidev->bus->number
707 || slot != PCI_SLOT(mite->pcidev->devfn))
710 for (i = 0; i < driver_labpc.num_names; i++) {
711 if (labpc_boards[i].bustype != pci_bustype)
713 if (mite_device_id(mite) == labpc_boards[i].device_id) {
714 devpriv->mite = mite;
715 // fixup board pointer, in case we were using the dummy "ni_labpc" entry
716 dev->board_ptr = &labpc_boards[i];
721 printk("no device found\n");
727 int labpc_common_detach(comedi_device * dev)
729 printk("comedi%d: ni_labpc: detach\n", dev->minor);
732 subdev_8255_cleanup(dev, dev->subdevices + 2);
734 /* only free stuff if it has been allocated by _attach */
735 if (devpriv->dma_buffer)
736 kfree(devpriv->dma_buffer);
737 if (devpriv->dma_chan)
738 free_dma(devpriv->dma_chan);
740 comedi_free_irq(dev->irq, dev);
741 if (thisboard->bustype == isa_bustype && dev->iobase)
742 release_region(dev->iobase, LABPC_SIZE);
743 #ifdef CONFIG_COMEDI_PCI
745 mite_unsetup(devpriv->mite);
751 static void labpc_clear_adc_fifo(const comedi_device * dev)
753 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
754 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
755 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
758 static int labpc_cancel(comedi_device * dev, comedi_subdevice * s)
762 comedi_spin_lock_irqsave(&dev->spinlock, flags);
763 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
764 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
765 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
767 devpriv->command3_bits = 0;
768 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
773 static enum scan_mode labpc_ai_scan_mode(const comedi_cmd * cmd)
775 if (cmd->chanlist_len == 1)
776 return MODE_SINGLE_CHAN;
778 /* chanlist may be NULL during cmdtest. */
779 if (cmd->chanlist == NULL)
780 return MODE_MULT_CHAN_UP;
782 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
783 return MODE_SINGLE_CHAN_INTERVAL;
785 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
786 return MODE_MULT_CHAN_UP;
788 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
789 return MODE_MULT_CHAN_DOWN;
791 rt_printk("ni_labpc: bug! this should never happen\n");
796 static int labpc_ai_chanlist_invalid(const comedi_device * dev,
797 const comedi_cmd * cmd)
799 int mode, channel, range, aref, i;
801 if (cmd->chanlist == NULL)
804 mode = labpc_ai_scan_mode(cmd);
806 if (mode == MODE_SINGLE_CHAN)
809 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
810 if (cmd->chanlist_len > 0xff) {
812 "ni_labpc: chanlist too long for single channel interval mode\n");
817 channel = CR_CHAN(cmd->chanlist[0]);
818 range = CR_RANGE(cmd->chanlist[0]);
819 aref = CR_AREF(cmd->chanlist[0]);
821 for (i = 0; i < cmd->chanlist_len; i++) {
824 case MODE_SINGLE_CHAN_INTERVAL:
825 if (CR_CHAN(cmd->chanlist[i]) != channel) {
827 "channel scanning order specified in chanlist is not supported by hardware.\n");
831 case MODE_MULT_CHAN_UP:
832 if (CR_CHAN(cmd->chanlist[i]) != i) {
834 "channel scanning order specified in chanlist is not supported by hardware.\n");
838 case MODE_MULT_CHAN_DOWN:
839 if (CR_CHAN(cmd->chanlist[i]) !=
840 cmd->chanlist_len - i - 1) {
842 "channel scanning order specified in chanlist is not supported by hardware.\n");
847 rt_printk("ni_labpc: bug! in chanlist check\n");
852 if (CR_RANGE(cmd->chanlist[i]) != range) {
854 "entries in chanlist must all have the same range\n");
858 if (CR_AREF(cmd->chanlist[i]) != aref) {
860 "entries in chanlist must all have the same reference\n");
868 static int labpc_use_continuous_mode(const comedi_cmd * cmd)
870 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
873 if (cmd->scan_begin_src == TRIG_FOLLOW)
879 static unsigned int labpc_ai_convert_period(const comedi_cmd * cmd)
881 if (cmd->convert_src != TRIG_TIMER)
884 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
885 cmd->scan_begin_src == TRIG_TIMER)
886 return cmd->scan_begin_arg;
888 return cmd->convert_arg;
891 static void labpc_set_ai_convert_period(comedi_cmd * cmd, unsigned int ns)
893 if (cmd->convert_src != TRIG_TIMER)
896 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
897 cmd->scan_begin_src == TRIG_TIMER) {
898 cmd->scan_begin_arg = ns;
899 if (cmd->convert_arg > cmd->scan_begin_arg)
900 cmd->convert_arg = cmd->scan_begin_arg;
902 cmd->convert_arg = ns;
905 static unsigned int labpc_ai_scan_period(const comedi_cmd * cmd)
907 if (cmd->scan_begin_src != TRIG_TIMER)
910 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
911 cmd->convert_src == TRIG_TIMER)
914 return cmd->scan_begin_arg;
917 static void labpc_set_ai_scan_period(comedi_cmd * cmd, unsigned int ns)
919 if (cmd->scan_begin_src != TRIG_TIMER)
922 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
923 cmd->convert_src == TRIG_TIMER)
926 cmd->scan_begin_arg = ns;
929 static int labpc_ai_cmdtest(comedi_device * dev, comedi_subdevice * s,
936 /* step 1: make sure trigger sources are trivially valid */
938 tmp = cmd->start_src;
939 cmd->start_src &= TRIG_NOW | TRIG_EXT;
940 if (!cmd->start_src || tmp != cmd->start_src)
943 tmp = cmd->scan_begin_src;
944 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
945 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
948 tmp = cmd->convert_src;
949 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
950 if (!cmd->convert_src || tmp != cmd->convert_src)
953 tmp = cmd->scan_end_src;
954 cmd->scan_end_src &= TRIG_COUNT;
955 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
959 stop_mask = TRIG_COUNT | TRIG_NONE;
960 if (thisboard->register_layout == labpc_1200_layout)
961 stop_mask |= TRIG_EXT;
962 cmd->stop_src &= stop_mask;
963 if (!cmd->stop_src || tmp != cmd->stop_src)
969 /* step 2: make sure trigger sources are unique and mutually compatible */
971 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
973 if (cmd->scan_begin_src != TRIG_TIMER &&
974 cmd->scan_begin_src != TRIG_FOLLOW &&
975 cmd->scan_begin_src != TRIG_EXT)
977 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
979 if (cmd->stop_src != TRIG_COUNT &&
980 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
983 // can't have external stop and start triggers at once
984 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
990 /* step 3: make sure arguments are trivially compatible */
992 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
997 if (!cmd->chanlist_len) {
1000 if (cmd->scan_end_arg != cmd->chanlist_len) {
1001 cmd->scan_end_arg = cmd->chanlist_len;
1005 if (cmd->convert_src == TRIG_TIMER) {
1006 if (cmd->convert_arg < thisboard->ai_speed) {
1007 cmd->convert_arg = thisboard->ai_speed;
1011 // make sure scan timing is not too fast
1012 if (cmd->scan_begin_src == TRIG_TIMER) {
1013 if (cmd->convert_src == TRIG_TIMER &&
1014 cmd->scan_begin_arg <
1015 cmd->convert_arg * cmd->chanlist_len) {
1016 cmd->scan_begin_arg =
1017 cmd->convert_arg * cmd->chanlist_len;
1020 if (cmd->scan_begin_arg <
1021 thisboard->ai_speed * cmd->chanlist_len) {
1022 cmd->scan_begin_arg =
1023 thisboard->ai_speed * cmd->chanlist_len;
1028 switch (cmd->stop_src) {
1030 if (!cmd->stop_arg) {
1036 if (cmd->stop_arg != 0) {
1041 // TRIG_EXT doesn't care since it doesn't trigger off a numbered channel
1049 /* step 4: fix up any arguments */
1051 tmp = cmd->convert_arg;
1052 tmp2 = cmd->scan_begin_arg;
1053 labpc_adc_timing(dev, cmd);
1054 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1060 if (labpc_ai_chanlist_invalid(dev, cmd))
1066 static int labpc_ai_cmd(comedi_device * dev, comedi_subdevice * s)
1068 int channel, range, aref;
1069 unsigned long irq_flags;
1071 comedi_async *async = s->async;
1072 comedi_cmd *cmd = &async->cmd;
1073 enum transfer_type xfer;
1074 unsigned long flags;
1077 comedi_error(dev, "no irq assigned, cannot perform command");
1081 range = CR_RANGE(cmd->chanlist[0]);
1082 aref = CR_AREF(cmd->chanlist[0]);
1084 // make sure board is disabled before setting up aquisition
1085 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1086 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1087 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1088 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1090 devpriv->command3_bits = 0;
1091 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1093 // initialize software conversion count
1094 if (cmd->stop_src == TRIG_COUNT) {
1095 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1097 // setup hardware conversion counter
1098 if (cmd->stop_src == TRIG_EXT) {
1099 // load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0
1100 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1103 comedi_error(dev, "error loading counter a1");
1106 } else // otherwise, just put a1 in mode 0 with no count to set its output low
1107 devpriv->write_byte(INIT_A1_BITS,
1108 dev->iobase + COUNTER_A_CONTROL_REG);
1110 // figure out what method we will use to transfer data
1111 if (devpriv->dma_chan && // need a dma channel allocated
1112 // dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for
1113 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1114 // only available on the isa boards
1115 thisboard->bustype == isa_bustype) {
1116 xfer = isa_dma_transfer;
1117 } else if (thisboard->register_layout == labpc_1200_layout && // pc-plus has no fifo-half full interrupt
1118 // wake-end-of-scan should interrupt on fifo not empty
1119 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1120 // make sure we are taking more than just a few points
1121 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1122 xfer = fifo_half_full_transfer;
1124 xfer = fifo_not_empty_transfer;
1125 devpriv->current_transfer = xfer;
1127 // setup command6 register for 1200 boards
1128 if (thisboard->register_layout == labpc_1200_layout) {
1129 // reference inputs to ground or common?
1130 if (aref != AREF_GROUND)
1131 devpriv->command6_bits |= ADC_COMMON_BIT;
1133 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1134 // bipolar or unipolar range?
1135 if (thisboard->ai_range_is_unipolar[range])
1136 devpriv->command6_bits |= ADC_UNIP_BIT;
1138 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1139 // interrupt on fifo half full?
1140 if (xfer == fifo_half_full_transfer)
1141 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1143 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1144 // enable interrupt on counter a1 terminal count?
1145 if (cmd->stop_src == TRIG_EXT)
1146 devpriv->command6_bits |= A1_INTR_EN_BIT;
1148 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1149 // are we scanning up or down through channels?
1150 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1151 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1153 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1154 // write to register
1155 devpriv->write_byte(devpriv->command6_bits,
1156 dev->iobase + COMMAND6_REG);
1159 /* setup channel list, etc (command1 register) */
1160 devpriv->command1_bits = 0;
1161 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1162 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1164 channel = CR_CHAN(cmd->chanlist[0]);
1165 // munge channel bits for differential / scan disabled mode
1166 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1168 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1169 devpriv->command1_bits |= thisboard->ai_range_code[range];
1170 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1171 // manual says to set scan enable bit on second pass
1172 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
1173 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
1174 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1175 /* need a brief delay before enabling scan, or scan list will get screwed when you switch
1176 * between scan up to scan down mode - dunno why */
1178 devpriv->write_byte(devpriv->command1_bits,
1179 dev->iobase + COMMAND1_REG);
1181 // setup any external triggering/pacing (command4 register)
1182 devpriv->command4_bits = 0;
1183 if (cmd->convert_src != TRIG_EXT)
1184 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1185 /* XXX should discard first scan when using interval scanning
1186 * since manual says it is not synced with scan clock */
1187 if (labpc_use_continuous_mode(cmd) == 0) {
1188 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1189 if (cmd->scan_begin_src == TRIG_EXT)
1190 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1192 // single-ended/differential
1193 if (aref == AREF_DIFF)
1194 devpriv->command4_bits |= ADC_DIFF_BIT;
1195 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1197 devpriv->write_byte(cmd->chanlist_len,
1198 dev->iobase + INTERVAL_COUNT_REG);
1200 devpriv->write_byte(INTERVAL_LOAD_BITS,
1201 dev->iobase + INTERVAL_LOAD_REG);
1203 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1205 labpc_adc_timing(dev, cmd);
1206 // load counter b0 in mode 3
1207 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1208 0, devpriv->divisor_b0, 3);
1210 comedi_error(dev, "error loading counter b0");
1214 // set up conversion pacing
1215 if (labpc_ai_convert_period(cmd)) {
1216 // load counter a0 in mode 2
1217 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1218 0, devpriv->divisor_a0, 2);
1220 comedi_error(dev, "error loading counter a0");
1224 devpriv->write_byte(INIT_A0_BITS,
1225 dev->iobase + COUNTER_A_CONTROL_REG);
1227 // set up scan pacing
1228 if (labpc_ai_scan_period(cmd)) {
1229 // load counter b1 in mode 2
1230 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1231 1, devpriv->divisor_b1, 2);
1233 comedi_error(dev, "error loading counter b1");
1238 labpc_clear_adc_fifo(dev);
1240 // set up dma transfer
1241 if (xfer == isa_dma_transfer) {
1242 irq_flags = claim_dma_lock();
1243 disable_dma(devpriv->dma_chan);
1244 /* clear flip-flop to make sure 2-byte registers for
1245 * count and address get set correctly */
1246 clear_dma_ff(devpriv->dma_chan);
1247 set_dma_addr(devpriv->dma_chan,
1248 virt_to_bus(devpriv->dma_buffer));
1249 // set appropriate size of transfer
1250 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1251 if (cmd->stop_src == TRIG_COUNT &&
1252 devpriv->count * sample_size <
1253 devpriv->dma_transfer_size) {
1254 devpriv->dma_transfer_size =
1255 devpriv->count * sample_size;
1257 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1258 enable_dma(devpriv->dma_chan);
1259 release_dma_lock(irq_flags);
1260 // enable board's dma
1261 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1263 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1265 // enable error interrupts
1266 devpriv->command3_bits |= ERR_INTR_EN_BIT;
1267 // enable fifo not empty interrupt?
1268 if (xfer == fifo_not_empty_transfer)
1269 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1271 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1272 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1274 // startup aquisition
1277 // use 2 cascaded counters for pacing
1278 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1279 devpriv->command2_bits |= CASCADE_BIT;
1280 switch (cmd->start_src) {
1282 devpriv->command2_bits |= HWTRIG_BIT;
1283 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1286 devpriv->command2_bits |= SWTRIG_BIT;
1287 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1290 comedi_error(dev, "bug with start_src");
1294 switch (cmd->stop_src) {
1296 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1302 comedi_error(dev, "bug with stop_src");
1305 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1306 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1311 /* interrupt service routine */
1312 static irqreturn_t labpc_interrupt(int irq, void *d PT_REGS_ARG)
1314 comedi_device *dev = d;
1315 comedi_subdevice *s = dev->read_subdev;
1316 comedi_async *async;
1319 if (dev->attached == 0) {
1320 comedi_error(dev, "premature interrupt");
1328 // read board status
1329 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1330 if (thisboard->register_layout == labpc_1200_layout)
1331 devpriv->status2_bits =
1332 devpriv->read_byte(dev->iobase + STATUS2_REG);
1334 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1335 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1336 && (devpriv->status2_bits & A1_TC_BIT) == 0
1337 && (devpriv->status2_bits & FNHF_BIT)) {
1341 if (devpriv->status1_bits & OVERRUN_BIT) {
1342 // clear error interrupt
1343 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1344 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1345 comedi_event(dev, s);
1346 comedi_error(dev, "overrun");
1350 if (devpriv->current_transfer == isa_dma_transfer) {
1351 // if a dma terminal count of external stop trigger has occurred
1352 if (devpriv->status1_bits & DMATC_BIT ||
1353 (thisboard->register_layout == labpc_1200_layout
1354 && devpriv->status2_bits & A1_TC_BIT)) {
1355 handle_isa_dma(dev);
1358 labpc_drain_fifo(dev);
1360 if (devpriv->status1_bits & TIMER_BIT) {
1361 comedi_error(dev, "handled timer interrupt?");
1363 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1366 if (devpriv->status1_bits & OVERFLOW_BIT) {
1367 // clear error interrupt
1368 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1369 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1370 comedi_event(dev, s);
1371 comedi_error(dev, "overflow");
1374 // handle external stop trigger
1375 if (cmd->stop_src == TRIG_EXT) {
1376 if (devpriv->status2_bits & A1_TC_BIT) {
1377 labpc_drain_dregs(dev);
1378 labpc_cancel(dev, s);
1379 async->events |= COMEDI_CB_EOA;
1383 /* TRIG_COUNT end of acquisition */
1384 if (cmd->stop_src == TRIG_COUNT) {
1385 if (devpriv->count == 0) {
1386 labpc_cancel(dev, s);
1387 async->events |= COMEDI_CB_EOA;
1391 comedi_event(dev, s);
1395 // read all available samples from ai fifo
1396 static int labpc_drain_fifo(comedi_device * dev)
1398 unsigned int lsb, msb;
1400 comedi_async *async = dev->read_subdev->async;
1401 const int timeout = 10000;
1404 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1406 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1408 // quit if we have all the data we want
1409 if (async->cmd.stop_src == TRIG_COUNT) {
1410 if (devpriv->count == 0)
1414 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1415 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1416 data = (msb << 8) | lsb;
1417 cfc_write_to_buffer(dev->read_subdev, data);
1418 devpriv->status1_bits =
1419 devpriv->read_byte(dev->iobase + STATUS1_REG);
1422 comedi_error(dev, "ai timeout, fifo never empties");
1423 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1430 static void labpc_drain_dma(comedi_device * dev)
1432 comedi_subdevice *s = dev->read_subdev;
1433 comedi_async *async = s->async;
1435 unsigned long flags;
1436 unsigned int max_points, num_points, residue, leftover;
1439 status = devpriv->status1_bits;
1441 flags = claim_dma_lock();
1442 disable_dma(devpriv->dma_chan);
1443 /* clear flip-flop to make sure 2-byte registers for
1444 * count and address get set correctly */
1445 clear_dma_ff(devpriv->dma_chan);
1447 // figure out how many points to read
1448 max_points = devpriv->dma_transfer_size / sample_size;
1449 /* residue is the number of points left to be done on the dma
1450 * transfer. It should always be zero at this point unless
1451 * the stop_src is set to external triggering.
1453 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1454 num_points = max_points - residue;
1455 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1456 num_points = devpriv->count;
1458 // figure out how many points will be stored next time
1460 if (async->cmd.stop_src != TRIG_COUNT) {
1461 leftover = devpriv->dma_transfer_size / sample_size;
1462 } else if (devpriv->count > num_points) {
1463 leftover = devpriv->count - num_points;
1464 if (leftover > max_points)
1465 leftover = max_points;
1468 /* write data to comedi buffer */
1469 for (i = 0; i < num_points; i++) {
1470 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1472 if (async->cmd.stop_src == TRIG_COUNT)
1473 devpriv->count -= num_points;
1475 // set address and count for next transfer
1476 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1477 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1478 release_dma_lock(flags);
1480 async->events |= COMEDI_CB_BLOCK;
1483 static void handle_isa_dma(comedi_device * dev)
1485 labpc_drain_dma(dev);
1487 enable_dma(devpriv->dma_chan);
1489 // clear dma tc interrupt
1490 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1493 /* makes sure all data aquired by board is transfered to comedi (used
1494 * when aquisition is terminated by stop_src == TRIG_EXT). */
1495 static void labpc_drain_dregs(comedi_device * dev)
1497 if (devpriv->current_transfer == isa_dma_transfer)
1498 labpc_drain_dma(dev);
1500 labpc_drain_fifo(dev);
1503 static int labpc_ai_rinsn(comedi_device * dev, comedi_subdevice * s,
1504 comedi_insn * insn, unsigned int * data)
1510 unsigned long flags;
1512 // disable timed conversions
1513 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1514 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1515 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1516 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1518 // disable interrupt generation and dma
1519 devpriv->command3_bits = 0;
1520 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1522 /* set gain and channel */
1523 devpriv->command1_bits = 0;
1524 chan = CR_CHAN(insn->chanspec);
1525 range = CR_RANGE(insn->chanspec);
1526 devpriv->command1_bits |= thisboard->ai_range_code[range];
1527 // munge channel bits for differential/scan disabled mode
1528 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1530 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1531 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1533 // setup command6 register for 1200 boards
1534 if (thisboard->register_layout == labpc_1200_layout) {
1535 // reference inputs to ground or common?
1536 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1537 devpriv->command6_bits |= ADC_COMMON_BIT;
1539 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1540 // bipolar or unipolar range?
1541 if (thisboard->ai_range_is_unipolar[range])
1542 devpriv->command6_bits |= ADC_UNIP_BIT;
1544 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1545 // don't interrupt on fifo half full
1546 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1547 // don't enable interrupt on counter a1 terminal count?
1548 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1549 // write to register
1550 devpriv->write_byte(devpriv->command6_bits,
1551 dev->iobase + COMMAND6_REG);
1553 // setup command4 register
1554 devpriv->command4_bits = 0;
1555 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1556 // single-ended/differential
1557 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1558 devpriv->command4_bits |= ADC_DIFF_BIT;
1559 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1561 // initialize pacer counter output to make sure it doesn't cause any problems
1562 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1564 labpc_clear_adc_fifo(dev);
1566 for (n = 0; n < insn->n; n++) {
1567 /* trigger conversion */
1568 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1570 for (i = 0; i < timeout; i++) {
1571 if (devpriv->read_byte(dev->iobase +
1572 STATUS1_REG) & DATA_AVAIL_BIT)
1577 comedi_error(dev, "timeout");
1580 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1581 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1582 data[n] = (msb << 8) | lsb;
1588 // analog output insn
1589 static int labpc_ao_winsn(comedi_device * dev, comedi_subdevice * s,
1590 comedi_insn * insn, unsigned int * data)
1593 unsigned long flags;
1596 channel = CR_CHAN(insn->chanspec);
1598 // turn off pacing of analog output channel
1599 /* note: hardware bug in daqcard-1200 means pacing cannot
1600 * be independently enabled/disabled for its the two channels */
1601 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1602 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1603 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1604 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1607 if (thisboard->register_layout == labpc_1200_layout) {
1608 range = CR_RANGE(insn->chanspec);
1609 if (range & AO_RANGE_IS_UNIPOLAR)
1610 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1612 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1613 // write to register
1614 devpriv->write_byte(devpriv->command6_bits,
1615 dev->iobase + COMMAND6_REG);
1618 lsb = data[0] & 0xff;
1619 msb = (data[0] >> 8) & 0xff;
1620 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1621 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1623 // remember value for readback
1624 devpriv->ao_value[channel] = data[0];
1629 // analog output readback insn
1630 static int labpc_ao_rinsn(comedi_device * dev, comedi_subdevice * s,
1631 comedi_insn * insn, unsigned int * data)
1633 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1638 static int labpc_calib_read_insn(comedi_device * dev, comedi_subdevice * s,
1639 comedi_insn * insn, unsigned int * data)
1641 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1646 static int labpc_calib_write_insn(comedi_device * dev, comedi_subdevice * s,
1647 comedi_insn * insn, unsigned int * data)
1649 int channel = CR_CHAN(insn->chanspec);
1651 write_caldac(dev, channel, data[0]);
1655 static int labpc_eeprom_read_insn(comedi_device * dev, comedi_subdevice * s,
1656 comedi_insn * insn, unsigned int * data)
1658 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1663 static int labpc_eeprom_write_insn(comedi_device * dev, comedi_subdevice * s,
1664 comedi_insn * insn, unsigned int * data)
1666 int channel = CR_CHAN(insn->chanspec);
1669 // only allow writes to user area of eeprom
1670 if (channel < 16 || channel > 127) {
1671 printk("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)");
1675 ret = labpc_eeprom_write(dev, channel, data[0]);
1682 // utility function that suggests a dma transfer size in bytes
1683 static unsigned int labpc_suggest_transfer_size(comedi_cmd cmd)
1688 if (cmd.convert_src == TRIG_TIMER)
1689 freq = 1000000000 / cmd.convert_arg;
1690 // return some default value
1694 // make buffer fill in no more than 1/3 second
1695 size = (freq / 3) * sample_size;
1697 // set a minimum and maximum size allowed
1698 if (size > dma_buffer_size)
1699 size = dma_buffer_size - dma_buffer_size % sample_size;
1700 else if (size < sample_size)
1706 // figures out what counter values to use based on command
1707 static void labpc_adc_timing(comedi_device * dev, comedi_cmd * cmd)
1709 const int max_counter_value = 0x10000; // max value for 16 bit counter in mode 2
1710 const int min_counter_value = 2; // min value for 16 bit counter in mode 2
1711 unsigned int base_period;
1713 // if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0
1714 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
1715 // pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters)
1716 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
1717 (LABPC_TIMER_BASE * max_counter_value) + 1;
1718 if (devpriv->divisor_b0 < min_counter_value)
1719 devpriv->divisor_b0 = min_counter_value;
1720 if (devpriv->divisor_b0 > max_counter_value)
1721 devpriv->divisor_b0 = max_counter_value;
1723 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1725 // set a0 for conversion frequency and b1 for scan frequency
1726 switch (cmd->flags & TRIG_ROUND_MASK) {
1728 case TRIG_ROUND_NEAREST:
1729 devpriv->divisor_a0 =
1730 (labpc_ai_convert_period(cmd) +
1731 (base_period / 2)) / base_period;
1732 devpriv->divisor_b1 =
1733 (labpc_ai_scan_period(cmd) +
1734 (base_period / 2)) / base_period;
1737 devpriv->divisor_a0 =
1738 (labpc_ai_convert_period(cmd) + (base_period -
1740 devpriv->divisor_b1 =
1741 (labpc_ai_scan_period(cmd) + (base_period -
1744 case TRIG_ROUND_DOWN:
1745 devpriv->divisor_a0 =
1746 labpc_ai_convert_period(cmd) / base_period;
1747 devpriv->divisor_b1 =
1748 labpc_ai_scan_period(cmd) / base_period;
1751 // make sure a0 and b1 values are acceptable
1752 if (devpriv->divisor_a0 < min_counter_value)
1753 devpriv->divisor_a0 = min_counter_value;
1754 if (devpriv->divisor_a0 > max_counter_value)
1755 devpriv->divisor_a0 = max_counter_value;
1756 if (devpriv->divisor_b1 < min_counter_value)
1757 devpriv->divisor_b1 = min_counter_value;
1758 if (devpriv->divisor_b1 > max_counter_value)
1759 devpriv->divisor_b1 = max_counter_value;
1760 // write corrected timings to command
1761 labpc_set_ai_convert_period(cmd,
1762 base_period * devpriv->divisor_a0);
1763 labpc_set_ai_scan_period(cmd,
1764 base_period * devpriv->divisor_b1);
1765 // if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions
1766 } else if (labpc_ai_scan_period(cmd)) {
1767 unsigned int scan_period;
1769 scan_period = labpc_ai_scan_period(cmd);
1770 /* calculate cascaded counter values that give desired scan timing */
1771 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1772 &(devpriv->divisor_b1), &(devpriv->divisor_b0),
1773 &scan_period, cmd->flags & TRIG_ROUND_MASK);
1774 labpc_set_ai_scan_period(cmd, scan_period);
1775 } else if (labpc_ai_convert_period(cmd)) {
1776 unsigned int convert_period;
1778 convert_period = labpc_ai_convert_period(cmd);
1779 /* calculate cascaded counter values that give desired conversion timing */
1780 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1781 &(devpriv->divisor_a0), &(devpriv->divisor_b0),
1782 &convert_period, cmd->flags & TRIG_ROUND_MASK);
1783 labpc_set_ai_convert_period(cmd, convert_period);
1787 static int labpc_dio_mem_callback(int dir, int port, int data,
1788 unsigned long iobase)
1791 writeb(data, (void *)(iobase + port));
1794 return readb((void *)(iobase + port));
1798 // lowlevel write to eeprom/dac
1799 static void labpc_serial_out(comedi_device * dev, unsigned int value,
1800 unsigned int value_width)
1804 for (i = 1; i <= value_width; i++) {
1805 // clear serial clock
1806 devpriv->command5_bits &= ~SCLOCK_BIT;
1807 // send bits most significant bit first
1808 if (value & (1 << (value_width - i)))
1809 devpriv->command5_bits |= SDATA_BIT;
1811 devpriv->command5_bits &= ~SDATA_BIT;
1813 devpriv->write_byte(devpriv->command5_bits,
1814 dev->iobase + COMMAND5_REG);
1815 // set clock to load bit
1816 devpriv->command5_bits |= SCLOCK_BIT;
1818 devpriv->write_byte(devpriv->command5_bits,
1819 dev->iobase + COMMAND5_REG);
1823 // lowlevel read from eeprom
1824 static unsigned int labpc_serial_in(comedi_device * dev)
1826 unsigned int value = 0;
1828 const int value_width = 8; // number of bits wide values are
1830 for (i = 1; i <= value_width; i++) {
1832 devpriv->command5_bits |= SCLOCK_BIT;
1834 devpriv->write_byte(devpriv->command5_bits,
1835 dev->iobase + COMMAND5_REG);
1837 devpriv->command5_bits &= ~SCLOCK_BIT;
1839 devpriv->write_byte(devpriv->command5_bits,
1840 dev->iobase + COMMAND5_REG);
1841 // read bits most significant bit first
1843 devpriv->status2_bits =
1844 devpriv->read_byte(dev->iobase + STATUS2_REG);
1845 if (devpriv->status2_bits & EEPROM_OUT_BIT) {
1846 value |= 1 << (value_width - i);
1853 static unsigned int labpc_eeprom_read(comedi_device * dev, unsigned int address)
1856 const int read_instruction = 0x3; // bits to tell eeprom to expect a read
1857 const int write_length = 8; // 8 bit write lengths to eeprom
1859 // enable read/write to eeprom
1860 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1862 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1863 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1865 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1867 // send read instruction
1868 labpc_serial_out(dev, read_instruction, write_length);
1869 // send 8 bit address to read from
1870 labpc_serial_out(dev, address, write_length);
1872 value = labpc_serial_in(dev);
1874 // disable read/write to eeprom
1875 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1877 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1882 static unsigned int labpc_eeprom_write(comedi_device * dev,
1883 unsigned int address, unsigned int value)
1885 const int write_enable_instruction = 0x6;
1886 const int write_instruction = 0x2;
1887 const int write_length = 8; // 8 bit write lengths to eeprom
1888 const int write_in_progress_bit = 0x1;
1889 const int timeout = 10000;
1892 // make sure there isn't already a write in progress
1893 for (i = 0; i < timeout; i++) {
1894 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1899 comedi_error(dev, "eeprom write timed out");
1902 // update software copy of eeprom
1903 devpriv->eeprom_data[address] = value;
1905 // enable read/write to eeprom
1906 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1908 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1909 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1911 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1913 // send write_enable instruction
1914 labpc_serial_out(dev, write_enable_instruction, write_length);
1915 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1917 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1919 // send write instruction
1920 devpriv->command5_bits |= EEPROM_EN_BIT;
1922 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1923 labpc_serial_out(dev, write_instruction, write_length);
1924 // send 8 bit address to write to
1925 labpc_serial_out(dev, address, write_length);
1927 labpc_serial_out(dev, value, write_length);
1928 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1930 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1932 // disable read/write to eeprom
1933 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1935 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1940 static unsigned int labpc_eeprom_read_status(comedi_device * dev)
1943 const int read_status_instruction = 0x5;
1944 const int write_length = 8; // 8 bit write lengths to eeprom
1946 // enable read/write to eeprom
1947 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1949 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1950 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1952 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1954 // send read status instruction
1955 labpc_serial_out(dev, read_status_instruction, write_length);
1957 value = labpc_serial_in(dev);
1959 // disable read/write to eeprom
1960 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1962 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1967 // writes to 8 bit calibration dacs
1968 static void write_caldac(comedi_device * dev, unsigned int channel,
1971 if (value == devpriv->caldac[channel])
1973 devpriv->caldac[channel] = value;
1975 // clear caldac load bit and make sure we don't write to eeprom
1976 devpriv->command5_bits &=
1977 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1979 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1981 // write 4 bit channel
1982 labpc_serial_out(dev, channel, 4);
1983 // write 8 bit caldac value
1984 labpc_serial_out(dev, value, 8);
1986 // set and clear caldac bit to load caldac value
1987 devpriv->command5_bits |= CALDAC_LOAD_BIT;
1989 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1990 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
1992 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1995 #ifdef CONFIG_COMEDI_PCI
1996 COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table);
1998 COMEDI_INITCLEANUP(driver_labpc);
2001 EXPORT_SYMBOL_GPL(labpc_common_attach);
2002 EXPORT_SYMBOL_GPL(labpc_common_detach);
2003 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
2004 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
2005 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);