2 comedi/drivers/cb_pcidas64.c
3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 64xx, 60xx, and 4020 cards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2001, 2002 Frank Mori Hess
9 Thanks also go to the following people:
11 Steve Rosenbluth, for providing the source code for
12 his pci-das6402 driver, and source code for working QNX pci-6402
13 drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 used directly here, but it was useful as an additional source of
15 documentation on how to program the boards.
17 John Sims, for much testing and feedback on pcidas-4020 support.
19 COMEDI - Linux Control and Measurement Device Interface
20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
22 This program is free software; you can redistribute it and/or modify
23 it under the terms of the GNU General Public License as published by
24 the Free Software Foundation; either version 2 of the License, or
25 (at your option) any later version.
27 This program is distributed in the hope that it will be useful,
28 but WITHOUT ANY WARRANTY; without even the implied warranty of
29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 GNU General Public License for more details.
32 You should have received a copy of the GNU General Public License
33 along with this program; if not, write to the Free Software
34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
36 ************************************************************************/
41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
42 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
46 PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
47 PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
48 PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
49 PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
50 PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
51 PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
52 PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
53 PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
55 Configuration options:
56 [0] - PCI bus of device (optional)
57 [1] - PCI slot of device (optional)
59 These boards may be autocalibrated with the comedi_calibrate utility.
61 To select the bnc trigger input on the 4020 (instead of the dio input),
62 specify a nonzero channel in the chanspec. If you wish to use an external
63 master clock on the 4020, you may do so by setting the scan_begin_src
64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
65 to configure the divisor to use for the external clock.
67 Some devices are not identified because the PCI device IDs are not yet
68 known. If you have such a board, please file a bug report at
69 https://bugs.comedi.org.
76 make it return error if user attempts an ai command that uses the
77 external queue, and an ao command simultaneously
78 user counter subdevice
79 there are a number of boards this driver will support when they are
80 fully released, but does not yet since the pci device id numbers
81 are not yet available.
82 support prescaled 100khz clock for slow pacing (not available on 6000 series?)
83 make ao fifo size adjustable like ai fifo
86 #include "../comedidev.h"
87 #include <linux/delay.h>
88 #include <asm/system.h>
90 #include "comedi_pci.h"
94 #include "comedi_fc.h"
96 #undef PCIDAS64_DEBUG // disable debugging code
97 //#define PCIDAS64_DEBUG // enable debugging code
100 #define DEBUG_PRINT(format, args...) rt_printk(format , ## args )
102 #define DEBUG_PRINT(format, args...)
105 #define TIMER_BASE 25 // 40MHz master clock
106 #define PRESCALED_TIMER_BASE 10000 // 100kHz 'prescaled' clock for slow aquisition, maybe I'll support this someday
107 #define DMA_BUFFER_SIZE 0x1000
109 /* maximum value that can be loaded into board's 24-bit counters*/
110 static const int max_counter_value = 0xffffff;
112 /* PCI-DAS64xxx base addresses */
114 // indices of base address regions
115 enum base_address_regions {
116 PLX9080_BADDRINDEX = 0,
118 DIO_COUNTER_BADDRINDEX = 3,
121 // priv(dev)->main_iobase registers
122 enum write_only_registers {
123 INTR_ENABLE_REG = 0x0, // interrupt enable register
124 HW_CONFIG_REG = 0x2, // hardware config register
126 DAQ_ATRIG_LOW_4020_REG = 0xc,
127 ADC_CONTROL0_REG = 0x10, // adc control register 0
128 ADC_CONTROL1_REG = 0x12, // adc control register 1
129 CALIBRATION_REG = 0x14,
130 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, // lower 16 bits of adc sample interval counter
131 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, // upper 8 bits of adc sample interval counter
132 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, // lower 16 bits of delay interval counter
133 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, // upper 8 bits of delay interval counter
134 ADC_COUNT_LOWER_REG = 0x1e, // lower 16 bits of hardware conversion/scan counter
135 ADC_COUNT_UPPER_REG = 0x20, // upper 8 bits of hardware conversion/scan counter
136 ADC_START_REG = 0x22, // software trigger to start aquisition
137 ADC_CONVERT_REG = 0x24, // initiates single conversion
138 ADC_QUEUE_CLEAR_REG = 0x26, // clears adc queue
139 ADC_QUEUE_LOAD_REG = 0x28, // loads adc queue
140 ADC_BUFFER_CLEAR_REG = 0x2a,
141 ADC_QUEUE_HIGH_REG = 0x2c, // high channel for internal queue, use adc_chan_bits() inline above
142 DAC_CONTROL0_REG = 0x50, // dac control register 0
143 DAC_CONTROL1_REG = 0x52, // dac control register 0
144 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, // lower 16 bits of dac sample interval counter
145 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, // upper 8 bits of dac sample interval counter
146 DAC_SELECT_REG = 0x60,
147 DAC_START_REG = 0x64,
148 DAC_BUFFER_CLEAR_REG = 0x66, // clear dac buffer
150 static inline unsigned int dac_convert_reg(unsigned int channel)
152 return 0x70 + (2 * (channel & 0x1));
154 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
156 return 0x70 + (4 * (channel & 0x1));
158 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
160 return 0x72 + (4 * (channel & 0x1));
163 enum read_only_registers {
164 HW_STATUS_REG = 0x0, // hardware status register, reading this apparently clears pending interrupts as well
165 PIPE1_READ_REG = 0x4,
166 ADC_READ_PNTR_REG = 0x8,
167 LOWER_XFER_REG = 0x10,
168 ADC_WRITE_PNTR_REG = 0xc,
172 enum read_write_registers {
173 I8255_4020_REG = 0x48, // 8255 offset, for 4020 only
174 ADC_QUEUE_FIFO_REG = 0x100, // external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG
175 ADC_FIFO_REG = 0x200, /* adc data fifo */
176 DAC_FIFO_REG = 0x300, /* dac data fifo, has weird interactions with external channel queue */
179 // priv(dev)->dio_counter_iobase registers
180 enum dio_counter_registers {
181 DIO_8255_OFFSET = 0x0,
184 DIO_DIRECTION_60XX_REG = 0x40,
185 DIO_DATA_60XX_REG = 0x48,
188 // bit definitions for write-only registers
190 enum intr_enable_contents {
191 ADC_INTR_SRC_MASK = 0x3, // bits that set adc interrupt source
192 ADC_INTR_QFULL_BITS = 0x0, // interrupt fifo quater full
193 ADC_INTR_EOC_BITS = 0x1, // interrupt end of conversion
194 ADC_INTR_EOSCAN_BITS = 0x2, // interrupt end of scan
195 ADC_INTR_EOSEQ_BITS = 0x3, // interrupt end of sequence (probably wont use this it's pretty fancy)
196 EN_ADC_INTR_SRC_BIT = 0x4, // enable adc interrupt source
197 EN_ADC_DONE_INTR_BIT = 0x8, // enable adc aquisition done interrupt
198 DAC_INTR_SRC_MASK = 0x30,
199 DAC_INTR_QEMPTY_BITS = 0x0,
200 DAC_INTR_HIGH_CHAN_BITS = 0x10,
201 EN_DAC_INTR_SRC_BIT = 0x40, // enable dac interrupt source
202 EN_DAC_DONE_INTR_BIT = 0x80,
203 EN_ADC_ACTIVE_INTR_BIT = 0x200, // enable adc active interrupt
204 EN_ADC_STOP_INTR_BIT = 0x400, // enable adc stop trigger interrupt
205 EN_DAC_ACTIVE_INTR_BIT = 0x800, // enable dac active interrupt
206 EN_DAC_UNDERRUN_BIT = 0x4000, // enable dac underrun status bit
207 EN_ADC_OVERRUN_BIT = 0x8000, // enable adc overrun status bit
210 enum hw_config_contents {
211 MASTER_CLOCK_4020_MASK = 0x3, // bits that specify master clock source for 4020
212 INTERNAL_CLOCK_4020_BITS = 0x1, // use 40 MHz internal master clock for 4020
213 BNC_CLOCK_4020_BITS = 0x2, // use BNC input for master clock
214 EXT_CLOCK_4020_BITS = 0x3, // use dio input for master clock
215 EXT_QUEUE_BIT = 0x200, // use external channel/gain queue (more versatile than internal queue)
216 SLOW_DAC_BIT = 0x400, // use 225 nanosec strobe when loading dac instead of 50 nanosec
217 HW_CONFIG_DUMMY_BITS = 0x2000, // bit with unknown function yet given as default value in pci-das64 manual
218 DMA_CH_SELECT_BIT = 0x8000, // bit selects channels 1/0 for analog input/output, otherwise 0/1
219 FIFO_SIZE_REG = 0x4, // allows adjustment of fifo sizes
220 DAC_FIFO_SIZE_MASK = 0xff00, // bits that set dac fifo size
221 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
223 #define DAC_FIFO_SIZE 0x2000
225 enum daq_atrig_low_4020_contents {
226 EXT_AGATE_BNC_BIT = 0x8000, // use trig/ext clk bnc input for analog gate signal
227 EXT_STOP_TRIG_BNC_BIT = 0x4000, // use trig/ext clk bnc input for external stop trigger signal
228 EXT_START_TRIG_BNC_BIT = 0x2000, // use trig/ext clk bnc input for external start trigger signal
230 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
232 return threshold & 0xfff;
235 enum adc_control0_contents {
236 ADC_GATE_SRC_MASK = 0x3, // bits that select gate
237 ADC_SOFT_GATE_BITS = 0x1, // software gate
238 ADC_EXT_GATE_BITS = 0x2, // external digital gate
239 ADC_ANALOG_GATE_BITS = 0x3, // analog level gate
240 ADC_GATE_LEVEL_BIT = 0x4, // level-sensitive gate (for digital)
241 ADC_GATE_POLARITY_BIT = 0x8, // gate active low
242 ADC_START_TRIG_SOFT_BITS = 0x10,
243 ADC_START_TRIG_EXT_BITS = 0x20,
244 ADC_START_TRIG_ANALOG_BITS = 0x30,
245 ADC_START_TRIG_MASK = 0x30,
246 ADC_START_TRIG_FALLING_BIT = 0x40, // trig 1 uses falling edge
247 ADC_EXT_CONV_FALLING_BIT = 0x800, // external pacing uses falling edge
248 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, // enable hardware scan counter
249 ADC_DMA_DISABLE_BIT = 0x4000, // disables dma
250 ADC_ENABLE_BIT = 0x8000, // master adc enable
253 enum adc_control1_contents {
254 ADC_QUEUE_CONFIG_BIT = 0x1, // should be set for boards with > 16 channels
255 CONVERT_POLARITY_BIT = 0x10,
256 EOC_POLARITY_BIT = 0x20,
257 ADC_SW_GATE_BIT = 0x40, // software gate of adc
258 ADC_DITHER_BIT = 0x200, // turn on extra noise for dithering
259 RETRIGGER_BIT = 0x800,
260 ADC_LO_CHANNEL_4020_MASK = 0x300,
261 ADC_HI_CHANNEL_4020_MASK = 0xc00,
262 TWO_CHANNEL_4020_BITS = 0x1000, // two channel mode for 4020
263 FOUR_CHANNEL_4020_BITS = 0x2000, // four channel mode for 4020
264 CHANNEL_MODE_4020_MASK = 0x3000,
265 ADC_MODE_MASK = 0xf000,
267 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
269 return (channel & 0x3) << 8;
271 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
273 return (channel & 0x3) << 10;
275 static inline uint16_t adc_mode_bits(unsigned int mode)
277 return (mode & 0xf) << 12;
280 enum calibration_contents {
281 SELECT_8800_BIT = 0x1,
282 SELECT_8402_64XX_BIT = 0x2,
283 SELECT_1590_60XX_BIT = 0x2,
284 CAL_EN_64XX_BIT = 0x40, // calibration enable for 64xx series
285 SERIAL_DATA_IN_BIT = 0x80,
286 SERIAL_CLOCK_BIT = 0x100,
287 CAL_EN_60XX_BIT = 0x200, // calibration enable for 60xx series
288 CAL_GAIN_BIT = 0x800,
290 /* calibration sources for 6025 are:
300 static inline uint16_t adc_src_bits(unsigned int source)
302 return (source & 0xf) << 3;
305 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
307 return (channel & 0x3) << 8;
310 enum adc_queue_load_contents {
311 UNIP_BIT = 0x800, // unipolar/bipolar bit
312 ADC_SE_DIFF_BIT = 0x1000, // single-ended/ differential bit
313 ADC_COMMON_BIT = 0x2000, // non-referenced single-ended (common-mode input)
314 QUEUE_EOSEQ_BIT = 0x4000, // queue end of sequence
315 QUEUE_EOSCAN_BIT = 0x8000, // queue end of scan
317 static inline uint16_t adc_chan_bits(unsigned int channel)
319 return channel & 0x3f;
322 enum dac_control0_contents {
323 DAC_ENABLE_BIT = 0x8000, // dac controller enable bit
324 DAC_CYCLIC_STOP_BIT = 0x4000,
325 DAC_WAVEFORM_MODE_BIT = 0x100,
326 DAC_EXT_UPDATE_FALLING_BIT = 0x80,
327 DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
328 WAVEFORM_TRIG_MASK = 0x30,
329 WAVEFORM_TRIG_DISABLED_BITS = 0x0,
330 WAVEFORM_TRIG_SOFT_BITS = 0x10,
331 WAVEFORM_TRIG_EXT_BITS = 0x20,
332 WAVEFORM_TRIG_ADC1_BITS = 0x30,
333 WAVEFORM_TRIG_FALLING_BIT = 0x8,
334 WAVEFORM_GATE_LEVEL_BIT = 0x4,
335 WAVEFORM_GATE_ENABLE_BIT = 0x2,
336 WAVEFORM_GATE_SELECT_BIT = 0x1,
339 enum dac_control1_contents {
340 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
341 DAC1_EXT_REF_BIT = 0x200,
342 DAC0_EXT_REF_BIT = 0x100,
343 DAC_OUTPUT_ENABLE_BIT = 0x80, // dac output enable bit
344 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
345 DAC_SW_GATE_BIT = 0x20,
346 DAC1_UNIPOLAR_BIT = 0x8,
347 DAC0_UNIPOLAR_BIT = 0x2,
350 // bit definitions for read-only registers
351 enum hw_status_contents {
352 DAC_UNDERRUN_BIT = 0x1,
353 ADC_OVERRUN_BIT = 0x2,
354 DAC_ACTIVE_BIT = 0x4,
355 ADC_ACTIVE_BIT = 0x8,
356 DAC_INTR_PENDING_BIT = 0x10,
357 ADC_INTR_PENDING_BIT = 0x20,
360 EXT_INTR_PENDING_BIT = 0x100,
361 ADC_STOP_BIT = 0x200,
363 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
365 return (hw_status_bits >> 10) & 0x3;
368 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
370 return (prepost_bits >> 6) & 0x3;
372 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
374 return (prepost_bits >> 12) & 0x3;
376 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
378 return (prepost_bits >> 14) & 0x3;
381 // I2C addresses for 4020
383 RANGE_CAL_I2C_ADDR = 0x20,
384 CALDAC0_I2C_ADDR = 0xc,
385 CALDAC1_I2C_ADDR = 0xd,
388 enum range_cal_i2c_contents {
389 ADC_SRC_4020_MASK = 0x70, // bits that set what source the adc converter measures
390 BNC_TRIG_THRESHOLD_0V_BIT = 0x80, // make bnc trig/ext clock threshold 0V instead of 2.5V
392 static inline uint8_t adc_src_4020_bits(unsigned int source)
394 return (source << 4) & ADC_SRC_4020_MASK;
396 static inline uint8_t attenuate_bit(unsigned int channel)
398 // attenuate channel (+-5V input range)
399 return 1 << (channel & 0x3);
402 // analog input ranges for 64xx boards
403 static const struct comedi_lrange ai_ranges_64xx = {
417 /* analog input ranges for 60xx boards */
418 static const struct comedi_lrange ai_ranges_60xx = {
428 /* analog input ranges for 6030, etc boards */
429 static const struct comedi_lrange ai_ranges_6030 = {
449 /* analog input ranges for 6052, etc boards */
450 static const struct comedi_lrange ai_ranges_6052 = {
471 // analog input ranges for 4020 board
472 static const struct comedi_lrange ai_ranges_4020 = {
480 // analog output ranges
481 static const struct comedi_lrange ao_ranges_64xx = {
490 static const int ao_range_code_64xx[] = {
497 static const struct comedi_lrange ao_ranges_60xx = {
503 static const int ao_range_code_60xx[] = {
507 static const struct comedi_lrange ao_ranges_6030 = {
514 static const int ao_range_code_6030[] = {
519 static const struct comedi_lrange ao_ranges_4020 = {
526 static const int ao_range_code_4020[] = {
531 enum register_layout {
537 struct hw_fifo_info {
538 unsigned int num_segments;
539 unsigned int max_segment_length;
540 unsigned int sample_packing_ratio;
541 uint16_t fifo_size_reg_mask;
544 struct pcidas64_board {
546 int device_id; // pci device id
547 int ai_se_chans; // number of ai inputs in single-ended mode
548 int ai_bits; // analog input resolution
549 int ai_speed; // fastest conversion period in ns
550 const struct comedi_lrange *ai_range_table;
551 int ao_nchan; // number of analog out channels
552 int ao_bits; // analog output resolution
553 int ao_scan_speed; // analog output speed (for a scan, not conversion)
554 const struct comedi_lrange *ao_range_table;
555 const int *ao_range_code;
556 const struct hw_fifo_info *const ai_fifo;
557 enum register_layout layout; // different board families have slightly different registers
561 static const struct hw_fifo_info ai_fifo_4020 = {
563 max_segment_length:0x8000,
564 sample_packing_ratio:2,
565 fifo_size_reg_mask:0x7f,
568 static const struct hw_fifo_info ai_fifo_64xx = {
570 max_segment_length:0x800,
571 sample_packing_ratio:1,
572 fifo_size_reg_mask:0x3f,
575 static const struct hw_fifo_info ai_fifo_60xx = {
577 max_segment_length:0x800,
578 sample_packing_ratio:1,
579 fifo_size_reg_mask:0x7f,
582 /* maximum number of dma transfers we will chain together into a ring
583 * (and the maximum number of dma buffers we maintain) */
584 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
585 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
586 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
587 static inline unsigned int ai_dma_ring_count(struct pcidas64_board * board)
589 if (board->layout == LAYOUT_4020)
590 return MAX_AI_DMA_RING_COUNT;
592 return MIN_AI_DMA_RING_COUNT;
595 static const int bytes_in_sample = 2;
597 static const struct pcidas64_board pcidas64_boards[] = {
599 name: "pci-das6402/16",
608 ai_range_table:&ai_ranges_64xx,
609 ao_range_table:&ao_ranges_64xx,
610 ao_range_code:ao_range_code_64xx,
611 ai_fifo: &ai_fifo_64xx,
615 name: "pci-das6402/12", // XXX check
624 ai_range_table:&ai_ranges_64xx,
625 ao_range_table:&ao_ranges_64xx,
626 ao_range_code:ao_range_code_64xx,
627 ai_fifo: &ai_fifo_64xx,
631 name: "pci-das64/m1/16",
640 ai_range_table:&ai_ranges_64xx,
641 ao_range_table:&ao_ranges_64xx,
642 ao_range_code:ao_range_code_64xx,
643 ai_fifo: &ai_fifo_64xx,
647 name: "pci-das64/m2/16",
656 ai_range_table:&ai_ranges_64xx,
657 ao_range_table:&ao_ranges_64xx,
658 ao_range_code:ao_range_code_64xx,
659 ai_fifo: &ai_fifo_64xx,
663 name: "pci-das64/m3/16",
672 ai_range_table:&ai_ranges_64xx,
673 ao_range_table:&ao_ranges_64xx,
674 ao_range_code:ao_range_code_64xx,
675 ai_fifo: &ai_fifo_64xx,
679 .name = "pci-das6013",
686 .layout = LAYOUT_60XX,
687 .ai_range_table = &ai_ranges_60xx,
688 .ao_range_table = &ao_ranges_60xx,
689 .ao_range_code = ao_range_code_60xx,
690 .ai_fifo = &ai_fifo_60xx,
701 ao_scan_speed:100000,
703 ai_range_table:&ai_ranges_60xx,
704 ao_range_table:&ao_ranges_60xx,
705 ao_range_code:ao_range_code_60xx,
706 ai_fifo: &ai_fifo_60xx,
716 ao_scan_speed:100000,
718 ai_range_table:&ai_ranges_60xx,
719 ao_range_table:&ao_ranges_60xx,
720 ao_range_code:ao_range_code_60xx,
721 ai_fifo: &ai_fifo_60xx,
732 ao_scan_speed:100000,
734 ai_range_table:&ai_ranges_60xx,
735 ao_range_table:&ao_ranges_60xx,
736 ao_range_code:ao_range_code_60xx,
737 ai_fifo: &ai_fifo_60xx,
750 ai_range_table:&ai_ranges_6030,
751 ao_range_table:&ao_ranges_6030,
752 ao_range_code:ao_range_code_6030,
753 ai_fifo: &ai_fifo_60xx,
766 ai_range_table:&ai_ranges_6030,
767 ao_range_table:&ao_ranges_6030,
768 ao_range_code:ao_range_code_6030,
769 ai_fifo: &ai_fifo_60xx,
780 ai_range_table:&ai_ranges_6030,
781 ai_fifo: &ai_fifo_60xx,
792 ai_range_table:&ai_ranges_6030,
793 ai_fifo: &ai_fifo_60xx,
805 ai_range_table:&ai_ranges_60xx,
806 ai_fifo: &ai_fifo_60xx,
817 ao_scan_speed:100000,
819 ai_range_table:&ai_ranges_60xx,
820 ao_range_table:&ao_ranges_60xx,
821 ao_range_code:ao_range_code_60xx,
822 ai_fifo: &ai_fifo_60xx,
833 ao_scan_speed:100000,
835 ai_range_table:&ai_ranges_60xx,
836 ao_range_table:&ao_ranges_60xx,
837 ao_range_code:ao_range_code_60xx,
838 ai_fifo: &ai_fifo_60xx,
851 ai_range_table:&ai_ranges_6052,
852 ao_range_table:&ao_ranges_6030,
853 ao_range_code:ao_range_code_6030,
854 ai_fifo: &ai_fifo_60xx,
867 ai_range_table:&ai_ranges_6052,
868 ao_range_table:&ao_ranges_6030,
869 ao_range_code:ao_range_code_6030,
870 ai_fifo: &ai_fifo_60xx,
883 ai_range_table:&ai_ranges_6052,
884 ao_range_table:&ao_ranges_6030,
885 ao_range_code:ao_range_code_6030,
886 ai_fifo: &ai_fifo_60xx,
899 ai_range_table:&ai_ranges_6052,
900 ao_range_table:&ao_ranges_6030,
901 ao_range_code:ao_range_code_6030,
902 ai_fifo: &ai_fifo_60xx,
906 name: "pci-das4020/12",
913 ao_scan_speed:0, // no hardware pacing on ao
915 ai_range_table:&ai_ranges_4020,
916 ao_range_table:&ao_ranges_4020,
917 ao_range_code:ao_range_code_4020,
918 ai_fifo: &ai_fifo_4020,
923 name: "pci-das6402/16/jr",
931 ai_range_table:&ai_ranges_64xx,
932 ai_fifo: ai_fifo_64xx,
936 name: "pci-das64/m1/16/jr",
944 ai_range_table:&ai_ranges_64xx,
945 ai_fifo: ai_fifo_64xx,
949 name: "pci-das64/m2/16/jr",
957 ai_range_table:&ai_ranges_64xx,
958 ai_fifo: ai_fifo_64xx,
962 name: "pci-das64/m3/16/jr",
970 ai_range_table:&ai_ranges_64xx,
971 ai_fifo: ai_fifo_64xx,
975 name: "pci-das64/m1/14",
983 ai_range_table:&ai_ranges_64xx,
984 ai_fifo: ai_fifo_64xx,
988 name: "pci-das64/m2/14",
996 ai_range_table:&ai_ranges_64xx,
997 ai_fifo: ai_fifo_64xx,
1001 name: "pci-das64/m3/14",
1007 ao_scan_speed:10000,
1008 layout: LAYOUT_64XX,
1009 ai_range_table:&ai_ranges_64xx,
1010 ai_fifo: ai_fifo_64xx,
1016 // Number of boards in cb_pcidas_boards
1017 static inline unsigned int num_boards(void)
1019 return sizeof(pcidas64_boards) / sizeof(struct pcidas64_board);
1022 static DEFINE_PCI_DEVICE_TABLE(pcidas64_pci_table) = {
1023 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1024 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1025 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1026 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1027 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1028 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1029 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1030 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1031 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1032 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1033 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1034 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1035 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1036 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1037 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1038 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1039 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1040 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1041 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1045 MODULE_DEVICE_TABLE(pci, pcidas64_pci_table);
1047 static inline struct pcidas64_board *board(const struct comedi_device * dev)
1049 return (struct pcidas64_board *) dev->board_ptr;
1052 static inline unsigned short se_diff_bit_6xxx(struct comedi_device * dev,
1053 int use_differential)
1055 if ((board(dev)->layout == LAYOUT_64XX && !use_differential) ||
1056 (board(dev)->layout == LAYOUT_60XX && use_differential))
1057 return ADC_SE_DIFF_BIT;
1062 struct ext_clock_info {
1063 unsigned int divisor; // master clock divisor to use for scans with external master clock
1064 unsigned int chanspec; // chanspec for master clock input when used as scan begin src
1067 /* this structure is for data unique to this hardware driver. */
1068 struct pcidas64_private {
1070 struct pci_dev *hw_dev; // pointer to board's pci_dev struct
1071 // base addresses (physical)
1072 resource_size_t plx9080_phys_iobase;
1073 resource_size_t main_phys_iobase;
1074 resource_size_t dio_counter_phys_iobase;
1075 // base addresses (ioremapped)
1076 void *plx9080_iobase;
1078 void *dio_counter_iobase;
1079 // local address (used by dma controller)
1080 uint32_t local0_iobase;
1081 uint32_t local1_iobase;
1082 volatile unsigned int ai_count; // number of analog input samples remaining
1083 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT]; // dma buffers for analog input
1084 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; // physical addresses of ai dma buffers
1085 struct plx_dma_desc *ai_dma_desc; // array of ai dma descriptors read by plx9080, allocated to get proper alignment
1086 dma_addr_t ai_dma_desc_bus_addr; // physical address of ai dma descriptor array
1087 volatile unsigned int ai_dma_index; // index of the ai dma descriptor/buffer that is currently being used
1088 uint16_t *ao_buffer[AO_DMA_RING_COUNT]; // dma buffers for analog output
1089 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; // physical addresses of ao dma buffers
1090 struct plx_dma_desc *ao_dma_desc;
1091 dma_addr_t ao_dma_desc_bus_addr;
1092 volatile unsigned int ao_dma_index; // keeps track of buffer where the next ao sample should go
1093 volatile unsigned long ao_count; // number of analog output samples remaining
1094 volatile unsigned int ao_value[2]; // remember what the analog outputs are set to, to allow readback
1095 unsigned int hw_revision; // stc chip hardware revision number
1096 volatile unsigned int intr_enable_bits; // last bits sent to INTR_ENABLE_REG register
1097 volatile uint16_t adc_control1_bits; // last bits sent to ADC_CONTROL1_REG register
1098 volatile uint16_t fifo_size_bits; // last bits sent to FIFO_SIZE_REG register
1099 volatile uint16_t hw_config_bits; // last bits sent to HW_CONFIG_REG register
1100 volatile uint16_t dac_control1_bits;
1101 volatile uint32_t plx_control_bits; // last bits written to plx9080 control register
1102 volatile uint32_t plx_intcsr_bits; // last bits written to plx interrupt control and status register
1103 volatile int calibration_source; // index of calibration source readable through ai ch0
1104 volatile uint8_t i2c_cal_range_bits; // bits written to i2c calibration/range register
1105 volatile unsigned int ext_trig_falling; // configure digital triggers to trigger on falling edge
1106 // states of various devices stored to enable read-back
1107 unsigned int ad8402_state[2];
1108 unsigned int caldac_state[8];
1109 volatile short ai_cmd_running;
1110 unsigned int ai_fifo_segment_length;
1111 struct ext_clock_info ext_clock;
1112 short ao_bounce_buffer[DAC_FIFO_SIZE];
1116 /* inline function that makes it easier to
1117 * access the private structure.
1119 static inline struct pcidas64_private *priv(struct comedi_device * dev)
1121 return dev->private;
1125 * The comedi_driver structure tells the Comedi core module
1126 * which functions to call to configure/deconfigure (attach/detach)
1127 * the board, and also about the kernel module that contains
1130 static int attach(struct comedi_device * dev, struct comedi_devconfig * it);
1131 static int detach(struct comedi_device * dev);
1132 static struct comedi_driver driver_cb_pcidas = {
1133 driver_name:"cb_pcidas64",
1139 static int ai_rinsn(struct comedi_device * dev, struct comedi_subdevice * s,
1140 struct comedi_insn * insn, unsigned int * data);
1141 static int ai_config_insn(struct comedi_device * dev, struct comedi_subdevice * s,
1142 struct comedi_insn * insn, unsigned int * data);
1143 static int ao_winsn(struct comedi_device * dev, struct comedi_subdevice * s,
1144 struct comedi_insn * insn, unsigned int * data);
1145 static int ao_readback_insn(struct comedi_device * dev, struct comedi_subdevice * s,
1146 struct comedi_insn * insn, unsigned int * data);
1147 static int ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s);
1148 static int ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
1149 struct comedi_cmd * cmd);
1150 static int ao_cmd(struct comedi_device * dev, struct comedi_subdevice * s);
1151 static int ao_inttrig(struct comedi_device * dev, struct comedi_subdevice * subdev,
1152 unsigned int trig_num);
1153 static int ao_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
1154 struct comedi_cmd * cmd);
1155 static irqreturn_t handle_interrupt(int irq, void *d PT_REGS_ARG);
1156 static int ai_cancel(struct comedi_device * dev, struct comedi_subdevice * s);
1157 static int ao_cancel(struct comedi_device * dev, struct comedi_subdevice * s);
1158 static int dio_callback(int dir, int port, int data, unsigned long arg);
1159 static int dio_callback_4020(int dir, int port, int data, unsigned long arg);
1160 static int di_rbits(struct comedi_device * dev, struct comedi_subdevice * s,
1161 struct comedi_insn * insn, unsigned int * data);
1162 static int do_wbits(struct comedi_device * dev, struct comedi_subdevice * s,
1163 struct comedi_insn * insn, unsigned int * data);
1164 static int dio_60xx_config_insn(struct comedi_device * dev, struct comedi_subdevice * s,
1165 struct comedi_insn * insn, unsigned int * data);
1166 static int dio_60xx_wbits(struct comedi_device * dev, struct comedi_subdevice * s,
1167 struct comedi_insn * insn, unsigned int * data);
1168 static int calib_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
1169 struct comedi_insn * insn, unsigned int * data);
1170 static int calib_write_insn(struct comedi_device * dev, struct comedi_subdevice * s,
1171 struct comedi_insn * insn, unsigned int * data);
1172 static int ad8402_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
1173 struct comedi_insn * insn, unsigned int * data);
1174 static void ad8402_write(struct comedi_device * dev, unsigned int channel,
1175 unsigned int value);
1176 static int ad8402_write_insn(struct comedi_device * dev, struct comedi_subdevice * s,
1177 struct comedi_insn * insn, unsigned int * data);
1178 static int eeprom_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
1179 struct comedi_insn * insn, unsigned int * data);
1180 static void check_adc_timing(struct comedi_device * dev, struct comedi_cmd * cmd);
1181 static unsigned int get_divisor(unsigned int ns, unsigned int flags);
1182 static void i2c_write(struct comedi_device * dev, unsigned int address,
1183 const uint8_t * data, unsigned int length);
1184 static void caldac_write(struct comedi_device * dev, unsigned int channel,
1185 unsigned int value);
1186 static int caldac_8800_write(struct comedi_device * dev, unsigned int address,
1188 //static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b);
1189 static int caldac_i2c_write(struct comedi_device * dev, unsigned int caldac_channel,
1190 unsigned int value);
1191 static void abort_dma(struct comedi_device * dev, unsigned int channel);
1192 static void disable_plx_interrupts(struct comedi_device * dev);
1193 static int set_ai_fifo_size(struct comedi_device * dev, unsigned int num_samples);
1194 static unsigned int ai_fifo_size(struct comedi_device * dev);
1195 static int set_ai_fifo_segment_length(struct comedi_device * dev,
1196 unsigned int num_entries);
1197 static void disable_ai_pacing(struct comedi_device * dev);
1198 static void disable_ai_interrupts(struct comedi_device * dev);
1199 static void enable_ai_interrupts(struct comedi_device * dev, const struct comedi_cmd * cmd);
1200 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags);
1201 static void load_ao_dma(struct comedi_device * dev, const struct comedi_cmd * cmd);
1203 COMEDI_PCI_INITCLEANUP(driver_cb_pcidas, pcidas64_pci_table);
1205 static unsigned int ai_range_bits_6xxx(const struct comedi_device * dev,
1206 unsigned int range_index)
1208 const struct comedi_krange *range =
1209 &board(dev)->ai_range_table->range[range_index];
1210 unsigned int bits = 0;
1212 switch (range->max) {
1241 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1244 if (range->min == 0)
1249 static unsigned int hw_revision(const struct comedi_device * dev,
1250 uint16_t hw_status_bits)
1252 if (board(dev)->layout == LAYOUT_4020)
1253 return (hw_status_bits >> 13) & 0x7;
1255 return (hw_status_bits >> 12) & 0xf;
1258 static void set_dac_range_bits(struct comedi_device * dev, volatile uint16_t * bits,
1259 unsigned int channel, unsigned int range)
1261 unsigned int code = board(dev)->ao_range_code[range];
1264 comedi_error(dev, "bug! bad channel?");
1266 comedi_error(dev, "bug! bad range code?");
1268 *bits &= ~(0x3 << (2 * channel));
1269 *bits |= code << (2 * channel);
1272 static inline int ao_cmd_is_supported(const struct pcidas64_board * board)
1274 return board->ao_nchan && board->layout != LAYOUT_4020;
1277 // initialize plx9080 chip
1278 static void init_plx9080(struct comedi_device * dev)
1281 void *plx_iobase = priv(dev)->plx9080_iobase;
1283 priv(dev)->plx_control_bits =
1284 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG);
1287 DEBUG_PRINT(" plx interrupt status 0x%x\n",
1288 readl(plx_iobase + PLX_INTRCS_REG));
1289 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1290 DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits);
1291 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1292 readl(plx_iobase + PLX_MARB_REG));
1293 DEBUG_PRINT(" plx region0 reg 0x%x\n",
1294 readl(plx_iobase + PLX_REGION0_REG));
1295 DEBUG_PRINT(" plx region1 reg 0x%x\n",
1296 readl(plx_iobase + PLX_REGION1_REG));
1298 DEBUG_PRINT(" plx revision 0x%x\n",
1299 readl(plx_iobase + PLX_REVISION_REG));
1300 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1301 readl(plx_iobase + PLX_DMA0_MODE_REG));
1302 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1303 readl(plx_iobase + PLX_DMA1_MODE_REG));
1304 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1305 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1306 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1307 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1308 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1309 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1310 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1311 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1312 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1313 readb(plx_iobase + PLX_DMA0_CS_REG));
1314 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1315 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1316 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1319 bits = BIGEND_DMA0 | BIGEND_DMA1;
1323 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
1325 disable_plx_interrupts(dev);
1330 // configure dma0 mode
1332 // enable ready input, not sure if this is necessary
1333 bits |= PLX_DMA_EN_READYIN_BIT;
1334 // enable bterm, not sure if this is necessary
1335 bits |= PLX_EN_BTERM_BIT;
1336 // enable dma chaining
1337 bits |= PLX_EN_CHAIN_BIT;
1338 // enable interrupt on dma done (probably don't need this, since chain never finishes)
1339 bits |= PLX_EN_DMA_DONE_INTR_BIT;
1340 // don't increment local address during transfers (we are transferring from a fixed fifo register)
1341 bits |= PLX_LOCAL_ADDR_CONST_BIT;
1342 // route dma interrupt to pci bus
1343 bits |= PLX_DMA_INTR_PCI_BIT;
1344 // enable demand mode
1345 bits |= PLX_DEMAND_MODE_BIT;
1346 // enable local burst mode
1347 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1348 // 4020 uses 32 bit dma
1349 if (board(dev)->layout == LAYOUT_4020) {
1350 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1351 } else { // localspace0 bus is 16 bits wide
1352 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1354 writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1355 if (ao_cmd_is_supported(board(dev)))
1356 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1358 // enable interrupts on plx 9080
1359 priv(dev)->plx_intcsr_bits |=
1360 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1361 ICS_DMA0_E | ICS_DMA1_E;
1362 writel(priv(dev)->plx_intcsr_bits,
1363 priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1366 /* Allocate and initialize the subdevice structures.
1368 static int setup_subdevices(struct comedi_device * dev)
1370 struct comedi_subdevice *s;
1371 void *dio_8255_iobase;
1374 if (alloc_subdevices(dev, 10) < 0)
1377 s = dev->subdevices + 0;
1378 /* analog input subdevice */
1379 dev->read_subdev = s;
1380 s->type = COMEDI_SUBD_AI;
1381 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
1382 if (board(dev)->layout == LAYOUT_60XX)
1383 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
1384 else if (board(dev)->layout == LAYOUT_64XX)
1385 s->subdev_flags |= SDF_DIFF;
1386 /* XXX Number of inputs in differential mode is ignored */
1387 s->n_chan = board(dev)->ai_se_chans;
1388 s->len_chanlist = 0x2000;
1389 s->maxdata = (1 << board(dev)->ai_bits) - 1;
1390 s->range_table = board(dev)->ai_range_table;
1391 s->insn_read = ai_rinsn;
1392 s->insn_config = ai_config_insn;
1394 s->do_cmdtest = ai_cmdtest;
1395 s->cancel = ai_cancel;
1396 if (board(dev)->layout == LAYOUT_4020) {
1399 // set adc to read from inputs (not internal calibration sources)
1400 priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4);
1401 // set channels to +-5 volt input ranges
1402 for (i = 0; i < s->n_chan; i++)
1403 priv(dev)->i2c_cal_range_bits |= attenuate_bit(i);
1404 data = priv(dev)->i2c_cal_range_bits;
1405 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
1408 /* analog output subdevice */
1409 s = dev->subdevices + 1;
1410 if (board(dev)->ao_nchan) {
1411 s->type = COMEDI_SUBD_AO;
1413 SDF_READABLE | SDF_WRITABLE | SDF_GROUND |
1415 s->n_chan = board(dev)->ao_nchan;
1416 s->maxdata = (1 << board(dev)->ao_bits) - 1;
1417 s->range_table = board(dev)->ao_range_table;
1418 s->insn_read = ao_readback_insn;
1419 s->insn_write = ao_winsn;
1420 if (ao_cmd_is_supported(board(dev))) {
1421 dev->write_subdev = s;
1422 s->do_cmdtest = ao_cmdtest;
1424 s->len_chanlist = board(dev)->ao_nchan;
1425 s->cancel = ao_cancel;
1428 s->type = COMEDI_SUBD_UNUSED;
1432 s = dev->subdevices + 2;
1433 if (board(dev)->layout == LAYOUT_64XX) {
1434 s->type = COMEDI_SUBD_DI;
1435 s->subdev_flags = SDF_READABLE;
1438 s->range_table = &range_digital;
1439 s->insn_bits = di_rbits;
1441 s->type = COMEDI_SUBD_UNUSED;
1444 if (board(dev)->layout == LAYOUT_64XX) {
1445 s = dev->subdevices + 3;
1446 s->type = COMEDI_SUBD_DO;
1447 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1450 s->range_table = &range_digital;
1451 s->insn_bits = do_wbits;
1453 s->type = COMEDI_SUBD_UNUSED;
1456 s = dev->subdevices + 4;
1457 if (board(dev)->has_8255) {
1458 if (board(dev)->layout == LAYOUT_4020) {
1460 priv(dev)->main_iobase + I8255_4020_REG;
1461 subdev_8255_init(dev, s, dio_callback_4020,
1462 (unsigned long)dio_8255_iobase);
1465 priv(dev)->dio_counter_iobase + DIO_8255_OFFSET;
1466 subdev_8255_init(dev, s, dio_callback,
1467 (unsigned long)dio_8255_iobase);
1470 s->type = COMEDI_SUBD_UNUSED;
1472 // 8 channel dio for 60xx
1473 s = dev->subdevices + 5;
1474 if (board(dev)->layout == LAYOUT_60XX) {
1475 s->type = COMEDI_SUBD_DIO;
1476 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1479 s->range_table = &range_digital;
1480 s->insn_config = dio_60xx_config_insn;
1481 s->insn_bits = dio_60xx_wbits;
1483 s->type = COMEDI_SUBD_UNUSED;
1486 s = dev->subdevices + 6;
1487 s->type = COMEDI_SUBD_CALIB;
1488 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1490 if (board(dev)->layout == LAYOUT_4020)
1494 s->insn_read = calib_read_insn;
1495 s->insn_write = calib_write_insn;
1496 for (i = 0; i < s->n_chan; i++)
1497 caldac_write(dev, i, s->maxdata / 2);
1499 // 2 channel ad8402 potentiometer
1500 s = dev->subdevices + 7;
1501 if (board(dev)->layout == LAYOUT_64XX) {
1502 s->type = COMEDI_SUBD_CALIB;
1503 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1505 s->insn_read = ad8402_read_insn;
1506 s->insn_write = ad8402_write_insn;
1508 for (i = 0; i < s->n_chan; i++)
1509 ad8402_write(dev, i, s->maxdata / 2);
1511 s->type = COMEDI_SUBD_UNUSED;
1513 //serial EEPROM, if present
1514 s = dev->subdevices + 8;
1515 if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
1516 s->type = COMEDI_SUBD_MEMORY;
1517 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
1519 s->maxdata = 0xffff;
1520 s->insn_read = eeprom_read_insn;
1522 s->type = COMEDI_SUBD_UNUSED;
1524 // user counter subd XXX
1525 s = dev->subdevices + 9;
1526 s->type = COMEDI_SUBD_UNUSED;
1531 static void disable_plx_interrupts(struct comedi_device * dev)
1533 priv(dev)->plx_intcsr_bits = 0;
1534 writel(priv(dev)->plx_intcsr_bits,
1535 priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1538 static void init_stc_registers(struct comedi_device * dev)
1541 unsigned long flags;
1543 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1545 // bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX
1547 priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1548 writew(priv(dev)->adc_control1_bits,
1549 priv(dev)->main_iobase + ADC_CONTROL1_REG);
1551 // 6402/16 manual says this register must be initialized to 0xff?
1552 writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1554 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1555 if (board(dev)->layout == LAYOUT_4020)
1556 bits |= INTERNAL_CLOCK_4020_BITS;
1557 priv(dev)->hw_config_bits |= bits;
1558 writew(priv(dev)->hw_config_bits,
1559 priv(dev)->main_iobase + HW_CONFIG_REG);
1561 writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG);
1562 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1564 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1566 // set fifos to maximum size
1567 priv(dev)->fifo_size_bits |= DAC_FIFO_BITS;
1568 set_ai_fifo_segment_length(dev,
1569 board(dev)->ai_fifo->max_segment_length);
1571 priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1572 priv(dev)->intr_enable_bits = /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1573 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1574 writew(priv(dev)->intr_enable_bits,
1575 priv(dev)->main_iobase + INTR_ENABLE_REG);
1577 disable_ai_pacing(dev);
1580 int alloc_and_init_dma_members(struct comedi_device * dev)
1584 // alocate pci dma buffers
1585 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1586 priv(dev)->ai_buffer[i] =
1587 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
1588 &priv(dev)->ai_buffer_bus_addr[i]);
1589 if (priv(dev)->ai_buffer[i] == NULL) {
1593 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1594 if (ao_cmd_is_supported(board(dev))) {
1595 priv(dev)->ao_buffer[i] =
1596 pci_alloc_consistent(priv(dev)->hw_dev,
1598 &priv(dev)->ao_buffer_bus_addr[i]);
1599 if (priv(dev)->ao_buffer[i] == NULL) {
1604 // allocate dma descriptors
1605 priv(dev)->ai_dma_desc =
1606 pci_alloc_consistent(priv(dev)->hw_dev,
1607 sizeof(struct plx_dma_desc) * ai_dma_ring_count(board(dev)),
1608 &priv(dev)->ai_dma_desc_bus_addr);
1609 if (priv(dev)->ai_dma_desc == NULL) {
1612 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1613 priv(dev)->ai_dma_desc_bus_addr);
1614 if (ao_cmd_is_supported(board(dev))) {
1615 priv(dev)->ao_dma_desc =
1616 pci_alloc_consistent(priv(dev)->hw_dev,
1617 sizeof(struct plx_dma_desc) * AO_DMA_RING_COUNT,
1618 &priv(dev)->ao_dma_desc_bus_addr);
1619 if (priv(dev)->ao_dma_desc == NULL) {
1622 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1623 priv(dev)->ao_dma_desc_bus_addr);
1625 // initialize dma descriptors
1626 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1627 priv(dev)->ai_dma_desc[i].pci_start_addr =
1628 cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]);
1629 if (board(dev)->layout == LAYOUT_4020)
1630 priv(dev)->ai_dma_desc[i].local_start_addr =
1631 cpu_to_le32(priv(dev)->local1_iobase +
1634 priv(dev)->ai_dma_desc[i].local_start_addr =
1635 cpu_to_le32(priv(dev)->local0_iobase +
1637 priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1638 priv(dev)->ai_dma_desc[i].next =
1639 cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i +
1641 ai_dma_ring_count(board(dev))) *
1643 ai_dma_desc[0])) | PLX_DESC_IN_PCI_BIT |
1644 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI);
1646 if (ao_cmd_is_supported(board(dev))) {
1647 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1648 priv(dev)->ao_dma_desc[i].pci_start_addr =
1649 cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]);
1650 priv(dev)->ao_dma_desc[i].local_start_addr =
1651 cpu_to_le32(priv(dev)->local0_iobase +
1653 priv(dev)->ao_dma_desc[i].transfer_size =
1655 priv(dev)->ao_dma_desc[i].next =
1656 cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr +
1657 ((i + 1) % (AO_DMA_RING_COUNT)) *
1660 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
1666 static inline void warn_external_queue(struct comedi_device * dev)
1669 "AO command and AI external channel queue cannot be used simultaneously.");
1671 "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1675 * Attach is called by the Comedi core to configure the driver
1676 * for a particular board.
1678 static int attach(struct comedi_device *dev, struct comedi_devconfig *it)
1680 struct pci_dev *pcidev;
1682 uint32_t local_range, local_decode;
1685 printk("comedi%d: cb_pcidas64\n", dev->minor);
1688 * Allocate the private structure area.
1690 if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0)
1694 * Probe the device to determine what device in the series it is.
1697 for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
1699 pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) {
1700 // is it not a computer boards card?
1701 if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS)
1703 // loop through cards supported by this driver
1704 for (index = 0; index < num_boards(); index++) {
1705 if (pcidas64_boards[index].device_id != pcidev->device)
1707 // was a particular bus/slot requested?
1708 if (it->options[0] || it->options[1]) {
1709 // are we on the wrong bus/slot?
1710 if (pcidev->bus->number != it->options[0] ||
1711 PCI_SLOT(pcidev->devfn) !=
1716 priv(dev)->hw_dev = pcidev;
1717 dev->board_ptr = pcidas64_boards + index;
1724 if (dev->board_ptr == NULL) {
1725 printk("No supported ComputerBoards/MeasurementComputing card found\n");
1729 printk("Found %s on bus %i, slot %i\n", board(dev)->name,
1730 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
1732 if (comedi_pci_enable(pcidev, driver_cb_pcidas.driver_name)) {
1734 " failed to enable PCI device and request regions\n");
1737 pci_set_master(pcidev);
1739 //Initialize dev->board_name
1740 dev->board_name = board(dev)->name;
1742 priv(dev)->plx9080_phys_iobase =
1743 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
1744 priv(dev)->main_phys_iobase =
1745 pci_resource_start(pcidev, MAIN_BADDRINDEX);
1746 priv(dev)->dio_counter_phys_iobase =
1747 pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
1749 // remap, won't work with 2.0 kernels but who cares
1750 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
1751 pci_resource_len(pcidev, PLX9080_BADDRINDEX));
1752 priv(dev)->main_iobase = ioremap(priv(dev)->main_phys_iobase,
1753 pci_resource_len(pcidev, MAIN_BADDRINDEX));
1754 priv(dev)->dio_counter_iobase =
1755 ioremap(priv(dev)->dio_counter_phys_iobase,
1756 pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
1758 if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase
1759 || !priv(dev)->dio_counter_iobase) {
1760 printk(" failed to remap io memory\n");
1764 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
1765 DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase);
1766 DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1767 priv(dev)->dio_counter_iobase);
1769 // figure out what local addresses are
1771 readl(priv(dev)->plx9080_iobase +
1772 PLX_LAS0RNG_REG) & LRNG_MEM_MASK;
1774 readl(priv(dev)->plx9080_iobase +
1775 PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK;
1776 priv(dev)->local0_iobase =
1777 ((uint32_t) priv(dev)->
1778 main_phys_iobase & ~local_range) | local_decode;
1780 readl(priv(dev)->plx9080_iobase +
1781 PLX_LAS1RNG_REG) & LRNG_MEM_MASK;
1783 readl(priv(dev)->plx9080_iobase +
1784 PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK;
1785 priv(dev)->local1_iobase =
1786 ((uint32_t) priv(dev)->
1787 dio_counter_phys_iobase & ~local_range) | local_decode;
1789 DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase);
1790 DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase);
1792 retval = alloc_and_init_dma_members(dev);
1796 priv(dev)->hw_revision =
1797 hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG));
1798 printk(" stc hardware revision %i\n", priv(dev)->hw_revision);
1800 init_stc_registers(dev);
1802 if (comedi_request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
1803 "cb_pcidas64", dev)) {
1804 printk(" unable to allocate irq %u\n", pcidev->irq);
1807 dev->irq = pcidev->irq;
1808 printk(" irq %u\n", dev->irq);
1810 retval = setup_subdevices(dev);
1819 * _detach is called to deconfigure a device. It should deallocate
1821 * This function is also called when _attach() fails, so it should be
1822 * careful not to release resources that were not necessarily
1823 * allocated by _attach(). dev->private and dev->subdevices are
1824 * deallocated automatically by the core.
1826 static int detach(struct comedi_device * dev)
1830 printk("comedi%d: cb_pcidas: remove\n", dev->minor);
1833 comedi_free_irq(dev->irq, dev);
1835 if (priv(dev)->hw_dev) {
1836 if (priv(dev)->plx9080_iobase) {
1837 disable_plx_interrupts(dev);
1838 iounmap((void *)priv(dev)->plx9080_iobase);
1840 if (priv(dev)->main_iobase)
1841 iounmap((void *)priv(dev)->main_iobase);
1842 if (priv(dev)->dio_counter_iobase)
1843 iounmap((void *)priv(dev)->dio_counter_iobase);
1844 // free pci dma buffers
1845 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1846 if (priv(dev)->ai_buffer[i])
1847 pci_free_consistent(priv(dev)->hw_dev,
1849 priv(dev)->ai_buffer[i],
1851 ai_buffer_bus_addr[i]);
1853 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1854 if (priv(dev)->ao_buffer[i])
1855 pci_free_consistent(priv(dev)->hw_dev,
1857 priv(dev)->ao_buffer[i],
1859 ao_buffer_bus_addr[i]);
1861 // free dma descriptors
1862 if (priv(dev)->ai_dma_desc)
1863 pci_free_consistent(priv(dev)->hw_dev,
1864 sizeof(struct plx_dma_desc) *
1865 ai_dma_ring_count(board(dev)),
1866 priv(dev)->ai_dma_desc,
1867 priv(dev)->ai_dma_desc_bus_addr);
1868 if (priv(dev)->ao_dma_desc)
1869 pci_free_consistent(priv(dev)->hw_dev,
1870 sizeof(struct plx_dma_desc) *
1872 priv(dev)->ao_dma_desc,
1873 priv(dev)->ao_dma_desc_bus_addr);
1874 if (priv(dev)->main_phys_iobase) {
1875 comedi_pci_disable(priv(dev)->hw_dev);
1877 pci_dev_put(priv(dev)->hw_dev);
1880 if (dev->subdevices)
1881 subdev_8255_cleanup(dev, dev->subdevices + 4);
1886 static int ai_rinsn(struct comedi_device * dev, struct comedi_subdevice * s,
1887 struct comedi_insn * insn, unsigned int * data)
1889 unsigned int bits = 0, n, i;
1890 unsigned int channel, range, aref;
1891 unsigned long flags;
1892 static const int timeout = 100;
1894 DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1895 channel = CR_CHAN(insn->chanspec);
1896 range = CR_RANGE(insn->chanspec);
1897 aref = CR_AREF(insn->chanspec);
1899 // disable card's analog input interrupt sources and pacing
1900 // 4020 generates dac done interrupts even though they are disabled
1901 disable_ai_pacing(dev);
1903 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1904 if (insn->chanspec & CR_ALT_FILTER)
1905 priv(dev)->adc_control1_bits |= ADC_DITHER_BIT;
1907 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
1908 writew(priv(dev)->adc_control1_bits,
1909 priv(dev)->main_iobase + ADC_CONTROL1_REG);
1910 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1912 if (board(dev)->layout != LAYOUT_4020) {
1913 // use internal queue
1914 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
1915 writew(priv(dev)->hw_config_bits,
1916 priv(dev)->main_iobase + HW_CONFIG_REG);
1918 // ALT_SOURCE is internal calibration reference
1919 if (insn->chanspec & CR_ALT_SOURCE) {
1920 unsigned int cal_en_bit;
1922 DEBUG_PRINT("reading calibration source\n");
1923 if (board(dev)->layout == LAYOUT_60XX)
1924 cal_en_bit = CAL_EN_60XX_BIT;
1926 cal_en_bit = CAL_EN_64XX_BIT;
1927 // select internal reference source to connect to channel 0
1928 writew(cal_en_bit | adc_src_bits(priv(dev)->
1929 calibration_source),
1930 priv(dev)->main_iobase + CALIBRATION_REG);
1932 // make sure internal calibration source is turned off
1933 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1935 // load internal queue
1938 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1939 // set single-ended / differential
1940 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1941 if (aref == AREF_COMMON)
1942 bits |= ADC_COMMON_BIT;
1943 bits |= adc_chan_bits(channel);
1945 writew(adc_chan_bits(channel),
1946 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
1947 // set start channel, and rest of settings
1948 writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
1950 uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits;
1952 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1953 if (insn->chanspec & CR_ALT_SOURCE) {
1954 DEBUG_PRINT("reading calibration source\n");
1955 priv(dev)->i2c_cal_range_bits |=
1956 adc_src_4020_bits(priv(dev)->
1957 calibration_source);
1958 } else { //select BNC inputs
1959 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
1963 priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel);
1965 priv(dev)->i2c_cal_range_bits &=
1966 ~attenuate_bit(channel);
1967 // update calibration/range i2c register only if necessary, as it is very slow
1968 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
1969 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
1970 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1974 /* 4020 manual asks that sample interval register to be set before writing to convert register.
1975 * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
1977 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1979 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1982 for (n = 0; n < insn->n; n++) {
1984 // clear adc buffer (inside loop for 4020 sake)
1985 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
1987 /* trigger conversion, bits sent only matter for 4020 */
1988 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1989 priv(dev)->main_iobase + ADC_CONVERT_REG);
1992 for (i = 0; i < timeout; i++) {
1993 bits = readw(priv(dev)->main_iobase + HW_STATUS_REG);
1994 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1995 if (board(dev)->layout == LAYOUT_4020) {
1996 if (readw(priv(dev)->main_iobase +
1997 ADC_WRITE_PNTR_REG))
2000 if (pipe_full_bits(bits))
2005 DEBUG_PRINT(" looped %i times waiting for data\n", i);
2007 comedi_error(dev, " analog input read insn timed out");
2008 rt_printk(" status 0x%x\n", bits);
2011 if (board(dev)->layout == LAYOUT_4020)
2013 readl(priv(dev)->dio_counter_iobase +
2014 ADC_FIFO_REG) & 0xffff;
2017 readw(priv(dev)->main_iobase + PIPE1_READ_REG);
2023 static int ai_config_calibration_source(struct comedi_device * dev, unsigned int * data)
2025 unsigned int source = data[1];
2026 int num_calibration_sources;
2028 if (board(dev)->layout == LAYOUT_60XX)
2029 num_calibration_sources = 16;
2031 num_calibration_sources = 8;
2032 if (source >= num_calibration_sources) {
2033 printk("invalid calibration source: %i\n", source);
2037 DEBUG_PRINT("setting calibration source to %i\n", source);
2038 priv(dev)->calibration_source = source;
2043 static int ai_config_block_size(struct comedi_device * dev, unsigned int * data)
2046 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
2047 unsigned int block_size, requested_block_size;
2050 requested_block_size = data[1];
2052 if (requested_block_size) {
2054 requested_block_size * fifo->num_segments /
2057 retval = set_ai_fifo_size(dev, fifo_size);
2063 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
2065 data[1] = block_size;
2070 static int ai_config_master_clock_4020(struct comedi_device * dev, unsigned int * data)
2072 unsigned int divisor = data[4];
2081 case COMEDI_EV_SCAN_BEGIN:
2082 priv(dev)->ext_clock.divisor = divisor;
2083 priv(dev)->ext_clock.chanspec = data[2];
2092 return retval ? retval : 5;
2095 // XXX could add support for 60xx series
2096 static int ai_config_master_clock(struct comedi_device * dev, unsigned int * data)
2099 switch (board(dev)->layout) {
2101 return ai_config_master_clock_4020(dev, data);
2111 static int ai_config_insn(struct comedi_device * dev, struct comedi_subdevice * s,
2112 struct comedi_insn * insn, unsigned int * data)
2117 case INSN_CONFIG_ALT_SOURCE:
2118 return ai_config_calibration_source(dev, data);
2120 case INSN_CONFIG_BLOCK_SIZE:
2121 return ai_config_block_size(dev, data);
2123 case INSN_CONFIG_TIMER_1:
2124 return ai_config_master_clock(dev, data);
2133 static int ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
2134 struct comedi_cmd * cmd)
2138 unsigned int tmp_arg, tmp_arg2;
2141 unsigned int triggers;
2143 /* step 1: make sure trigger sources are trivially valid */
2145 tmp = cmd->start_src;
2146 cmd->start_src &= TRIG_NOW | TRIG_EXT;
2147 if (!cmd->start_src || tmp != cmd->start_src)
2150 tmp = cmd->scan_begin_src;
2151 triggers = TRIG_TIMER;
2152 if (board(dev)->layout == LAYOUT_4020)
2153 triggers |= TRIG_OTHER;
2155 triggers |= TRIG_FOLLOW;
2156 cmd->scan_begin_src &= triggers;
2157 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2160 tmp = cmd->convert_src;
2161 triggers = TRIG_TIMER;
2162 if (board(dev)->layout == LAYOUT_4020)
2163 triggers |= TRIG_NOW;
2165 triggers |= TRIG_EXT;
2166 cmd->convert_src &= triggers;
2167 if (!cmd->convert_src || tmp != cmd->convert_src)
2170 tmp = cmd->scan_end_src;
2171 cmd->scan_end_src &= TRIG_COUNT;
2172 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2175 tmp = cmd->stop_src;
2176 cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE;
2177 if (!cmd->stop_src || tmp != cmd->stop_src)
2183 /* step 2: make sure trigger sources are unique and mutually compatible */
2186 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
2188 if (cmd->scan_begin_src != TRIG_TIMER &&
2189 cmd->scan_begin_src != TRIG_OTHER &&
2190 cmd->scan_begin_src != TRIG_FOLLOW)
2192 if (cmd->convert_src != TRIG_TIMER &&
2193 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2195 if (cmd->stop_src != TRIG_COUNT &&
2196 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2199 // compatibility check
2200 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2202 if (cmd->stop_src != TRIG_COUNT &&
2203 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2209 /* step 3: make sure arguments are trivially compatible */
2211 if (cmd->convert_src == TRIG_TIMER) {
2212 if (board(dev)->layout == LAYOUT_4020) {
2213 if (cmd->convert_arg) {
2214 cmd->convert_arg = 0;
2218 if (cmd->convert_arg < board(dev)->ai_speed) {
2219 cmd->convert_arg = board(dev)->ai_speed;
2222 if (cmd->scan_begin_src == TRIG_TIMER) {
2223 // if scans are timed faster than conversion rate allows
2224 if (cmd->convert_arg * cmd->chanlist_len >
2225 cmd->scan_begin_arg) {
2226 cmd->scan_begin_arg =
2235 if (!cmd->chanlist_len) {
2236 cmd->chanlist_len = 1;
2239 if (cmd->scan_end_arg != cmd->chanlist_len) {
2240 cmd->scan_end_arg = cmd->chanlist_len;
2244 switch (cmd->stop_src) {
2248 if (!cmd->stop_arg) {
2254 if (cmd->stop_arg != 0) {
2266 /* step 4: fix up any arguments */
2268 if (cmd->convert_src == TRIG_TIMER) {
2269 tmp_arg = cmd->convert_arg;
2270 tmp_arg2 = cmd->scan_begin_arg;
2271 check_adc_timing(dev, cmd);
2272 if (tmp_arg != cmd->convert_arg)
2274 if (tmp_arg2 != cmd->scan_begin_arg)
2281 // make sure user is doesn't change analog reference mid chanlist
2282 if (cmd->chanlist) {
2283 aref = CR_AREF(cmd->chanlist[0]);
2284 for (i = 1; i < cmd->chanlist_len; i++) {
2285 if (aref != CR_AREF(cmd->chanlist[i])) {
2287 "all elements in chanlist must use the same analog reference");
2292 // check 4020 chanlist
2293 if (board(dev)->layout == LAYOUT_4020) {
2294 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2295 for (i = 1; i < cmd->chanlist_len; i++) {
2296 if (CR_CHAN(cmd->chanlist[i]) !=
2297 first_channel + i) {
2299 "chanlist must use consecutive channels");
2304 if (cmd->chanlist_len == 3) {
2306 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2318 static int use_hw_sample_counter(struct comedi_cmd * cmd)
2320 // disable for now until I work out a race
2323 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2329 static void setup_sample_counters(struct comedi_device * dev, struct comedi_cmd * cmd)
2331 if (cmd->stop_src == TRIG_COUNT) {
2332 // set software count
2333 priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len;
2335 // load hardware conversion counter
2336 if (use_hw_sample_counter(cmd)) {
2337 writew(cmd->stop_arg & 0xffff,
2338 priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2339 writew((cmd->stop_arg >> 16) & 0xff,
2340 priv(dev)->main_iobase + ADC_COUNT_UPPER_REG);
2342 writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2346 static inline unsigned int dma_transfer_size(struct comedi_device * dev)
2348 unsigned int num_samples;
2351 priv(dev)->ai_fifo_segment_length *
2352 board(dev)->ai_fifo->sample_packing_ratio;
2353 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2354 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2359 static void disable_ai_pacing(struct comedi_device * dev)
2361 unsigned long flags;
2363 disable_ai_interrupts(dev);
2365 comedi_spin_lock_irqsave(&dev->spinlock, flags);
2366 priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT;
2367 writew(priv(dev)->adc_control1_bits,
2368 priv(dev)->main_iobase + ADC_CONTROL1_REG);
2369 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
2371 /* disable pacing, triggering, etc */
2372 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
2373 priv(dev)->main_iobase + ADC_CONTROL0_REG);
2376 static void disable_ai_interrupts(struct comedi_device * dev)
2378 unsigned long flags;
2380 comedi_spin_lock_irqsave(&dev->spinlock, flags);
2381 priv(dev)->intr_enable_bits &=
2382 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
2383 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
2384 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
2385 writew(priv(dev)->intr_enable_bits,
2386 priv(dev)->main_iobase + INTR_ENABLE_REG);
2387 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
2389 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2392 static void enable_ai_interrupts(struct comedi_device * dev, const struct comedi_cmd * cmd)
2395 unsigned long flags;
2397 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
2398 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
2399 // Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set.
2400 if (cmd->flags & TRIG_WAKE_EOS) {
2401 // 4020 doesn't support pio transfers except for fifo dregs
2402 if (board(dev)->layout != LAYOUT_4020)
2403 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
2405 comedi_spin_lock_irqsave(&dev->spinlock, flags);
2406 priv(dev)->intr_enable_bits |= bits;
2407 writew(priv(dev)->intr_enable_bits,
2408 priv(dev)->main_iobase + INTR_ENABLE_REG);
2409 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2410 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
2413 static uint32_t ai_convert_counter_6xxx(const struct comedi_device * dev,
2414 const struct comedi_cmd * cmd)
2416 // supposed to load counter with desired divisor minus 3
2417 return cmd->convert_arg / TIMER_BASE - 3;
2420 static uint32_t ai_scan_counter_6xxx(struct comedi_device * dev, struct comedi_cmd * cmd)
2423 // figure out how long we need to delay at end of scan
2424 switch (cmd->scan_begin_src) {
2426 count = (cmd->scan_begin_arg -
2427 (cmd->convert_arg * (cmd->chanlist_len - 1)))
2431 count = cmd->convert_arg / TIMER_BASE;
2440 static uint32_t ai_convert_counter_4020(struct comedi_device * dev, struct comedi_cmd * cmd)
2442 unsigned int divisor;
2444 switch (cmd->scan_begin_src) {
2446 divisor = cmd->scan_begin_arg / TIMER_BASE;
2449 divisor = priv(dev)->ext_clock.divisor;
2451 default: // should never happen
2452 comedi_error(dev, "bug! failed to set ai pacing!");
2457 // supposed to load counter with desired divisor minus 2 for 4020
2461 static void select_master_clock_4020(struct comedi_device * dev,
2462 const struct comedi_cmd * cmd)
2464 // select internal/external master clock
2465 priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2466 if (cmd->scan_begin_src == TRIG_OTHER) {
2467 int chanspec = priv(dev)->ext_clock.chanspec;
2469 if (CR_CHAN(chanspec))
2470 priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS;
2472 priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS;
2474 priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2476 writew(priv(dev)->hw_config_bits,
2477 priv(dev)->main_iobase + HW_CONFIG_REG);
2480 static void select_master_clock(struct comedi_device * dev, const struct comedi_cmd * cmd)
2482 switch (board(dev)->layout) {
2484 select_master_clock_4020(dev, cmd);
2491 static inline void dma_start_sync(struct comedi_device * dev, unsigned int channel)
2493 unsigned long flags;
2495 // spinlock for plx dma control/status reg
2496 comedi_spin_lock_irqsave(&dev->spinlock, flags);
2498 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2499 PLX_CLEAR_DMA_INTR_BIT,
2500 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2502 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2503 PLX_CLEAR_DMA_INTR_BIT,
2504 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
2505 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
2508 static void set_ai_pacing(struct comedi_device * dev, struct comedi_cmd * cmd)
2510 uint32_t convert_counter = 0, scan_counter = 0;
2512 check_adc_timing(dev, cmd);
2514 select_master_clock(dev, cmd);
2516 if (board(dev)->layout == LAYOUT_4020) {
2517 convert_counter = ai_convert_counter_4020(dev, cmd);
2519 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2520 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2523 // load lower 16 bits of convert interval
2524 writew(convert_counter & 0xffff,
2525 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2526 DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2527 // load upper 8 bits of convert interval
2528 writew((convert_counter >> 16) & 0xff,
2529 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2530 // load lower 16 bits of scan delay
2531 writew(scan_counter & 0xffff,
2532 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2533 // load upper 8 bits of scan delay
2534 writew((scan_counter >> 16) & 0xff,
2535 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2536 DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2539 static int use_internal_queue_6xxx(const struct comedi_cmd * cmd)
2542 for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2543 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2544 CR_CHAN(cmd->chanlist[i]) + 1)
2546 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2547 CR_RANGE(cmd->chanlist[i]))
2549 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2555 static int setup_channel_queue(struct comedi_device * dev, const struct comedi_cmd * cmd)
2557 unsigned short bits;
2560 if (board(dev)->layout != LAYOUT_4020) {
2561 if (use_internal_queue_6xxx(cmd)) {
2562 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
2563 writew(priv(dev)->hw_config_bits,
2564 priv(dev)->main_iobase + HW_CONFIG_REG);
2567 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2569 bits |= ai_range_bits_6xxx(dev,
2570 CR_RANGE(cmd->chanlist[0]));
2571 // set single-ended / differential
2572 bits |= se_diff_bit_6xxx(dev,
2573 CR_AREF(cmd->chanlist[0]) == AREF_DIFF);
2574 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2575 bits |= ADC_COMMON_BIT;
2577 writew(adc_chan_bits(CR_CHAN(cmd->chanlist[cmd->
2578 chanlist_len - 1])),
2579 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2580 // set start channel, and rest of settings
2582 priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2584 // use external queue
2585 if (dev->write_subdev && dev->write_subdev->busy) {
2586 warn_external_queue(dev);
2589 priv(dev)->hw_config_bits |= EXT_QUEUE_BIT;
2590 writew(priv(dev)->hw_config_bits,
2591 priv(dev)->main_iobase + HW_CONFIG_REG);
2592 // clear DAC buffer to prevent weird interactions
2594 priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
2595 // clear queue pointer
2596 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2597 // load external queue
2598 for (i = 0; i < cmd->chanlist_len; i++) {
2601 bits |= adc_chan_bits(CR_CHAN(cmd->
2604 bits |= ai_range_bits_6xxx(dev,
2605 CR_RANGE(cmd->chanlist[i]));
2606 // set single-ended / differential
2607 bits |= se_diff_bit_6xxx(dev,
2608 CR_AREF(cmd->chanlist[i]) == AREF_DIFF);
2609 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2610 bits |= ADC_COMMON_BIT;
2611 // mark end of queue
2612 if (i == cmd->chanlist_len - 1)
2613 bits |= QUEUE_EOSCAN_BIT |
2616 priv(dev)->main_iobase +
2617 ADC_QUEUE_FIFO_REG);
2619 ("wrote 0x%x to external channel queue\n",
2622 /* doing a queue clear is not specified in board docs,
2623 * but required for reliable operation */
2624 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2625 // prime queue holding register
2626 writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2629 unsigned short old_cal_range_bits =
2630 priv(dev)->i2c_cal_range_bits;
2632 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2634 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2636 for (i = 0; i < cmd->chanlist_len; i++) {
2637 unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2638 unsigned int range = CR_RANGE(cmd->chanlist[i]);
2641 priv(dev)->i2c_cal_range_bits |=
2642 attenuate_bit(channel);
2644 priv(dev)->i2c_cal_range_bits &=
2645 ~attenuate_bit(channel);
2647 // update calibration/range i2c register only if necessary, as it is very slow
2648 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2649 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2650 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2657 static inline void load_first_dma_descriptor(struct comedi_device * dev,
2658 unsigned int dma_channel, unsigned int descriptor_bits)
2660 /* The transfer size, pci address, and local address registers
2661 * are supposedly unused during chained dma,
2662 * but I have found that left over values from last operation
2663 * occasionally cause problems with transfer of first dma
2664 * block. Initializing them to zero seems to fix the problem. */
2667 priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2668 writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2670 priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2671 writel(descriptor_bits,
2672 priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2675 priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2676 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2678 priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2679 writel(descriptor_bits,
2680 priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2684 static int ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
2686 struct comedi_async *async = s->async;
2687 struct comedi_cmd *cmd = &async->cmd;
2690 unsigned long flags;
2693 disable_ai_pacing(dev);
2696 retval = setup_channel_queue(dev, cmd);
2700 // make sure internal calibration source is turned off
2701 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
2703 set_ai_pacing(dev, cmd);
2705 setup_sample_counters(dev, cmd);
2707 enable_ai_interrupts(dev, cmd);
2709 comedi_spin_lock_irqsave(&dev->spinlock, flags);
2710 /* set mode, allow conversions through software gate */
2711 priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT;
2712 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
2713 if (board(dev)->layout != LAYOUT_4020) {
2714 priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK;
2715 if (cmd->convert_src == TRIG_EXT)
2716 priv(dev)->adc_control1_bits |= adc_mode_bits(13); // good old mode 13
2718 priv(dev)->adc_control1_bits |= adc_mode_bits(8); // mode 8. What else could you need?
2720 priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2721 if (cmd->chanlist_len == 4)
2722 priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2723 else if (cmd->chanlist_len == 2)
2724 priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2725 priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2726 priv(dev)->adc_control1_bits |=
2727 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2728 priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2729 priv(dev)->adc_control1_bits |=
2730 adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist[cmd->
2731 chanlist_len - 1]));
2733 writew(priv(dev)->adc_control1_bits,
2734 priv(dev)->main_iobase + ADC_CONTROL1_REG);
2735 DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits);
2736 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
2739 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2741 if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2742 board(dev)->layout == LAYOUT_4020) {
2743 priv(dev)->ai_dma_index = 0;
2745 // set dma transfer size
2746 for (i = 0; i < ai_dma_ring_count(board(dev)); i++)
2747 priv(dev)->ai_dma_desc[i].transfer_size =
2748 cpu_to_le32(dma_transfer_size(dev) *
2751 // give location of first dma descriptor
2752 load_first_dma_descriptor(dev, 1,
2754 ai_dma_desc_bus_addr | PLX_DESC_IN_PCI_BIT |
2755 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI);
2757 dma_start_sync(dev, 1);
2760 if (board(dev)->layout == LAYOUT_4020) {
2761 /* set source for external triggers */
2763 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2764 bits |= EXT_START_TRIG_BNC_BIT;
2765 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2766 bits |= EXT_STOP_TRIG_BNC_BIT;
2767 writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2770 comedi_spin_lock_irqsave(&dev->spinlock, flags);
2772 /* enable pacing, triggering, etc */
2773 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2774 if (cmd->flags & TRIG_WAKE_EOS)
2775 bits |= ADC_DMA_DISABLE_BIT;
2776 // set start trigger
2777 if (cmd->start_src == TRIG_EXT) {
2778 bits |= ADC_START_TRIG_EXT_BITS;
2779 if (cmd->start_arg & CR_INVERT)
2780 bits |= ADC_START_TRIG_FALLING_BIT;
2781 } else if (cmd->start_src == TRIG_NOW)
2782 bits |= ADC_START_TRIG_SOFT_BITS;
2783 if (use_hw_sample_counter(cmd))
2784 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2785 writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG);
2786 DEBUG_PRINT("control0 bits 0x%x\n", bits);
2788 priv(dev)->ai_cmd_running = 1;
2790 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
2793 if (cmd->start_src == TRIG_NOW) {
2794 writew(0, priv(dev)->main_iobase + ADC_START_REG);
2795 DEBUG_PRINT("soft trig\n");
2801 // read num_samples from 16 bit wide ai fifo
2802 static void pio_drain_ai_fifo_16(struct comedi_device * dev)
2804 struct comedi_subdevice *s = dev->read_subdev;
2805 struct comedi_async *async = s->async;
2806 struct comedi_cmd *cmd = &async->cmd;
2808 uint16_t prepost_bits;
2809 int read_segment, read_index, write_segment, write_index;
2813 // get least significant 15 bits
2815 readw(priv(dev)->main_iobase +
2816 ADC_READ_PNTR_REG) & 0x7fff;
2818 readw(priv(dev)->main_iobase +
2819 ADC_WRITE_PNTR_REG) & 0x7fff;
2820 /* Get most significant bits (grey code). Different boards use different code
2821 * so use a scheme that doesn't depend on encoding. This read must
2822 * occur after reading least significant 15 bits to avoid race
2823 * with fifo switching to next segment. */
2824 prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG);
2826 /* if read and write pointers are not on the same fifo segment, read to the
2827 * end of the read segment */
2828 read_segment = adc_upper_read_ptr_code(prepost_bits);
2829 write_segment = adc_upper_write_ptr_code(prepost_bits);
2831 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2832 read_segment, write_segment, read_index, write_index);
2834 if (read_segment != write_segment)
2836 priv(dev)->ai_fifo_segment_length - read_index;
2838 num_samples = write_index - read_index;
2840 if (cmd->stop_src == TRIG_COUNT) {
2841 if (priv(dev)->ai_count == 0)
2843 if (num_samples > priv(dev)->ai_count) {
2844 num_samples = priv(dev)->ai_count;
2846 priv(dev)->ai_count -= num_samples;
2849 if (num_samples < 0) {
2850 rt_printk(" cb_pcidas64: bug! num_samples < 0\n");
2854 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2856 for (i = 0; i < num_samples; i++) {
2857 cfc_write_to_buffer(s,
2858 readw(priv(dev)->main_iobase + ADC_FIFO_REG));
2861 } while (read_segment != write_segment);
2864 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2865 * The pci-4020 hardware only supports
2866 * dma transfers (it only supports the use of pio for draining the last remaining
2867 * points from the fifo when a data aquisition operation has completed).
2869 static void pio_drain_ai_fifo_32(struct comedi_device * dev)
2871 struct comedi_subdevice *s = dev->read_subdev;
2872 struct comedi_async *async = s->async;
2873 struct comedi_cmd *cmd = &async->cmd;
2875 unsigned int max_transfer = 100000;
2878 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2880 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2882 if (cmd->stop_src == TRIG_COUNT) {
2883 if (max_transfer > priv(dev)->ai_count) {
2884 max_transfer = priv(dev)->ai_count;
2887 for (i = 0; read_code != write_code && i < max_transfer;) {
2888 fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG);
2889 cfc_write_to_buffer(s, fifo_data & 0xffff);
2891 if (i < max_transfer) {
2892 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2896 readw(priv(dev)->main_iobase +
2897 ADC_READ_PNTR_REG) & 0x7fff;
2899 priv(dev)->ai_count -= i;
2903 static void pio_drain_ai_fifo(struct comedi_device * dev)
2905 if (board(dev)->layout == LAYOUT_4020) {
2906 pio_drain_ai_fifo_32(dev);
2908 pio_drain_ai_fifo_16(dev);
2911 static void drain_dma_buffers(struct comedi_device * dev, unsigned int channel)
2913 struct comedi_async *async = dev->read_subdev->async;
2914 uint32_t next_transfer_addr;
2916 int num_samples = 0;
2921 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2924 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2926 // loop until we have read all the full buffers
2927 for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2928 (next_transfer_addr <
2929 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index]
2930 || next_transfer_addr >=
2931 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] +
2932 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev));
2934 // transfer data from dma buffer to comedi buffer
2935 num_samples = dma_transfer_size(dev);
2936 if (async->cmd.stop_src == TRIG_COUNT) {
2937 if (num_samples > priv(dev)->ai_count)
2938 num_samples = priv(dev)->ai_count;
2939 priv(dev)->ai_count -= num_samples;
2941 cfc_write_array_to_buffer(dev->read_subdev,
2942 priv(dev)->ai_buffer[priv(dev)->ai_dma_index],
2943 num_samples * sizeof(uint16_t));
2944 priv(dev)->ai_dma_index =
2945 (priv(dev)->ai_dma_index +
2946 1) % ai_dma_ring_count(board(dev));
2948 DEBUG_PRINT("next buffer addr 0x%lx\n",
2949 (unsigned long)priv(dev)->ai_buffer_bus_addr[priv(dev)->
2951 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2953 /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
2957 void handle_ai_interrupt(struct comedi_device * dev, unsigned short status,
2958 unsigned int plx_status)
2960 struct comedi_subdevice *s = dev->read_subdev;
2961 struct comedi_async *async = s->async;
2962 struct comedi_cmd *cmd = &async->cmd;
2963 uint8_t dma1_status;
2964 unsigned long flags;
2966 // check for fifo overrun
2967 if (status & ADC_OVERRUN_BIT) {
2968 comedi_error(dev, "fifo overrun");
2969 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2971 // spin lock makes sure noone else changes plx dma control reg
2972 comedi_spin_lock_irqsave(&dev->spinlock, flags);
2973 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2974 if (plx_status & ICS_DMA1_A) { // dma chan 1 interrupt
2975 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2976 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2977 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2979 if (dma1_status & PLX_DMA_EN_BIT) {
2980 drain_dma_buffers(dev, 1);
2982 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2984 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
2986 if (status & ADC_DONE_BIT)
2987 DEBUG_PRINT("adc done interrupt\n");
2989 // drain fifo with pio
2990 if ((status & ADC_DONE_BIT) ||
2991 ((cmd->flags & TRIG_WAKE_EOS) &&
2992 (status & ADC_INTR_PENDING_BIT) &&
2993 (board(dev)->layout != LAYOUT_4020))) {
2994 DEBUG_PRINT("pio fifo drain\n");
2995 comedi_spin_lock_irqsave(&dev->spinlock, flags);
2996 if (priv(dev)->ai_cmd_running) {
2997 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
2998 pio_drain_ai_fifo(dev);
3000 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
3002 // if we are have all the data, then quit
3003 if ((cmd->stop_src == TRIG_COUNT && priv(dev)->ai_count <= 0) ||
3004 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
3005 async->events |= COMEDI_CB_EOA;
3008 cfc_handle_events(dev, s);
3011 static inline unsigned int prev_ao_dma_index(struct comedi_device * dev)
3013 unsigned int buffer_index;
3015 if (priv(dev)->ao_dma_index == 0)
3016 buffer_index = AO_DMA_RING_COUNT - 1;
3018 buffer_index = priv(dev)->ao_dma_index - 1;
3019 return buffer_index;
3022 static int last_ao_dma_load_completed(struct comedi_device * dev)
3024 unsigned int buffer_index;
3025 unsigned int transfer_address;
3026 unsigned short dma_status;
3028 buffer_index = prev_ao_dma_index(dev);
3029 dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3030 if ((dma_status & PLX_DMA_DONE_BIT) == 0)
3034 readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
3035 if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index])
3041 static int ao_stopped_by_error(struct comedi_device * dev, const struct comedi_cmd * cmd)
3043 if (cmd->stop_src == TRIG_NONE)
3045 if (cmd->stop_src == TRIG_COUNT) {
3046 if (priv(dev)->ao_count)
3048 if (last_ao_dma_load_completed(dev) == 0)
3054 static inline int ao_dma_needs_restart(struct comedi_device * dev,
3055 unsigned short dma_status)
3057 if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
3058 (dma_status & PLX_DMA_EN_BIT) == 0)
3060 if (last_ao_dma_load_completed(dev))
3066 static void restart_ao_dma(struct comedi_device * dev)
3068 unsigned int dma_desc_bits;
3071 readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
3072 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
3073 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
3074 load_first_dma_descriptor(dev, 0, dma_desc_bits);
3076 dma_start_sync(dev, 0);
3079 static void handle_ao_interrupt(struct comedi_device * dev, unsigned short status,
3080 unsigned int plx_status)
3082 struct comedi_subdevice *s = dev->write_subdev;
3083 struct comedi_async *async;
3084 struct comedi_cmd *cmd;
3085 uint8_t dma0_status;
3086 unsigned long flags;
3088 /* board might not support ao, in which case write_subdev is NULL */
3094 // spin lock makes sure noone else changes plx dma control reg
3095 comedi_spin_lock_irqsave(&dev->spinlock, flags);
3096 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3097 if (plx_status & ICS_DMA0_A) { // dma chan 0 interrupt
3098 if ((dma0_status & PLX_DMA_EN_BIT)
3099 && !(dma0_status & PLX_DMA_DONE_BIT))
3100 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3101 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3103 writeb(PLX_CLEAR_DMA_INTR_BIT,
3104 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3105 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
3106 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3107 if (dma0_status & PLX_DMA_EN_BIT) {
3108 load_ao_dma(dev, cmd);
3109 /* try to recover from dma end-of-chain event */
3110 if (ao_dma_needs_restart(dev, dma0_status))
3111 restart_ao_dma(dev);
3113 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3115 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
3117 if ((status & DAC_DONE_BIT)) {
3118 async->events |= COMEDI_CB_EOA;
3119 if (ao_stopped_by_error(dev, cmd))
3120 async->events |= COMEDI_CB_ERROR;
3121 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3122 readl(priv(dev)->plx9080_iobase +
3123 PLX_DMA0_DESCRIPTOR_REG));
3124 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3125 readl(priv(dev)->plx9080_iobase +
3126 PLX_DMA0_PCI_ADDRESS_REG));
3128 cfc_handle_events(dev, s);
3131 static irqreturn_t handle_interrupt(int irq, void *d PT_REGS_ARG)
3133 struct comedi_device *dev = d;
3134 unsigned short status;
3135 uint32_t plx_status;
3138 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
3139 status = readw(priv(dev)->main_iobase + HW_STATUS_REG);
3141 DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status);
3142 DEBUG_PRINT("plx status 0x%x\n", plx_status);
3144 /* an interrupt before all the postconfig stuff gets done could
3145 * cause a NULL dereference if we continue through the
3146 * interrupt handler */
3147 if (dev->attached == 0) {
3148 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3152 handle_ai_interrupt(dev, status, plx_status);
3153 handle_ao_interrupt(dev, status, plx_status);
3155 // clear possible plx9080 interrupt sources
3156 if (plx_status & ICS_LDIA) { // clear local doorbell interrupt
3157 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3158 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3159 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3162 DEBUG_PRINT("exiting handler\n");
3167 void abort_dma(struct comedi_device * dev, unsigned int channel)
3169 unsigned long flags;
3171 // spinlock for plx dma control/status reg
3172 comedi_spin_lock_irqsave(&dev->spinlock, flags);
3174 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
3176 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
3179 static int ai_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
3181 unsigned long flags;
3183 comedi_spin_lock_irqsave(&dev->spinlock, flags);
3184 if (priv(dev)->ai_cmd_running == 0) {
3185 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
3188 priv(dev)->ai_cmd_running = 0;
3189 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
3191 disable_ai_pacing(dev);
3195 DEBUG_PRINT("ai canceled\n");
3199 static int ao_winsn(struct comedi_device * dev, struct comedi_subdevice * s,
3200 struct comedi_insn * insn, unsigned int * data)
3202 int chan = CR_CHAN(insn->chanspec);
3203 int range = CR_RANGE(insn->chanspec);
3205 // do some initializing
3206 writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3209 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range);
3210 writew(priv(dev)->dac_control1_bits,
3211 priv(dev)->main_iobase + DAC_CONTROL1_REG);
3214 if (board(dev)->layout == LAYOUT_4020) {
3215 writew(data[0] & 0xff,
3216 priv(dev)->main_iobase + dac_lsb_4020_reg(chan));
3217 writew((data[0] >> 8) & 0xf,
3218 priv(dev)->main_iobase + dac_msb_4020_reg(chan));
3220 writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan));
3223 // remember output value
3224 priv(dev)->ao_value[chan] = data[0];
3229 static int ao_readback_insn(struct comedi_device * dev, struct comedi_subdevice * s,
3230 struct comedi_insn * insn, unsigned int * data)
3232 data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)];
3237 static void set_dac_control0_reg(struct comedi_device * dev, const struct comedi_cmd * cmd)
3239 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3240 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3242 if (cmd->start_src == TRIG_EXT) {
3243 bits |= WAVEFORM_TRIG_EXT_BITS;
3244 if (cmd->start_arg & CR_INVERT)
3245 bits |= WAVEFORM_TRIG_FALLING_BIT;
3247 bits |= WAVEFORM_TRIG_SOFT_BITS;
3249 if (cmd->scan_begin_src == TRIG_EXT) {
3250 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3251 if (cmd->scan_begin_arg & CR_INVERT)
3252 bits |= DAC_EXT_UPDATE_FALLING_BIT;
3254 writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3257 static void set_dac_control1_reg(struct comedi_device * dev, const struct comedi_cmd * cmd)
3261 for (i = 0; i < cmd->chanlist_len; i++) {
3264 channel = CR_CHAN(cmd->chanlist[i]);
3265 range = CR_RANGE(cmd->chanlist[i]);
3266 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel,
3269 priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT;
3270 writew(priv(dev)->dac_control1_bits,
3271 priv(dev)->main_iobase + DAC_CONTROL1_REG);
3274 static void set_dac_select_reg(struct comedi_device * dev, const struct comedi_cmd * cmd)
3277 unsigned int first_channel, last_channel;
3279 first_channel = CR_CHAN(cmd->chanlist[0]);
3280 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3281 if (last_channel < first_channel)
3282 comedi_error(dev, "bug! last ao channel < first ao channel");
3284 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3286 writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG);
3289 static void set_dac_interval_regs(struct comedi_device * dev, const struct comedi_cmd * cmd)
3291 unsigned int divisor;
3293 if (cmd->scan_begin_src != TRIG_TIMER)
3296 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3297 if (divisor > max_counter_value) {
3298 comedi_error(dev, "bug! ao divisor too big");
3299 divisor = max_counter_value;
3301 writew(divisor & 0xffff,
3302 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3303 writew((divisor >> 16) & 0xff,
3304 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3307 static unsigned int load_ao_dma_buffer(struct comedi_device * dev,
3308 const struct comedi_cmd * cmd)
3310 unsigned int num_bytes, buffer_index, prev_buffer_index;
3311 unsigned int next_bits;
3313 buffer_index = priv(dev)->ao_dma_index;
3314 prev_buffer_index = prev_ao_dma_index(dev);
3316 DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index,
3317 priv(dev)->ao_buffer_bus_addr[buffer_index]);
3319 num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3320 if (num_bytes > DMA_BUFFER_SIZE)
3321 num_bytes = DMA_BUFFER_SIZE;
3322 if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count)
3323 num_bytes = priv(dev)->ao_count;
3324 num_bytes -= num_bytes % bytes_in_sample;
3329 DEBUG_PRINT("loading %i bytes\n", num_bytes);
3331 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3332 priv(dev)->ao_buffer[buffer_index], num_bytes);
3333 priv(dev)->ao_dma_desc[buffer_index].transfer_size =
3334 cpu_to_le32(num_bytes);
3335 /* set end of chain bit so we catch underruns */
3336 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next);
3337 next_bits |= PLX_END_OF_CHAIN_BIT;
3338 priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3339 /* clear end of chain bit on previous buffer now that we have set it
3340 * for the last buffer */
3341 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next);
3342 next_bits &= ~PLX_END_OF_CHAIN_BIT;
3343 priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3345 priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3346 priv(dev)->ao_count -= num_bytes;
3351 static void load_ao_dma(struct comedi_device * dev, const struct comedi_cmd * cmd)
3353 unsigned int num_bytes;
3354 unsigned int next_transfer_addr;
3355 void *pci_addr_reg =
3356 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3357 unsigned int buffer_index;
3360 buffer_index = priv(dev)->ao_dma_index;
3361 /* don't overwrite data that hasn't been transferred yet */
3362 next_transfer_addr = readl(pci_addr_reg);
3363 if (next_transfer_addr >=
3364 priv(dev)->ao_buffer_bus_addr[buffer_index]
3365 && next_transfer_addr <
3366 priv(dev)->ao_buffer_bus_addr[buffer_index] +
3369 num_bytes = load_ao_dma_buffer(dev, cmd);
3370 } while (num_bytes >= DMA_BUFFER_SIZE);
3373 static int prep_ao_dma(struct comedi_device * dev, const struct comedi_cmd * cmd)
3375 unsigned int num_bytes;
3378 /* clear queue pointer too, since external queue has
3379 * weird interactions with ao fifo */
3380 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
3381 writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
3383 num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3384 if (cmd->stop_src == TRIG_COUNT &&
3385 num_bytes / bytes_in_sample > priv(dev)->ao_count)
3386 num_bytes = priv(dev)->ao_count * bytes_in_sample;
3387 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3388 priv(dev)->ao_bounce_buffer, num_bytes);
3389 for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3390 writew(priv(dev)->ao_bounce_buffer[i],
3391 priv(dev)->main_iobase + DAC_FIFO_REG);
3393 priv(dev)->ao_count -= num_bytes / bytes_in_sample;
3394 if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0)
3396 num_bytes = load_ao_dma_buffer(dev, cmd);
3399 if (num_bytes >= DMA_BUFFER_SIZE) ;
3400 load_ao_dma(dev, cmd);
3402 dma_start_sync(dev, 0);
3407 static inline int external_ai_queue_in_use(struct comedi_device * dev)
3409 if (dev->read_subdev->busy)
3411 if (board(dev)->layout == LAYOUT_4020)
3413 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3418 static int ao_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
3420 struct comedi_cmd *cmd = &s->async->cmd;
3422 if (external_ai_queue_in_use(dev)) {
3423 warn_external_queue(dev);
3426 /* disable analog output system during setup */
3427 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3429 priv(dev)->ao_dma_index = 0;
3430 priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len;
3432 set_dac_select_reg(dev, cmd);
3433 set_dac_interval_regs(dev, cmd);
3434 load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr |
3435 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3437 set_dac_control1_reg(dev, cmd);
3438 s->async->inttrig = ao_inttrig;
3443 static int ao_inttrig(struct comedi_device * dev, struct comedi_subdevice * s,
3444 unsigned int trig_num)
3446 struct comedi_cmd *cmd = &s->async->cmd;
3452 retval = prep_ao_dma(dev, cmd);
3456 set_dac_control0_reg(dev, cmd);
3458 if (cmd->start_src == TRIG_INT)
3459 writew(0, priv(dev)->main_iobase + DAC_START_REG);
3461 s->async->inttrig = NULL;
3466 static int ao_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
3467 struct comedi_cmd * cmd)
3471 unsigned int tmp_arg;
3474 /* step 1: make sure trigger sources are trivially valid */
3476 tmp = cmd->start_src;
3477 cmd->start_src &= TRIG_INT | TRIG_EXT;
3478 if (!cmd->start_src || tmp != cmd->start_src)
3481 tmp = cmd->scan_begin_src;
3482 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3483 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3486 tmp = cmd->convert_src;
3487 cmd->convert_src &= TRIG_NOW;
3488 if (!cmd->convert_src || tmp != cmd->convert_src)
3491 tmp = cmd->scan_end_src;
3492 cmd->scan_end_src &= TRIG_COUNT;
3493 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3496 tmp = cmd->stop_src;
3497 cmd->stop_src &= TRIG_NONE;
3498 if (!cmd->stop_src || tmp != cmd->stop_src)
3504 /* step 2: make sure trigger sources are unique and mutually compatible */
3507 if (cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
3509 if (cmd->scan_begin_src != TRIG_TIMER &&
3510 cmd->scan_begin_src != TRIG_EXT)
3513 // compatibility check
3514 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3516 if (cmd->stop_src != TRIG_COUNT &&
3517 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3523 /* step 3: make sure arguments are trivially compatible */
3525 if (cmd->scan_begin_src == TRIG_TIMER) {
3526 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) {
3527 cmd->scan_begin_arg = board(dev)->ao_scan_speed;
3530 if (get_ao_divisor(cmd->scan_begin_arg,
3531 cmd->flags) > max_counter_value) {
3532 cmd->scan_begin_arg =
3533 (max_counter_value + 2) * TIMER_BASE;
3538 if (!cmd->chanlist_len) {
3539 cmd->chanlist_len = 1;
3542 if (cmd->scan_end_arg != cmd->chanlist_len) {
3543 cmd->scan_end_arg = cmd->chanlist_len;
3550 /* step 4: fix up any arguments */
3552 if (cmd->scan_begin_src == TRIG_TIMER) {
3553 tmp_arg = cmd->scan_begin_arg;
3554 cmd->scan_begin_arg =
3555 get_divisor(cmd->scan_begin_arg,
3556 cmd->flags) * TIMER_BASE;
3557 if (tmp_arg != cmd->scan_begin_arg)
3564 if (cmd->chanlist) {
3565 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3566 for (i = 1; i < cmd->chanlist_len; i++) {
3567 if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3569 "chanlist must use consecutive channels");
3582 static int ao_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
3584 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3589 static int dio_callback(int dir, int port, int data, unsigned long iobase)
3592 writeb(data, (void *)(iobase + port));
3593 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3596 return readb((void *)(iobase + port));
3600 static int dio_callback_4020(int dir, int port, int data, unsigned long iobase)
3603 writew(data, (void *)(iobase + 2 * port));
3606 return readw((void *)(iobase + 2 * port));
3610 static int di_rbits(struct comedi_device * dev, struct comedi_subdevice * s,
3611 struct comedi_insn * insn, unsigned int * data)
3615 bits = readb(priv(dev)->dio_counter_iobase + DI_REG);
3623 static int do_wbits(struct comedi_device * dev, struct comedi_subdevice * s,
3624 struct comedi_insn * insn, unsigned int * data)
3627 // zero bits we are going to change
3628 s->state &= ~data[0];
3630 s->state |= data[0] & data[1];
3632 writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG);
3639 static int dio_60xx_config_insn(struct comedi_device * dev, struct comedi_subdevice * s,
3640 struct comedi_insn * insn, unsigned int * data)
3644 mask = 1 << CR_CHAN(insn->chanspec);
3647 case INSN_CONFIG_DIO_INPUT:
3648 s->io_bits &= ~mask;
3650 case INSN_CONFIG_DIO_OUTPUT:
3653 case INSN_CONFIG_DIO_QUERY:
3654 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3661 priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3666 static int dio_60xx_wbits(struct comedi_device * dev, struct comedi_subdevice * s,
3667 struct comedi_insn * insn, unsigned int * data)
3670 s->state &= ~data[0];
3671 s->state |= (data[0] & data[1]);
3673 priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3676 data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3681 static void caldac_write(struct comedi_device * dev, unsigned int channel,
3684 priv(dev)->caldac_state[channel] = value;
3686 switch (board(dev)->layout) {
3689 caldac_8800_write(dev, channel, value);
3692 caldac_i2c_write(dev, channel, value);
3699 static int calib_write_insn(struct comedi_device * dev, struct comedi_subdevice * s,
3700 struct comedi_insn * insn, unsigned int * data)
3702 int channel = CR_CHAN(insn->chanspec);
3704 /* return immediately if setting hasn't changed, since
3705 * programming these things is slow */
3706 if (priv(dev)->caldac_state[channel] == data[0])
3709 caldac_write(dev, channel, data[0]);
3714 static int calib_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
3715 struct comedi_insn * insn, unsigned int * data)
3717 unsigned int channel = CR_CHAN(insn->chanspec);
3719 data[0] = priv(dev)->caldac_state[channel];
3724 static void ad8402_write(struct comedi_device * dev, unsigned int channel,
3727 static const int bitstream_length = 10;
3728 unsigned int bit, register_bits;
3729 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3730 static const int ad8402_comedi_udelay = 1;
3732 priv(dev)->ad8402_state[channel] = value;
3734 register_bits = SELECT_8402_64XX_BIT;
3735 comedi_udelay(ad8402_comedi_udelay);
3736 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3738 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3739 if (bitstream & bit)
3740 register_bits |= SERIAL_DATA_IN_BIT;
3742 register_bits &= ~SERIAL_DATA_IN_BIT;
3743 comedi_udelay(ad8402_comedi_udelay);
3744 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3745 comedi_udelay(ad8402_comedi_udelay);
3746 writew(register_bits | SERIAL_CLOCK_BIT,
3747 priv(dev)->main_iobase + CALIBRATION_REG);
3750 comedi_udelay(ad8402_comedi_udelay);
3751 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
3754 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3755 static int ad8402_write_insn(struct comedi_device * dev, struct comedi_subdevice * s,
3756 struct comedi_insn * insn, unsigned int * data)
3758 int channel = CR_CHAN(insn->chanspec);
3760 /* return immediately if setting hasn't changed, since
3761 * programming these things is slow */
3762 if (priv(dev)->ad8402_state[channel] == data[0])
3765 priv(dev)->ad8402_state[channel] = data[0];
3767 ad8402_write(dev, channel, data[0]);
3772 static int ad8402_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
3773 struct comedi_insn * insn, unsigned int * data)
3775 unsigned int channel = CR_CHAN(insn->chanspec);
3777 data[0] = priv(dev)->ad8402_state[channel];
3782 static uint16_t read_eeprom(struct comedi_device * dev, uint8_t address)
3784 static const int bitstream_length = 11;
3785 static const int read_command = 0x6;
3786 unsigned int bitstream = (read_command << 8) | address;
3788 void *const plx_control_addr =
3789 priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
3791 static const int value_length = 16;
3792 static const int eeprom_comedi_udelay = 1;
3794 comedi_udelay(eeprom_comedi_udelay);
3795 priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3796 // make sure we don't send anything to the i2c bus on 4020
3797 priv(dev)->plx_control_bits |= CTL_USERO;
3798 writel(priv(dev)->plx_control_bits, plx_control_addr);
3799 // activate serial eeprom
3800 comedi_udelay(eeprom_comedi_udelay);
3801 priv(dev)->plx_control_bits |= CTL_EE_CS;
3802 writel(priv(dev)->plx_control_bits, plx_control_addr);
3804 // write read command and desired memory address
3805 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3806 // set bit to be written
3807 comedi_udelay(eeprom_comedi_udelay);
3808 if (bitstream & bit)
3809 priv(dev)->plx_control_bits |= CTL_EE_W;
3811 priv(dev)->plx_control_bits &= ~CTL_EE_W;
3812 writel(priv(dev)->plx_control_bits, plx_control_addr);
3814 comedi_udelay(eeprom_comedi_udelay);
3815 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3816 writel(priv(dev)->plx_control_bits, plx_control_addr);
3817 comedi_udelay(eeprom_comedi_udelay);
3818 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3819 writel(priv(dev)->plx_control_bits, plx_control_addr);
3821 // read back value from eeprom memory location
3823 for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3825 comedi_udelay(eeprom_comedi_udelay);
3826 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3827 writel(priv(dev)->plx_control_bits, plx_control_addr);
3828 comedi_udelay(eeprom_comedi_udelay);
3829 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3830 writel(priv(dev)->plx_control_bits, plx_control_addr);
3831 comedi_udelay(eeprom_comedi_udelay);
3832 if (readl(plx_control_addr) & CTL_EE_R)
3836 // deactivate eeprom serial input
3837 comedi_udelay(eeprom_comedi_udelay);
3838 priv(dev)->plx_control_bits &= ~CTL_EE_CS;
3839 writel(priv(dev)->plx_control_bits, plx_control_addr);
3844 static int eeprom_read_insn(struct comedi_device * dev, struct comedi_subdevice * s,
3845 struct comedi_insn * insn, unsigned int * data)
3847 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3852 /* utility function that rounds desired timing to an achievable time, and
3853 * sets cmd members appropriately.
3854 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3856 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
3858 unsigned int convert_divisor = 0, scan_divisor;
3859 static const int min_convert_divisor = 3;
3860 static const int max_convert_divisor =
3861 max_counter_value + min_convert_divisor;
3862 static const int min_scan_divisor_4020 = 2;
3863 unsigned long long max_scan_divisor, min_scan_divisor;
3865 if (cmd->convert_src == TRIG_TIMER) {
3866 if (board(dev)->layout == LAYOUT_4020) {
3867 cmd->convert_arg = 0;
3870 get_divisor(cmd->convert_arg, cmd->flags);
3871 if (convert_divisor > max_convert_divisor)
3872 convert_divisor = max_convert_divisor;
3873 if (convert_divisor < min_convert_divisor)
3874 convert_divisor = min_convert_divisor;
3875 cmd->convert_arg = convert_divisor * TIMER_BASE;
3877 } else if (cmd->convert_src == TRIG_NOW)
3878 cmd->convert_arg = 0;
3880 if (cmd->scan_begin_src == TRIG_TIMER) {
3881 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
3882 if (cmd->convert_src == TRIG_TIMER) {
3883 // XXX check for integer overflows
3884 min_scan_divisor = convert_divisor * cmd->chanlist_len;
3886 (convert_divisor * cmd->chanlist_len - 1) +
3889 min_scan_divisor = min_scan_divisor_4020;
3890 max_scan_divisor = max_counter_value + min_scan_divisor;
3892 if (scan_divisor > max_scan_divisor)
3893 scan_divisor = max_scan_divisor;
3894 if (scan_divisor < min_scan_divisor)
3895 scan_divisor = min_scan_divisor;
3896 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
3902 /* Gets nearest achievable timing given master clock speed, does not
3903 * take into account possible minimum/maximum divisor values. Used
3904 * by other timing checking functions. */
3905 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
3907 unsigned int divisor;
3909 switch (flags & TRIG_ROUND_MASK) {
3911 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
3913 case TRIG_ROUND_DOWN:
3914 divisor = ns / TIMER_BASE;
3916 case TRIG_ROUND_NEAREST:
3918 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
3924 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3926 return get_divisor(ns, flags) - 2;
3929 // adjusts the size of hardware fifo (which determines block size for dma xfers)
3930 static int set_ai_fifo_size(struct comedi_device * dev, unsigned int num_samples)
3932 unsigned int num_fifo_entries;
3934 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3936 num_fifo_entries = num_samples / fifo->sample_packing_ratio;
3938 retval = set_ai_fifo_segment_length(dev,
3939 num_fifo_entries / fifo->num_segments);
3943 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
3945 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
3950 // query length of fifo
3951 static unsigned int ai_fifo_size(struct comedi_device * dev)
3953 return priv(dev)->ai_fifo_segment_length *
3954 board(dev)->ai_fifo->num_segments *
3955 board(dev)->ai_fifo->sample_packing_ratio;
3958 static int set_ai_fifo_segment_length(struct comedi_device * dev,
3959 unsigned int num_entries)
3961 static const int increment_size = 0x100;
3962 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3963 unsigned int num_increments;
3966 if (num_entries < increment_size)
3967 num_entries = increment_size;
3968 if (num_entries > fifo->max_segment_length)
3969 num_entries = fifo->max_segment_length;
3971 // 1 == 256 entries, 2 == 512 entries, etc
3972 num_increments = (num_entries + increment_size / 2) / increment_size;
3974 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
3975 priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
3976 priv(dev)->fifo_size_bits |= bits;
3977 writew(priv(dev)->fifo_size_bits,
3978 priv(dev)->main_iobase + FIFO_SIZE_REG);
3980 priv(dev)->ai_fifo_segment_length = num_increments * increment_size;
3982 DEBUG_PRINT("set hardware fifo segment length to %i\n",
3983 priv(dev)->ai_fifo_segment_length);
3985 return priv(dev)->ai_fifo_segment_length;
3988 /* pci-6025 8800 caldac:
3989 * address 0 == dac channel 0 offset
3990 * address 1 == dac channel 0 gain
3991 * address 2 == dac channel 1 offset
3992 * address 3 == dac channel 1 gain
3993 * address 4 == fine adc offset
3994 * address 5 == coarse adc offset
3995 * address 6 == coarse adc gain
3996 * address 7 == fine adc gain
3998 /* pci-6402/16 uses all 8 channels for dac:
3999 * address 0 == dac channel 0 fine gain
4000 * address 1 == dac channel 0 coarse gain
4001 * address 2 == dac channel 0 coarse offset
4002 * address 3 == dac channel 1 coarse offset
4003 * address 4 == dac channel 1 fine gain
4004 * address 5 == dac channel 1 coarse gain
4005 * address 6 == dac channel 0 fine offset
4006 * address 7 == dac channel 1 fine offset
4009 static int caldac_8800_write(struct comedi_device * dev, unsigned int address,
4012 static const int num_caldac_channels = 8;
4013 static const int bitstream_length = 11;
4014 unsigned int bitstream = ((address & 0x7) << 8) | value;
4015 unsigned int bit, register_bits;
4016 static const int caldac_8800_udelay = 1;
4018 if (address >= num_caldac_channels) {
4019 comedi_error(dev, "illegal caldac channel");
4022 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
4024 if (bitstream & bit)
4025 register_bits |= SERIAL_DATA_IN_BIT;
4026 comedi_udelay(caldac_8800_udelay);
4027 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4028 register_bits |= SERIAL_CLOCK_BIT;
4029 comedi_udelay(caldac_8800_udelay);
4030 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4032 comedi_udelay(caldac_8800_udelay);
4033 writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG);
4034 comedi_udelay(caldac_8800_udelay);
4035 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
4036 comedi_udelay(caldac_8800_udelay);
4041 static int caldac_i2c_write(struct comedi_device * dev, unsigned int caldac_channel,
4044 uint8_t serial_bytes[3];
4047 // manual has gain and offset bits switched
4054 NOT_CLEAR_REGISTERS = 0x20,
4057 switch (caldac_channel) {
4058 case 0: // chan 0 offset
4059 i2c_addr = CALDAC0_I2C_ADDR;
4060 serial_bytes[0] = OFFSET_0_2;
4062 case 1: // chan 1 offset
4063 i2c_addr = CALDAC0_I2C_ADDR;
4064 serial_bytes[0] = OFFSET_1_3;
4066 case 2: // chan 2 offset
4067 i2c_addr = CALDAC1_I2C_ADDR;
4068 serial_bytes[0] = OFFSET_0_2;
4070 case 3: // chan 3 offset
4071 i2c_addr = CALDAC1_I2C_ADDR;
4072 serial_bytes[0] = OFFSET_1_3;
4074 case 4: // chan 0 gain
4075 i2c_addr = CALDAC0_I2C_ADDR;
4076 serial_bytes[0] = GAIN_0_2;
4078 case 5: // chan 1 gain
4079 i2c_addr = CALDAC0_I2C_ADDR;
4080 serial_bytes[0] = GAIN_1_3;
4082 case 6: // chan 2 gain
4083 i2c_addr = CALDAC1_I2C_ADDR;
4084 serial_bytes[0] = GAIN_0_2;
4086 case 7: // chan 3 gain
4087 i2c_addr = CALDAC1_I2C_ADDR;
4088 serial_bytes[0] = GAIN_1_3;
4091 comedi_error(dev, "invalid caldac channel\n");
4095 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
4096 serial_bytes[2] = value & 0xff;
4097 i2c_write(dev, i2c_addr, serial_bytes, 3);
4101 // Their i2c requires a huge delay on setting clock or data high for some reason
4102 static const int i2c_high_comedi_udelay = 1000;
4103 static const int i2c_low_comedi_udelay = 10;
4105 // set i2c data line high or low
4106 static void i2c_set_sda(struct comedi_device * dev, int state)
4108 static const int data_bit = CTL_EE_W;
4109 void *plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
4112 // set data line high
4113 priv(dev)->plx_control_bits &= ~data_bit;
4114 writel(priv(dev)->plx_control_bits, plx_control_addr);
4115 comedi_udelay(i2c_high_comedi_udelay);
4116 } else // set data line low
4118 priv(dev)->plx_control_bits |= data_bit;
4119 writel(priv(dev)->plx_control_bits, plx_control_addr);
4120 comedi_udelay(i2c_low_comedi_udelay);
4124 // set i2c clock line high or low
4125 static void i2c_set_scl(struct comedi_device * dev, int state)
4127 static const int clock_bit = CTL_USERO;
4128 void *plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
4131 // set clock line high
4132 priv(dev)->plx_control_bits &= ~clock_bit;
4133 writel(priv(dev)->plx_control_bits, plx_control_addr);
4134 comedi_udelay(i2c_high_comedi_udelay);
4135 } else // set clock line low
4137 priv(dev)->plx_control_bits |= clock_bit;
4138 writel(priv(dev)->plx_control_bits, plx_control_addr);
4139 comedi_udelay(i2c_low_comedi_udelay);
4143 static void i2c_write_byte(struct comedi_device * dev, uint8_t byte)
4146 unsigned int num_bits = 8;
4148 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
4150 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
4151 i2c_set_scl(dev, 0);
4153 i2c_set_sda(dev, 1);
4155 i2c_set_sda(dev, 0);
4156 i2c_set_scl(dev, 1);
4160 // we can't really read the lines, so fake it
4161 static int i2c_read_ack(struct comedi_device * dev)
4163 i2c_set_scl(dev, 0);
4164 i2c_set_sda(dev, 1);
4165 i2c_set_scl(dev, 1);
4167 return 0; // return fake acknowledge bit
4171 static void i2c_start(struct comedi_device * dev)
4173 i2c_set_scl(dev, 1);
4174 i2c_set_sda(dev, 1);
4175 i2c_set_sda(dev, 0);
4179 static void i2c_stop(struct comedi_device * dev)
4181 i2c_set_scl(dev, 0);
4182 i2c_set_sda(dev, 0);
4183 i2c_set_scl(dev, 1);
4184 i2c_set_sda(dev, 1);
4187 static void i2c_write(struct comedi_device * dev, unsigned int address,
4188 const uint8_t * data, unsigned int length)
4192 static const int read_bit = 0x1;
4194 //XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus
4196 // make sure we dont send anything to eeprom
4197 priv(dev)->plx_control_bits &= ~CTL_EE_CS;
4202 // send address and write bit
4203 bitstream = (address << 1) & ~read_bit;
4204 i2c_write_byte(dev, bitstream);
4207 if (i2c_read_ack(dev) != 0) {
4208 comedi_error(dev, "i2c write failed: no acknowledge");
4213 for (i = 0; i < length; i++) {
4214 i2c_write_byte(dev, data[i]);
4215 if (i2c_read_ack(dev) != 0) {
4216 comedi_error(dev, "i2c write failed: no acknowledge");