3 comedi/drivers/adl_pci9111.c
5 Hardware driver for PCI9111 ADLink cards:
9 Copyright (C) 2002-2005 Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Description: Adlink PCI-9111HR
29 Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>
30 Devices: [ADLink] PCI-9111HR (adl_pci9111)
39 - ai_do_cmd mode with the following sources:
42 - scan_begin_src TRIG_FOLLOW TRIG_TIMER TRIG_EXT
43 - convert_src TRIG_TIMER TRIG_EXT
44 - scan_end_src TRIG_COUNT
45 - stop_src TRIG_COUNT TRIG_NONE
47 The scanned channels must be consecutive and start from 0. They must
48 all have the same range and aref.
50 Configuration options:
52 [0] - PCI bus number (optional)
53 [1] - PCI slot number (optional)
55 If bus/slot is not specified, the first available PCI
63 2005/02/17 Extend AI streaming capabilities. Now, scan_begin_arg can be
64 a multiple of chanlist_len*convert_arg.
65 2002/02/19 Fixed the two's complement conversion in pci9111_(hr_)ai_get_data.
66 2002/02/18 Added external trigger support for analog input.
70 - Really test implemented functionality.
71 - Add support for the PCI-9111DG with a probe routine to identify the card type
72 (perhaps with the help of the channel number readback of the A/D Data register).
73 - Add external multiplexer support.
77 #include "../comedidev.h"
79 #include <linux/delay.h>
80 #include <linux/interrupt.h>
83 #include "comedi_pci.h"
84 #include "comedi_fc.h"
86 #define PCI9111_DRIVER_NAME "adl_pci9111"
87 #define PCI9111_HR_DEVICE_ID 0x9111
89 /* TODO: Add other pci9111 board id */
91 #define PCI9111_IO_RANGE 0x0100
93 #define PCI9111_FIFO_HALF_SIZE 512
95 #define PCI9111_AI_CHANNEL_NBR 16
97 #define PCI9111_AI_RESOLUTION 12
98 #define PCI9111_AI_RESOLUTION_MASK 0x0FFF
99 #define PCI9111_AI_RESOLUTION_2_CMP_BIT 0x0800
101 #define PCI9111_HR_AI_RESOLUTION 16
102 #define PCI9111_HR_AI_RESOLUTION_MASK 0xFFFF
103 #define PCI9111_HR_AI_RESOLUTION_2_CMP_BIT 0x8000
105 #define PCI9111_AI_ACQUISITION_PERIOD_MIN_NS 10000
106 #define PCI9111_AO_CHANNEL_NBR 1
107 #define PCI9111_AO_RESOLUTION 12
108 #define PCI9111_AO_RESOLUTION_MASK 0x0FFF
109 #define PCI9111_DI_CHANNEL_NBR 16
110 #define PCI9111_DO_CHANNEL_NBR 16
111 #define PCI9111_DO_MASK 0xFFFF
113 #define PCI9111_RANGE_SETTING_DELAY 10
114 #define PCI9111_AI_INSTANT_READ_UDELAY_US 2
115 #define PCI9111_AI_INSTANT_READ_TIMEOUT 100
117 #define PCI9111_8254_CLOCK_PERIOD_NS 500
119 #define PCI9111_8254_COUNTER_0 0x00
120 #define PCI9111_8254_COUNTER_1 0x40
121 #define PCI9111_8254_COUNTER_2 0x80
122 #define PCI9111_8254_COUNTER_LATCH 0x00
123 #define PCI9111_8254_READ_LOAD_LSB_ONLY 0x10
124 #define PCI9111_8254_READ_LOAD_MSB_ONLY 0x20
125 #define PCI9111_8254_READ_LOAD_LSB_MSB 0x30
126 #define PCI9111_8254_MODE_0 0x00
127 #define PCI9111_8254_MODE_1 0x02
128 #define PCI9111_8254_MODE_2 0x04
129 #define PCI9111_8254_MODE_3 0x06
130 #define PCI9111_8254_MODE_4 0x08
131 #define PCI9111_8254_MODE_5 0x0A
132 #define PCI9111_8254_BINARY_COUNTER 0x00
133 #define PCI9111_8254_BCD_COUNTER 0x01
137 #define PCI9111_REGISTER_AD_FIFO_VALUE 0x00 /* AD Data stored in FIFO */
138 #define PCI9111_REGISTER_DA_OUTPUT 0x00
139 #define PCI9111_REGISTER_DIGITAL_IO 0x02
140 #define PCI9111_REGISTER_EXTENDED_IO_PORTS 0x04
141 #define PCI9111_REGISTER_AD_CHANNEL_CONTROL 0x06 /* Channel selection */
142 #define PCI9111_REGISTER_AD_CHANNEL_READBACK 0x06
143 #define PCI9111_REGISTER_INPUT_SIGNAL_RANGE 0x08
144 #define PCI9111_REGISTER_RANGE_STATUS_READBACK 0x08
145 #define PCI9111_REGISTER_TRIGGER_MODE_CONTROL 0x0A
146 #define PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK 0x0A
147 #define PCI9111_REGISTER_SOFTWARE_TRIGGER 0x0E
148 #define PCI9111_REGISTER_INTERRUPT_CONTROL 0x0C
149 #define PCI9111_REGISTER_8254_COUNTER_0 0x40
150 #define PCI9111_REGISTER_8254_COUNTER_1 0x42
151 #define PCI9111_REGISTER_8254_COUNTER_2 0X44
152 #define PCI9111_REGISTER_8254_CONTROL 0x46
153 #define PCI9111_REGISTER_INTERRUPT_CLEAR 0x48
155 #define PCI9111_TRIGGER_MASK 0x0F
156 #define PCI9111_PTRG_OFF (0 << 3)
157 #define PCI9111_PTRG_ON (1 << 3)
158 #define PCI9111_EITS_EXTERNAL (1 << 2)
159 #define PCI9111_EITS_INTERNAL (0 << 2)
160 #define PCI9111_TPST_SOFTWARE_TRIGGER (0 << 1)
161 #define PCI9111_TPST_TIMER_PACER (1 << 1)
162 #define PCI9111_ASCAN_ON (1 << 0)
163 #define PCI9111_ASCAN_OFF (0 << 0)
165 #define PCI9111_ISC0_SET_IRQ_ON_ENDING_OF_AD_CONVERSION (0 << 0)
166 #define PCI9111_ISC0_SET_IRQ_ON_FIFO_HALF_FULL (1 << 0)
167 #define PCI9111_ISC1_SET_IRQ_ON_TIMER_TICK (0 << 1)
168 #define PCI9111_ISC1_SET_IRQ_ON_EXT_TRG (1 << 1)
169 #define PCI9111_FFEN_SET_FIFO_ENABLE (0 << 2)
170 #define PCI9111_FFEN_SET_FIFO_DISABLE (1 << 2)
172 #define PCI9111_CHANNEL_MASK 0x0F
174 #define PCI9111_RANGE_MASK 0x07
175 #define PCI9111_FIFO_EMPTY_MASK 0x10
176 #define PCI9111_FIFO_HALF_FULL_MASK 0x20
177 #define PCI9111_FIFO_FULL_MASK 0x40
178 #define PCI9111_AD_BUSY_MASK 0x80
180 #define PCI9111_IO_BASE dev->iobase
183 * Define inlined function
186 #define pci9111_trigger_and_autoscan_get() \
187 (inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK)&0x0F)
189 #define pci9111_trigger_and_autoscan_set(flags) \
190 outb(flags, PCI9111_IO_BASE+PCI9111_REGISTER_TRIGGER_MODE_CONTROL)
192 #define pci9111_interrupt_and_fifo_get() \
193 ((inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK) >> 4) &0x03)
195 #define pci9111_interrupt_and_fifo_set(flags) \
196 outb(flags, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL)
198 #define pci9111_interrupt_clear() \
199 outb(0, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CLEAR)
201 #define pci9111_software_trigger() \
202 outb(0, PCI9111_IO_BASE+PCI9111_REGISTER_SOFTWARE_TRIGGER)
204 #define pci9111_fifo_reset() \
205 outb(PCI9111_FFEN_SET_FIFO_ENABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \
206 outb(PCI9111_FFEN_SET_FIFO_DISABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \
207 outb(PCI9111_FFEN_SET_FIFO_ENABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL)
209 #define pci9111_is_fifo_full() \
210 ((inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)& \
211 PCI9111_FIFO_FULL_MASK)==0)
213 #define pci9111_is_fifo_half_full() \
214 ((inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)& \
215 PCI9111_FIFO_HALF_FULL_MASK)==0)
217 #define pci9111_is_fifo_empty() \
218 ((inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)& \
219 PCI9111_FIFO_EMPTY_MASK)==0)
221 #define pci9111_ai_channel_set(channel) \
222 outb((channel)&PCI9111_CHANNEL_MASK, PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_CONTROL)
224 #define pci9111_ai_channel_get() \
225 inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_READBACK)&PCI9111_CHANNEL_MASK
227 #define pci9111_ai_range_set(range) \
228 outb((range)&PCI9111_RANGE_MASK, PCI9111_IO_BASE+PCI9111_REGISTER_INPUT_SIGNAL_RANGE)
230 #define pci9111_ai_range_get() \
231 inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)&PCI9111_RANGE_MASK
233 #define pci9111_ai_get_data() \
234 ((inw(PCI9111_IO_BASE+PCI9111_REGISTER_AD_FIFO_VALUE)>>4)&PCI9111_AI_RESOLUTION_MASK) \
235 ^ PCI9111_AI_RESOLUTION_2_CMP_BIT
237 #define pci9111_hr_ai_get_data() \
238 (inw(PCI9111_IO_BASE+PCI9111_REGISTER_AD_FIFO_VALUE) & PCI9111_HR_AI_RESOLUTION_MASK) \
239 ^ PCI9111_HR_AI_RESOLUTION_2_CMP_BIT
241 #define pci9111_ao_set_data(data) \
242 outw(data&PCI9111_AO_RESOLUTION_MASK, PCI9111_IO_BASE+PCI9111_REGISTER_DA_OUTPUT)
244 #define pci9111_di_get_bits() \
245 inw(PCI9111_IO_BASE+PCI9111_REGISTER_DIGITAL_IO)
247 #define pci9111_do_set_bits(bits) \
248 outw(bits, PCI9111_IO_BASE+PCI9111_REGISTER_DIGITAL_IO)
250 #define pci9111_8254_control_set(flags) \
251 outb(flags, PCI9111_IO_BASE+PCI9111_REGISTER_8254_CONTROL)
253 #define pci9111_8254_counter_0_set(data) \
254 outb(data & 0xFF, PCI9111_IO_BASE+PCI9111_REGISTER_8254_COUNTER_0); \
255 outb((data >> 8) & 0xFF, PCI9111_IO_BASE+PCI9111_REGISTER_8254_COUNTER_0)
257 #define pci9111_8254_counter_1_set(data) \
258 outb(data & 0xFF, PCI9111_IO_BASE+PCI9111_REGISTER_8254_COUNTER_1); \
259 outb((data >> 8) & 0xFF, PCI9111_IO_BASE+PCI9111_REGISTER_8254_COUNTER_1)
261 #define pci9111_8254_counter_2_set(data) \
262 outb(data & 0xFF, PCI9111_IO_BASE+PCI9111_REGISTER_8254_COUNTER_2); \
263 outb((data >> 8) & 0xFF, PCI9111_IO_BASE+PCI9111_REGISTER_8254_COUNTER_2)
265 /* Function prototypes */
267 static int pci9111_attach(struct comedi_device *dev,
268 struct comedi_devconfig *it);
269 static int pci9111_detach(struct comedi_device *dev);
270 static void pci9111_ai_munge(struct comedi_device *dev,
271 struct comedi_subdevice *s, void *data,
272 unsigned int num_bytes,
273 unsigned int start_chan_index);
275 static const struct comedi_lrange pci9111_hr_ai_range = {
286 static DEFINE_PCI_DEVICE_TABLE(pci9111_pci_table) = {
288 PCI_VENDOR_ID_ADLINK, PCI9111_HR_DEVICE_ID, PCI_ANY_ID,
289 PCI_ANY_ID, 0, 0, 0},
290 /* { PCI_VENDOR_ID_ADLINK, PCI9111_HG_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, */
295 MODULE_DEVICE_TABLE(pci, pci9111_pci_table);
298 /* Board specification structure */
301 struct pci9111_board {
302 const char *name; /* driver name */
304 int ai_channel_nbr; /* num of A/D chans */
305 int ao_channel_nbr; /* num of D/A chans */
306 int ai_resolution; /* resolution of A/D */
307 int ai_resolution_mask;
308 int ao_resolution; /* resolution of D/A */
309 int ao_resolution_mask;
310 const struct comedi_lrange *ai_range_list; /* rangelist for A/D */
311 const struct comedi_lrange *ao_range_list; /* rangelist for D/A */
312 unsigned int ai_acquisition_period_min_ns;
315 static const struct pci9111_board pci9111_boards[] = {
317 .name = "pci9111_hr",
318 .device_id = PCI9111_HR_DEVICE_ID,
319 .ai_channel_nbr = PCI9111_AI_CHANNEL_NBR,
320 .ao_channel_nbr = PCI9111_AO_CHANNEL_NBR,
321 .ai_resolution = PCI9111_HR_AI_RESOLUTION,
322 .ai_resolution_mask = PCI9111_HR_AI_RESOLUTION_MASK,
323 .ao_resolution = PCI9111_AO_RESOLUTION,
324 .ao_resolution_mask = PCI9111_AO_RESOLUTION_MASK,
325 .ai_range_list = &pci9111_hr_ai_range,
326 .ao_range_list = &range_bipolar10,
327 .ai_acquisition_period_min_ns = PCI9111_AI_ACQUISITION_PERIOD_MIN_NS}
330 #define pci9111_board_nbr \
331 (sizeof(pci9111_boards)/sizeof(struct pci9111_board))
333 static struct comedi_driver pci9111_driver = {
334 .driver_name = PCI9111_DRIVER_NAME,
335 .module = THIS_MODULE,
336 .attach = pci9111_attach,
337 .detach = pci9111_detach,
340 COMEDI_PCI_INITCLEANUP(pci9111_driver, pci9111_pci_table);
342 /* Private data structure */
344 struct pci9111_private_data {
345 struct pci_dev *pci_device;
346 unsigned long io_range; /* PCI6503 io range */
348 unsigned long lcr_io_base; /* Local configuration register base address */
349 unsigned long lcr_io_range;
354 unsigned int scan_delay;
355 unsigned int chanlist_len;
356 unsigned int chunk_counter;
357 unsigned int chunk_num_samples;
359 int ao_readback; /* Last written analog output data */
361 int timer_divisor_1; /* Divisor values for the 8254 timer pacer */
364 int is_valid; /* Is device valid */
366 short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE];
369 #define dev_private ((struct pci9111_private_data *)dev->private)
371 /* ------------------------------------------------------------------ */
372 /* PLX9050 SECTION */
373 /* ------------------------------------------------------------------ */
375 #define PLX9050_REGISTER_INTERRUPT_CONTROL 0x4c
377 #define PLX9050_LINTI1_ENABLE (1 << 0)
378 #define PLX9050_LINTI1_ACTIVE_HIGH (1 << 1)
379 #define PLX9050_LINTI1_STATUS (1 << 2)
380 #define PLX9050_LINTI2_ENABLE (1 << 3)
381 #define PLX9050_LINTI2_ACTIVE_HIGH (1 << 4)
382 #define PLX9050_LINTI2_STATUS (1 << 5)
383 #define PLX9050_PCI_INTERRUPT_ENABLE (1 << 6)
384 #define PLX9050_SOFTWARE_INTERRUPT (1 << 7)
386 static void plx9050_interrupt_control(unsigned long io_base,
388 bool LINTi1_active_high,
390 bool LINTi2_active_high,
391 bool interrupt_enable)
396 flags |= PLX9050_LINTI1_ENABLE;
397 if (LINTi1_active_high)
398 flags |= PLX9050_LINTI1_ACTIVE_HIGH;
400 flags |= PLX9050_LINTI2_ENABLE;
401 if (LINTi2_active_high)
402 flags |= PLX9050_LINTI2_ACTIVE_HIGH;
404 if (interrupt_enable)
405 flags |= PLX9050_PCI_INTERRUPT_ENABLE;
407 outb(flags, io_base + PLX9050_REGISTER_INTERRUPT_CONTROL);
410 /* ------------------------------------------------------------------ */
411 /* MISCELLANEOUS SECTION */
412 /* ------------------------------------------------------------------ */
416 static void pci9111_timer_set(struct comedi_device *dev)
418 pci9111_8254_control_set(PCI9111_8254_COUNTER_0 |
419 PCI9111_8254_READ_LOAD_LSB_MSB |
420 PCI9111_8254_MODE_0 |
421 PCI9111_8254_BINARY_COUNTER);
423 pci9111_8254_control_set(PCI9111_8254_COUNTER_1 |
424 PCI9111_8254_READ_LOAD_LSB_MSB |
425 PCI9111_8254_MODE_2 |
426 PCI9111_8254_BINARY_COUNTER);
428 pci9111_8254_control_set(PCI9111_8254_COUNTER_2 |
429 PCI9111_8254_READ_LOAD_LSB_MSB |
430 PCI9111_8254_MODE_2 |
431 PCI9111_8254_BINARY_COUNTER);
435 pci9111_8254_counter_2_set(dev_private->timer_divisor_2);
436 pci9111_8254_counter_1_set(dev_private->timer_divisor_1);
439 enum pci9111_trigger_sources {
445 static void pci9111_trigger_source_set(struct comedi_device *dev,
446 enum pci9111_trigger_sources source)
450 flags = pci9111_trigger_and_autoscan_get() & 0x09;
454 flags |= PCI9111_EITS_INTERNAL | PCI9111_TPST_SOFTWARE_TRIGGER;
458 flags |= PCI9111_EITS_INTERNAL | PCI9111_TPST_TIMER_PACER;
462 flags |= PCI9111_EITS_EXTERNAL;
466 pci9111_trigger_and_autoscan_set(flags);
469 static void pci9111_pretrigger_set(struct comedi_device *dev, bool pretrigger)
473 flags = pci9111_trigger_and_autoscan_get() & 0x07;
476 flags |= PCI9111_PTRG_ON;
478 pci9111_trigger_and_autoscan_set(flags);
481 static void pci9111_autoscan_set(struct comedi_device *dev, bool autoscan)
485 flags = pci9111_trigger_and_autoscan_get() & 0x0e;
488 flags |= PCI9111_ASCAN_ON;
490 pci9111_trigger_and_autoscan_set(flags);
493 enum pci9111_ISC0_sources {
495 irq_on_fifo_half_full
498 enum pci9111_ISC1_sources {
500 irq_on_external_trigger
503 static void pci9111_interrupt_source_set(struct comedi_device *dev,
504 enum pci9111_ISC0_sources irq_0_source,
505 enum pci9111_ISC1_sources irq_1_source)
509 flags = pci9111_interrupt_and_fifo_get() & 0x04;
511 if (irq_0_source == irq_on_fifo_half_full)
512 flags |= PCI9111_ISC0_SET_IRQ_ON_FIFO_HALF_FULL;
514 if (irq_1_source == irq_on_external_trigger)
515 flags |= PCI9111_ISC1_SET_IRQ_ON_EXT_TRG;
517 pci9111_interrupt_and_fifo_set(flags);
520 /* ------------------------------------------------------------------ */
521 /* HARDWARE TRIGGERED ANALOG INPUT SECTION */
522 /* ------------------------------------------------------------------ */
524 /* Cancel analog input autoscan */
526 #undef AI_DO_CMD_DEBUG
528 static int pci9111_ai_cancel(struct comedi_device *dev,
529 struct comedi_subdevice *s)
531 /* Disable interrupts */
533 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true,
536 pci9111_trigger_source_set(dev, software);
538 pci9111_autoscan_set(dev, false);
540 pci9111_fifo_reset();
542 #ifdef AI_DO_CMD_DEBUG
543 printk(PCI9111_DRIVER_NAME ": ai_cancel\n");
549 /* Test analog input command */
551 #define pci9111_check_trigger_src(src, flags) \
554 if (!src || tmp != src) error++
557 pci9111_ai_do_cmd_test(struct comedi_device *dev,
558 struct comedi_subdevice *s, struct comedi_cmd *cmd)
562 int range, reference;
564 struct pci9111_board *board = (struct pci9111_board *)dev->board_ptr;
566 /* Step 1 : check if trigger are trivialy valid */
568 pci9111_check_trigger_src(cmd->start_src, TRIG_NOW);
569 pci9111_check_trigger_src(cmd->scan_begin_src,
570 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
571 pci9111_check_trigger_src(cmd->convert_src, TRIG_TIMER | TRIG_EXT);
572 pci9111_check_trigger_src(cmd->scan_end_src, TRIG_COUNT);
573 pci9111_check_trigger_src(cmd->stop_src, TRIG_COUNT | TRIG_NONE);
578 /* step 2 : make sure trigger sources are unique and mutually compatible */
580 if (cmd->start_src != TRIG_NOW)
583 if ((cmd->scan_begin_src != TRIG_TIMER) &&
584 (cmd->scan_begin_src != TRIG_FOLLOW) &&
585 (cmd->scan_begin_src != TRIG_EXT))
588 if ((cmd->convert_src != TRIG_TIMER) && (cmd->convert_src != TRIG_EXT)) {
591 if ((cmd->convert_src == TRIG_TIMER) &&
592 !((cmd->scan_begin_src == TRIG_TIMER) ||
593 (cmd->scan_begin_src == TRIG_FOLLOW))) {
596 if ((cmd->convert_src == TRIG_EXT) &&
597 !((cmd->scan_begin_src == TRIG_EXT) ||
598 (cmd->scan_begin_src == TRIG_FOLLOW))) {
602 if (cmd->scan_end_src != TRIG_COUNT)
604 if ((cmd->stop_src != TRIG_COUNT) && (cmd->stop_src != TRIG_NONE))
610 /* Step 3 : make sure arguments are trivialy compatible */
612 if (cmd->chanlist_len < 1) {
613 cmd->chanlist_len = 1;
617 if (cmd->chanlist_len > board->ai_channel_nbr) {
618 cmd->chanlist_len = board->ai_channel_nbr;
622 if ((cmd->start_src == TRIG_NOW) && (cmd->start_arg != 0)) {
627 if ((cmd->convert_src == TRIG_TIMER) &&
628 (cmd->convert_arg < board->ai_acquisition_period_min_ns)) {
629 cmd->convert_arg = board->ai_acquisition_period_min_ns;
632 if ((cmd->convert_src == TRIG_EXT) && (cmd->convert_arg != 0)) {
633 cmd->convert_arg = 0;
637 if ((cmd->scan_begin_src == TRIG_TIMER) &&
638 (cmd->scan_begin_arg < board->ai_acquisition_period_min_ns)) {
639 cmd->scan_begin_arg = board->ai_acquisition_period_min_ns;
642 if ((cmd->scan_begin_src == TRIG_FOLLOW) && (cmd->scan_begin_arg != 0)) {
643 cmd->scan_begin_arg = 0;
646 if ((cmd->scan_begin_src == TRIG_EXT) && (cmd->scan_begin_arg != 0)) {
647 cmd->scan_begin_arg = 0;
651 if ((cmd->scan_end_src == TRIG_COUNT) &&
652 (cmd->scan_end_arg != cmd->chanlist_len)) {
653 cmd->scan_end_arg = cmd->chanlist_len;
657 if ((cmd->stop_src == TRIG_COUNT) && (cmd->stop_arg < 1)) {
661 if ((cmd->stop_src == TRIG_NONE) && (cmd->stop_arg != 0)) {
669 /* Step 4 : fix up any arguments */
671 if (cmd->convert_src == TRIG_TIMER) {
672 tmp = cmd->convert_arg;
673 i8253_cascade_ns_to_timer_2div(PCI9111_8254_CLOCK_PERIOD_NS,
674 &(dev_private->timer_divisor_1),
675 &(dev_private->timer_divisor_2),
677 cmd->flags & TRIG_ROUND_MASK);
678 if (tmp != cmd->convert_arg)
681 /* There's only one timer on this card, so the scan_begin timer must */
682 /* be a multiple of chanlist_len*convert_arg */
684 if (cmd->scan_begin_src == TRIG_TIMER) {
686 unsigned int scan_begin_min;
687 unsigned int scan_begin_arg;
688 unsigned int scan_factor;
690 scan_begin_min = cmd->chanlist_len * cmd->convert_arg;
692 if (cmd->scan_begin_arg != scan_begin_min) {
693 if (scan_begin_min < cmd->scan_begin_arg) {
695 cmd->scan_begin_arg / scan_begin_min;
696 scan_begin_arg = scan_factor * scan_begin_min;
697 if (cmd->scan_begin_arg != scan_begin_arg) {
698 cmd->scan_begin_arg = scan_begin_arg;
702 cmd->scan_begin_arg = scan_begin_min;
711 /* Step 5 : check channel list */
715 range = CR_RANGE(cmd->chanlist[0]);
716 reference = CR_AREF(cmd->chanlist[0]);
718 if (cmd->chanlist_len > 1) {
719 for (i = 0; i < cmd->chanlist_len; i++) {
720 if (CR_CHAN(cmd->chanlist[i]) != i) {
722 "entries in chanlist must be consecutive "
723 "channels,counting upwards from 0\n");
726 if (CR_RANGE(cmd->chanlist[i]) != range) {
728 "entries in chanlist must all have the same gain\n");
731 if (CR_AREF(cmd->chanlist[i]) != reference) {
733 "entries in chanlist must all have the same reference\n");
738 if ((CR_CHAN(cmd->chanlist[0]) >
739 (board->ai_channel_nbr - 1))
740 || (CR_CHAN(cmd->chanlist[0]) < 0)) {
742 "channel number is out of limits\n");
755 /* Analog input command */
757 static int pci9111_ai_do_cmd(struct comedi_device *dev,
758 struct comedi_subdevice *subdevice)
760 struct comedi_cmd *async_cmd = &subdevice->async->cmd;
764 "no irq assigned for PCI9111, cannot do hardware conversion");
767 /* Set channel scan limit */
768 /* PCI9111 allows only scanning from channel 0 to channel n */
769 /* TODO: handle the case of an external multiplexer */
771 if (async_cmd->chanlist_len > 1) {
772 pci9111_ai_channel_set((async_cmd->chanlist_len) - 1);
773 pci9111_autoscan_set(dev, true);
775 pci9111_ai_channel_set(CR_CHAN(async_cmd->chanlist[0]));
776 pci9111_autoscan_set(dev, false);
780 /* This is the same gain on every channel */
782 pci9111_ai_range_set(CR_RANGE(async_cmd->chanlist[0]));
786 switch (async_cmd->stop_src) {
788 dev_private->stop_counter =
789 async_cmd->stop_arg * async_cmd->chanlist_len;
790 dev_private->stop_is_none = 0;
794 dev_private->stop_counter = 0;
795 dev_private->stop_is_none = 1;
799 comedi_error(dev, "Invalid stop trigger");
803 /* Set timer pacer */
805 dev_private->scan_delay = 0;
806 switch (async_cmd->convert_src) {
808 i8253_cascade_ns_to_timer_2div(PCI9111_8254_CLOCK_PERIOD_NS,
809 &(dev_private->timer_divisor_1),
810 &(dev_private->timer_divisor_2),
811 &(async_cmd->convert_arg),
813 flags & TRIG_ROUND_MASK);
814 #ifdef AI_DO_CMD_DEBUG
815 printk(PCI9111_DRIVER_NAME ": divisors = %d, %d\n",
816 dev_private->timer_divisor_1,
817 dev_private->timer_divisor_2);
820 pci9111_trigger_source_set(dev, software);
821 pci9111_timer_set(dev);
822 pci9111_fifo_reset();
823 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full,
825 pci9111_trigger_source_set(dev, timer_pacer);
826 plx9050_interrupt_control(dev_private->lcr_io_base, true, true,
829 dev_private->scan_delay =
830 (async_cmd->scan_begin_arg / (async_cmd->convert_arg *
831 async_cmd->chanlist_len)) - 1;
837 pci9111_trigger_source_set(dev, external);
838 pci9111_fifo_reset();
839 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full,
841 plx9050_interrupt_control(dev_private->lcr_io_base, true, true,
847 comedi_error(dev, "Invalid convert trigger");
851 dev_private->stop_counter *= (1 + dev_private->scan_delay);
852 dev_private->chanlist_len = async_cmd->chanlist_len;
853 dev_private->chunk_counter = 0;
854 dev_private->chunk_num_samples =
855 dev_private->chanlist_len * (1 + dev_private->scan_delay);
857 #ifdef AI_DO_CMD_DEBUG
858 printk(PCI9111_DRIVER_NAME ": start interruptions!\n");
859 printk(PCI9111_DRIVER_NAME ": trigger source = %2x\n",
860 pci9111_trigger_and_autoscan_get());
861 printk(PCI9111_DRIVER_NAME ": irq source = %2x\n",
862 pci9111_interrupt_and_fifo_get());
863 printk(PCI9111_DRIVER_NAME ": ai_do_cmd\n");
864 printk(PCI9111_DRIVER_NAME ": stop counter = %d\n",
865 dev_private->stop_counter);
866 printk(PCI9111_DRIVER_NAME ": scan delay = %d\n",
867 dev_private->scan_delay);
868 printk(PCI9111_DRIVER_NAME ": chanlist_len = %d\n",
869 dev_private->chanlist_len);
870 printk(PCI9111_DRIVER_NAME ": chunk num samples = %d\n",
871 dev_private->chunk_num_samples);
877 static void pci9111_ai_munge(struct comedi_device *dev,
878 struct comedi_subdevice *s, void *data,
879 unsigned int num_bytes,
880 unsigned int start_chan_index)
882 unsigned int i, num_samples = num_bytes / sizeof(short);
885 ((struct pci9111_board *)dev->board_ptr)->ai_resolution;
887 for (i = 0; i < num_samples; i++) {
888 if (resolution == PCI9111_HR_AI_RESOLUTION)
890 (array[i] & PCI9111_HR_AI_RESOLUTION_MASK) ^
891 PCI9111_HR_AI_RESOLUTION_2_CMP_BIT;
894 ((array[i] >> 4) & PCI9111_AI_RESOLUTION_MASK) ^
895 PCI9111_AI_RESOLUTION_2_CMP_BIT;
899 /* ------------------------------------------------------------------ */
900 /* INTERRUPT SECTION */
901 /* ------------------------------------------------------------------ */
903 #undef INTERRUPT_DEBUG
905 static irqreturn_t pci9111_interrupt(int irq, void *p_device)
907 struct comedi_device *dev = p_device;
908 struct comedi_subdevice *subdevice = dev->read_subdev;
909 struct comedi_async *async;
910 unsigned long irq_flags;
911 unsigned char intcsr;
913 if (!dev->attached) {
914 /* Ignore interrupt before device fully attached. */
915 /* Might not even have allocated subdevices yet! */
919 async = subdevice->async;
921 spin_lock_irqsave(&dev->spinlock, irq_flags);
923 /* Check if we are source of interrupt */
924 intcsr = inb(dev_private->lcr_io_base +
925 PLX9050_REGISTER_INTERRUPT_CONTROL);
926 if (!(((intcsr & PLX9050_PCI_INTERRUPT_ENABLE) != 0)
927 && (((intcsr & (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS))
928 == (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS))
929 || ((intcsr & (PLX9050_LINTI2_ENABLE | PLX9050_LINTI2_STATUS))
930 == (PLX9050_LINTI2_ENABLE | PLX9050_LINTI2_STATUS))))) {
931 /* Not the source of the interrupt. */
932 /* (N.B. not using PLX9050_SOFTWARE_INTERRUPT) */
933 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
937 if ((intcsr & (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) ==
938 (PLX9050_LINTI1_ENABLE | PLX9050_LINTI1_STATUS)) {
939 /* Interrupt comes from fifo_half-full signal */
941 if (pci9111_is_fifo_full()) {
942 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
943 comedi_error(dev, PCI9111_DRIVER_NAME " fifo overflow");
944 pci9111_interrupt_clear();
945 pci9111_ai_cancel(dev, subdevice);
946 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
947 comedi_event(dev, subdevice);
952 if (pci9111_is_fifo_half_full()) {
953 unsigned int num_samples;
954 unsigned int bytes_written = 0;
956 #ifdef INTERRUPT_DEBUG
957 printk(PCI9111_DRIVER_NAME ": fifo is half full\n");
961 PCI9111_FIFO_HALF_SIZE >
962 dev_private->stop_counter
964 stop_is_none ? dev_private->stop_counter :
965 PCI9111_FIFO_HALF_SIZE;
966 insw(PCI9111_IO_BASE + PCI9111_REGISTER_AD_FIFO_VALUE,
967 dev_private->ai_bounce_buffer, num_samples);
969 if (dev_private->scan_delay < 1) {
971 cfc_write_array_to_buffer(subdevice,
980 while (position < num_samples) {
981 if (dev_private->chunk_counter <
982 dev_private->chanlist_len) {
984 dev_private->chanlist_len -
985 dev_private->chunk_counter;
988 num_samples - position)
994 cfc_write_array_to_buffer
996 dev_private->ai_bounce_buffer
998 to_read * sizeof(short));
1001 dev_private->chunk_num_samples
1003 dev_private->chunk_counter;
1005 num_samples - position)
1011 sizeof(short) * to_read;
1014 position += to_read;
1015 dev_private->chunk_counter += to_read;
1017 if (dev_private->chunk_counter >=
1018 dev_private->chunk_num_samples)
1019 dev_private->chunk_counter = 0;
1023 dev_private->stop_counter -=
1024 bytes_written / sizeof(short);
1028 if ((dev_private->stop_counter == 0) && (!dev_private->stop_is_none)) {
1029 async->events |= COMEDI_CB_EOA;
1030 pci9111_ai_cancel(dev, subdevice);
1033 /* Very important, otherwise another interrupt request will be inserted
1034 * and will cause driver hangs on processing interrupt event. */
1036 pci9111_interrupt_clear();
1038 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
1040 comedi_event(dev, subdevice);
1045 /* ------------------------------------------------------------------ */
1046 /* INSTANT ANALOG INPUT OUTPUT SECTION */
1047 /* ------------------------------------------------------------------ */
1049 /* analog instant input */
1051 #undef AI_INSN_DEBUG
1053 static int pci9111_ai_insn_read(struct comedi_device *dev,
1054 struct comedi_subdevice *subdevice,
1055 struct comedi_insn *insn, unsigned int *data)
1058 ((struct pci9111_board *)dev->board_ptr)->ai_resolution;
1062 #ifdef AI_INSN_DEBUG
1063 printk(PCI9111_DRIVER_NAME ": ai_insn set c/r/n = %2x/%2x/%2x\n",
1064 CR_CHAN((&insn->chanspec)[0]),
1065 CR_RANGE((&insn->chanspec)[0]), insn->n);
1068 pci9111_ai_channel_set(CR_CHAN((&insn->chanspec)[0]));
1070 if ((pci9111_ai_range_get()) != CR_RANGE((&insn->chanspec)[0])) {
1071 pci9111_ai_range_set(CR_RANGE((&insn->chanspec)[0]));
1074 pci9111_fifo_reset();
1076 for (i = 0; i < insn->n; i++) {
1077 pci9111_software_trigger();
1079 timeout = PCI9111_AI_INSTANT_READ_TIMEOUT;
1082 if (!pci9111_is_fifo_empty())
1083 goto conversion_done;
1086 comedi_error(dev, "A/D read timeout");
1088 pci9111_fifo_reset();
1093 if (resolution == PCI9111_HR_AI_RESOLUTION) {
1094 data[i] = pci9111_hr_ai_get_data();
1096 data[i] = pci9111_ai_get_data();
1100 #ifdef AI_INSN_DEBUG
1101 printk(PCI9111_DRIVER_NAME ": ai_insn get c/r/t = %2x/%2x/%2x\n",
1102 pci9111_ai_channel_get(),
1103 pci9111_ai_range_get(), pci9111_trigger_and_autoscan_get());
1109 /* Analog instant output */
1112 pci9111_ao_insn_write(struct comedi_device *dev,
1113 struct comedi_subdevice *s, struct comedi_insn *insn,
1118 for (i = 0; i < insn->n; i++) {
1119 pci9111_ao_set_data(data[i]);
1120 dev_private->ao_readback = data[i];
1126 /* Analog output readback */
1128 static int pci9111_ao_insn_read(struct comedi_device *dev,
1129 struct comedi_subdevice *s,
1130 struct comedi_insn *insn, unsigned int *data)
1134 for (i = 0; i < insn->n; i++) {
1135 data[i] = dev_private->ao_readback & PCI9111_AO_RESOLUTION_MASK;
1141 /* ------------------------------------------------------------------ */
1142 /* DIGITAL INPUT OUTPUT SECTION */
1143 /* ------------------------------------------------------------------ */
1145 /* Digital inputs */
1147 static int pci9111_di_insn_bits(struct comedi_device *dev,
1148 struct comedi_subdevice *subdevice,
1149 struct comedi_insn *insn, unsigned int *data)
1153 bits = pci9111_di_get_bits();
1159 /* Digital outputs */
1161 static int pci9111_do_insn_bits(struct comedi_device *dev,
1162 struct comedi_subdevice *subdevice,
1163 struct comedi_insn *insn, unsigned int *data)
1167 /* Only set bits that have been masked */
1168 /* data[0] = mask */
1169 /* data[1] = bit state */
1171 data[0] &= PCI9111_DO_MASK;
1173 bits = subdevice->state;
1175 bits |= data[0] & data[1];
1176 subdevice->state = bits;
1178 pci9111_do_set_bits(bits);
1185 /* ------------------------------------------------------------------ */
1186 /* INITIALISATION SECTION */
1187 /* ------------------------------------------------------------------ */
1191 static int pci9111_reset(struct comedi_device *dev)
1193 /* Set trigger source to software */
1195 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true,
1198 pci9111_trigger_source_set(dev, software);
1199 pci9111_pretrigger_set(dev, false);
1200 pci9111_autoscan_set(dev, false);
1202 /* Reset 8254 chip */
1204 dev_private->timer_divisor_1 = 0;
1205 dev_private->timer_divisor_2 = 0;
1207 pci9111_timer_set(dev);
1213 /* - Register PCI device */
1214 /* - Declare device driver capability */
1216 static int pci9111_attach(struct comedi_device *dev,
1217 struct comedi_devconfig *it)
1219 struct comedi_subdevice *subdevice;
1220 unsigned long io_base, io_range, lcr_io_base, lcr_io_range;
1221 struct pci_dev *pci_device;
1223 const struct pci9111_board *board;
1225 if (alloc_private(dev, sizeof(struct pci9111_private_data)) < 0) {
1228 /* Probe the device to determine what device in the series it is. */
1230 printk("comedi%d: " PCI9111_DRIVER_NAME " driver\n", dev->minor);
1232 for (pci_device = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
1234 pci_device = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pci_device)) {
1235 if (pci_device->vendor == PCI_VENDOR_ID_ADLINK) {
1236 for (i = 0; i < pci9111_board_nbr; i++) {
1237 if (pci9111_boards[i].device_id ==
1238 pci_device->device) {
1239 /* was a particular bus/slot requested? */
1240 if ((it->options[0] != 0)
1241 || (it->options[1] != 0)) {
1242 /* are we on the wrong bus/slot? */
1243 if (pci_device->bus->number !=
1246 PCI_SLOT(pci_device->devfn)
1247 != it->options[1]) {
1252 dev->board_ptr = pci9111_boards + i;
1254 (struct pci9111_board *)
1256 dev_private->pci_device = pci_device;
1263 printk("comedi%d: no supported board found! (req. bus/slot : %d/%d)\n",
1264 dev->minor, it->options[0], it->options[1]);
1269 printk("comedi%d: found %s (b:s:f=%d:%d:%d) , irq=%d\n",
1271 pci9111_boards[i].name,
1272 pci_device->bus->number,
1273 PCI_SLOT(pci_device->devfn),
1274 PCI_FUNC(pci_device->devfn), pci_device->irq);
1276 /* TODO: Warn about non-tested boards. */
1278 switch (board->device_id) {
1281 /* Read local configuration register base address [PCI_BASE_ADDRESS #1]. */
1283 lcr_io_base = pci_resource_start(pci_device, 1);
1284 lcr_io_range = pci_resource_len(pci_device, 1);
1287 ("comedi%d: local configuration registers at address 0x%4lx [0x%4lx]\n",
1288 dev->minor, lcr_io_base, lcr_io_range);
1290 /* Enable PCI device and request regions */
1291 if (comedi_pci_enable(pci_device, PCI9111_DRIVER_NAME) < 0) {
1293 ("comedi%d: Failed to enable PCI device and request regions\n",
1297 /* Read PCI6308 register base address [PCI_BASE_ADDRESS #2]. */
1299 io_base = pci_resource_start(pci_device, 2);
1300 io_range = pci_resource_len(pci_device, 2);
1302 printk("comedi%d: 6503 registers at address 0x%4lx [0x%4lx]\n",
1303 dev->minor, io_base, io_range);
1305 dev->iobase = io_base;
1306 dev->board_name = board->name;
1307 dev_private->io_range = io_range;
1308 dev_private->is_valid = 0;
1309 dev_private->lcr_io_base = lcr_io_base;
1310 dev_private->lcr_io_range = lcr_io_range;
1317 if (pci_device->irq > 0) {
1318 if (request_irq(pci_device->irq, pci9111_interrupt,
1319 IRQF_SHARED, PCI9111_DRIVER_NAME, dev) != 0) {
1320 printk("comedi%d: unable to allocate irq %u\n",
1321 dev->minor, pci_device->irq);
1325 dev->irq = pci_device->irq;
1327 /* TODO: Add external multiplexer setup (according to option[2]). */
1329 error = alloc_subdevices(dev, 4);
1333 subdevice = dev->subdevices + 0;
1334 dev->read_subdev = subdevice;
1336 subdevice->type = COMEDI_SUBD_AI;
1337 subdevice->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
1339 /* TODO: Add external multiplexer data */
1340 /* if (devpriv->usemux) { subdevice->n_chan = devpriv->usemux; } */
1341 /* else { subdevice->n_chan = this_board->n_aichan; } */
1343 subdevice->n_chan = board->ai_channel_nbr;
1344 subdevice->maxdata = board->ai_resolution_mask;
1345 subdevice->len_chanlist = board->ai_channel_nbr;
1346 subdevice->range_table = board->ai_range_list;
1347 subdevice->cancel = pci9111_ai_cancel;
1348 subdevice->insn_read = pci9111_ai_insn_read;
1349 subdevice->do_cmdtest = pci9111_ai_do_cmd_test;
1350 subdevice->do_cmd = pci9111_ai_do_cmd;
1351 subdevice->munge = pci9111_ai_munge;
1353 subdevice = dev->subdevices + 1;
1354 subdevice->type = COMEDI_SUBD_AO;
1355 subdevice->subdev_flags = SDF_WRITABLE | SDF_COMMON;
1356 subdevice->n_chan = board->ao_channel_nbr;
1357 subdevice->maxdata = board->ao_resolution_mask;
1358 subdevice->len_chanlist = board->ao_channel_nbr;
1359 subdevice->range_table = board->ao_range_list;
1360 subdevice->insn_write = pci9111_ao_insn_write;
1361 subdevice->insn_read = pci9111_ao_insn_read;
1363 subdevice = dev->subdevices + 2;
1364 subdevice->type = COMEDI_SUBD_DI;
1365 subdevice->subdev_flags = SDF_READABLE;
1366 subdevice->n_chan = PCI9111_DI_CHANNEL_NBR;
1367 subdevice->maxdata = 1;
1368 subdevice->range_table = &range_digital;
1369 subdevice->insn_bits = pci9111_di_insn_bits;
1371 subdevice = dev->subdevices + 3;
1372 subdevice->type = COMEDI_SUBD_DO;
1373 subdevice->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1374 subdevice->n_chan = PCI9111_DO_CHANNEL_NBR;
1375 subdevice->maxdata = 1;
1376 subdevice->range_table = &range_digital;
1377 subdevice->insn_bits = pci9111_do_insn_bits;
1379 dev_private->is_valid = 1;
1386 static int pci9111_detach(struct comedi_device *dev)
1390 if (dev->private != 0) {
1391 if (dev_private->is_valid)
1395 /* Release previously allocated irq */
1397 if (dev->irq != 0) {
1398 free_irq(dev->irq, dev);
1401 if (dev_private != 0 && dev_private->pci_device != 0) {
1403 comedi_pci_disable(dev_private->pci_device);
1405 pci_dev_put(dev_private->pci_device);