drivers/staging/brcm80211/sys/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef WLC_LOW
  18 #error "This file needs WLC_LOW"
  19 #endif
  20
  21 #include <linux/kernel.h>
  22 #include <wlc_cfg.h>
  23 #include <linuxver.h>
  24 #include <bcmdefs.h>
  25 #include <osl.h>
  26 #include <proto/802.11.h>
  27 #include <bcmwifi.h>
  28 #include <bcmutils.h>
  29 #include <siutils.h>
  30 #include <bcmendian.h>
  31 #include <wlioctl.h>
  32 #include <sbconfig.h>
  33 #include <sbchipc.h>
  34 #include <pcicfg.h>
  35 #include <sbhndpio.h>
  36 #include <sbhnddma.h>
  37 #include <hnddma.h>
  38 #include <hndpmu.h>
  39 #include <d11.h>
  40 #include <wlc_rate.h>
  41 #include <wlc_pub.h>
  42 #include <wlc_channel.h>
  43 #include <bcmsrom.h>
  44 #include <wlc_key.h>
  45 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
  46  * dependencies. Need to include these to files to allow a clean include of wlc.h
  47  * with WLC_HIGH defined.
  48  * At some point we may be able to skip the include of wlc.h and instead just
  49  * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
  50  */
  51 #include <wlc_mac80211.h>
  52 #include <wlc_bmac.h>
  53 #include <wlc_phy_shim.h>
  54 #include <wlc_phy_hal.h>
  55 #include <wl_export.h>
  56 #include "wl_ucode.h"
  57 #include "d11ucode_ext.h"
  58 #ifdef BCMSDIO
  59 #include <bcmsdh.h>
  60 #endif
  61 #include <bcmotp.h>
  62
  63 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
  64  * functions defined in the headers below. We should be eliminating those calls and
  65  * will be able to delete these include lines.
  66  */
  67 #include <wlc_antsel.h>
  68
  69 #include <pcie_core.h>
  70
  71 #include <wlc_alloc.h>
  72
  73 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  74
  75 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  76 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  77 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  78 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  79
  80 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  81
  82 #ifndef BMAC_DUP_TO_REMOVE
  83 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  84
  85 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  86
  87 #endif                          /* BMAC_DUP_TO_REMOVE */
  88
  89 #define DMAREG(wlc_hw, direction, fifonum)      (D11REV_LT(wlc_hw->corerev, 11) ? \
  90         ((direction == DMA_TX) ? \
  91                 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
  92                 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
  93         ((direction == DMA_TX) ? \
  94                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
  95                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
  96
  97 /*
  98  * The following table lists the buffer memory allocated to xmt fifos in HW.
  99  * the size is in units of 256bytes(one block), total size is HW dependent
 100  * ucode has default fifo partition, sw can overwrite if necessary
 101  *
 102  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 103  * the twiki is updated before making changes.
 104  */
 105
 106 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
 107
 108 static u16 xmtfifo_sz[][NFIFO] = {
 109         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 110         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 111         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 112         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 113         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 114 };
 115
 116 static void wlc_clkctl_clk(wlc_hw_info_t *wlc, uint mode);
 117 static void wlc_coreinit(wlc_info_t *wlc);
 118
 119 /* used by wlc_wakeucode_init() */
 120 static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits);
 121 static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
 122                             const uint nbytes);
 123 static void wlc_ucode_download(wlc_hw_info_t *wlc);
 124 static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw);
 125
 126 /* used by wlc_dpc() */
 127 static bool wlc_bmac_dotxstatus(wlc_hw_info_t *wlc, tx_status_t *txs,
 128                                 u32 s2);
 129 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc);
 130 static bool wlc_bmac_txstatus(wlc_hw_info_t *wlc, bool bound, bool *fatal);
 131 static bool wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound);
 132
 133 /* used by wlc_down() */
 134 static void wlc_flushqueues(wlc_info_t *wlc);
 135
 136 static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs);
 137 static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw);
 138 static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw);
 139
 140 /* Low Level Prototypes */
 141 static u16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset,
 142                                    u32 sel);
 143 static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v,
 144                                   u32 sel);
 145 static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme);
 146 static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw);
 147 static void wlc_ucode_bsinit(wlc_hw_info_t *wlc_hw);
 148 static bool wlc_validboardtype(wlc_hw_info_t *wlc);
 149 static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw);
 150 static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw);
 151 static void wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init);
 152 static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw);
 153 static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw);
 154 static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw);
 155 static u32 wlc_wlintrsoff(wlc_info_t *wlc);
 156 static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask);
 157 static void wlc_gpio_init(wlc_info_t *wlc);
 158 static void wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn,
 159                                       int len);
 160 static void wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn,
 161                                       int len);
 162 static void wlc_bmac_bsinit(wlc_info_t *wlc, chanspec_t chanspec);
 163 static u32 wlc_setband_inact(wlc_info_t *wlc, uint bandunit);
 164 static void wlc_bmac_setband(wlc_hw_info_t *wlc_hw, uint bandunit,
 165                              chanspec_t chanspec);
 166 static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot);
 167 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw);
 168 static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw,
 169                                              u8 rate);
 170
 171 /* === Low Level functions === */
 172
 173 void wlc_bmac_set_shortslot(wlc_hw_info_t *wlc_hw, bool shortslot)
 174 {
 175         wlc_hw->shortslot = shortslot;
 176
 177         if (BAND_2G(wlc_hw->band->bandtype) && wlc_hw->up) {
 178                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 179                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 180                 wlc_enable_mac(wlc_hw->wlc);
 181         }
 182 }
 183
 184 /*
 185  * Update the slot timing for standard 11b/g (20us slots)
 186  * or shortslot 11g (9us slots)
 187  * The PSM needs to be suspended for this call.
 188  */
 189 static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot)
 190 {
 191         osl_t *osh;
 192         d11regs_t *regs;
 193
 194         osh = wlc_hw->osh;
 195         regs = wlc_hw->regs;
 196
 197         if (shortslot) {
 198                 /* 11g short slot: 11a timing */
 199                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 200                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 201         } else {
 202                 /* 11g long slot: 11b timing */
 203                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 204                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 205         }
 206 }
 207
 208 static void WLBANDINITFN(wlc_ucode_bsinit) (wlc_hw_info_t *wlc_hw)
 209 {
 210         /* init microcode host flags */
 211         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 212
 213         /* do band-specific ucode IHR, SHM, and SCR inits */
 214         if (D11REV_IS(wlc_hw->corerev, 23)) {
 215                 if (WLCISNPHY(wlc_hw->band)) {
 216                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 217                 } else {
 218                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
 219                                   __func__, wlc_hw->unit, wlc_hw->corerev));
 220                 }
 221         } else {
 222                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 223                         if (WLCISLCNPHY(wlc_hw->band)) {
 224                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 225                         } else
 226                                 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n", __func__, wlc_hw->unit, wlc_hw->corerev));
 227                 } else {
 228                         WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
 229                                   __func__, wlc_hw->unit, wlc_hw->corerev));
 230                 }
 231         }
 232 }
 233
 234 /* switch to new band but leave it inactive */
 235 static u32 WLBANDINITFN(wlc_setband_inact) (wlc_info_t *wlc, uint bandunit)
 236 {
 237         wlc_hw_info_t *wlc_hw = wlc->hw;
 238         u32 macintmask;
 239         u32 tmp;
 240
 241         WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw->unit));
 242
 243         ASSERT(bandunit != wlc_hw->band->bandunit);
 244         ASSERT(si_iscoreup(wlc_hw->sih));
 245         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 246                0);
 247
 248         /* disable interrupts */
 249         macintmask = wl_intrsoff(wlc->wl);
 250
 251         /* radio off */
 252         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 253
 254         ASSERT(wlc_hw->clk);
 255
 256         if (D11REV_LT(wlc_hw->corerev, 17))
 257                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
 258
 259         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 260
 261         wlc_setxband(wlc_hw, bandunit);
 262
 263         return macintmask;
 264 }
 265
 266 /* Process received frames */
 267 /*
 268  * Return true if more frames need to be processed. false otherwise.
 269  * Param 'bound' indicates max. # frames to process before break out.
 270  */
 271 static bool BCMFASTPATH
 272 wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound)
 273 {
 274         void *p;
 275         void *head = NULL;
 276         void *tail = NULL;
 277         uint n = 0;
 278         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 279         u32 tsf_h, tsf_l;
 280         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 281
 282         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
 283         /* gather received frames */
 284         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 285
 286                 if (!tail)
 287                         head = tail = p;
 288                 else {
 289                         PKTSETLINK(tail, p);
 290                         tail = p;
 291                 }
 292
 293                 /* !give others some time to run! */
 294                 if (++n >= bound_limit)
 295                         break;
 296         }
 297
 298         /* get the TSF REG reading */
 299         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 300
 301         /* post more rbufs */
 302         dma_rxfill(wlc_hw->di[fifo]);
 303
 304         /* process each frame */
 305         while ((p = head) != NULL) {
 306                 head = PKTLINK(head);
 307                 PKTSETLINK(p, NULL);
 308
 309                 /* record the tsf_l in wlc_rxd11hdr */
 310                 wlc_rxhdr = (wlc_d11rxhdr_t *) PKTDATA(p);
 311                 wlc_rxhdr->tsf_l = htol32(tsf_l);
 312
 313                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 314                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 315
 316                 wlc_recv(wlc_hw->wlc, p);
 317         }
 318
 319         return n >= bound_limit;
 320 }
 321
 322 /* second-level interrupt processing
 323  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 324  *   Param 'bounded' indicates if applicable loops should be bounded.
 325  */
 326 bool BCMFASTPATH wlc_dpc(wlc_info_t *wlc, bool bounded)
 327 {
 328         u32 macintstatus;
 329         wlc_hw_info_t *wlc_hw = wlc->hw;
 330         d11regs_t *regs = wlc_hw->regs;
 331         bool fatal = false;
 332
 333         if (DEVICEREMOVED(wlc)) {
 334                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
 335                 wl_down(wlc->wl);
 336                 return false;
 337         }
 338
 339         /* grab and clear the saved software intstatus bits */
 340         macintstatus = wlc->macintstatus;
 341         wlc->macintstatus = 0;
 342
 343         WL_TRACE(("wl%d: wlc_dpc: macintstatus 0x%x\n", wlc_hw->unit,
 344                   macintstatus));
 345
 346         if (macintstatus & MI_PRQ) {
 347                 /* Process probe request FIFO */
 348                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 349         }
 350
 351         /* BCN template is available */
 352         /* ZZZ: Use AP_ACTIVE ? */
 353         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 354             && (macintstatus & MI_BCNTPL)) {
 355                 wlc_update_beacon(wlc);
 356         }
 357
 358         /* PMQ entry addition */
 359         if (macintstatus & MI_PMQ) {
 360         }
 361
 362         /* tx status */
 363         if (macintstatus & MI_TFS) {
 364                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 365                         wlc->macintstatus |= MI_TFS;
 366                 if (fatal) {
 367                         WL_ERROR(("MI_TFS: fatal\n"));
 368                         goto fatal;
 369                 }
 370         }
 371
 372         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 373                 wlc_tbtt(wlc, regs);
 374
 375         /* ATIM window end */
 376         if (macintstatus & MI_ATIMWINEND) {
 377                 WL_TRACE(("wlc_isr: end of ATIM window\n"));
 378
 379                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 380                 wlc->qvalid = 0;
 381         }
 382
 383         /* phy tx error */
 384         if (macintstatus & MI_PHYTXERR) {
 385                 WLCNTINCR(wlc->pub->_cnt->txphyerr);
 386         }
 387
 388         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 389         if (macintstatus & MI_DMAINT) {
 390                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 391                         wlc->macintstatus |= MI_DMAINT;
 392                 }
 393         }
 394
 395         /* TX FIFO suspend/flush completion */
 396         if (macintstatus & MI_TXSTOP) {
 397                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 398                         /*      WL_ERROR(("dpc: fifo_suspend_comlete\n")); */
 399                 }
 400         }
 401
 402         /* noise sample collected */
 403         if (macintstatus & MI_BG_NOISE) {
 404                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 405         }
 406
 407         if (macintstatus & MI_GP0) {
 408                 WL_ERROR(("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now));
 409
 410                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 411                             __func__, CHIPID(wlc_hw->sih->chip),
 412                             CHIPREV(wlc_hw->sih->chiprev));
 413
 414                 WLCNTINCR(wlc->pub->_cnt->psmwds);
 415
 416                 /* big hammer */
 417                 wl_init(wlc->wl);
 418         }
 419
 420         /* gptimer timeout */
 421         if (macintstatus & MI_TO) {
 422                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 423         }
 424
 425         if (macintstatus & MI_RFDISABLE) {
 426 #if defined(BCMDBG)
 427                 u32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD;
 428 #endif
 429
 430                 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw->unit, rfd));
 431
 432                 WLCNTINCR(wlc->pub->_cnt->rfdisable);
 433         }
 434
 435         /* send any enq'd tx packets. Just makes sure to jump start tx */
 436         if (!pktq_empty(&wlc->active_queue->q))
 437                 wlc_send_q(wlc, wlc->active_queue);
 438
 439         ASSERT(wlc_ps_check(wlc));
 440
 441         /* make sure the bound indication and the implementation are in sync */
 442         ASSERT(bounded == true || wlc->macintstatus == 0);
 443
 444         /* it isn't done and needs to be resched if macintstatus is non-zero */
 445         return wlc->macintstatus != 0;
 446
 447  fatal:
 448         wl_init(wlc->wl);
 449         return wlc->macintstatus != 0;
 450 }
 451
 452 /* common low-level watchdog code */
 453 void wlc_bmac_watchdog(void *arg)
 454 {
 455         wlc_info_t *wlc = (wlc_info_t *) arg;
 456         wlc_hw_info_t *wlc_hw = wlc->hw;
 457
 458         WL_TRACE(("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit));
 459
 460         if (!wlc_hw->up)
 461                 return;
 462
 463         /* increment second count */
 464         wlc_hw->now++;
 465
 466         /* Check for FIFO error interrupts */
 467         wlc_bmac_fifoerrors(wlc_hw);
 468
 469         /* make sure RX dma has buffers */
 470         dma_rxfill(wlc->hw->di[RX_FIFO]);
 471         if (D11REV_IS(wlc_hw->corerev, 4)) {
 472                 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
 473         }
 474
 475         wlc_phy_watchdog(wlc_hw->band->pi);
 476 }
 477
 478 void
 479 wlc_bmac_set_chanspec(wlc_hw_info_t *wlc_hw, chanspec_t chanspec, bool mute,
 480                       struct txpwr_limits *txpwr)
 481 {
 482         uint bandunit;
 483
 484         WL_TRACE(("wl%d: wlc_bmac_set_chanspec 0x%x\n", wlc_hw->unit,
 485                   chanspec));
 486
 487         wlc_hw->chanspec = chanspec;
 488
 489         /* Switch bands if necessary */
 490         if (NBANDS_HW(wlc_hw) > 1) {
 491                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 492                 if (wlc_hw->band->bandunit != bandunit) {
 493                         /* wlc_bmac_setband disables other bandunit,
 494                          *  use light band switch if not up yet
 495                          */
 496                         if (wlc_hw->up) {
 497                                 wlc_phy_chanspec_radio_set(wlc_hw->
 498                                                            bandstate[bandunit]->
 499                                                            pi, chanspec);
 500                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 501                         } else {
 502                                 wlc_setxband(wlc_hw, bandunit);
 503                         }
 504                 }
 505         }
 506
 507         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 508
 509         if (!wlc_hw->up) {
 510                 if (wlc_hw->clk)
 511                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 512                                                   chanspec);
 513                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 514         } else {
 515                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 516                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 517
 518                 /* Update muting of the channel */
 519                 wlc_bmac_mute(wlc_hw, mute, 0);
 520         }
 521 }
 522
 523 int wlc_bmac_revinfo_get(wlc_hw_info_t *wlc_hw, wlc_bmac_revinfo_t *revinfo)
 524 {
 525         si_t *sih = wlc_hw->sih;
 526         uint idx;
 527
 528         revinfo->vendorid = wlc_hw->vendorid;
 529         revinfo->deviceid = wlc_hw->deviceid;
 530
 531         revinfo->boardrev = wlc_hw->boardrev;
 532         revinfo->corerev = wlc_hw->corerev;
 533         revinfo->sromrev = wlc_hw->sromrev;
 534         revinfo->chiprev = sih->chiprev;
 535         revinfo->chip = sih->chip;
 536         revinfo->chippkg = sih->chippkg;
 537         revinfo->boardtype = sih->boardtype;
 538         revinfo->boardvendor = sih->boardvendor;
 539         revinfo->bustype = sih->bustype;
 540         revinfo->buscoretype = sih->buscoretype;
 541         revinfo->buscorerev = sih->buscorerev;
 542         revinfo->issim = sih->issim;
 543
 544         revinfo->nbands = NBANDS_HW(wlc_hw);
 545
 546         for (idx = 0; idx < NBANDS_HW(wlc_hw); idx++) {
 547                 wlc_hwband_t *band = wlc_hw->bandstate[idx];
 548                 revinfo->band[idx].bandunit = band->bandunit;
 549                 revinfo->band[idx].bandtype = band->bandtype;
 550                 revinfo->band[idx].phytype = band->phytype;
 551                 revinfo->band[idx].phyrev = band->phyrev;
 552                 revinfo->band[idx].radioid = band->radioid;
 553                 revinfo->band[idx].radiorev = band->radiorev;
 554                 revinfo->band[idx].abgphy_encore = band->abgphy_encore;
 555                 revinfo->band[idx].anarev = 0;
 556
 557         }
 558         return 0;
 559 }
 560
 561 int wlc_bmac_state_get(wlc_hw_info_t *wlc_hw, wlc_bmac_state_t *state)
 562 {
 563         state->machwcap = wlc_hw->machwcap;
 564
 565         return 0;
 566 }
 567
 568 static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme)
 569 {
 570         uint i;
 571         char name[8];
 572         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 573         u16 pio_mhf2 = 0;
 574         wlc_hw_info_t *wlc_hw = wlc->hw;
 575         uint unit = wlc_hw->unit;
 576         wlc_tunables_t *tune = wlc->pub->tunables;
 577
 578         /* name and offsets for dma_attach */
 579         snprintf(name, sizeof(name), "wl%d", unit);
 580
 581         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 582                 uint addrwidth;
 583                 int dma_attach_err = 0;
 584                 osl_t *osh = wlc_hw->osh;
 585
 586                 /* Find out the DMA addressing capability and let OS know
 587                  * All the channels within one DMA core have 'common-minimum' same
 588                  * capability
 589                  */
 590                 addrwidth =
 591                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 592                 OSL_DMADDRWIDTH(osh, addrwidth);
 593
 594                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 595                         WL_ERROR(("wl%d: wlc_attach: alloc_dma_resources failed\n", unit));
 596                         return false;
 597                 }
 598
 599                 /*
 600                  * FIFO 0
 601                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 602                  * RX: RX_FIFO (RX data packets)
 603                  */
 604                 ASSERT(TX_AC_BK_FIFO == 0);
 605                 ASSERT(RX_FIFO == 0);
 606                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 607                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 608                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 609                                            (wme ? tune->ntxd : 0), tune->nrxd,
 610                                            tune->rxbufsz, -1, tune->nrxbufpost,
 611                                            WL_HWRXOFF, &wl_msg_level);
 612                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 613
 614                 /*
 615                  * FIFO 1
 616                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 617                  *   (legacy) TX_DATA_FIFO (TX data packets)
 618                  * RX: UNUSED
 619                  */
 620                 ASSERT(TX_AC_BE_FIFO == 1);
 621                 ASSERT(TX_DATA_FIFO == 1);
 622                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 623                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 624                                            tune->ntxd, 0, 0, -1, 0, 0,
 625                                            &wl_msg_level);
 626                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 627
 628                 /*
 629                  * FIFO 2
 630                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 631                  * RX: UNUSED
 632                  */
 633                 ASSERT(TX_AC_VI_FIFO == 2);
 634                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 635                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 636                                            tune->ntxd, 0, 0, -1, 0, 0,
 637                                            &wl_msg_level);
 638                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 639                 /*
 640                  * FIFO 3
 641                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 642                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 643                  * RX: RX_TXSTATUS_FIFO (transmit-status packets)
 644                  *      for corerev < 5 only
 645                  */
 646                 ASSERT(TX_AC_VO_FIFO == 3);
 647                 ASSERT(TX_CTL_FIFO == 3);
 648                 if (D11REV_IS(wlc_hw->corerev, 4)) {
 649                         ASSERT(RX_TXSTATUS_FIFO == 3);
 650                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 651                                                    DMAREG(wlc_hw, DMA_TX, 3),
 652                                                    DMAREG(wlc_hw, DMA_RX, 3),
 653                                                    tune->ntxd, tune->nrxd,
 654                                                    sizeof(tx_status_t), -1,
 655                                                    tune->nrxbufpost, 0,
 656                                                    &wl_msg_level);
 657                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 658                 } else {
 659                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 660                                                    DMAREG(wlc_hw, DMA_TX, 3),
 661                                                    NULL, tune->ntxd, 0, 0, -1,
 662                                                    0, 0, &wl_msg_level);
 663                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 664                 }
 665 /* Cleaner to leave this as if with AP defined */
 666
 667                 if (dma_attach_err) {
 668                         WL_ERROR(("wl%d: wlc_attach: dma_attach failed\n",
 669                                   unit));
 670                         return false;
 671                 }
 672
 673                 /* get pointer to dma engine tx flow control variable */
 674                 for (i = 0; i < NFIFO; i++)
 675                         if (wlc_hw->di[i])
 676                                 wlc_hw->txavail[i] =
 677                                     (uint *) dma_getvar(wlc_hw->di[i],
 678                                                         "&txavail");
 679         }
 680
 681         /* initial ucode host flags */
 682         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 683
 684         return true;
 685 }
 686
 687 static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw)
 688 {
 689         uint j;
 690
 691         for (j = 0; j < NFIFO; j++) {
 692                 if (wlc_hw->di[j]) {
 693                         dma_detach(wlc_hw->di[j]);
 694                         wlc_hw->di[j] = NULL;
 695                 }
 696         }
 697 }
 698
 699 /* low level attach
 700  *    run backplane attach, init nvram
 701  *    run phy attach
 702  *    initialize software state for each core and band
 703  *    put the whole chip in reset(driver down state), no clock
 704  */
 705 int wlc_bmac_attach(wlc_info_t *wlc, u16 vendor, u16 device, uint unit,
 706                     bool piomode, osl_t *osh, void *regsva, uint bustype,
 707                     void *btparam)
 708 {
 709         wlc_hw_info_t *wlc_hw;
 710         d11regs_t *regs;
 711         char *macaddr = NULL;
 712         char *vars;
 713         uint err = 0;
 714         uint j;
 715         bool wme = false;
 716         shared_phy_params_t sha_params;
 717
 718         WL_TRACE(("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n", unit,
 719                   vendor, device));
 720
 721         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 722
 723         wme = true;
 724
 725         wlc_hw = wlc->hw;
 726         wlc_hw->wlc = wlc;
 727         wlc_hw->unit = unit;
 728         wlc_hw->osh = osh;
 729         wlc_hw->band = wlc_hw->bandstate[0];
 730         wlc_hw->_piomode = piomode;
 731
 732         /* populate wlc_hw_info_t with default values  */
 733         wlc_bmac_info_init(wlc_hw);
 734
 735         /*
 736          * Do the hardware portion of the attach.
 737          * Also initialize software state that depends on the particular hardware
 738          * we are running.
 739          */
 740         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 741                                 &wlc_hw->vars, &wlc_hw->vars_size);
 742         if (wlc_hw->sih == NULL) {
 743                 WL_ERROR(("wl%d: wlc_bmac_attach: si_attach failed\n", unit));
 744                 err = 11;
 745                 goto fail;
 746         }
 747         vars = wlc_hw->vars;
 748
 749         /*
 750          * Get vendid/devid nvram overwrites, which could be different
 751          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 752          * SDIO_BUS, and SROMless devices on PCI_BUS.
 753          */
 754 #ifdef BCMBUSTYPE
 755         bustype = BCMBUSTYPE;
 756 #endif
 757         if (bustype != SI_BUS) {
 758                 char *var;
 759
 760                 var = getvar(vars, "vendid");
 761                 if (var) {
 762                         vendor = (u16) simple_strtoul(var, NULL, 0);
 763                         WL_ERROR(("Overriding vendor id = 0x%x\n", vendor));
 764                 }
 765                 var = getvar(vars, "devid");
 766                 if (var) {
 767                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 768                         if (devid != 0xffff) {
 769                                 device = devid;
 770                                 WL_ERROR(("Overriding device id = 0x%x\n",
 771                                           device));
 772                         }
 773                 }
 774
 775                 /* verify again the device is supported */
 776                 if (!wlc_chipmatch(vendor, device)) {
 777                         WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n", unit, vendor, device));
 778                         err = 12;
 779                         goto fail;
 780                 }
 781         }
 782
 783         wlc_hw->vendorid = vendor;
 784         wlc_hw->deviceid = device;
 785
 786         /* set bar0 window to point at D11 core */
 787         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 788         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 789
 790         regs = wlc_hw->regs;
 791
 792         wlc->regs = wlc_hw->regs;
 793
 794         /* validate chip, chiprev and corerev */
 795         if (!wlc_isgoodchip(wlc_hw)) {
 796                 err = 13;
 797                 goto fail;
 798         }
 799
 800         /* initialize power control registers */
 801         si_clkctl_init(wlc_hw->sih);
 802
 803         /* request fastclock and force fastclock for the rest of attach
 804          * bring the d11 core out of reset.
 805          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 806          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 807          */
 808         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 809         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 810
 811         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 812                 WL_ERROR(("wl%d: wlc_bmac_attach: validate_chip_access failed\n", unit));
 813                 err = 14;
 814                 goto fail;
 815         }
 816
 817         /* get the board rev, used just below */
 818         j = getintvar(vars, "boardrev");
 819         /* promote srom boardrev of 0xFF to 1 */
 820         if (j == BOARDREV_PROMOTABLE)
 821                 j = BOARDREV_PROMOTED;
 822         wlc_hw->boardrev = (u16) j;
 823         if (!wlc_validboardtype(wlc_hw)) {
 824                 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit, wlc_hw->sih->boardtype, wlc_hw->boardrev));
 825                 err = 15;
 826                 goto fail;
 827         }
 828         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 829         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 830         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 831
 832         if (D11REV_LE(wlc_hw->corerev, 4)
 833             || (wlc_hw->boardflags & BFL_NOPLLDOWN))
 834                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 835
 836         if ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
 837             && (si_pci_war16165(wlc_hw->sih)))
 838                 wlc->war16165 = true;
 839
 840         /* check device id(srom, nvram etc.) to set bands */
 841         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 842                 /* Dualband boards */
 843                 wlc_hw->_nbands = 2;
 844         } else
 845                 wlc_hw->_nbands = 1;
 846
 847         if ((CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID))
 848                 wlc_hw->_nbands = 1;
 849
 850         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 851          * init of these values
 852          */
 853         wlc->vendorid = wlc_hw->vendorid;
 854         wlc->deviceid = wlc_hw->deviceid;
 855         wlc->pub->sih = wlc_hw->sih;
 856         wlc->pub->corerev = wlc_hw->corerev;
 857         wlc->pub->sromrev = wlc_hw->sromrev;
 858         wlc->pub->boardrev = wlc_hw->boardrev;
 859         wlc->pub->boardflags = wlc_hw->boardflags;
 860         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 861         wlc->pub->_nbands = wlc_hw->_nbands;
 862
 863         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 864
 865         if (wlc_hw->physhim == NULL) {
 866                 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 867                           unit));
 868                 err = 25;
 869                 goto fail;
 870         }
 871
 872         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 873         sha_params.osh = osh;
 874         sha_params.sih = wlc_hw->sih;
 875         sha_params.physhim = wlc_hw->physhim;
 876         sha_params.unit = unit;
 877         sha_params.corerev = wlc_hw->corerev;
 878         sha_params.vars = vars;
 879         sha_params.vid = wlc_hw->vendorid;
 880         sha_params.did = wlc_hw->deviceid;
 881         sha_params.chip = wlc_hw->sih->chip;
 882         sha_params.chiprev = wlc_hw->sih->chiprev;
 883         sha_params.chippkg = wlc_hw->sih->chippkg;
 884         sha_params.sromrev = wlc_hw->sromrev;
 885         sha_params.boardtype = wlc_hw->sih->boardtype;
 886         sha_params.boardrev = wlc_hw->boardrev;
 887         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 888         sha_params.boardflags = wlc_hw->boardflags;
 889         sha_params.boardflags2 = wlc_hw->boardflags2;
 890         sha_params.bustype = wlc_hw->sih->bustype;
 891         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 892
 893         /* alloc and save pointer to shared phy state area */
 894         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 895         if (!wlc_hw->phy_sh) {
 896                 err = 16;
 897                 goto fail;
 898         }
 899
 900         /* initialize software state for each core and band */
 901         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 902                 /*
 903                  * band0 is always 2.4Ghz
 904                  * band1, if present, is 5Ghz
 905                  */
 906
 907                 /* So if this is a single band 11a card, use band 1 */
 908                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 909                         j = BAND_5G_INDEX;
 910
 911                 wlc_setxband(wlc_hw, j);
 912
 913                 wlc_hw->band->bandunit = j;
 914                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 915                 wlc->band->bandunit = j;
 916                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 917                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 918
 919                 if (D11REV_GE(wlc_hw->corerev, 13)) {
 920                         wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 921                         wlc_hw->machwcap_backup = wlc_hw->machwcap;
 922                 }
 923
 924                 /* init tx fifo size */
 925                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 926                        ARRAY_SIZE(xmtfifo_sz));
 927                 wlc_hw->xmtfifo_sz =
 928                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 929
 930                 /* Get a phy for this band */
 931                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 932                         (void *)regs, wlc_hw->band->bandtype, vars);
 933                 if (wlc_hw->band->pi == NULL) {
 934                         WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n", unit));
 935                         err = 17;
 936                         goto fail;
 937                 }
 938
 939                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 940
 941                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 942                                        &wlc_hw->band->phyrev,
 943                                        &wlc_hw->band->radioid,
 944                                        &wlc_hw->band->radiorev);
 945                 wlc_hw->band->abgphy_encore =
 946                     wlc_phy_get_encore(wlc_hw->band->pi);
 947                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 948                 wlc_hw->band->core_flags =
 949                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 950
 951                 /* verify good phy_type & supported phy revision */
 952                 if (WLCISNPHY(wlc_hw->band)) {
 953                         if (NCONF_HAS(wlc_hw->band->phyrev))
 954                                 goto good_phy;
 955                         else
 956                                 goto bad_phy;
 957                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 958                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 959                                 goto good_phy;
 960                         else
 961                                 goto bad_phy;
 962                 } else {
 963  bad_phy:
 964                         WL_ERROR(("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n", unit, wlc_hw->band->phytype, wlc_hw->band->phyrev));
 965                         err = 18;
 966                         goto fail;
 967                 }
 968
 969  good_phy:
 970                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 971                  * high level attach. However we can not make that change until all low level access
 972                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 973                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 974                  * low only init when all fns updated.
 975                  */
 976                 wlc->band->pi = wlc_hw->band->pi;
 977                 wlc->band->phytype = wlc_hw->band->phytype;
 978                 wlc->band->phyrev = wlc_hw->band->phyrev;
 979                 wlc->band->radioid = wlc_hw->band->radioid;
 980                 wlc->band->radiorev = wlc_hw->band->radiorev;
 981
 982                 /* default contention windows size limits */
 983                 wlc_hw->band->CWmin = APHY_CWMIN;
 984                 wlc_hw->band->CWmax = PHY_CWMAX;
 985
 986                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 987                         err = 19;
 988                         goto fail;
 989                 }
 990         }
 991
 992         /* disable core to match driver "down" state */
 993         wlc_coredisable(wlc_hw);
 994
 995         /* Match driver "down" state */
 996         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
 997                 si_pci_down(wlc_hw->sih);
 998
 999         /* register sb interrupt callback functions */
1000         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
1001                                   (void *)wlc_wlintrsrestore, NULL, wlc);
1002
1003         /* turn off pll and xtal to match driver "down" state */
1004         wlc_bmac_xtal(wlc_hw, OFF);
1005
1006         /* *********************************************************************
1007          * The hardware is in the DOWN state at this point. D11 core
1008          * or cores are in reset with clocks off, and the board PLLs
1009          * are off if possible.
1010          *
1011          * Beyond this point, wlc->sbclk == false and chip registers
1012          * should not be touched.
1013          *********************************************************************
1014          */
1015
1016         /* init etheraddr state variables */
1017         macaddr = wlc_get_macaddr(wlc_hw);
1018         if (macaddr == NULL) {
1019                 WL_ERROR(("wl%d: wlc_bmac_attach: macaddr not found\n", unit));
1020                 err = 21;
1021                 goto fail;
1022         }
1023         bcm_ether_atoe(macaddr, &wlc_hw->etheraddr);
1024         if (ETHER_ISBCAST((char *)&wlc_hw->etheraddr) ||
1025             ETHER_ISNULLADDR((char *)&wlc_hw->etheraddr)) {
1026                 WL_ERROR(("wl%d: wlc_bmac_attach: bad macaddr %s\n", unit,
1027                           macaddr));
1028                 err = 22;
1029                 goto fail;
1030         }
1031
1032         WL_ERROR(("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1033                   __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1034                   wlc_hw->sih->boardtype, macaddr));
1035
1036         return err;
1037
1038  fail:
1039         WL_ERROR(("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err));
1040         return err;
1041 }
1042
1043 /*
1044  * Initialize wlc_info default values ...
1045  * may get overrides later in this function
1046  *  BMAC_NOTES, move low out and resolve the dangling ones
1047  */
1048 void wlc_bmac_info_init(wlc_hw_info_t *wlc_hw)
1049 {
1050         wlc_info_t *wlc = wlc_hw->wlc;
1051
1052         /* set default sw macintmask value */
1053         wlc->defmacintmask = DEF_MACINTMASK;
1054
1055         /* various 802.11g modes */
1056         wlc_hw->shortslot = false;
1057
1058         wlc_hw->SFBL = RETRY_SHORT_FB;
1059         wlc_hw->LFBL = RETRY_LONG_FB;
1060
1061         /* default mac retry limits */
1062         wlc_hw->SRL = RETRY_SHORT_DEF;
1063         wlc_hw->LRL = RETRY_LONG_DEF;
1064         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1065 }
1066
1067 /*
1068  * low level detach
1069  */
1070 int wlc_bmac_detach(wlc_info_t *wlc)
1071 {
1072         uint i;
1073         wlc_hwband_t *band;
1074         wlc_hw_info_t *wlc_hw = wlc->hw;
1075         int callbacks;
1076
1077         callbacks = 0;
1078
1079         if (wlc_hw->sih) {
1080                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1081                  * interrupt object may has been freed. this must be done before sb core switch
1082                  */
1083                 si_deregister_intr_callback(wlc_hw->sih);
1084
1085                 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1086                         si_pci_sleep(wlc_hw->sih);
1087         }
1088
1089         wlc_bmac_detach_dmapio(wlc_hw);
1090
1091         band = wlc_hw->band;
1092         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1093                 if (band->pi) {
1094                         /* Detach this band's phy */
1095                         wlc_phy_detach(band->pi);
1096                         band->pi = NULL;
1097                 }
1098                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1099         }
1100
1101         /* Free shared phy state */
1102         wlc_phy_shared_detach(wlc_hw->phy_sh);
1103
1104         wlc_phy_shim_detach(wlc_hw->physhim);
1105
1106         /* free vars */
1107         if (wlc_hw->vars) {
1108                 kfree(wlc_hw->vars);
1109                 wlc_hw->vars = NULL;
1110         }
1111
1112         if (wlc_hw->sih) {
1113                 si_detach(wlc_hw->sih);
1114                 wlc_hw->sih = NULL;
1115         }
1116
1117         return callbacks;
1118
1119 }
1120
1121 void wlc_bmac_reset(wlc_hw_info_t *wlc_hw)
1122 {
1123         WL_TRACE(("wl%d: wlc_bmac_reset\n", wlc_hw->unit));
1124
1125         WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1126
1127         /* reset the core */
1128         if (!DEVICEREMOVED(wlc_hw->wlc))
1129                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1130
1131         /* purge the dma rings */
1132         wlc_flushqueues(wlc_hw->wlc);
1133
1134         wlc_reset_bmac_done(wlc_hw->wlc);
1135 }
1136
1137 void
1138 wlc_bmac_init(wlc_hw_info_t *wlc_hw, chanspec_t chanspec,
1139                           bool mute) {
1140         u32 macintmask;
1141         bool fastclk;
1142         wlc_info_t *wlc = wlc_hw->wlc;
1143
1144         WL_TRACE(("wl%d: wlc_bmac_init\n", wlc_hw->unit));
1145
1146         /* request FAST clock if not on */
1147         fastclk = wlc_hw->forcefastclk;
1148         if (!fastclk)
1149                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1150
1151         /* disable interrupts */
1152         macintmask = wl_intrsoff(wlc->wl);
1153
1154         /* set up the specified band and chanspec */
1155         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1156         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1157
1158         /* do one-time phy inits and calibration */
1159         wlc_phy_cal_init(wlc_hw->band->pi);
1160
1161         /* core-specific initialization */
1162         wlc_coreinit(wlc);
1163
1164         /* suspend the tx fifos and mute the phy for preism cac time */
1165         if (mute)
1166                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1167
1168         /* band-specific inits */
1169         wlc_bmac_bsinit(wlc, chanspec);
1170
1171         /* restore macintmask */
1172         wl_intrsrestore(wlc->wl, macintmask);
1173
1174         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1175          * and wlc_enable_mac() will clear this override bit.
1176          */
1177         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1178
1179         /*
1180          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1181          */
1182         wlc_hw->mac_suspend_depth = 1;
1183
1184         /* restore the clk */
1185         if (!fastclk)
1186                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1187 }
1188
1189 int wlc_bmac_up_prep(wlc_hw_info_t *wlc_hw)
1190 {
1191         uint coremask;
1192
1193         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1194
1195         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1196
1197         /*
1198          * Enable pll and xtal, initialize the power control registers,
1199          * and force fastclock for the remainder of wlc_up().
1200          */
1201         wlc_bmac_xtal(wlc_hw, ON);
1202         si_clkctl_init(wlc_hw->sih);
1203         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1204
1205         /*
1206          * Configure pci/pcmcia here instead of in wlc_attach()
1207          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1208          */
1209         coremask = (1 << wlc_hw->wlc->core->coreidx);
1210
1211         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1212                 si_pci_setup(wlc_hw->sih, coremask);
1213
1214         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1215
1216         /*
1217          * Need to read the hwradio status here to cover the case where the system
1218          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1219          */
1220         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1221                 /* put SB PCI in down state again */
1222                 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1223                         si_pci_down(wlc_hw->sih);
1224                 wlc_bmac_xtal(wlc_hw, OFF);
1225                 return BCME_RADIOOFF;
1226         }
1227
1228         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1229                 si_pci_up(wlc_hw->sih);
1230
1231         /* reset the d11 core */
1232         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1233
1234         return 0;
1235 }
1236
1237 int wlc_bmac_up_finish(wlc_hw_info_t *wlc_hw)
1238 {
1239         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1240
1241         wlc_hw->up = true;
1242         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1243
1244         /* FULLY enable dynamic power control and d11 core interrupt */
1245         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1246         ASSERT(wlc_hw->wlc->macintmask == 0);
1247         wl_intrson(wlc_hw->wlc->wl);
1248         return 0;
1249 }
1250
1251 int wlc_bmac_down_prep(wlc_hw_info_t *wlc_hw)
1252 {
1253         bool dev_gone;
1254         uint callbacks = 0;
1255
1256         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1257
1258         if (!wlc_hw->up)
1259                 return callbacks;
1260
1261         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1262
1263         /* disable interrupts */
1264         if (dev_gone)
1265                 wlc_hw->wlc->macintmask = 0;
1266         else {
1267                 /* now disable interrupts */
1268                 wl_intrsoff(wlc_hw->wlc->wl);
1269
1270                 /* ensure we're running on the pll clock again */
1271                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1272         }
1273         /* down phy at the last of this stage */
1274         callbacks += wlc_phy_down(wlc_hw->band->pi);
1275
1276         return callbacks;
1277 }
1278
1279 int wlc_bmac_down_finish(wlc_hw_info_t *wlc_hw)
1280 {
1281         uint callbacks = 0;
1282         bool dev_gone;
1283
1284         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1285
1286         if (!wlc_hw->up)
1287                 return callbacks;
1288
1289         wlc_hw->up = false;
1290         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1291
1292         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1293
1294         if (dev_gone) {
1295                 wlc_hw->sbclk = false;
1296                 wlc_hw->clk = false;
1297                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1298
1299                 /* reclaim any posted packets */
1300                 wlc_flushqueues(wlc_hw->wlc);
1301         } else {
1302
1303                 /* Reset and disable the core */
1304                 if (si_iscoreup(wlc_hw->sih)) {
1305                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1306                             MCTL_EN_MAC)
1307                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1308                         callbacks += wl_reset(wlc_hw->wlc->wl);
1309                         wlc_coredisable(wlc_hw);
1310                 }
1311
1312                 /* turn off primary xtal and pll */
1313                 if (!wlc_hw->noreset) {
1314                         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1315                                 si_pci_down(wlc_hw->sih);
1316                         wlc_bmac_xtal(wlc_hw, OFF);
1317                 }
1318         }
1319
1320         return callbacks;
1321 }
1322
1323 void wlc_bmac_wait_for_wake(wlc_hw_info_t *wlc_hw)
1324 {
1325         if (D11REV_IS(wlc_hw->corerev, 4))      /* no slowclock */
1326                 udelay(5);
1327         else {
1328                 /* delay before first read of ucode state */
1329                 udelay(40);
1330
1331                 /* wait until ucode is no longer asleep */
1332                 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1333                           DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1334         }
1335
1336         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1337 }
1338
1339 void wlc_bmac_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
1340 {
1341         bcopy(&wlc_hw->etheraddr, ea, ETHER_ADDR_LEN);
1342 }
1343
1344 void wlc_bmac_set_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
1345 {
1346         bcopy(ea, &wlc_hw->etheraddr, ETHER_ADDR_LEN);
1347 }
1348
1349 int wlc_bmac_bandtype(wlc_hw_info_t *wlc_hw)
1350 {
1351         return wlc_hw->band->bandtype;
1352 }
1353
1354 void *wlc_cur_phy(wlc_info_t *wlc)
1355 {
1356         wlc_hw_info_t *wlc_hw = wlc->hw;
1357         return (void *)wlc_hw->band->pi;
1358 }
1359
1360 /* control chip clock to save power, enable dynamic clock or force fast clock */
1361 static void wlc_clkctl_clk(wlc_hw_info_t *wlc_hw, uint mode)
1362 {
1363         if (PMUCTL_ENAB(wlc_hw->sih)) {
1364                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1365                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1366                  *      which means the FCA bit may not be set.
1367                  *      should wakeup mac if driver wants it to run on HT.
1368                  */
1369
1370                 if (wlc_hw->clk) {
1371                         if (mode == CLK_FAST) {
1372                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1373                                        CCS_FORCEHT);
1374
1375                                 udelay(64);
1376
1377                                 SPINWAIT(((R_REG
1378                                            (wlc_hw->osh,
1379                                             &wlc_hw->regs->
1380                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1381                                          PMU_MAX_TRANSITION_DLY);
1382                                 ASSERT(R_REG
1383                                        (wlc_hw->osh,
1384                                         &wlc_hw->regs->
1385                                         clk_ctl_st) & CCS_HTAVAIL);
1386                         } else {
1387                                 if ((wlc_hw->sih->pmurev == 0) &&
1388                                     (R_REG
1389                                      (wlc_hw->osh,
1390                                       &wlc_hw->regs->
1391                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1392                                         SPINWAIT(((R_REG
1393                                                    (wlc_hw->osh,
1394                                                     &wlc_hw->regs->
1395                                                     clk_ctl_st) & CCS_HTAVAIL)
1396                                                   == 0),
1397                                                  PMU_MAX_TRANSITION_DLY);
1398                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1399                                         ~CCS_FORCEHT);
1400                         }
1401                 }
1402                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1403         } else {
1404                 bool wakeup_ucode;
1405
1406                 /* old chips w/o PMU, force HT through cc,
1407                  * then use FCA to verify mac is running fast clock
1408                  */
1409
1410                 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1411
1412                 if (wlc_hw->up && wakeup_ucode)
1413                         wlc_ucode_wake_override_set(wlc_hw,
1414                                                     WLC_WAKE_OVERRIDE_CLKCTL);
1415
1416                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1417
1418                 if (D11REV_LT(wlc_hw->corerev, 11)) {
1419                         /* ucode WAR for old chips */
1420                         if (wlc_hw->forcefastclk)
1421                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1422                                              MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1423                         else
1424                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1425                                              WLC_BAND_ALL);
1426                 }
1427
1428                 /* check fast clock is available (if core is not in reset) */
1429                 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1430                     && wlc_hw->clk)
1431                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1432
1433                 /* keep the ucode wake bit on if forcefastclk is on
1434                  * since we do not want ucode to put us back to slow clock
1435                  * when it dozes for PM mode.
1436                  * Code below matches the wake override bit with current forcefastclk state
1437                  * Only setting bit in wake_override instead of waking ucode immediately
1438                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1439                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1440                  * (protected by an up check) was executed just below.
1441                  */
1442                 if (wlc_hw->forcefastclk)
1443                         mboolset(wlc_hw->wake_override,
1444                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1445                 else
1446                         mboolclr(wlc_hw->wake_override,
1447                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1448
1449                 /* ok to clear the wakeup now */
1450                 if (wlc_hw->up && wakeup_ucode)
1451                         wlc_ucode_wake_override_clear(wlc_hw,
1452                                                       WLC_WAKE_OVERRIDE_CLKCTL);
1453         }
1454 }
1455
1456 /* set initial host flags value */
1457 static void
1458 wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init)
1459 {
1460         wlc_hw_info_t *wlc_hw = wlc->hw;
1461
1462         bzero(mhfs, sizeof(u16) * MHFMAX);
1463
1464         mhfs[MHF2] |= mhf2_init;
1465
1466         /* prohibit use of slowclock on multifunction boards */
1467         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1468                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1469
1470         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1471                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1472                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1473         }
1474 }
1475
1476 /* set or clear ucode host flag bits
1477  * it has an optimization for no-change write
1478  * it only writes through shared memory when the core has clock;
1479  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1480  *
1481  *
1482  * bands values are: WLC_BAND_AUTO <--- Current band only
1483  *                   WLC_BAND_5G   <--- 5G band only
1484  *                   WLC_BAND_2G   <--- 2G band only
1485  *                   WLC_BAND_ALL  <--- All bands
1486  */
1487 void
1488 wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask, u16 val,
1489              int bands)
1490 {
1491         u16 save;
1492         u16 addr[MHFMAX] = {
1493                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1494                 M_HOST_FLAGS5
1495         };
1496         wlc_hwband_t *band;
1497
1498         ASSERT((val & ~mask) == 0);
1499         ASSERT(idx < MHFMAX);
1500         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1501
1502         switch (bands) {
1503                 /* Current band only or all bands,
1504                  * then set the band to current band
1505                  */
1506         case WLC_BAND_AUTO:
1507         case WLC_BAND_ALL:
1508                 band = wlc_hw->band;
1509                 break;
1510         case WLC_BAND_5G:
1511                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1512                 break;
1513         case WLC_BAND_2G:
1514                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1515                 break;
1516         default:
1517                 ASSERT(0);
1518                 band = NULL;
1519         }
1520
1521         if (band) {
1522                 save = band->mhfs[idx];
1523                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1524
1525                 /* optimization: only write through if changed, and
1526                  * changed band is the current band
1527                  */
1528                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1529                     && (band == wlc_hw->band))
1530                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1531                                            (u16) band->mhfs[idx]);
1532         }
1533
1534         if (bands == WLC_BAND_ALL) {
1535                 wlc_hw->bandstate[0]->mhfs[idx] =
1536                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1537                 wlc_hw->bandstate[1]->mhfs[idx] =
1538                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1539         }
1540 }
1541
1542 u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands)
1543 {
1544         wlc_hwband_t *band;
1545         ASSERT(idx < MHFMAX);
1546
1547         switch (bands) {
1548         case WLC_BAND_AUTO:
1549                 band = wlc_hw->band;
1550                 break;
1551         case WLC_BAND_5G:
1552                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1553                 break;
1554         case WLC_BAND_2G:
1555                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1556                 break;
1557         default:
1558                 ASSERT(0);
1559                 band = NULL;
1560         }
1561
1562         if (!band)
1563                 return 0;
1564
1565         return band->mhfs[idx];
1566 }
1567
1568 static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs)
1569 {
1570         u8 idx;
1571         u16 addr[] = {
1572                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1573                 M_HOST_FLAGS5
1574         };
1575
1576         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1577
1578         for (idx = 0; idx < MHFMAX; idx++) {
1579                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1580         }
1581 }
1582
1583 /* set the maccontrol register to desired reset state and
1584  * initialize the sw cache of the register
1585  */
1586 static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw)
1587 {
1588         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1589         wlc_hw->maccontrol = 0;
1590         wlc_hw->suspended_fifos = 0;
1591         wlc_hw->wake_override = 0;
1592         wlc_hw->mute_override = 0;
1593         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1594 }
1595
1596 /* set or clear maccontrol bits */
1597 void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, u32 mask, u32 val)
1598 {
1599         u32 maccontrol;
1600         u32 new_maccontrol;
1601
1602         ASSERT((val & ~mask) == 0);
1603
1604         maccontrol = wlc_hw->maccontrol;
1605         new_maccontrol = (maccontrol & ~mask) | val;
1606
1607         /* if the new maccontrol value is the same as the old, nothing to do */
1608         if (new_maccontrol == maccontrol)
1609                 return;
1610
1611         /* something changed, cache the new value */
1612         wlc_hw->maccontrol = new_maccontrol;
1613
1614         /* write the new values with overrides applied */
1615         wlc_mctrl_write(wlc_hw);
1616 }
1617
1618 /* write the software state of maccontrol and overrides to the maccontrol register */
1619 static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw)
1620 {
1621         u32 maccontrol = wlc_hw->maccontrol;
1622
1623         /* OR in the wake bit if overridden */
1624         if (wlc_hw->wake_override)
1625                 maccontrol |= MCTL_WAKE;
1626
1627         /* set AP and INFRA bits for mute if needed */
1628         if (wlc_hw->mute_override) {
1629                 maccontrol &= ~(MCTL_AP);
1630                 maccontrol |= MCTL_INFRA;
1631         }
1632
1633         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1634 }
1635
1636 void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, u32 override_bit)
1637 {
1638         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1639
1640         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1641                 mboolset(wlc_hw->wake_override, override_bit);
1642                 return;
1643         }
1644
1645         mboolset(wlc_hw->wake_override, override_bit);
1646
1647         wlc_mctrl_write(wlc_hw);
1648         wlc_bmac_wait_for_wake(wlc_hw);
1649
1650         return;
1651 }
1652
1653 void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw, u32 override_bit)
1654 {
1655         ASSERT(wlc_hw->wake_override & override_bit);
1656
1657         mboolclr(wlc_hw->wake_override, override_bit);
1658
1659         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1660                 return;
1661
1662         wlc_mctrl_write(wlc_hw);
1663
1664         return;
1665 }
1666
1667 /* When driver needs ucode to stop beaconing, it has to make sure that
1668  * MCTL_AP is clear and MCTL_INFRA is set
1669  * Mode           MCTL_AP        MCTL_INFRA
1670  * AP                1              1
1671  * STA               0              1 <--- This will ensure no beacons
1672  * IBSS              0              0
1673  */
1674 static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw)
1675 {
1676         wlc_hw->mute_override = 1;
1677
1678         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1679          * override, then there is no change to write
1680          */
1681         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1682                 return;
1683
1684         wlc_mctrl_write(wlc_hw);
1685
1686         return;
1687 }
1688
1689 /* Clear the override on AP and INFRA bits */
1690 static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw)
1691 {
1692         if (wlc_hw->mute_override == 0)
1693                 return;
1694
1695         wlc_hw->mute_override = 0;
1696
1697         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1698          * override, then there is no change to write
1699          */
1700         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1701                 return;
1702
1703         wlc_mctrl_write(wlc_hw);
1704 }
1705
1706 /*
1707  * Write a MAC address to the rcmta structure
1708  */
1709 void
1710 wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx,
1711                    const struct ether_addr *addr)
1712 {
1713         d11regs_t *regs = wlc_hw->regs;
1714         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1715         u32 mac_hm;
1716         u16 mac_l;
1717         osl_t *osh;
1718
1719         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
1720
1721         ASSERT(wlc_hw->corerev > 4);
1722
1723         mac_hm =
1724             (addr->octet[3] << 24) | (addr->octet[2] << 16) | (addr->
1725                                                                octet[1] << 8) |
1726             addr->octet[0];
1727         mac_l = (addr->octet[5] << 8) | addr->octet[4];
1728
1729         osh = wlc_hw->osh;
1730
1731         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1732         (void)R_REG(osh, &regs->objaddr);
1733         W_REG(osh, &regs->objdata, mac_hm);
1734         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1735         (void)R_REG(osh, &regs->objaddr);
1736         W_REG(osh, objdata16, mac_l);
1737 }
1738
1739 /*
1740  * Write a MAC address to the given match reg offset in the RXE match engine.
1741  */
1742 void
1743 wlc_bmac_set_addrmatch(wlc_hw_info_t *wlc_hw, int match_reg_offset,
1744                        const struct ether_addr *addr)
1745 {
1746         d11regs_t *regs;
1747         u16 mac_l;
1748         u16 mac_m;
1749         u16 mac_h;
1750         osl_t *osh;
1751
1752         WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit));
1753
1754         ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1755
1756         regs = wlc_hw->regs;
1757         mac_l = addr->octet[0] | (addr->octet[1] << 8);
1758         mac_m = addr->octet[2] | (addr->octet[3] << 8);
1759         mac_h = addr->octet[4] | (addr->octet[5] << 8);
1760
1761         osh = wlc_hw->osh;
1762
1763         /* enter the MAC addr into the RXE match registers */
1764         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1765         W_REG(osh, &regs->rcm_mat_data, mac_l);
1766         W_REG(osh, &regs->rcm_mat_data, mac_m);
1767         W_REG(osh, &regs->rcm_mat_data, mac_h);
1768
1769 }
1770
1771 void
1772 wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
1773                             void *buf)
1774 {
1775         d11regs_t *regs;
1776         u32 word;
1777         bool be_bit;
1778 #ifdef IL_BIGENDIAN
1779         volatile u16 *dptr = NULL;
1780 #endif                          /* IL_BIGENDIAN */
1781         osl_t *osh;
1782
1783         WL_TRACE(("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit));
1784
1785         regs = wlc_hw->regs;
1786         osh = wlc_hw->osh;
1787
1788         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1789         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1790         ASSERT((offset & ~0xffff) == 0);
1791
1792         W_REG(osh, &regs->tplatewrptr, offset);
1793
1794         /* if MCTL_BIGEND bit set in mac control register,
1795          * the chip swaps data in fifo, as well as data in
1796          * template ram
1797          */
1798         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1799
1800         while (len > 0) {
1801                 bcopy((u8 *) buf, &word, sizeof(u32));
1802
1803                 if (be_bit)
1804                         word = hton32(word);
1805                 else
1806                         word = htol32(word);
1807
1808                 W_REG(osh, &regs->tplatewrdata, word);
1809
1810                 buf = (u8 *) buf + sizeof(u32);
1811                 len -= sizeof(u32);
1812         }
1813 }
1814
1815 void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin)
1816 {
1817         osl_t *osh;
1818
1819         osh = wlc_hw->osh;
1820         wlc_hw->band->CWmin = newmin;
1821
1822         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1823         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1824         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1825 }
1826
1827 void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax)
1828 {
1829         osl_t *osh;
1830
1831         osh = wlc_hw->osh;
1832         wlc_hw->band->CWmax = newmax;
1833
1834         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1835         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1836         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1837 }
1838
1839 void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw)
1840 {
1841         bool fastclk;
1842         u32 tmp;
1843
1844         /* request FAST clock if not on */
1845         fastclk = wlc_hw->forcefastclk;
1846         if (!fastclk)
1847                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1848
1849         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1850
1851         ASSERT(wlc_hw->clk);
1852         if (D11REV_LT(wlc_hw->corerev, 17))
1853                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1854
1855         wlc_bmac_phy_reset(wlc_hw);
1856         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1857
1858         /* restore the clk */
1859         if (!fastclk)
1860                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1861 }
1862
1863 static void
1864 wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn, int len)
1865 {
1866         d11regs_t *regs = wlc_hw->regs;
1867
1868         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1869                                     bcn);
1870         /* write beacon length to SCR */
1871         ASSERT(len < 65536);
1872         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1873         /* mark beacon0 valid */
1874         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1875 }
1876
1877 static void
1878 wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn, int len)
1879 {
1880         d11regs_t *regs = wlc_hw->regs;
1881
1882         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1883                                     bcn);
1884         /* write beacon length to SCR */
1885         ASSERT(len < 65536);
1886         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1887         /* mark beacon1 valid */
1888         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1889 }
1890
1891 /* mac is assumed to be suspended at this point */
1892 void
1893 wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn, int len,
1894                                bool both)
1895 {
1896         d11regs_t *regs = wlc_hw->regs;
1897
1898         if (both) {
1899                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1900                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1901         } else {
1902                 /* bcn 0 */
1903                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1904                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1905                 /* bcn 1 */
1906                 else if (!
1907                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1908                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1909                 else            /* one template should always have been available */
1910                         ASSERT(0);
1911         }
1912 }
1913
1914 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (wlc_hw_info_t *wlc_hw)
1915 {
1916         u16 v;
1917         wlc_info_t *wlc = wlc_hw->wlc;
1918         /* update SYNTHPU_DLY */
1919
1920         if (WLCISLCNPHY(wlc->band)) {
1921                 v = SYNTHPU_DLY_LPPHY_US;
1922         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1923                 v = SYNTHPU_DLY_NPHY_US;
1924         } else {
1925                 v = SYNTHPU_DLY_BPHY_US;
1926         }
1927
1928         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1929 }
1930
1931 /* band-specific init */
1932 static void
1933 WLBANDINITFN(wlc_bmac_bsinit) (wlc_info_t *wlc, chanspec_t chanspec)
1934 {
1935         wlc_hw_info_t *wlc_hw = wlc->hw;
1936
1937         WL_TRACE(("wl%d: wlc_bmac_bsinit: bandunit %d\n", wlc_hw->unit,
1938                   wlc_hw->band->bandunit));
1939
1940         /* sanity check */
1941         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1942             PHY_TYPE_LCNXN)
1943                 ASSERT((uint)
1944                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1945                        == wlc_hw->band->phytype);
1946
1947         wlc_ucode_bsinit(wlc_hw);
1948
1949         wlc_phy_init(wlc_hw->band->pi, chanspec);
1950
1951         wlc_ucode_txant_set(wlc_hw);
1952
1953         /* cwmin is band-specific, update hardware with value for current band */
1954         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1955         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1956
1957         wlc_bmac_update_slot_timing(wlc_hw,
1958                                     BAND_5G(wlc_hw->band->
1959                                             bandtype) ? true : wlc_hw->
1960                                     shortslot);
1961
1962         /* write phytype and phyvers */
1963         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1964         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1965
1966         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1967         wlc_upd_ofdm_pctl1_table(wlc_hw);
1968
1969         wlc_bmac_upd_synthpu(wlc_hw);
1970 }
1971
1972 void wlc_bmac_core_phy_clk(wlc_hw_info_t *wlc_hw, bool clk)
1973 {
1974         WL_TRACE(("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk));
1975
1976         wlc_hw->phyclk = clk;
1977
1978         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1979
1980                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1981                                (SICF_PRST | SICF_FGC));
1982                 udelay(1);
1983                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1984                 udelay(1);
1985
1986         } else {                /* take phy out of reset */
1987
1988                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1989                 udelay(1);
1990                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1991                 udelay(1);
1992
1993         }
1994 }
1995
1996 /* Perform a soft reset of the PHY PLL */
1997 void wlc_bmac_core_phypll_reset(wlc_hw_info_t *wlc_hw)
1998 {
1999         WL_TRACE(("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit));
2000
2001         si_corereg(wlc_hw->sih, SI_CC_IDX,
2002                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
2003         udelay(1);
2004         si_corereg(wlc_hw->sih, SI_CC_IDX,
2005                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
2006         udelay(1);
2007         si_corereg(wlc_hw->sih, SI_CC_IDX,
2008                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
2009         udelay(1);
2010         si_corereg(wlc_hw->sih, SI_CC_IDX,
2011                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
2012         udelay(1);
2013 }
2014
2015 /* light way to turn on phy clock without reset for NPHY only
2016  *  refer to wlc_bmac_core_phy_clk for full version
2017  */
2018 void wlc_bmac_phyclk_fgc(wlc_hw_info_t *wlc_hw, bool clk)
2019 {
2020         /* support(necessary for NPHY and HYPHY) only */
2021         if (!WLCISNPHY(wlc_hw->band))
2022                 return;
2023
2024         if (ON == clk)
2025                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
2026         else
2027                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
2028
2029 }
2030
2031 void wlc_bmac_macphyclk_set(wlc_hw_info_t *wlc_hw, bool clk)
2032 {
2033         if (ON == clk)
2034                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
2035         else
2036                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
2037 }
2038
2039 void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw)
2040 {
2041         wlc_phy_t *pih = wlc_hw->band->pi;
2042         u32 phy_bw_clkbits;
2043         bool phy_in_reset = false;
2044
2045         WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit));
2046
2047         if (pih == NULL)
2048                 return;
2049
2050         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2051
2052         /* Specfic reset sequence required for NPHY rev 3 and 4 */
2053         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2054             NREV_LE(wlc_hw->band->phyrev, 4)) {
2055                 /* Set the PHY bandwidth */
2056                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2057
2058                 udelay(1);
2059
2060                 /* Perform a soft reset of the PHY PLL */
2061                 wlc_bmac_core_phypll_reset(wlc_hw);
2062
2063                 /* reset the PHY */
2064                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2065                                (SICF_PRST | SICF_PCLKE));
2066                 phy_in_reset = true;
2067         } else {
2068
2069                 si_core_cflags(wlc_hw->sih,
2070                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2071                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2072         }
2073
2074         udelay(2);
2075         wlc_bmac_core_phy_clk(wlc_hw, ON);
2076
2077         if (pih)
2078                 wlc_phy_anacore(pih, ON);
2079 }
2080
2081 /* switch to and initialize new band */
2082 static void
2083 WLBANDINITFN(wlc_bmac_setband) (wlc_hw_info_t *wlc_hw, uint bandunit,
2084                                 chanspec_t chanspec) {
2085         wlc_info_t *wlc = wlc_hw->wlc;
2086         u32 macintmask;
2087
2088         ASSERT(NBANDS_HW(wlc_hw) > 1);
2089         ASSERT(bandunit != wlc_hw->band->bandunit);
2090
2091         /* Enable the d11 core before accessing it */
2092         if (!si_iscoreup(wlc_hw->sih)) {
2093                 si_core_reset(wlc_hw->sih, 0, 0);
2094                 ASSERT(si_iscoreup(wlc_hw->sih));
2095                 wlc_mctrl_reset(wlc_hw);
2096         }
2097
2098         macintmask = wlc_setband_inact(wlc, bandunit);
2099
2100         if (!wlc_hw->up)
2101                 return;
2102
2103         wlc_bmac_core_phy_clk(wlc_hw, ON);
2104
2105         /* band-specific initializations */
2106         wlc_bmac_bsinit(wlc, chanspec);
2107
2108         /*
2109          * If there are any pending software interrupt bits,
2110          * then replace these with a harmless nonzero value
2111          * so wlc_dpc() will re-enable interrupts when done.
2112          */
2113         if (wlc->macintstatus)
2114                 wlc->macintstatus = MI_DMAINT;
2115
2116         /* restore macintmask */
2117         wl_intrsrestore(wlc->wl, macintmask);
2118
2119         /* ucode should still be suspended.. */
2120         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2121                0);
2122 }
2123
2124 /* low-level band switch utility routine */
2125 void WLBANDINITFN(wlc_setxband) (wlc_hw_info_t *wlc_hw, uint bandunit)
2126 {
2127         WL_TRACE(("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit));
2128
2129         wlc_hw->band = wlc_hw->bandstate[bandunit];
2130
2131         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2132         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2133
2134         /* set gmode core flag */
2135         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2136                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2137                                ((bandunit == 0) ? SICF_GMODE : 0));
2138         }
2139 }
2140
2141 static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw)
2142 {
2143
2144         /* reject unsupported corerev */
2145         if (!VALID_COREREV(wlc_hw->corerev)) {
2146                 WL_ERROR(("unsupported core rev %d\n", wlc_hw->corerev));
2147                 return false;
2148         }
2149
2150         return true;
2151 }
2152
2153 static bool wlc_validboardtype(wlc_hw_info_t *wlc_hw)
2154 {
2155         bool goodboard = true;
2156         uint boardrev = wlc_hw->boardrev;
2157
2158         if (boardrev == 0)
2159                 goodboard = false;
2160         else if (boardrev > 0xff) {
2161                 uint brt = (boardrev & 0xf000) >> 12;
2162                 uint b0 = (boardrev & 0xf00) >> 8;
2163                 uint b1 = (boardrev & 0xf0) >> 4;
2164                 uint b2 = boardrev & 0xf;
2165
2166                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2167                     || (b2 > 9))
2168                         goodboard = false;
2169         }
2170
2171         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2172                 return goodboard;
2173
2174         return goodboard;
2175 }
2176
2177 static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw)
2178 {
2179         const char *varname = "macaddr";
2180         char *macaddr;
2181
2182         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2183         macaddr = getvar(wlc_hw->vars, varname);
2184         if (macaddr != NULL)
2185                 return macaddr;
2186
2187         if (NBANDS_HW(wlc_hw) > 1)
2188                 varname = "et1macaddr";
2189         else
2190                 varname = "il0macaddr";
2191
2192         macaddr = getvar(wlc_hw->vars, varname);
2193         if (macaddr == NULL) {
2194                 WL_ERROR(("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n", wlc_hw->unit, varname));
2195         }
2196
2197         return macaddr;
2198 }
2199
2200 /*
2201  * Return true if radio is disabled, otherwise false.
2202  * hw radio disable signal is an external pin, users activate it asynchronously
2203  * this function could be called when driver is down and w/o clock
2204  * it operates on different registers depending on corerev and boardflag.
2205  */
2206 bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t *wlc_hw)
2207 {
2208         bool v, clk, xtal;
2209         u32 resetbits = 0, flags = 0;
2210
2211         xtal = wlc_hw->sbclk;
2212         if (!xtal)
2213                 wlc_bmac_xtal(wlc_hw, ON);
2214
2215         /* may need to take core out of reset first */
2216         clk = wlc_hw->clk;
2217         if (!clk) {
2218                 if (D11REV_LE(wlc_hw->corerev, 11))
2219                         resetbits |= SICF_PCLKE;
2220
2221                 /*
2222                  * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2223                  * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2224                  */
2225                 if (D11REV_GE(wlc_hw->corerev, 18))
2226                         flags |= SICF_PCLKE;
2227
2228                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2229                 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2230                     (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2231                     (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2232                         wlc_hw->regs =
2233                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2234                                                      0);
2235                 si_core_reset(wlc_hw->sih, flags, resetbits);
2236                 wlc_mctrl_reset(wlc_hw);
2237         }
2238
2239         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2240
2241         /* put core back into reset */
2242         if (!clk)
2243                 si_core_disable(wlc_hw->sih, 0);
2244
2245         if (!xtal)
2246                 wlc_bmac_xtal(wlc_hw, OFF);
2247
2248         return v;
2249 }
2250
2251 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2252 void wlc_bmac_hw_up(wlc_hw_info_t *wlc_hw)
2253 {
2254         if (wlc_hw->wlc->pub->hw_up)
2255                 return;
2256
2257         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
2258
2259         /*
2260          * Enable pll and xtal, initialize the power control registers,
2261          * and force fastclock for the remainder of wlc_up().
2262          */
2263         wlc_bmac_xtal(wlc_hw, ON);
2264         si_clkctl_init(wlc_hw->sih);
2265         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2266
2267         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) {
2268                 si_pci_fixcfg(wlc_hw->sih);
2269
2270                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2271                 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2272                     (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2273                     (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2274                         wlc_hw->regs =
2275                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2276                                                      0);
2277         }
2278
2279         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2280         wlc_phy_por_inform(wlc_hw->band->pi);
2281
2282         wlc_hw->ucode_loaded = false;
2283         wlc_hw->wlc->pub->hw_up = true;
2284
2285         if ((wlc_hw->boardflags & BFL_FEM)
2286             && (CHIPID(wlc_hw->sih->chip) == BCM4313_CHIP_ID)) {
2287                 if (!
2288                     (wlc_hw->boardrev >= 0x1250
2289                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2290                         si_epa_4313war(wlc_hw->sih);
2291         }
2292 }
2293
2294 static bool wlc_dma_rxreset(wlc_hw_info_t *wlc_hw, uint fifo)
2295 {
2296         hnddma_t *di = wlc_hw->di[fifo];
2297         osl_t *osh;
2298
2299         if (D11REV_LT(wlc_hw->corerev, 12)) {
2300                 bool rxidle = true;
2301                 u16 rcv_frm_cnt = 0;
2302
2303                 osh = wlc_hw->osh;
2304
2305                 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2306                 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2307                          ((rcv_frm_cnt =
2308                            R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2309                          50000);
2310
2311                 if (!rxidle && (rcv_frm_cnt != 0))
2312                         WL_ERROR(("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n", wlc_hw->unit, __func__, fifo, rcv_frm_cnt));
2313                 mdelay(2);
2314         }
2315
2316         return dma_rxreset(di);
2317 }
2318
2319 /* d11 core reset
2320  *   ensure fask clock during reset
2321  *   reset dma
2322  *   reset d11(out of reset)
2323  *   reset phy(out of reset)
2324  *   clear software macintstatus for fresh new start
2325  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2326  */
2327 void wlc_bmac_corereset(wlc_hw_info_t *wlc_hw, u32 flags)
2328 {
2329         d11regs_t *regs;
2330         uint i;
2331         bool fastclk;
2332         u32 resetbits = 0;
2333
2334         if (flags == WLC_USE_COREFLAGS)
2335                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2336
2337         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
2338
2339         regs = wlc_hw->regs;
2340
2341         /* request FAST clock if not on  */
2342         fastclk = wlc_hw->forcefastclk;
2343         if (!fastclk)
2344                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2345
2346         /* reset the dma engines except first time thru */
2347         if (si_iscoreup(wlc_hw->sih)) {
2348                 for (i = 0; i < NFIFO; i++)
2349                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2350                                 WL_ERROR(("wl%d: %s: dma_txreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, i));
2351                         }
2352
2353                 if ((wlc_hw->di[RX_FIFO])
2354                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2355                         WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_FIFO));
2356                 }
2357                 if (D11REV_IS(wlc_hw->corerev, 4)
2358                     && wlc_hw->di[RX_TXSTATUS_FIFO]
2359                     && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2360                         WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_TXSTATUS_FIFO));
2361                 }
2362         }
2363         /* if noreset, just stop the psm and return */
2364         if (wlc_hw->noreset) {
2365                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2366                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2367                 return;
2368         }
2369
2370         if (D11REV_LE(wlc_hw->corerev, 11))
2371                 resetbits |= SICF_PCLKE;
2372
2373         /*
2374          * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2375          * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2376          * need to enable PHY CLK
2377          */
2378         if (D11REV_GE(wlc_hw->corerev, 18))
2379                 flags |= SICF_PCLKE;
2380
2381         /* reset the core
2382          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2383          *  is cleared by the core_reset. have to re-request it.
2384          *  This adds some delay and we can optimize it by also requesting fastclk through
2385          *  chipcommon during this period if necessary. But that has to work coordinate
2386          *  with other driver like mips/arm since they may touch chipcommon as well.
2387          */
2388         wlc_hw->clk = false;
2389         si_core_reset(wlc_hw->sih, flags, resetbits);
2390         wlc_hw->clk = true;
2391         if (wlc_hw->band && wlc_hw->band->pi)
2392                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2393
2394         wlc_mctrl_reset(wlc_hw);
2395
2396         if (PMUCTL_ENAB(wlc_hw->sih))
2397                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2398
2399         wlc_bmac_phy_reset(wlc_hw);
2400
2401         /* turn on PHY_PLL */
2402         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2403
2404         /* clear sw intstatus */
2405         wlc_hw->wlc->macintstatus = 0;
2406
2407         /* restore the clk setting */
2408         if (!fastclk)
2409                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2410 }
2411
2412 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2413  * txfifo sizes needs to be modified(increased) since the newer cores
2414  * have more memory.
2415  */
2416 static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw)
2417 {
2418         d11regs_t *regs = wlc_hw->regs;
2419         u16 fifo_nu;
2420         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2421         u16 txfifo_def, txfifo_def1;
2422         u16 txfifo_cmd;
2423         osl_t *osh;
2424
2425         if (D11REV_LT(wlc_hw->corerev, 9))
2426                 goto exit;
2427
2428         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2429         txfifo_startblk = TXFIFO_START_BLK;
2430
2431         osh = wlc_hw->osh;
2432
2433         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2434         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2435
2436                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2437                 txfifo_def = (txfifo_startblk & 0xff) |
2438                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2439                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2440                     ((((txfifo_endblk -
2441                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2442                 txfifo_cmd =
2443                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2444
2445                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2446                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2447                 if (D11REV_GE(wlc_hw->corerev, 16))
2448                         W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2449
2450                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2451
2452                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2453         }
2454  exit:
2455         /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2456         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2457                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2458         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2459                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2460         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2461                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2462                             xmtfifo_sz[TX_AC_BK_FIFO]));
2463         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2464                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2465                             xmtfifo_sz[TX_BCMC_FIFO]));
2466 }
2467
2468 /* d11 core init
2469  *   reset PSM
2470  *   download ucode/PCM
2471  *   let ucode run to suspended
2472  *   download ucode inits
2473  *   config other core registers
2474  *   init dma
2475  */
2476 static void wlc_coreinit(wlc_info_t *wlc)
2477 {
2478         wlc_hw_info_t *wlc_hw = wlc->hw;
2479         d11regs_t *regs;
2480         u32 sflags;
2481         uint bcnint_us;
2482         uint i = 0;
2483         bool fifosz_fixup = false;
2484         osl_t *osh;
2485         int err = 0;
2486         u16 buf[NFIFO];
2487
2488         regs = wlc_hw->regs;
2489         osh = wlc_hw->osh;
2490
2491         WL_TRACE(("wl%d: wlc_coreinit\n", wlc_hw->unit));
2492
2493         /* reset PSM */
2494         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2495
2496         wlc_ucode_download(wlc_hw);
2497         /*
2498          * FIFOSZ fixup
2499          * 1) core5-9 use ucode 5 to save space since the PSM is the same
2500          * 2) newer chips, driver wants to controls the fifo allocation
2501          */
2502         if (D11REV_GE(wlc_hw->corerev, 4))
2503                 fifosz_fixup = true;
2504
2505         /* let the PSM run to the suspended state, set mode to BSS STA */
2506         W_REG(osh, &regs->macintstatus, -1);
2507         wlc_bmac_mctrl(wlc_hw, ~0,
2508                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2509
2510         /* wait for ucode to self-suspend after auto-init */
2511         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2512                  1000 * 1000);
2513         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2514                 WL_ERROR(("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2515                           wlc_hw->unit));
2516
2517         wlc_gpio_init(wlc);
2518
2519         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2520
2521         if (D11REV_IS(wlc_hw->corerev, 23)) {
2522                 if (WLCISNPHY(wlc_hw->band))
2523                         wlc_write_inits(wlc_hw, d11n0initvals16);
2524                 else
2525                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2526                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2527         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2528                 if (WLCISLCNPHY(wlc_hw->band)) {
2529                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2530                 } else {
2531                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2532                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2533                 }
2534         } else {
2535                 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
2536                           __func__, wlc_hw->unit, wlc_hw->corerev));
2537         }
2538
2539         /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2540         if (fifosz_fixup == true) {
2541                 wlc_corerev_fifofixup(wlc_hw);
2542         }
2543
2544         /* check txfifo allocations match between ucode and driver */
2545         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2546         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2547                 i = TX_AC_BE_FIFO;
2548                 err = -1;
2549         }
2550         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2551         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2552                 i = TX_AC_VI_FIFO;
2553                 err = -1;
2554         }
2555         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2556         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2557         buf[TX_AC_BK_FIFO] &= 0xff;
2558         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2559                 i = TX_AC_BK_FIFO;
2560                 err = -1;
2561         }
2562         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2563                 i = TX_AC_VO_FIFO;
2564                 err = -1;
2565         }
2566         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2567         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2568         buf[TX_BCMC_FIFO] &= 0xff;
2569         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2570                 i = TX_BCMC_FIFO;
2571                 err = -1;
2572         }
2573         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2574                 i = TX_ATIM_FIFO;
2575                 err = -1;
2576         }
2577         if (err != 0) {
2578                 WL_ERROR(("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n", buf[i], wlc_hw->xmtfifo_sz[i], i));
2579                 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2580                  * shmem, since driver don't overwrite those chip and
2581                  * ucode initialize data will be used.
2582                  */
2583                 if (D11REV_GE(wlc_hw->corerev, 4))
2584                         ASSERT(0);
2585         }
2586
2587         /* make sure we can still talk to the mac */
2588         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2589
2590         /* band-specific inits done by wlc_bsinit() */
2591
2592         /* Set up frame burst size and antenna swap threshold init values */
2593         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2594         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2595
2596         /* enable one rx interrupt per received frame */
2597         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2598         if (D11REV_IS(wlc_hw->corerev, 4))
2599                 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2600
2601         /* set the station mode (BSS STA) */
2602         wlc_bmac_mctrl(wlc_hw,
2603                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2604                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2605
2606         /* set up Beacon interval */
2607         bcnint_us = 0x8000 << 10;
2608         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2609         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2610         W_REG(osh, &regs->macintstatus, MI_GP1);
2611
2612         /* write interrupt mask */
2613         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2614         if (D11REV_IS(wlc_hw->corerev, 4))
2615                 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2616                       DEF_RXINTMASK);
2617
2618         /* allow the MAC to control the PHY clock (dynamic on/off) */
2619         wlc_bmac_macphyclk_set(wlc_hw, ON);
2620
2621         /* program dynamic clock control fast powerup delay register */
2622         if (D11REV_GT(wlc_hw->corerev, 4)) {
2623                 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2624                 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2625         }
2626
2627         /* tell the ucode the corerev */
2628         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2629
2630         /* tell the ucode MAC capabilities */
2631         if (D11REV_GE(wlc_hw->corerev, 13)) {
2632                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2633                                    (u16) (wlc_hw->machwcap & 0xffff));
2634                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2635                                    (u16) ((wlc_hw->
2636                                               machwcap >> 16) & 0xffff));
2637         }
2638
2639         /* write retry limits to SCR, this done after PSM init */
2640         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2641         (void)R_REG(osh, &regs->objaddr);
2642         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2643         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2644         (void)R_REG(osh, &regs->objaddr);
2645         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2646
2647         /* write rate fallback retry limits */
2648         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2649         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2650
2651         if (D11REV_GE(wlc_hw->corerev, 16)) {
2652                 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2653                 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2654         }
2655
2656         /* dma initializations */
2657         wlc->txpend16165war = 0;
2658
2659         /* init the tx dma engines */
2660         for (i = 0; i < NFIFO; i++) {
2661                 if (wlc_hw->di[i])
2662                         dma_txinit(wlc_hw->di[i]);
2663         }
2664
2665         /* init the rx dma engine(s) and post receive buffers */
2666         dma_rxinit(wlc_hw->di[RX_FIFO]);
2667         dma_rxfill(wlc_hw->di[RX_FIFO]);
2668         if (D11REV_IS(wlc_hw->corerev, 4)) {
2669                 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2670                 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2671         }
2672 }
2673
2674 /* This function is used for changing the tsf frac register
2675  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2676  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2677  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2678  * HTPHY Formula is 2^26/freq(MHz) e.g.
2679  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2680  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2681  * For spuron: 123MHz -> 2^26/123    = 545600.5
2682  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2683  * For spur off: 120MHz -> 2^26/120    = 559240.5
2684  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2685  */
2686
2687 void wlc_bmac_switch_macfreq(wlc_hw_info_t *wlc_hw, u8 spurmode)
2688 {
2689         d11regs_t *regs;
2690         osl_t *osh;
2691         regs = wlc_hw->regs;
2692         osh = wlc_hw->osh;
2693
2694         if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2695             (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID)) {
2696                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2697                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2698                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2699                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2700                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2701                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2702                 } else {        /* 120Mhz */
2703                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2704                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2705                 }
2706         } else if (WLCISLCNPHY(wlc_hw->band)) {
2707                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2708                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2709                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2710                 } else {        /* 80Mhz */
2711                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2712                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2713                 }
2714         }
2715 }
2716
2717 /* Initialize GPIOs that are controlled by D11 core */
2718 static void wlc_gpio_init(wlc_info_t *wlc)
2719 {
2720         wlc_hw_info_t *wlc_hw = wlc->hw;
2721         d11regs_t *regs;
2722         u32 gc, gm;
2723         osl_t *osh;
2724
2725         regs = wlc_hw->regs;
2726         osh = wlc_hw->osh;
2727
2728         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2729         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2730
2731         /*
2732          * Common GPIO setup:
2733          *      G0 = LED 0 = WLAN Activity
2734          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2735          *      G2 = LED 2 = WLAN 5 GHz Radio State
2736          *      G4 = radio disable input (HI enabled, LO disabled)
2737          */
2738
2739         gc = gm = 0;
2740
2741         /* Allocate GPIOs for mimo antenna diversity feature */
2742         if (WLANTSEL_ENAB(wlc)) {
2743                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2744                         /* Enable antenna diversity, use 2x3 mode */
2745                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2746                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2747                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2748                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2749
2750                         /* init superswitch control */
2751                         wlc_phy_antsel_init(wlc_hw->band->pi, false);
2752
2753                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2754                         ASSERT((gm & BOARD_GPIO_12) == 0);
2755                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2756                         /* The board itself is powered by these GPIOs (when not sending pattern)
2757                          * So set them high
2758                          */
2759                         OR_REG(osh, &regs->psm_gpio_oe,
2760                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2761                         OR_REG(osh, &regs->psm_gpio_out,
2762                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2763
2764                         /* Enable antenna diversity, use 2x4 mode */
2765                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2766                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2767                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2768                                      WLC_BAND_ALL);
2769
2770                         /* Configure the desired clock to be 4Mhz */
2771                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2772                                            ANTSEL_CLKDIV_4MHZ);
2773                 }
2774         }
2775         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2776         if (wlc_hw->boardflags & BFL_PACTRL)
2777                 gm |= gc |= BOARD_GPIO_PACTRL;
2778
2779         /* apply to gpiocontrol register */
2780         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2781 }
2782
2783 static void wlc_ucode_download(wlc_hw_info_t *wlc_hw)
2784 {
2785         wlc_info_t *wlc;
2786         wlc = wlc_hw->wlc;
2787
2788         if (wlc_hw->ucode_loaded)
2789                 return;
2790
2791         if (D11REV_IS(wlc_hw->corerev, 23)) {
2792                 if (WLCISNPHY(wlc_hw->band)) {
2793                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2794                                         bcm43xx_16_mimosz);
2795                         wlc_hw->ucode_loaded = true;
2796                 } else
2797                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2798                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2799         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2800                 if (WLCISLCNPHY(wlc_hw->band)) {
2801                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2802                                         bcm43xx_24_lcnsz);
2803                         wlc_hw->ucode_loaded = true;
2804                 } else {
2805                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2806                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2807                 }
2808         }
2809 }
2810
2811 static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
2812                               const uint nbytes) {
2813         osl_t *osh;
2814         d11regs_t *regs = wlc_hw->regs;
2815         uint i;
2816         uint count;
2817
2818         osh = wlc_hw->osh;
2819
2820         WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw->unit));
2821
2822         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2823
2824         count = (nbytes / sizeof(u32));
2825
2826         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2827         (void)R_REG(osh, &regs->objaddr);
2828         for (i = 0; i < count; i++)
2829                 W_REG(osh, &regs->objdata, ucode[i]);
2830 }
2831
2832 static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits)
2833 {
2834         int i;
2835         osl_t *osh;
2836         volatile u8 *base;
2837
2838         WL_TRACE(("wl%d: wlc_write_inits\n", wlc_hw->unit));
2839
2840         osh = wlc_hw->osh;
2841         base = (volatile u8 *)wlc_hw->regs;
2842
2843         for (i = 0; inits[i].addr != 0xffff; i++) {
2844                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2845
2846                 if (inits[i].size == 2)
2847                         W_REG(osh, (u16 *)(base + inits[i].addr),
2848                               inits[i].value);
2849                 else if (inits[i].size == 4)
2850                         W_REG(osh, (u32 *)(base + inits[i].addr),
2851                               inits[i].value);
2852         }
2853 }
2854
2855 static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw)
2856 {
2857         u16 phyctl;
2858         u16 phytxant = wlc_hw->bmac_phytxant;
2859         u16 mask = PHY_TXC_ANT_MASK;
2860
2861         /* set the Probe Response frame phy control word */
2862         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2863         phyctl = (phyctl & ~mask) | phytxant;
2864         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2865
2866         /* set the Response (ACK/CTS) frame phy control word */
2867         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2868         phyctl = (phyctl & ~mask) | phytxant;
2869         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2870 }
2871
2872 void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, u16 phytxant)
2873 {
2874         /* update sw state */
2875         wlc_hw->bmac_phytxant = phytxant;
2876
2877         /* push to ucode if up */
2878         if (!wlc_hw->up)
2879                 return;
2880         wlc_ucode_txant_set(wlc_hw);
2881
2882 }
2883
2884 u16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw)
2885 {
2886         return (u16) wlc_hw->wlc->stf->txant;
2887 }
2888
2889 void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type)
2890 {
2891         wlc_hw->antsel_type = antsel_type;
2892
2893         /* Update the antsel type for phy module to use */
2894         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2895 }
2896
2897 void wlc_bmac_fifoerrors(wlc_hw_info_t *wlc_hw)
2898 {
2899         bool fatal = false;
2900         uint unit;
2901         uint intstatus, idx;
2902         d11regs_t *regs = wlc_hw->regs;
2903
2904         unit = wlc_hw->unit;
2905
2906         for (idx = 0; idx < NFIFO; idx++) {
2907                 /* read intstatus register and ignore any non-error bits */
2908                 intstatus =
2909                     R_REG(wlc_hw->osh,
2910                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2911                 if (!intstatus)
2912                         continue;
2913
2914                 WL_TRACE(("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n", unit,
2915                           idx, intstatus));
2916
2917                 if (intstatus & I_RO) {
2918                         WL_ERROR(("wl%d: fifo %d: receive fifo overflow\n",
2919                                   unit, idx));
2920                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
2921                         fatal = true;
2922                 }
2923
2924                 if (intstatus & I_PC) {
2925                         WL_ERROR(("wl%d: fifo %d: descriptor error\n", unit,
2926                                   idx));
2927                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
2928                         fatal = true;
2929                 }
2930
2931                 if (intstatus & I_PD) {
2932                         WL_ERROR(("wl%d: fifo %d: data error\n", unit, idx));
2933                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
2934                         fatal = true;
2935                 }
2936
2937                 if (intstatus & I_DE) {
2938                         WL_ERROR(("wl%d: fifo %d: descriptor protocol error\n",
2939                                   unit, idx));
2940                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
2941                         fatal = true;
2942                 }
2943
2944                 if (intstatus & I_RU) {
2945                         WL_ERROR(("wl%d: fifo %d: receive descriptor underflow\n", unit, idx));
2946                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2947                 }
2948
2949                 if (intstatus & I_XU) {
2950                         WL_ERROR(("wl%d: fifo %d: transmit fifo underflow\n",
2951                                   idx, unit));
2952                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
2953                         fatal = true;
2954                 }
2955
2956                 if (fatal) {
2957                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2958                         break;
2959                 } else
2960                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2961                               intstatus);
2962         }
2963 }
2964
2965 void wlc_intrson(wlc_info_t *wlc)
2966 {
2967         wlc_hw_info_t *wlc_hw = wlc->hw;
2968         ASSERT(wlc->defmacintmask);
2969         wlc->macintmask = wlc->defmacintmask;
2970         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2971 }
2972
2973 /* callback for siutils.c, which has only wlc handler, no wl
2974  * they both check up, not only because there is no need to off/restore d11 interrupt
2975  *  but also because per-port code may require sync with valid interrupt.
2976  */
2977
2978 static u32 wlc_wlintrsoff(wlc_info_t *wlc)
2979 {
2980         if (!wlc->hw->up)
2981                 return 0;
2982
2983         return wl_intrsoff(wlc->wl);
2984 }
2985
2986 static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask)
2987 {
2988         if (!wlc->hw->up)
2989                 return;
2990
2991         wl_intrsrestore(wlc->wl, macintmask);
2992 }
2993
2994 u32 wlc_intrsoff(wlc_info_t *wlc)
2995 {
2996         wlc_hw_info_t *wlc_hw = wlc->hw;
2997         u32 macintmask;
2998
2999         if (!wlc_hw->clk)
3000                 return 0;
3001
3002         macintmask = wlc->macintmask;   /* isr can still happen */
3003
3004         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
3005         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
3006         udelay(1);              /* ensure int line is no longer driven */
3007         wlc->macintmask = 0;
3008
3009         /* return previous macintmask; resolve race between us and our isr */
3010         return wlc->macintstatus ? 0 : macintmask;
3011 }
3012
3013 void wlc_intrsrestore(wlc_info_t *wlc, u32 macintmask)
3014 {
3015         wlc_hw_info_t *wlc_hw = wlc->hw;
3016         if (!wlc_hw->clk)
3017                 return;
3018
3019         wlc->macintmask = macintmask;
3020         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
3021 }
3022
3023 void wlc_bmac_mute(wlc_hw_info_t *wlc_hw, bool on, mbool flags)
3024 {
3025         struct ether_addr null_ether_addr = { {0, 0, 0, 0, 0, 0} };
3026
3027         if (on) {
3028                 /* suspend tx fifos */
3029                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
3030                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
3031                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
3032                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
3033
3034                 /* zero the address match register so we do not send ACKs */
3035                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3036                                        &null_ether_addr);
3037         } else {
3038                 /* resume tx fifos */
3039                 if (!wlc_hw->wlc->tx_suspended) {
3040                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3041                 }
3042                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3043                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3044                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3045
3046                 /* Restore address */
3047                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3048                                        &wlc_hw->etheraddr);
3049         }
3050
3051         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3052
3053         if (on)
3054                 wlc_ucode_mute_override_set(wlc_hw);
3055         else
3056                 wlc_ucode_mute_override_clear(wlc_hw);
3057 }
3058
3059 void wlc_bmac_set_deaf(wlc_hw_info_t *wlc_hw, bool user_flag)
3060 {
3061         wlc_phy_set_deaf(wlc_hw->band->pi, user_flag);
3062 }
3063
3064 int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t *wlc_hw, uint fifo, uint *blocks)
3065 {
3066         if (fifo >= NFIFO)
3067                 return BCME_RANGE;
3068
3069         *blocks = wlc_hw->xmtfifo_sz[fifo];
3070
3071         return 0;
3072 }
3073
3074 int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, uint blocks)
3075 {
3076         if (fifo >= NFIFO || blocks > 299)
3077                 return BCME_RANGE;
3078
3079         /* BMAC_NOTE, change blocks to u16 */
3080         wlc_hw->xmtfifo_sz[fifo] = (u16) blocks;
3081
3082         return 0;
3083 }
3084
3085 /* wlc_bmac_tx_fifo_suspended:
3086  * Check the MAC's tx suspend status for a tx fifo.
3087  *
3088  * When the MAC acknowledges a tx suspend, it indicates that no more
3089  * packets will be transmitted out the radio. This is independent of
3090  * DMA channel suspension---the DMA may have finished suspending, or may still
3091  * be pulling data into a tx fifo, by the time the MAC acks the suspend
3092  * request.
3093  */
3094 bool wlc_bmac_tx_fifo_suspended(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3095 {
3096         /* check that a suspend has been requested and is no longer pending */
3097
3098         /*
3099          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3100          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3101          * chnstatus register.
3102          * The tx fifo suspend completion is independent of the DMA suspend completion and
3103          *   may be acked before or after the DMA is suspended.
3104          */
3105         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3106             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3107              (1 << tx_fifo)) == 0)
3108                 return true;
3109
3110         return false;
3111 }
3112
3113 void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3114 {
3115         u8 fifo = 1 << tx_fifo;
3116
3117         /* Two clients of this code, 11h Quiet period and scanning. */
3118
3119         /* only suspend if not already suspended */
3120         if ((wlc_hw->suspended_fifos & fifo) == fifo)
3121                 return;
3122
3123         /* force the core awake only if not already */
3124         if (wlc_hw->suspended_fifos == 0)
3125                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3126
3127         wlc_hw->suspended_fifos |= fifo;
3128
3129         if (wlc_hw->di[tx_fifo]) {
3130                 /* Suspending AMPDU transmissions in the middle can cause underflow
3131                  * which may result in mismatch between ucode and driver
3132                  * so suspend the mac before suspending the FIFO
3133                  */
3134                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3135                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
3136
3137                 dma_txsuspend(wlc_hw->di[tx_fifo]);
3138
3139                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3140                         wlc_enable_mac(wlc_hw->wlc);
3141         }
3142 }
3143
3144 void wlc_bmac_tx_fifo_resume(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3145 {
3146         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3147          * here for PIO otherwise the watchdog will catch the inconsistency and fire
3148          */
3149         /* Two clients of this code, 11h Quiet period and scanning. */
3150         if (wlc_hw->di[tx_fifo])
3151                 dma_txresume(wlc_hw->di[tx_fifo]);
3152
3153         /* allow core to sleep again */
3154         if (wlc_hw->suspended_fifos == 0)
3155                 return;
3156         else {
3157                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3158                 if (wlc_hw->suspended_fifos == 0)
3159                         wlc_ucode_wake_override_clear(wlc_hw,
3160                                                       WLC_WAKE_OVERRIDE_TXFIFO);
3161         }
3162 }
3163
3164 /*
3165  * Read and clear macintmask and macintstatus and intstatus registers.
3166  * This routine should be called with interrupts off
3167  * Return:
3168  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
3169  *   0 if the interrupt is not for us, or we are in some special cases;
3170  *   device interrupt status bits otherwise.
3171  */
3172 static inline u32 wlc_intstatus(wlc_info_t *wlc, bool in_isr)
3173 {
3174         wlc_hw_info_t *wlc_hw = wlc->hw;
3175         d11regs_t *regs = wlc_hw->regs;
3176         u32 macintstatus;
3177         u32 intstatus_rxfifo, intstatus_txsfifo;
3178         osl_t *osh;
3179
3180         osh = wlc_hw->osh;
3181
3182         /* macintstatus includes a DMA interrupt summary bit */
3183         macintstatus = R_REG(osh, &regs->macintstatus);
3184
3185         WL_TRACE(("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus));
3186
3187         /* detect cardbus removed, in power down(suspend) and in reset */
3188         if (DEVICEREMOVED(wlc))
3189                 return -1;
3190
3191         /* DEVICEREMOVED succeeds even when the core is still resetting,
3192          * handle that case here.
3193          */
3194         if (macintstatus == 0xffffffff)
3195                 return 0;
3196
3197         /* defer unsolicited interrupts */
3198         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3199
3200         /* if not for us */
3201         if (macintstatus == 0)
3202                 return 0;
3203
3204         /* interrupts are already turned off for CFE build
3205          * Caution: For CFE Turning off the interrupts again has some undesired
3206          * consequences
3207          */
3208         /* turn off the interrupts */
3209         W_REG(osh, &regs->macintmask, 0);
3210 #ifndef BCMSDIO
3211         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3212 #endif
3213         wlc->macintmask = 0;
3214
3215         /* clear device interrupts */
3216         W_REG(osh, &regs->macintstatus, macintstatus);
3217
3218         /* MI_DMAINT is indication of non-zero intstatus */
3219         if (macintstatus & MI_DMAINT) {
3220                 if (D11REV_IS(wlc_hw->corerev, 4)) {
3221                         intstatus_rxfifo =
3222                             R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3223                         intstatus_txsfifo =
3224                             R_REG(osh,
3225                                   &regs->intctrlregs[RX_TXSTATUS_FIFO].
3226                                   intstatus);
3227                         WL_TRACE(("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n", wlc_hw->unit, intstatus_rxfifo, intstatus_txsfifo));
3228
3229                         /* defer unsolicited interrupt hints */
3230                         intstatus_rxfifo &= DEF_RXINTMASK;
3231                         intstatus_txsfifo &= DEF_RXINTMASK;
3232
3233                         /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3234                         /* clear interrupt hints */
3235                         if (intstatus_rxfifo)
3236                                 W_REG(osh,
3237                                       &regs->intctrlregs[RX_FIFO].intstatus,
3238                                       intstatus_rxfifo);
3239                         else
3240                                 macintstatus &= ~MI_DMAINT;
3241
3242                         /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3243                         if (intstatus_txsfifo) {
3244                                 W_REG(osh,
3245                                       &regs->intctrlregs[RX_TXSTATUS_FIFO].
3246                                       intstatus, intstatus_txsfifo);
3247                                 macintstatus |= MI_TFS;
3248                         }
3249                 } else {
3250                         /*
3251                          * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3252                          * If MI_DMAINT is set, assume it is set and clear the interrupt.
3253                          */
3254                         W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3255                               DEF_RXINTMASK);
3256                 }
3257         }
3258
3259         return macintstatus;
3260 }
3261
3262 /* Update wlc->macintstatus and wlc->intstatus[]. */
3263 /* Return true if they are updated successfully. false otherwise */
3264 bool wlc_intrsupd(wlc_info_t *wlc)
3265 {
3266         u32 macintstatus;
3267
3268         ASSERT(wlc->macintstatus != 0);
3269
3270         /* read and clear macintstatus and intstatus registers */
3271         macintstatus = wlc_intstatus(wlc, false);
3272
3273         /* device is removed */
3274         if (macintstatus == 0xffffffff)
3275                 return false;
3276
3277         /* update interrupt status in software */
3278         wlc->macintstatus |= macintstatus;
3279
3280         return true;
3281 }
3282
3283 /*
3284  * First-level interrupt processing.
3285  * Return true if this was our interrupt, false otherwise.
3286  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3287  * false otherwise.
3288  */
3289 bool BCMFASTPATH wlc_isr(wlc_info_t *wlc, bool *wantdpc)
3290 {
3291         wlc_hw_info_t *wlc_hw = wlc->hw;
3292         u32 macintstatus;
3293
3294         *wantdpc = false;
3295
3296         if (!wlc_hw->up || !wlc->macintmask)
3297                 return false;
3298
3299         /* read and clear macintstatus and intstatus registers */
3300         macintstatus = wlc_intstatus(wlc, true);
3301
3302         if (macintstatus == 0xffffffff)
3303                 WL_ERROR(("DEVICEREMOVED detected in the ISR code path.\n"));
3304
3305         /* it is not for us */
3306         if (macintstatus == 0)
3307                 return false;
3308
3309         *wantdpc = true;
3310
3311         /* save interrupt status bits */
3312         ASSERT(wlc->macintstatus == 0);
3313         wlc->macintstatus = macintstatus;
3314
3315         return true;
3316
3317 }
3318
3319 /* process tx completion events for corerev < 5 */
3320 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc_hw)
3321 {
3322         void *status_p;
3323         tx_status_t *txs;
3324         osl_t *osh;
3325         bool fatal = false;
3326
3327         WL_TRACE(("wl%d: wlc_txstatusrecv\n", wlc_hw->unit));
3328
3329         osh = wlc_hw->osh;
3330
3331         while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3332
3333                 txs = (tx_status_t *) PKTDATA(status_p);
3334                 /* MAC uses little endian only */
3335                 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3336
3337                 /* shift low bits for tx_status_t status compatibility */
3338                 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3339                     | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3340
3341                 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3342
3343                 PKTFREE(osh, status_p, false);
3344         }
3345
3346         if (fatal)
3347                 return true;
3348
3349         /* post more rbufs */
3350         dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3351
3352         return false;
3353 }
3354
3355 static bool BCMFASTPATH
3356 wlc_bmac_dotxstatus(wlc_hw_info_t *wlc_hw, tx_status_t *txs, u32 s2)
3357 {
3358         /* discard intermediate indications for ucode with one legitimate case:
3359          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3360          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3361          *   transmission count)
3362          */
3363         if (!(txs->status & TX_STATUS_AMPDU)
3364             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3365                 return false;
3366         }
3367
3368         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3369 }
3370
3371 /* process tx completion events in BMAC
3372  * Return true if more tx status need to be processed. false otherwise.
3373  */
3374 static bool BCMFASTPATH
3375 wlc_bmac_txstatus(wlc_hw_info_t *wlc_hw, bool bound, bool *fatal)
3376 {
3377         bool morepending = false;
3378         wlc_info_t *wlc = wlc_hw->wlc;
3379
3380         WL_TRACE(("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit));
3381
3382         if (D11REV_IS(wlc_hw->corerev, 4)) {
3383                 /* to retire soon */
3384                 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3385
3386                 if (*fatal)
3387                         return 0;
3388         } else {
3389                 /* corerev >= 5 */
3390                 d11regs_t *regs;
3391                 osl_t *osh;
3392                 tx_status_t txstatus, *txs;
3393                 u32 s1, s2;
3394                 uint n = 0;
3395                 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3396                 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3397
3398                 txs = &txstatus;
3399                 regs = wlc_hw->regs;
3400                 osh = wlc_hw->osh;
3401                 while (!(*fatal)
3402                        && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3403
3404                         if (s1 == 0xffffffff) {
3405                                 WL_ERROR(("wl%d: %s: dead chip\n",
3406                                           wlc_hw->unit, __func__));
3407                                 ASSERT(s1 != 0xffffffff);
3408                                 return morepending;
3409                         }
3410
3411                         s2 = R_REG(osh, &regs->frmtxstatus2);
3412
3413                         txs->status = s1 & TXS_STATUS_MASK;
3414                         txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3415                         txs->sequence = s2 & TXS_SEQ_MASK;
3416                         txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3417                         txs->lasttxtime = 0;
3418
3419                         *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3420
3421                         /* !give others some time to run! */
3422                         if (++n >= max_tx_num)
3423                                 break;
3424                 }
3425
3426                 if (*fatal)
3427                         return 0;
3428
3429                 if (n >= max_tx_num)
3430                         morepending = true;
3431         }
3432
3433         if (!pktq_empty(&wlc->active_queue->q))
3434                 wlc_send_q(wlc, wlc->active_queue);
3435
3436         return morepending;
3437 }
3438
3439 void wlc_suspend_mac_and_wait(wlc_info_t *wlc)
3440 {
3441         wlc_hw_info_t *wlc_hw = wlc->hw;
3442         d11regs_t *regs = wlc_hw->regs;
3443         u32 mc, mi;
3444         osl_t *osh;
3445
3446         WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw->unit,
3447                   wlc_hw->band->bandunit));
3448
3449         /*
3450          * Track overlapping suspend requests
3451          */
3452         wlc_hw->mac_suspend_depth++;
3453         if (wlc_hw->mac_suspend_depth > 1)
3454                 return;
3455
3456         osh = wlc_hw->osh;
3457
3458         /* force the core awake */
3459         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3460
3461         mc = R_REG(osh, &regs->maccontrol);
3462
3463         if (mc == 0xffffffff) {
3464                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3465                 wl_down(wlc->wl);
3466                 return;
3467         }
3468         ASSERT(!(mc & MCTL_PSM_JMP_0));
3469         ASSERT(mc & MCTL_PSM_RUN);
3470         ASSERT(mc & MCTL_EN_MAC);
3471
3472         mi = R_REG(osh, &regs->macintstatus);
3473         if (mi == 0xffffffff) {
3474                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3475                 wl_down(wlc->wl);
3476                 return;
3477         }
3478         ASSERT(!(mi & MI_MACSSPNDD));
3479
3480         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3481
3482         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3483                  WLC_MAX_MAC_SUSPEND);
3484
3485         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3486                 WL_ERROR(("wl%d: wlc_suspend_mac_and_wait: waited %d uS and "
3487                           "MI_MACSSPNDD is still not on.\n",
3488                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND));
3489                 WL_ERROR(("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n", wlc_hw->unit, R_REG(osh, &regs->psmdebug), R_REG(osh, &regs->phydebug), R_REG(osh, &regs->psm_brc)));
3490         }
3491
3492         mc = R_REG(osh, &regs->maccontrol);
3493         if (mc == 0xffffffff) {
3494                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3495                 wl_down(wlc->wl);
3496                 return;
3497         }
3498         ASSERT(!(mc & MCTL_PSM_JMP_0));
3499         ASSERT(mc & MCTL_PSM_RUN);
3500         ASSERT(!(mc & MCTL_EN_MAC));
3501 }
3502
3503 void wlc_enable_mac(wlc_info_t *wlc)
3504 {
3505         wlc_hw_info_t *wlc_hw = wlc->hw;
3506         d11regs_t *regs = wlc_hw->regs;
3507         u32 mc, mi;
3508         osl_t *osh;
3509
3510         WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw->unit,
3511                   wlc->band->bandunit));
3512
3513         /*
3514          * Track overlapping suspend requests
3515          */
3516         ASSERT(wlc_hw->mac_suspend_depth > 0);
3517         wlc_hw->mac_suspend_depth--;
3518         if (wlc_hw->mac_suspend_depth > 0)
3519                 return;
3520
3521         osh = wlc_hw->osh;
3522
3523         mc = R_REG(osh, &regs->maccontrol);
3524         ASSERT(!(mc & MCTL_PSM_JMP_0));
3525         ASSERT(!(mc & MCTL_EN_MAC));
3526         ASSERT(mc & MCTL_PSM_RUN);
3527
3528         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3529         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3530
3531         mc = R_REG(osh, &regs->maccontrol);
3532         ASSERT(!(mc & MCTL_PSM_JMP_0));
3533         ASSERT(mc & MCTL_EN_MAC);
3534         ASSERT(mc & MCTL_PSM_RUN);
3535
3536         mi = R_REG(osh, &regs->macintstatus);
3537         ASSERT(!(mi & MI_MACSSPNDD));
3538
3539         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3540 }
3541
3542 void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t *wlc_hw, bool abie, bool isht)
3543 {
3544         if (!(WLCISNPHY(wlc_hw->band) && (D11REV_GE(wlc_hw->corerev, 16))))
3545                 return;
3546
3547         if (isht) {
3548                 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 3)) {
3549                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3550                                 ~IFS_CTL1_EDCRS);
3551                 }
3552         } else {
3553                 /* enable EDCRS for non-11n association */
3554                 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1, IFS_CTL1_EDCRS);
3555         }
3556
3557         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3)) {
3558                 if (CHSPEC_IS20(wlc_hw->chanspec)) {
3559                         /* 20 mhz, use 20U ED only */
3560                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3561                                IFS_CTL1_EDCRS);
3562                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3563                                 ~IFS_CTL1_EDCRS_20L);
3564                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3565                                 ~IFS_CTL1_EDCRS_40);
3566                 } else {
3567                         /* 40 mhz, use 20U 20L and 40 ED */
3568                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3569                                IFS_CTL1_EDCRS);
3570                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3571                                IFS_CTL1_EDCRS_20L);
3572                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3573                                IFS_CTL1_EDCRS_40);
3574                 }
3575         }
3576 }
3577
3578 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw)
3579 {
3580         u8 rate;
3581         u8 rates[8] = {
3582                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3583                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3584         };
3585         u16 entry_ptr;
3586         u16 pctl1;
3587         uint i;
3588
3589         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3590                 return;
3591
3592         /* walk the phy rate table and update the entries */
3593         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3594                 rate = rates[i];
3595
3596                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3597
3598                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3599                 pctl1 =
3600                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3601
3602                 /* modify the value */
3603                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3604                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3605
3606                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3607                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3608                                    pctl1);
3609         }
3610 }
3611
3612 static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, u8 rate)
3613 {
3614         uint i;
3615         u8 plcp_rate = 0;
3616         struct plcp_signal_rate_lookup {
3617                 u8 rate;
3618                 u8 signal_rate;
3619         };
3620         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3621         const struct plcp_signal_rate_lookup rate_lookup[] = {
3622                 {WLC_RATE_6M, 0xB},
3623                 {WLC_RATE_9M, 0xF},
3624                 {WLC_RATE_12M, 0xA},
3625                 {WLC_RATE_18M, 0xE},
3626                 {WLC_RATE_24M, 0x9},
3627                 {WLC_RATE_36M, 0xD},
3628                 {WLC_RATE_48M, 0x8},
3629                 {WLC_RATE_54M, 0xC}
3630         };
3631
3632         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3633                 if (rate == rate_lookup[i].rate) {
3634                         plcp_rate = rate_lookup[i].signal_rate;
3635                         break;
3636                 }
3637         }
3638
3639         /* Find the SHM pointer to the rate table entry by looking in the
3640          * Direct-map Table
3641          */
3642         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3643 }
3644
3645 void wlc_bmac_band_stf_ss_set(wlc_hw_info_t *wlc_hw, u8 stf_mode)
3646 {
3647         wlc_hw->hw_stf_ss_opmode = stf_mode;
3648
3649         if (wlc_hw->clk)
3650                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3651 }
3652
3653 void BCMFASTPATH
3654 wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, u32 *tsf_l_ptr,
3655                   u32 *tsf_h_ptr)
3656 {
3657         d11regs_t *regs = wlc_hw->regs;
3658
3659         /* read the tsf timer low, then high to get an atomic read */
3660         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3661         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3662
3663         return;
3664 }
3665
3666 bool wlc_bmac_validate_chip_access(wlc_hw_info_t *wlc_hw)
3667 {
3668         d11regs_t *regs;
3669         u32 w, val;
3670         volatile u16 *reg16;
3671         osl_t *osh;
3672
3673         WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw->unit));
3674
3675         regs = wlc_hw->regs;
3676         osh = wlc_hw->osh;
3677
3678         /* Validate dchip register access */
3679
3680         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3681         (void)R_REG(osh, &regs->objaddr);
3682         w = R_REG(osh, &regs->objdata);
3683
3684         /* Can we write and read back a 32bit register? */
3685         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3686         (void)R_REG(osh, &regs->objaddr);
3687         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3688
3689         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3690         (void)R_REG(osh, &regs->objaddr);
3691         val = R_REG(osh, &regs->objdata);
3692         if (val != (u32) 0xaa5555aa) {
3693                 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val));
3694                 return false;
3695         }
3696
3697         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3698         (void)R_REG(osh, &regs->objaddr);
3699         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3700
3701         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3702         (void)R_REG(osh, &regs->objaddr);
3703         val = R_REG(osh, &regs->objdata);
3704         if (val != (u32) 0x55aaaa55) {
3705                 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val));
3706                 return false;
3707         }
3708
3709         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3710         (void)R_REG(osh, &regs->objaddr);
3711         W_REG(osh, &regs->objdata, w);
3712
3713         if (D11REV_LT(wlc_hw->corerev, 11)) {
3714                 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3715                  * for our interface, low to high
3716                  */
3717                 reg16 = (volatile u16 *)&regs->tsf_cfpstart;
3718
3719                 /* write the CFPStart register low half explicitly, starting a buffered write */
3720                 W_REG(osh, reg16, 0xAAAA);
3721
3722                 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3723                  * If the low 16 bits are written first, followed by the high 16 bits then the
3724                  * 32 bit value 0xCCCCBBBB should end up in the register.
3725                  * If the order is reversed, then the write to the high half will trigger a buffered
3726                  * write of 0xCCCCAAAA.
3727                  * If the bus is 32 bits, then this is not much of a test, and the reg should
3728                  * have the correct value 0xCCCCBBBB.
3729                  */
3730                 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3731
3732                 /* verify with the 16 bit registers that have no side effects */
3733                 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3734                 if (val != (uint) 0xBBBB) {
3735                         WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xBBBB));
3736                         return false;
3737                 }
3738                 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3739                 if (val != (uint) 0xCCCC) {
3740                         WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xCCCC));
3741                         return false;
3742                 }
3743
3744         }
3745
3746         /* clear CFPStart */
3747         W_REG(osh, &regs->tsf_cfpstart, 0);
3748
3749         w = R_REG(osh, &regs->maccontrol);
3750         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3751             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3752                 WL_ERROR(("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, (MCTL_IHR_EN | MCTL_WAKE), (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)));
3753                 return false;
3754         }
3755
3756         return true;
3757 }
3758
3759 #define PHYPLL_WAIT_US  100000
3760
3761 void wlc_bmac_core_phypll_ctl(wlc_hw_info_t *wlc_hw, bool on)
3762 {
3763         d11regs_t *regs;
3764         osl_t *osh;
3765         u32 tmp;
3766
3767         WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit));
3768
3769         tmp = 0;
3770         regs = wlc_hw->regs;
3771         osh = wlc_hw->osh;
3772
3773         if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3774                 return;
3775
3776         if (on) {
3777                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3778                         OR_REG(osh, &regs->clk_ctl_st,
3779                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3780                                 CCS_ERSRC_REQ_PHYPLL));
3781                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3782                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3783                                  PHYPLL_WAIT_US);
3784
3785                         tmp = R_REG(osh, &regs->clk_ctl_st);
3786                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3787                             (CCS_ERSRC_AVAIL_HT)) {
3788                                 WL_ERROR(("%s: turn on PHY PLL failed\n",
3789                                           __func__));
3790                                 ASSERT(0);
3791                         }
3792                 } else {
3793                         OR_REG(osh, &regs->clk_ctl_st,
3794                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3795                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3796                                   (CCS_ERSRC_AVAIL_D11PLL |
3797                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3798                                  (CCS_ERSRC_AVAIL_D11PLL |
3799                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3800
3801                         tmp = R_REG(osh, &regs->clk_ctl_st);
3802                         if ((tmp &
3803                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3804                             !=
3805                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3806                                 WL_ERROR(("%s: turn on PHY PLL failed\n",
3807                                           __func__));
3808                                 ASSERT(0);
3809                         }
3810                 }
3811         } else {
3812                 /* Since the PLL may be shared, other cores can still be requesting it;
3813                  * so we'll deassert the request but not wait for status to comply.
3814                  */
3815                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3816                 tmp = R_REG(osh, &regs->clk_ctl_st);
3817         }
3818 }
3819
3820 void wlc_coredisable(wlc_hw_info_t *wlc_hw)
3821 {
3822         bool dev_gone;
3823
3824         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
3825
3826         ASSERT(!wlc_hw->up);
3827
3828         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3829
3830         if (dev_gone)
3831                 return;
3832
3833         if (wlc_hw->noreset)
3834                 return;
3835
3836         /* radio off */
3837         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3838
3839         /* turn off analog core */
3840         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3841
3842         /* turn off PHYPLL to save power */
3843         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3844
3845         /* No need to set wlc->pub->radio_active = OFF
3846          * because this function needs down capability and
3847          * radio_active is designed for BCMNODOWN.
3848          */
3849
3850         /* remove gpio controls */
3851         if (wlc_hw->ucode_dbgsel)
3852                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3853
3854         wlc_hw->clk = false;
3855         si_core_disable(wlc_hw->sih, 0);
3856         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3857 }
3858
3859 /* power both the pll and external oscillator on/off */
3860 void wlc_bmac_xtal(wlc_hw_info_t *wlc_hw, bool want)
3861 {
3862         WL_TRACE(("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want));
3863
3864         /* dont power down if plldown is false or we must poll hw radio disable */
3865         if (!want && wlc_hw->pllreq)
3866                 return;
3867
3868         if (wlc_hw->sih)
3869                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3870
3871         wlc_hw->sbclk = want;
3872         if (!wlc_hw->sbclk) {
3873                 wlc_hw->clk = false;
3874                 if (wlc_hw->band && wlc_hw->band->pi)
3875                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3876         }
3877 }
3878
3879 static void wlc_flushqueues(wlc_info_t *wlc)
3880 {
3881         wlc_hw_info_t *wlc_hw = wlc->hw;
3882         uint i;
3883
3884         wlc->txpend16165war = 0;
3885
3886         /* free any posted tx packets */
3887         for (i = 0; i < NFIFO; i++)
3888                 if (wlc_hw->di[i]) {
3889                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3890                         TXPKTPENDCLR(wlc, i);
3891                         WL_TRACE(("wlc_flushqueues: pktpend fifo %d cleared\n",
3892                                   i));
3893                 }
3894
3895         /* free any posted rx packets */
3896         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3897         if (D11REV_IS(wlc_hw->corerev, 4))
3898                 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3899 }
3900
3901 u16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset)
3902 {
3903         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3904 }
3905
3906 void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v)
3907 {
3908         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3909 }
3910
3911 /* Set a range of shared memory to a value.
3912  * SHM 'offset' needs to be an even address and
3913  * Buffer length 'len' must be an even number of bytes
3914  */
3915 void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v, int len)
3916 {
3917         int i;
3918
3919         /* offset and len need to be even */
3920         ASSERT((offset & 1) == 0);
3921         ASSERT((len & 1) == 0);
3922
3923         if (len <= 0)
3924                 return;
3925
3926         for (i = 0; i < len; i += 2) {
3927                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3928         }
3929 }
3930
3931 static u16
3932 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, u32 sel)
3933 {
3934         d11regs_t *regs = wlc_hw->regs;
3935         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3936         volatile u16 *objdata_hi = objdata_lo + 1;
3937         u16 v;
3938
3939         ASSERT((offset & 1) == 0);
3940
3941         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3942         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3943         if (offset & 2) {
3944                 v = R_REG(wlc_hw->osh, objdata_hi);
3945         } else {
3946                 v = R_REG(wlc_hw->osh, objdata_lo);
3947         }
3948
3949         return v;
3950 }
3951
3952 static void
3953 wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, u32 sel)
3954 {
3955         d11regs_t *regs = wlc_hw->regs;
3956         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3957         volatile u16 *objdata_hi = objdata_lo + 1;
3958
3959         ASSERT((offset & 1) == 0);
3960
3961         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3962         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3963         if (offset & 2) {
3964                 W_REG(wlc_hw->osh, objdata_hi, v);
3965         } else {
3966                 W_REG(wlc_hw->osh, objdata_lo, v);
3967         }
3968 }
3969
3970 /* Copy a buffer to shared memory of specified type .
3971  * SHM 'offset' needs to be an even address and
3972  * Buffer length 'len' must be an even number of bytes
3973  * 'sel' selects the type of memory
3974  */
3975 void
3976 wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf,
3977                        int len, u32 sel)
3978 {
3979         u16 v;
3980         const u8 *p = (const u8 *)buf;
3981         int i;
3982
3983         /* offset and len need to be even */
3984         ASSERT((offset & 1) == 0);
3985         ASSERT((len & 1) == 0);
3986
3987         if (len <= 0)
3988                 return;
3989
3990         for (i = 0; i < len; i += 2) {
3991                 v = p[i] | (p[i + 1] << 8);
3992                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3993         }
3994 }
3995
3996 /* Copy a piece of shared memory of specified type to a buffer .
3997  * SHM 'offset' needs to be an even address and
3998  * Buffer length 'len' must be an even number of bytes
3999  * 'sel' selects the type of memory
4000  */
4001 void
4002 wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf,
4003                          int len, u32 sel)
4004 {
4005         u16 v;
4006         u8 *p = (u8 *) buf;
4007         int i;
4008
4009         /* offset and len need to be even */
4010         ASSERT((offset & 1) == 0);
4011         ASSERT((len & 1) == 0);
4012
4013         if (len <= 0)
4014                 return;
4015
4016         for (i = 0; i < len; i += 2) {
4017                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
4018                 p[i] = v & 0xFF;
4019                 p[i + 1] = (v >> 8) & 0xFF;
4020         }
4021 }
4022
4023 void wlc_bmac_copyfrom_vars(wlc_hw_info_t *wlc_hw, char **buf, uint *len)
4024 {
4025         WL_TRACE(("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
4026                   wlc_hw->vars_size));
4027
4028         *buf = wlc_hw->vars;
4029         *len = wlc_hw->vars_size;
4030 }
4031
4032 void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, u16 SRL, u16 LRL)
4033 {
4034         wlc_hw->SRL = SRL;
4035         wlc_hw->LRL = LRL;
4036
4037         /* write retry limit to SCR, shouldn't need to suspend */
4038         if (wlc_hw->up) {
4039                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4040                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
4041                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4042                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
4043                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4044                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
4045                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4046                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
4047         }
4048 }
4049
4050 void wlc_bmac_set_noreset(wlc_hw_info_t *wlc_hw, bool noreset_flag)
4051 {
4052         wlc_hw->noreset = noreset_flag;
4053 }
4054
4055 void wlc_bmac_set_ucode_loaded(wlc_hw_info_t *wlc_hw, bool ucode_loaded)
4056 {
4057         wlc_hw->ucode_loaded = ucode_loaded;
4058 }
4059
4060 void wlc_bmac_pllreq(wlc_hw_info_t *wlc_hw, bool set, mbool req_bit)
4061 {
4062         ASSERT(req_bit);
4063
4064         if (set) {
4065                 if (mboolisset(wlc_hw->pllreq, req_bit))
4066                         return;
4067
4068                 mboolset(wlc_hw->pllreq, req_bit);
4069
4070                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4071                         if (!wlc_hw->sbclk) {
4072                                 wlc_bmac_xtal(wlc_hw, ON);
4073                         }
4074                 }
4075         } else {
4076                 if (!mboolisset(wlc_hw->pllreq, req_bit))
4077                         return;
4078
4079                 mboolclr(wlc_hw->pllreq, req_bit);
4080
4081                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4082                         if (wlc_hw->sbclk) {
4083                                 wlc_bmac_xtal(wlc_hw, OFF);
4084                         }
4085                 }
4086         }
4087
4088         return;
4089 }
4090
4091 void wlc_bmac_set_clk(wlc_hw_info_t *wlc_hw, bool on)
4092 {
4093         if (on) {
4094                 /* power up pll and oscillator */
4095                 wlc_bmac_xtal(wlc_hw, ON);
4096
4097                 /* enable core(s), ignore bandlocked
4098                  * Leave with the same band selected as we entered
4099                  */
4100                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
4101         } else {
4102                 /* if already down, must skip the core disable */
4103                 if (wlc_hw->clk) {
4104                         /* disable core(s), ignore bandlocked */
4105                         wlc_coredisable(wlc_hw);
4106                 }
4107                 /* power down pll and oscillator */
4108                 wlc_bmac_xtal(wlc_hw, OFF);
4109         }
4110 }
4111
4112 /* this will be true for all ai chips */
4113 bool wlc_bmac_taclear(wlc_hw_info_t *wlc_hw, bool ta_ok)
4114 {
4115         return true;
4116 }
4117
4118 /* Lower down relevant GPIOs like LED when going down w/o
4119  * doing PCI config cycles or touching interrupts
4120  */
4121 void wlc_gpio_fast_deinit(wlc_hw_info_t *wlc_hw)
4122 {
4123         if ((wlc_hw == NULL) || (wlc_hw->sih == NULL))
4124                 return;
4125
4126         /* Only chips with internal bus or PCIE cores or certain PCI cores
4127          * are able to switch cores w/o disabling interrupts
4128          */
4129         if (!((BUSTYPE(wlc_hw->sih->bustype) == SI_BUS) ||
4130               ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) &&
4131                ((wlc_hw->sih->buscoretype == PCIE_CORE_ID) ||
4132                 (wlc_hw->sih->buscorerev >= 13)))))
4133                 return;
4134
4135         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
4136         return;
4137 }
4138
4139 bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable)
4140 {
4141         /* Do not access Phy registers if core is not up */
4142         if (si_iscoreup(wlc_hw->sih) == false)
4143                 return false;
4144
4145         if (enable) {
4146                 if (PMUCTL_ENAB(wlc_hw->sih)) {
4147                         AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4148                                 ~CCS_FORCEHWREQOFF);
4149                         si_pmu_radio_enable(wlc_hw->sih, true);
4150                 }
4151
4152                 wlc_phy_anacore(wlc_hw->band->pi, ON);
4153                 wlc_phy_switch_radio(wlc_hw->band->pi, ON);
4154
4155                 /* resume d11 core */
4156                 wlc_enable_mac(wlc_hw->wlc);
4157         } else {
4158                 /* suspend d11 core */
4159                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
4160
4161                 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
4162                 wlc_phy_anacore(wlc_hw->band->pi, OFF);
4163
4164                 if (PMUCTL_ENAB(wlc_hw->sih)) {
4165                         si_pmu_radio_enable(wlc_hw->sih, false);
4166                         OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4167                                CCS_FORCEHWREQOFF);
4168                 }
4169         }
4170
4171         return true;
4172 }
4173
4174 u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate)
4175 {
4176         u16 table_ptr;
4177         u8 phy_rate, index;
4178
4179         /* get the phy specific rate encoding for the PLCP SIGNAL field */
4180         /* XXX4321 fixup needed ? */
4181         if (IS_OFDM(rate))
4182                 table_ptr = M_RT_DIRMAP_A;
4183         else
4184                 table_ptr = M_RT_DIRMAP_B;
4185
4186         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4187          * the index into the rate table.
4188          */
4189         phy_rate = rate_info[rate] & RATE_MASK;
4190         index = phy_rate & 0xf;
4191
4192         /* Find the SHM pointer to the rate table entry by looking in the
4193          * Direct-map Table
4194          */
4195         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
4196 }
4197
4198 void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val)
4199 {
4200         wlc_phy_txpwr_percent_set(wlc_hw->band->pi, val);
4201 }
4202
4203 void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, u32 antsel_avail)
4204 {
4205         wlc_hw->antsel_avail = antsel_avail;
4206 }