drivers/staging/brcm80211/brcmsmac/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <wlc_cfg.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <bcmdefs.h>
  25 #include <osl.h>
  26 #include <proto/802.11.h>
  27 #include <bcmwifi.h>
  28 #include <bcmutils.h>
  29 #include <siutils.h>
  30 #include <bcmendian.h>
  31 #include <wlioctl.h>
  32 #include <sbconfig.h>
  33 #include <sbchipc.h>
  34 #include <pcicfg.h>
  35 #include <sbhndpio.h>
  36 #include <sbhnddma.h>
  37 #include <hnddma.h>
  38 #include <hndpmu.h>
  39 #include <d11.h>
  40 #include <wlc_rate.h>
  41 #include <wlc_pub.h>
  42 #include <wlc_channel.h>
  43 #include <bcmsrom.h>
  44 #include <wlc_key.h>
  45 #include <bcmdevs.h>
  46 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
  47  * dependencies. Need to include these to files to allow a clean include of wlc.h
  48  * with WLC_HIGH defined.
  49  * At some point we may be able to skip the include of wlc.h and instead just
  50  * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
  51  */
  52 #include <wlc_event.h>
  53 #include <wlc_mac80211.h>
  54 #include <wlc_bmac.h>
  55 #include <wlc_phy_shim.h>
  56 #include <wlc_phy_hal.h>
  57 #include <wl_export.h>
  58 #include "wl_ucode.h"
  59 #include "d11ucode_ext.h"
  60 #include <bcmotp.h>
  61
  62 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
  63  * functions defined in the headers below. We should be eliminating those calls and
  64  * will be able to delete these include lines.
  65  */
  66 #include <wlc_antsel.h>
  67
  68 #include <pcie_core.h>
  69
  70 #include <wlc_alloc.h>
  71 #include <wl_dbg.h>
  72
  73 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  74
  75 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  76 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  77 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  78 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  79
  80 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  81
  82 #ifndef BMAC_DUP_TO_REMOVE
  83 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  84
  85 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  86
  87 #endif                          /* BMAC_DUP_TO_REMOVE */
  88
  89 #define DMAREG(wlc_hw, direction, fifonum)      (D11REV_LT(wlc_hw->corerev, 11) ? \
  90         ((direction == DMA_TX) ? \
  91                 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
  92                 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
  93         ((direction == DMA_TX) ? \
  94                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
  95                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
  96
  97 /*
  98  * The following table lists the buffer memory allocated to xmt fifos in HW.
  99  * the size is in units of 256bytes(one block), total size is HW dependent
 100  * ucode has default fifo partition, sw can overwrite if necessary
 101  *
 102  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 103  * the twiki is updated before making changes.
 104  */
 105
 106 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
 107
 108 static u16 xmtfifo_sz[][NFIFO] = {
 109         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 110         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 111         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 112         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 113         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 114 };
 115
 116 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
 117 static void wlc_coreinit(struct wlc_info *wlc);
 118
 119 /* used by wlc_wakeucode_init() */
 120 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits);
 121 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 122                             const uint nbytes);
 123 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 124 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 125
 126 /* used by wlc_dpc() */
 127 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 128                                 u32 s2);
 129 static bool wlc_bmac_txstatus_corerev4(struct wlc_hw_info *wlc);
 130 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 131 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 132
 133 /* used by wlc_down() */
 134 static void wlc_flushqueues(struct wlc_info *wlc);
 135
 136 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 137 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 138 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 139
 140 /* Low Level Prototypes */
 141 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 142                                    u32 sel);
 143 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 144                                   u16 v, u32 sel);
 145 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 146 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 147 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 148 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 149 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 150 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 151 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 152 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 153 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 154 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 155 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 156 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 157 static void wlc_gpio_init(struct wlc_info *wlc);
 158 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 159                                       int len);
 160 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 161                                       int len);
 162 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 163 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 164 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 165                              chanspec_t chanspec);
 166 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 167                                         bool shortslot);
 168 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 169 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 170                                              u8 rate);
 171
 172 /* === Low Level functions === */
 173
 174 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 175 {
 176         wlc_hw->shortslot = shortslot;
 177
 178         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 179                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 180                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 181                 wlc_enable_mac(wlc_hw->wlc);
 182         }
 183 }
 184
 185 /*
 186  * Update the slot timing for standard 11b/g (20us slots)
 187  * or shortslot 11g (9us slots)
 188  * The PSM needs to be suspended for this call.
 189  */
 190 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 191                                         bool shortslot)
 192 {
 193         struct osl_info *osh;
 194         d11regs_t *regs;
 195
 196         osh = wlc_hw->osh;
 197         regs = wlc_hw->regs;
 198
 199         if (shortslot) {
 200                 /* 11g short slot: 11a timing */
 201                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 202                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 203         } else {
 204                 /* 11g long slot: 11b timing */
 205                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 206                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 207         }
 208 }
 209
 210 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 211 {
 212         /* init microcode host flags */
 213         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 214
 215         /* do band-specific ucode IHR, SHM, and SCR inits */
 216         if (D11REV_IS(wlc_hw->corerev, 23)) {
 217                 if (WLCISNPHY(wlc_hw->band)) {
 218                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 219                 } else {
 220                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 221                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 222                 }
 223         } else {
 224                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 225                         if (WLCISLCNPHY(wlc_hw->band)) {
 226                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 227                         } else
 228                                 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 229                                          __func__, wlc_hw->unit,
 230                                          wlc_hw->corerev);
 231                 } else {
 232                         WL_ERROR("%s: wl%d: unsupported corerev %d\n",
 233                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 234                 }
 235         }
 236 }
 237
 238 /* switch to new band but leave it inactive */
 239 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 240 {
 241         struct wlc_hw_info *wlc_hw = wlc->hw;
 242         u32 macintmask;
 243         u32 tmp;
 244
 245         WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
 246
 247         ASSERT(bandunit != wlc_hw->band->bandunit);
 248         ASSERT(si_iscoreup(wlc_hw->sih));
 249         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 250                0);
 251
 252         /* disable interrupts */
 253         macintmask = wl_intrsoff(wlc->wl);
 254
 255         /* radio off */
 256         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 257
 258         ASSERT(wlc_hw->clk);
 259
 260         if (D11REV_LT(wlc_hw->corerev, 17))
 261                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
 262
 263         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 264
 265         wlc_setxband(wlc_hw, bandunit);
 266
 267         return macintmask;
 268 }
 269
 270 /* Process received frames */
 271 /*
 272  * Return true if more frames need to be processed. false otherwise.
 273  * Param 'bound' indicates max. # frames to process before break out.
 274  */
 275 static bool BCMFASTPATH
 276 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 277 {
 278         struct sk_buff *p;
 279         struct sk_buff *head = NULL;
 280         struct sk_buff *tail = NULL;
 281         uint n = 0;
 282         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 283         u32 tsf_h, tsf_l;
 284         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 285
 286         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
 287         /* gather received frames */
 288         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 289
 290                 if (!tail)
 291                         head = tail = p;
 292                 else {
 293                         tail->prev = p;
 294                         tail = p;
 295                 }
 296
 297                 /* !give others some time to run! */
 298                 if (++n >= bound_limit)
 299                         break;
 300         }
 301
 302         /* get the TSF REG reading */
 303         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 304
 305         /* post more rbufs */
 306         dma_rxfill(wlc_hw->di[fifo]);
 307
 308         /* process each frame */
 309         while ((p = head) != NULL) {
 310                 head = head->prev;
 311                 p->prev = NULL;
 312
 313                 /* record the tsf_l in wlc_rxd11hdr */
 314                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 315                 wlc_rxhdr->tsf_l = htol32(tsf_l);
 316
 317                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 318                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 319
 320                 wlc_recv(wlc_hw->wlc, p);
 321         }
 322
 323         return n >= bound_limit;
 324 }
 325
 326 /* second-level interrupt processing
 327  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 328  *   Param 'bounded' indicates if applicable loops should be bounded.
 329  */
 330 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
 331 {
 332         u32 macintstatus;
 333         struct wlc_hw_info *wlc_hw = wlc->hw;
 334         d11regs_t *regs = wlc_hw->regs;
 335         bool fatal = false;
 336
 337         if (DEVICEREMOVED(wlc)) {
 338                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
 339                 wl_down(wlc->wl);
 340                 return false;
 341         }
 342
 343         /* grab and clear the saved software intstatus bits */
 344         macintstatus = wlc->macintstatus;
 345         wlc->macintstatus = 0;
 346
 347         WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
 348                  wlc_hw->unit, macintstatus);
 349
 350         if (macintstatus & MI_PRQ) {
 351                 /* Process probe request FIFO */
 352                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 353         }
 354
 355         /* BCN template is available */
 356         /* ZZZ: Use AP_ACTIVE ? */
 357         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 358             && (macintstatus & MI_BCNTPL)) {
 359                 wlc_update_beacon(wlc);
 360         }
 361
 362         /* PMQ entry addition */
 363         if (macintstatus & MI_PMQ) {
 364         }
 365
 366         /* tx status */
 367         if (macintstatus & MI_TFS) {
 368                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 369                         wlc->macintstatus |= MI_TFS;
 370                 if (fatal) {
 371                         WL_ERROR("MI_TFS: fatal\n");
 372                         goto fatal;
 373                 }
 374         }
 375
 376         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 377                 wlc_tbtt(wlc, regs);
 378
 379         /* ATIM window end */
 380         if (macintstatus & MI_ATIMWINEND) {
 381                 WL_TRACE("wlc_isr: end of ATIM window\n");
 382
 383                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 384                 wlc->qvalid = 0;
 385         }
 386
 387         /* phy tx error */
 388         if (macintstatus & MI_PHYTXERR) {
 389                 WLCNTINCR(wlc->pub->_cnt->txphyerr);
 390         }
 391
 392         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 393         if (macintstatus & MI_DMAINT) {
 394                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 395                         wlc->macintstatus |= MI_DMAINT;
 396                 }
 397         }
 398
 399         /* TX FIFO suspend/flush completion */
 400         if (macintstatus & MI_TXSTOP) {
 401                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 402                         /*      WL_ERROR("dpc: fifo_suspend_comlete\n"); */
 403                 }
 404         }
 405
 406         /* noise sample collected */
 407         if (macintstatus & MI_BG_NOISE) {
 408                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 409         }
 410
 411         if (macintstatus & MI_GP0) {
 412                 WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
 413                          wlc_hw->unit, wlc_hw->now);
 414
 415                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 416                                         __func__, wlc_hw->sih->chip,
 417                                         wlc_hw->sih->chiprev);
 418
 419                 WLCNTINCR(wlc->pub->_cnt->psmwds);
 420
 421                 /* big hammer */
 422                 wl_init(wlc->wl);
 423         }
 424
 425         /* gptimer timeout */
 426         if (macintstatus & MI_TO) {
 427                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 428         }
 429
 430         if (macintstatus & MI_RFDISABLE) {
 431                 WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
 432
 433                 WLCNTINCR(wlc->pub->_cnt->rfdisable);
 434                 wl_rfkill_set_hw_state(wlc->wl);
 435         }
 436
 437         /* send any enq'd tx packets. Just makes sure to jump start tx */
 438         if (!pktq_empty(&wlc->active_queue->q))
 439                 wlc_send_q(wlc, wlc->active_queue);
 440
 441         ASSERT(wlc_ps_check(wlc));
 442
 443         /* make sure the bound indication and the implementation are in sync */
 444         ASSERT(bounded == true || wlc->macintstatus == 0);
 445
 446         /* it isn't done and needs to be resched if macintstatus is non-zero */
 447         return wlc->macintstatus != 0;
 448
 449  fatal:
 450         wl_init(wlc->wl);
 451         return wlc->macintstatus != 0;
 452 }
 453
 454 /* common low-level watchdog code */
 455 void wlc_bmac_watchdog(void *arg)
 456 {
 457         struct wlc_info *wlc = (struct wlc_info *) arg;
 458         struct wlc_hw_info *wlc_hw = wlc->hw;
 459
 460         WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
 461
 462         if (!wlc_hw->up)
 463                 return;
 464
 465         /* increment second count */
 466         wlc_hw->now++;
 467
 468         /* Check for FIFO error interrupts */
 469         wlc_bmac_fifoerrors(wlc_hw);
 470
 471         /* make sure RX dma has buffers */
 472         dma_rxfill(wlc->hw->di[RX_FIFO]);
 473         if (D11REV_IS(wlc_hw->corerev, 4)) {
 474                 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
 475         }
 476
 477         wlc_phy_watchdog(wlc_hw->band->pi);
 478 }
 479
 480 void
 481 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 482                       bool mute, struct txpwr_limits *txpwr)
 483 {
 484         uint bandunit;
 485
 486         WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
 487                  wlc_hw->unit, chanspec);
 488
 489         wlc_hw->chanspec = chanspec;
 490
 491         /* Switch bands if necessary */
 492         if (NBANDS_HW(wlc_hw) > 1) {
 493                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 494                 if (wlc_hw->band->bandunit != bandunit) {
 495                         /* wlc_bmac_setband disables other bandunit,
 496                          *  use light band switch if not up yet
 497                          */
 498                         if (wlc_hw->up) {
 499                                 wlc_phy_chanspec_radio_set(wlc_hw->
 500                                                            bandstate[bandunit]->
 501                                                            pi, chanspec);
 502                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 503                         } else {
 504                                 wlc_setxband(wlc_hw, bandunit);
 505                         }
 506                 }
 507         }
 508
 509         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 510
 511         if (!wlc_hw->up) {
 512                 if (wlc_hw->clk)
 513                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 514                                                   chanspec);
 515                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 516         } else {
 517                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 518                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 519
 520                 /* Update muting of the channel */
 521                 wlc_bmac_mute(wlc_hw, mute, 0);
 522         }
 523 }
 524
 525 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 526 {
 527         state->machwcap = wlc_hw->machwcap;
 528
 529         return 0;
 530 }
 531
 532 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 533 {
 534         uint i;
 535         char name[8];
 536         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 537         u16 pio_mhf2 = 0;
 538         struct wlc_hw_info *wlc_hw = wlc->hw;
 539         uint unit = wlc_hw->unit;
 540         wlc_tunables_t *tune = wlc->pub->tunables;
 541
 542         /* name and offsets for dma_attach */
 543         snprintf(name, sizeof(name), "wl%d", unit);
 544
 545         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 546                 uint addrwidth;
 547                 int dma_attach_err = 0;
 548                 struct osl_info *osh = wlc_hw->osh;
 549
 550                 /* Find out the DMA addressing capability and let OS know
 551                  * All the channels within one DMA core have 'common-minimum' same
 552                  * capability
 553                  */
 554                 addrwidth =
 555                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 556
 557                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 558                         WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
 559                                  unit);
 560                         return false;
 561                 }
 562
 563                 /*
 564                  * FIFO 0
 565                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 566                  * RX: RX_FIFO (RX data packets)
 567                  */
 568                 ASSERT(TX_AC_BK_FIFO == 0);
 569                 ASSERT(RX_FIFO == 0);
 570                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 571                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 572                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 573                                            (wme ? tune->ntxd : 0), tune->nrxd,
 574                                            tune->rxbufsz, -1, tune->nrxbufpost,
 575                                            WL_HWRXOFF, &wl_msg_level);
 576                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 577
 578                 /*
 579                  * FIFO 1
 580                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 581                  *   (legacy) TX_DATA_FIFO (TX data packets)
 582                  * RX: UNUSED
 583                  */
 584                 ASSERT(TX_AC_BE_FIFO == 1);
 585                 ASSERT(TX_DATA_FIFO == 1);
 586                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 587                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 588                                            tune->ntxd, 0, 0, -1, 0, 0,
 589                                            &wl_msg_level);
 590                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 591
 592                 /*
 593                  * FIFO 2
 594                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 595                  * RX: UNUSED
 596                  */
 597                 ASSERT(TX_AC_VI_FIFO == 2);
 598                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 599                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 600                                            tune->ntxd, 0, 0, -1, 0, 0,
 601                                            &wl_msg_level);
 602                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 603                 /*
 604                  * FIFO 3
 605                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 606                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 607                  * RX: RX_TXSTATUS_FIFO (transmit-status packets)
 608                  *      for corerev < 5 only
 609                  */
 610                 ASSERT(TX_AC_VO_FIFO == 3);
 611                 ASSERT(TX_CTL_FIFO == 3);
 612                 if (D11REV_IS(wlc_hw->corerev, 4)) {
 613                         ASSERT(RX_TXSTATUS_FIFO == 3);
 614                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 615                                                    DMAREG(wlc_hw, DMA_TX, 3),
 616                                                    DMAREG(wlc_hw, DMA_RX, 3),
 617                                                    tune->ntxd, tune->nrxd,
 618                                                    sizeof(tx_status_t), -1,
 619                                                    tune->nrxbufpost, 0,
 620                                                    &wl_msg_level);
 621                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 622                 } else {
 623                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 624                                                    DMAREG(wlc_hw, DMA_TX, 3),
 625                                                    NULL, tune->ntxd, 0, 0, -1,
 626                                                    0, 0, &wl_msg_level);
 627                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 628                 }
 629 /* Cleaner to leave this as if with AP defined */
 630
 631                 if (dma_attach_err) {
 632                         WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
 633                         return false;
 634                 }
 635
 636                 /* get pointer to dma engine tx flow control variable */
 637                 for (i = 0; i < NFIFO; i++)
 638                         if (wlc_hw->di[i])
 639                                 wlc_hw->txavail[i] =
 640                                     (uint *) dma_getvar(wlc_hw->di[i],
 641                                                         "&txavail");
 642         }
 643
 644         /* initial ucode host flags */
 645         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 646
 647         return true;
 648 }
 649
 650 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 651 {
 652         uint j;
 653
 654         for (j = 0; j < NFIFO; j++) {
 655                 if (wlc_hw->di[j]) {
 656                         dma_detach(wlc_hw->di[j]);
 657                         wlc_hw->di[j] = NULL;
 658                 }
 659         }
 660 }
 661
 662 /* low level attach
 663  *    run backplane attach, init nvram
 664  *    run phy attach
 665  *    initialize software state for each core and band
 666  *    put the whole chip in reset(driver down state), no clock
 667  */
 668 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 669                     bool piomode, struct osl_info *osh, void *regsva,
 670                     uint bustype, void *btparam)
 671 {
 672         struct wlc_hw_info *wlc_hw;
 673         d11regs_t *regs;
 674         char *macaddr = NULL;
 675         char *vars;
 676         uint err = 0;
 677         uint j;
 678         bool wme = false;
 679         shared_phy_params_t sha_params;
 680
 681         WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
 682                  unit, vendor, device);
 683
 684         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 685
 686         wme = true;
 687
 688         wlc_hw = wlc->hw;
 689         wlc_hw->wlc = wlc;
 690         wlc_hw->unit = unit;
 691         wlc_hw->osh = osh;
 692         wlc_hw->band = wlc_hw->bandstate[0];
 693         wlc_hw->_piomode = piomode;
 694
 695         /* populate struct wlc_hw_info with default values  */
 696         wlc_bmac_info_init(wlc_hw);
 697
 698         /*
 699          * Do the hardware portion of the attach.
 700          * Also initialize software state that depends on the particular hardware
 701          * we are running.
 702          */
 703         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 704                                 &wlc_hw->vars, &wlc_hw->vars_size);
 705         if (wlc_hw->sih == NULL) {
 706                 WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
 707                 err = 11;
 708                 goto fail;
 709         }
 710         vars = wlc_hw->vars;
 711
 712         /*
 713          * Get vendid/devid nvram overwrites, which could be different
 714          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 715          * SDIO_BUS, and SROMless devices on PCI_BUS.
 716          */
 717 #ifdef BCMBUSTYPE
 718         bustype = BCMBUSTYPE;
 719 #endif
 720         if (bustype != SI_BUS) {
 721                 char *var;
 722
 723                 var = getvar(vars, "vendid");
 724                 if (var) {
 725                         vendor = (u16) simple_strtoul(var, NULL, 0);
 726                         WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
 727                 }
 728                 var = getvar(vars, "devid");
 729                 if (var) {
 730                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 731                         if (devid != 0xffff) {
 732                                 device = devid;
 733                                 WL_ERROR("Overriding device id = 0x%x\n",
 734                                          device);
 735                         }
 736                 }
 737
 738                 /* verify again the device is supported */
 739                 if (!wlc_chipmatch(vendor, device)) {
 740                         WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
 741                                  unit, vendor, device);
 742                         err = 12;
 743                         goto fail;
 744                 }
 745         }
 746
 747         wlc_hw->vendorid = vendor;
 748         wlc_hw->deviceid = device;
 749
 750         /* set bar0 window to point at D11 core */
 751         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 752         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 753
 754         regs = wlc_hw->regs;
 755
 756         wlc->regs = wlc_hw->regs;
 757
 758         /* validate chip, chiprev and corerev */
 759         if (!wlc_isgoodchip(wlc_hw)) {
 760                 err = 13;
 761                 goto fail;
 762         }
 763
 764         /* initialize power control registers */
 765         si_clkctl_init(wlc_hw->sih);
 766
 767         /* request fastclock and force fastclock for the rest of attach
 768          * bring the d11 core out of reset.
 769          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 770          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 771          */
 772         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 773         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 774
 775         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 776                 WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
 777                          unit);
 778                 err = 14;
 779                 goto fail;
 780         }
 781
 782         /* get the board rev, used just below */
 783         j = getintvar(vars, "boardrev");
 784         /* promote srom boardrev of 0xFF to 1 */
 785         if (j == BOARDREV_PROMOTABLE)
 786                 j = BOARDREV_PROMOTED;
 787         wlc_hw->boardrev = (u16) j;
 788         if (!wlc_validboardtype(wlc_hw)) {
 789                 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
 790                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 791                 err = 15;
 792                 goto fail;
 793         }
 794         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 795         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 796         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 797
 798         if (D11REV_LE(wlc_hw->corerev, 4)
 799             || (wlc_hw->boardflags & BFL_NOPLLDOWN))
 800                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 801
 802         if ((wlc_hw->sih->bustype == PCI_BUS)
 803             && (si_pci_war16165(wlc_hw->sih)))
 804                 wlc->war16165 = true;
 805
 806         /* check device id(srom, nvram etc.) to set bands */
 807         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 808                 /* Dualband boards */
 809                 wlc_hw->_nbands = 2;
 810         } else
 811                 wlc_hw->_nbands = 1;
 812
 813         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 814                 wlc_hw->_nbands = 1;
 815
 816         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 817          * init of these values
 818          */
 819         wlc->vendorid = wlc_hw->vendorid;
 820         wlc->deviceid = wlc_hw->deviceid;
 821         wlc->pub->sih = wlc_hw->sih;
 822         wlc->pub->corerev = wlc_hw->corerev;
 823         wlc->pub->sromrev = wlc_hw->sromrev;
 824         wlc->pub->boardrev = wlc_hw->boardrev;
 825         wlc->pub->boardflags = wlc_hw->boardflags;
 826         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 827         wlc->pub->_nbands = wlc_hw->_nbands;
 828
 829         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 830
 831         if (wlc_hw->physhim == NULL) {
 832                 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 833                          unit);
 834                 err = 25;
 835                 goto fail;
 836         }
 837
 838         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 839         sha_params.osh = osh;
 840         sha_params.sih = wlc_hw->sih;
 841         sha_params.physhim = wlc_hw->physhim;
 842         sha_params.unit = unit;
 843         sha_params.corerev = wlc_hw->corerev;
 844         sha_params.vars = vars;
 845         sha_params.vid = wlc_hw->vendorid;
 846         sha_params.did = wlc_hw->deviceid;
 847         sha_params.chip = wlc_hw->sih->chip;
 848         sha_params.chiprev = wlc_hw->sih->chiprev;
 849         sha_params.chippkg = wlc_hw->sih->chippkg;
 850         sha_params.sromrev = wlc_hw->sromrev;
 851         sha_params.boardtype = wlc_hw->sih->boardtype;
 852         sha_params.boardrev = wlc_hw->boardrev;
 853         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 854         sha_params.boardflags = wlc_hw->boardflags;
 855         sha_params.boardflags2 = wlc_hw->boardflags2;
 856         sha_params.bustype = wlc_hw->sih->bustype;
 857         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 858
 859         /* alloc and save pointer to shared phy state area */
 860         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 861         if (!wlc_hw->phy_sh) {
 862                 err = 16;
 863                 goto fail;
 864         }
 865
 866         /* initialize software state for each core and band */
 867         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 868                 /*
 869                  * band0 is always 2.4Ghz
 870                  * band1, if present, is 5Ghz
 871                  */
 872
 873                 /* So if this is a single band 11a card, use band 1 */
 874                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 875                         j = BAND_5G_INDEX;
 876
 877                 wlc_setxband(wlc_hw, j);
 878
 879                 wlc_hw->band->bandunit = j;
 880                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 881                 wlc->band->bandunit = j;
 882                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 883                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 884
 885                 if (D11REV_GE(wlc_hw->corerev, 13)) {
 886                         wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 887                         wlc_hw->machwcap_backup = wlc_hw->machwcap;
 888                 }
 889
 890                 /* init tx fifo size */
 891                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 892                        ARRAY_SIZE(xmtfifo_sz));
 893                 wlc_hw->xmtfifo_sz =
 894                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 895
 896                 /* Get a phy for this band */
 897                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 898                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
 899                 if (wlc_hw->band->pi == NULL) {
 900                         WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
 901                                  unit);
 902                         err = 17;
 903                         goto fail;
 904                 }
 905
 906                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 907
 908                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 909                                        &wlc_hw->band->phyrev,
 910                                        &wlc_hw->band->radioid,
 911                                        &wlc_hw->band->radiorev);
 912                 wlc_hw->band->abgphy_encore =
 913                     wlc_phy_get_encore(wlc_hw->band->pi);
 914                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 915                 wlc_hw->band->core_flags =
 916                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 917
 918                 /* verify good phy_type & supported phy revision */
 919                 if (WLCISNPHY(wlc_hw->band)) {
 920                         if (NCONF_HAS(wlc_hw->band->phyrev))
 921                                 goto good_phy;
 922                         else
 923                                 goto bad_phy;
 924                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 925                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 926                                 goto good_phy;
 927                         else
 928                                 goto bad_phy;
 929                 } else {
 930  bad_phy:
 931                         WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
 932                                  unit,
 933                                  wlc_hw->band->phytype, wlc_hw->band->phyrev);
 934                         err = 18;
 935                         goto fail;
 936                 }
 937
 938  good_phy:
 939                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 940                  * high level attach. However we can not make that change until all low level access
 941                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 942                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 943                  * low only init when all fns updated.
 944                  */
 945                 wlc->band->pi = wlc_hw->band->pi;
 946                 wlc->band->phytype = wlc_hw->band->phytype;
 947                 wlc->band->phyrev = wlc_hw->band->phyrev;
 948                 wlc->band->radioid = wlc_hw->band->radioid;
 949                 wlc->band->radiorev = wlc_hw->band->radiorev;
 950
 951                 /* default contention windows size limits */
 952                 wlc_hw->band->CWmin = APHY_CWMIN;
 953                 wlc_hw->band->CWmax = PHY_CWMAX;
 954
 955                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 956                         err = 19;
 957                         goto fail;
 958                 }
 959         }
 960
 961         /* disable core to match driver "down" state */
 962         wlc_coredisable(wlc_hw);
 963
 964         /* Match driver "down" state */
 965         if (wlc_hw->sih->bustype == PCI_BUS)
 966                 si_pci_down(wlc_hw->sih);
 967
 968         /* register sb interrupt callback functions */
 969         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 970                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 971
 972         /* turn off pll and xtal to match driver "down" state */
 973         wlc_bmac_xtal(wlc_hw, OFF);
 974
 975         /* *********************************************************************
 976          * The hardware is in the DOWN state at this point. D11 core
 977          * or cores are in reset with clocks off, and the board PLLs
 978          * are off if possible.
 979          *
 980          * Beyond this point, wlc->sbclk == false and chip registers
 981          * should not be touched.
 982          *********************************************************************
 983          */
 984
 985         /* init etheraddr state variables */
 986         macaddr = wlc_get_macaddr(wlc_hw);
 987         if (macaddr == NULL) {
 988                 WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
 989                 err = 21;
 990                 goto fail;
 991         }
 992         bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
 993         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 994             is_zero_ether_addr(wlc_hw->etheraddr)) {
 995                 WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
 996                          unit, macaddr);
 997                 err = 22;
 998                 goto fail;
 999         }
1000
1001         WL_ERROR("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1002                  __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1003                  wlc_hw->sih->boardtype, macaddr);
1004
1005         return err;
1006
1007  fail:
1008         WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
1009         return err;
1010 }
1011
1012 /*
1013  * Initialize wlc_info default values ...
1014  * may get overrides later in this function
1015  *  BMAC_NOTES, move low out and resolve the dangling ones
1016  */
1017 void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
1018 {
1019         struct wlc_info *wlc = wlc_hw->wlc;
1020
1021         /* set default sw macintmask value */
1022         wlc->defmacintmask = DEF_MACINTMASK;
1023
1024         /* various 802.11g modes */
1025         wlc_hw->shortslot = false;
1026
1027         wlc_hw->SFBL = RETRY_SHORT_FB;
1028         wlc_hw->LFBL = RETRY_LONG_FB;
1029
1030         /* default mac retry limits */
1031         wlc_hw->SRL = RETRY_SHORT_DEF;
1032         wlc_hw->LRL = RETRY_LONG_DEF;
1033         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1034 }
1035
1036 /*
1037  * low level detach
1038  */
1039 int wlc_bmac_detach(struct wlc_info *wlc)
1040 {
1041         uint i;
1042         wlc_hwband_t *band;
1043         struct wlc_hw_info *wlc_hw = wlc->hw;
1044         int callbacks;
1045
1046         callbacks = 0;
1047
1048         if (wlc_hw->sih) {
1049                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1050                  * interrupt object may has been freed. this must be done before sb core switch
1051                  */
1052                 si_deregister_intr_callback(wlc_hw->sih);
1053
1054                 if (wlc_hw->sih->bustype == PCI_BUS)
1055                         si_pci_sleep(wlc_hw->sih);
1056         }
1057
1058         wlc_bmac_detach_dmapio(wlc_hw);
1059
1060         band = wlc_hw->band;
1061         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1062                 if (band->pi) {
1063                         /* Detach this band's phy */
1064                         wlc_phy_detach(band->pi);
1065                         band->pi = NULL;
1066                 }
1067                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1068         }
1069
1070         /* Free shared phy state */
1071         wlc_phy_shared_detach(wlc_hw->phy_sh);
1072
1073         wlc_phy_shim_detach(wlc_hw->physhim);
1074
1075         /* free vars */
1076         if (wlc_hw->vars) {
1077                 kfree(wlc_hw->vars);
1078                 wlc_hw->vars = NULL;
1079         }
1080
1081         if (wlc_hw->sih) {
1082                 si_detach(wlc_hw->sih);
1083                 wlc_hw->sih = NULL;
1084         }
1085
1086         return callbacks;
1087
1088 }
1089
1090 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1091 {
1092         WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1093
1094         WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1095
1096         /* reset the core */
1097         if (!DEVICEREMOVED(wlc_hw->wlc))
1098                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1099
1100         /* purge the dma rings */
1101         wlc_flushqueues(wlc_hw->wlc);
1102
1103         wlc_reset_bmac_done(wlc_hw->wlc);
1104 }
1105
1106 void
1107 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1108                           bool mute) {
1109         u32 macintmask;
1110         bool fastclk;
1111         struct wlc_info *wlc = wlc_hw->wlc;
1112
1113         WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1114
1115         /* request FAST clock if not on */
1116         fastclk = wlc_hw->forcefastclk;
1117         if (!fastclk)
1118                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1119
1120         /* disable interrupts */
1121         macintmask = wl_intrsoff(wlc->wl);
1122
1123         /* set up the specified band and chanspec */
1124         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1125         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1126
1127         /* do one-time phy inits and calibration */
1128         wlc_phy_cal_init(wlc_hw->band->pi);
1129
1130         /* core-specific initialization */
1131         wlc_coreinit(wlc);
1132
1133         /* suspend the tx fifos and mute the phy for preism cac time */
1134         if (mute)
1135                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1136
1137         /* band-specific inits */
1138         wlc_bmac_bsinit(wlc, chanspec);
1139
1140         /* restore macintmask */
1141         wl_intrsrestore(wlc->wl, macintmask);
1142
1143         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1144          * and wlc_enable_mac() will clear this override bit.
1145          */
1146         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1147
1148         /*
1149          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1150          */
1151         wlc_hw->mac_suspend_depth = 1;
1152
1153         /* restore the clk */
1154         if (!fastclk)
1155                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1156 }
1157
1158 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1159 {
1160         uint coremask;
1161
1162         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1163
1164         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1165
1166         /*
1167          * Enable pll and xtal, initialize the power control registers,
1168          * and force fastclock for the remainder of wlc_up().
1169          */
1170         wlc_bmac_xtal(wlc_hw, ON);
1171         si_clkctl_init(wlc_hw->sih);
1172         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1173
1174         /*
1175          * Configure pci/pcmcia here instead of in wlc_attach()
1176          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1177          */
1178         coremask = (1 << wlc_hw->wlc->core->coreidx);
1179
1180         if (wlc_hw->sih->bustype == PCI_BUS)
1181                 si_pci_setup(wlc_hw->sih, coremask);
1182
1183         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1184
1185         /*
1186          * Need to read the hwradio status here to cover the case where the system
1187          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1188          */
1189         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1190                 /* put SB PCI in down state again */
1191                 if (wlc_hw->sih->bustype == PCI_BUS)
1192                         si_pci_down(wlc_hw->sih);
1193                 wlc_bmac_xtal(wlc_hw, OFF);
1194                 return BCME_RADIOOFF;
1195         }
1196
1197         if (wlc_hw->sih->bustype == PCI_BUS)
1198                 si_pci_up(wlc_hw->sih);
1199
1200         /* reset the d11 core */
1201         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1202
1203         return 0;
1204 }
1205
1206 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1207 {
1208         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1209
1210         wlc_hw->up = true;
1211         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1212
1213         /* FULLY enable dynamic power control and d11 core interrupt */
1214         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1215         ASSERT(wlc_hw->wlc->macintmask == 0);
1216         wl_intrson(wlc_hw->wlc->wl);
1217         return 0;
1218 }
1219
1220 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1221 {
1222         bool dev_gone;
1223         uint callbacks = 0;
1224
1225         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1226
1227         if (!wlc_hw->up)
1228                 return callbacks;
1229
1230         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1231
1232         /* disable interrupts */
1233         if (dev_gone)
1234                 wlc_hw->wlc->macintmask = 0;
1235         else {
1236                 /* now disable interrupts */
1237                 wl_intrsoff(wlc_hw->wlc->wl);
1238
1239                 /* ensure we're running on the pll clock again */
1240                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1241         }
1242         /* down phy at the last of this stage */
1243         callbacks += wlc_phy_down(wlc_hw->band->pi);
1244
1245         return callbacks;
1246 }
1247
1248 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1249 {
1250         uint callbacks = 0;
1251         bool dev_gone;
1252
1253         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1254
1255         if (!wlc_hw->up)
1256                 return callbacks;
1257
1258         wlc_hw->up = false;
1259         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1260
1261         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1262
1263         if (dev_gone) {
1264                 wlc_hw->sbclk = false;
1265                 wlc_hw->clk = false;
1266                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1267
1268                 /* reclaim any posted packets */
1269                 wlc_flushqueues(wlc_hw->wlc);
1270         } else {
1271
1272                 /* Reset and disable the core */
1273                 if (si_iscoreup(wlc_hw->sih)) {
1274                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1275                             MCTL_EN_MAC)
1276                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1277                         callbacks += wl_reset(wlc_hw->wlc->wl);
1278                         wlc_coredisable(wlc_hw);
1279                 }
1280
1281                 /* turn off primary xtal and pll */
1282                 if (!wlc_hw->noreset) {
1283                         if (wlc_hw->sih->bustype == PCI_BUS)
1284                                 si_pci_down(wlc_hw->sih);
1285                         wlc_bmac_xtal(wlc_hw, OFF);
1286                 }
1287         }
1288
1289         return callbacks;
1290 }
1291
1292 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1293 {
1294         if (D11REV_IS(wlc_hw->corerev, 4))      /* no slowclock */
1295                 udelay(5);
1296         else {
1297                 /* delay before first read of ucode state */
1298                 udelay(40);
1299
1300                 /* wait until ucode is no longer asleep */
1301                 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1302                           DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1303         }
1304
1305         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1306 }
1307
1308 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1309 {
1310         bcopy(wlc_hw->etheraddr, ea, ETH_ALEN);
1311 }
1312
1313 int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1314 {
1315         return wlc_hw->band->bandtype;
1316 }
1317
1318 /* control chip clock to save power, enable dynamic clock or force fast clock */
1319 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1320 {
1321         if (PMUCTL_ENAB(wlc_hw->sih)) {
1322                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1323                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1324                  *      which means the FCA bit may not be set.
1325                  *      should wakeup mac if driver wants it to run on HT.
1326                  */
1327
1328                 if (wlc_hw->clk) {
1329                         if (mode == CLK_FAST) {
1330                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1331                                        CCS_FORCEHT);
1332
1333                                 udelay(64);
1334
1335                                 SPINWAIT(((R_REG
1336                                            (wlc_hw->osh,
1337                                             &wlc_hw->regs->
1338                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1339                                          PMU_MAX_TRANSITION_DLY);
1340                                 ASSERT(R_REG
1341                                        (wlc_hw->osh,
1342                                         &wlc_hw->regs->
1343                                         clk_ctl_st) & CCS_HTAVAIL);
1344                         } else {
1345                                 if ((wlc_hw->sih->pmurev == 0) &&
1346                                     (R_REG
1347                                      (wlc_hw->osh,
1348                                       &wlc_hw->regs->
1349                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1350                                         SPINWAIT(((R_REG
1351                                                    (wlc_hw->osh,
1352                                                     &wlc_hw->regs->
1353                                                     clk_ctl_st) & CCS_HTAVAIL)
1354                                                   == 0),
1355                                                  PMU_MAX_TRANSITION_DLY);
1356                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1357                                         ~CCS_FORCEHT);
1358                         }
1359                 }
1360                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1361         } else {
1362                 bool wakeup_ucode;
1363
1364                 /* old chips w/o PMU, force HT through cc,
1365                  * then use FCA to verify mac is running fast clock
1366                  */
1367
1368                 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1369
1370                 if (wlc_hw->up && wakeup_ucode)
1371                         wlc_ucode_wake_override_set(wlc_hw,
1372                                                     WLC_WAKE_OVERRIDE_CLKCTL);
1373
1374                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1375
1376                 if (D11REV_LT(wlc_hw->corerev, 11)) {
1377                         /* ucode WAR for old chips */
1378                         if (wlc_hw->forcefastclk)
1379                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1380                                              MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1381                         else
1382                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1383                                              WLC_BAND_ALL);
1384                 }
1385
1386                 /* check fast clock is available (if core is not in reset) */
1387                 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1388                     && wlc_hw->clk)
1389                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1390
1391                 /* keep the ucode wake bit on if forcefastclk is on
1392                  * since we do not want ucode to put us back to slow clock
1393                  * when it dozes for PM mode.
1394                  * Code below matches the wake override bit with current forcefastclk state
1395                  * Only setting bit in wake_override instead of waking ucode immediately
1396                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1397                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1398                  * (protected by an up check) was executed just below.
1399                  */
1400                 if (wlc_hw->forcefastclk)
1401                         mboolset(wlc_hw->wake_override,
1402                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1403                 else
1404                         mboolclr(wlc_hw->wake_override,
1405                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1406
1407                 /* ok to clear the wakeup now */
1408                 if (wlc_hw->up && wakeup_ucode)
1409                         wlc_ucode_wake_override_clear(wlc_hw,
1410                                                       WLC_WAKE_OVERRIDE_CLKCTL);
1411         }
1412 }
1413
1414 /* set initial host flags value */
1415 static void
1416 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1417 {
1418         struct wlc_hw_info *wlc_hw = wlc->hw;
1419
1420         memset(mhfs, 0, MHFMAX * sizeof(u16));
1421
1422         mhfs[MHF2] |= mhf2_init;
1423
1424         /* prohibit use of slowclock on multifunction boards */
1425         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1426                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1427
1428         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1429                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1430                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1431         }
1432 }
1433
1434 /* set or clear ucode host flag bits
1435  * it has an optimization for no-change write
1436  * it only writes through shared memory when the core has clock;
1437  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1438  *
1439  *
1440  * bands values are: WLC_BAND_AUTO <--- Current band only
1441  *                   WLC_BAND_5G   <--- 5G band only
1442  *                   WLC_BAND_2G   <--- 2G band only
1443  *                   WLC_BAND_ALL  <--- All bands
1444  */
1445 void
1446 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1447              int bands)
1448 {
1449         u16 save;
1450         u16 addr[MHFMAX] = {
1451                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1452                 M_HOST_FLAGS5
1453         };
1454         wlc_hwband_t *band;
1455
1456         ASSERT((val & ~mask) == 0);
1457         ASSERT(idx < MHFMAX);
1458         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1459
1460         switch (bands) {
1461                 /* Current band only or all bands,
1462                  * then set the band to current band
1463                  */
1464         case WLC_BAND_AUTO:
1465         case WLC_BAND_ALL:
1466                 band = wlc_hw->band;
1467                 break;
1468         case WLC_BAND_5G:
1469                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1470                 break;
1471         case WLC_BAND_2G:
1472                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1473                 break;
1474         default:
1475                 ASSERT(0);
1476                 band = NULL;
1477         }
1478
1479         if (band) {
1480                 save = band->mhfs[idx];
1481                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1482
1483                 /* optimization: only write through if changed, and
1484                  * changed band is the current band
1485                  */
1486                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1487                     && (band == wlc_hw->band))
1488                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1489                                            (u16) band->mhfs[idx]);
1490         }
1491
1492         if (bands == WLC_BAND_ALL) {
1493                 wlc_hw->bandstate[0]->mhfs[idx] =
1494                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1495                 wlc_hw->bandstate[1]->mhfs[idx] =
1496                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1497         }
1498 }
1499
1500 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1501 {
1502         wlc_hwband_t *band;
1503         ASSERT(idx < MHFMAX);
1504
1505         switch (bands) {
1506         case WLC_BAND_AUTO:
1507                 band = wlc_hw->band;
1508                 break;
1509         case WLC_BAND_5G:
1510                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1511                 break;
1512         case WLC_BAND_2G:
1513                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1514                 break;
1515         default:
1516                 ASSERT(0);
1517                 band = NULL;
1518         }
1519
1520         if (!band)
1521                 return 0;
1522
1523         return band->mhfs[idx];
1524 }
1525
1526 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1527 {
1528         u8 idx;
1529         u16 addr[] = {
1530                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1531                 M_HOST_FLAGS5
1532         };
1533
1534         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1535
1536         for (idx = 0; idx < MHFMAX; idx++) {
1537                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1538         }
1539 }
1540
1541 /* set the maccontrol register to desired reset state and
1542  * initialize the sw cache of the register
1543  */
1544 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1545 {
1546         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1547         wlc_hw->maccontrol = 0;
1548         wlc_hw->suspended_fifos = 0;
1549         wlc_hw->wake_override = 0;
1550         wlc_hw->mute_override = 0;
1551         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1552 }
1553
1554 /* set or clear maccontrol bits */
1555 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1556 {
1557         u32 maccontrol;
1558         u32 new_maccontrol;
1559
1560         ASSERT((val & ~mask) == 0);
1561
1562         maccontrol = wlc_hw->maccontrol;
1563         new_maccontrol = (maccontrol & ~mask) | val;
1564
1565         /* if the new maccontrol value is the same as the old, nothing to do */
1566         if (new_maccontrol == maccontrol)
1567                 return;
1568
1569         /* something changed, cache the new value */
1570         wlc_hw->maccontrol = new_maccontrol;
1571
1572         /* write the new values with overrides applied */
1573         wlc_mctrl_write(wlc_hw);
1574 }
1575
1576 /* write the software state of maccontrol and overrides to the maccontrol register */
1577 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1578 {
1579         u32 maccontrol = wlc_hw->maccontrol;
1580
1581         /* OR in the wake bit if overridden */
1582         if (wlc_hw->wake_override)
1583                 maccontrol |= MCTL_WAKE;
1584
1585         /* set AP and INFRA bits for mute if needed */
1586         if (wlc_hw->mute_override) {
1587                 maccontrol &= ~(MCTL_AP);
1588                 maccontrol |= MCTL_INFRA;
1589         }
1590
1591         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1592 }
1593
1594 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1595 {
1596         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1597
1598         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1599                 mboolset(wlc_hw->wake_override, override_bit);
1600                 return;
1601         }
1602
1603         mboolset(wlc_hw->wake_override, override_bit);
1604
1605         wlc_mctrl_write(wlc_hw);
1606         wlc_bmac_wait_for_wake(wlc_hw);
1607
1608         return;
1609 }
1610
1611 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1612 {
1613         ASSERT(wlc_hw->wake_override & override_bit);
1614
1615         mboolclr(wlc_hw->wake_override, override_bit);
1616
1617         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1618                 return;
1619
1620         wlc_mctrl_write(wlc_hw);
1621
1622         return;
1623 }
1624
1625 /* When driver needs ucode to stop beaconing, it has to make sure that
1626  * MCTL_AP is clear and MCTL_INFRA is set
1627  * Mode           MCTL_AP        MCTL_INFRA
1628  * AP                1              1
1629  * STA               0              1 <--- This will ensure no beacons
1630  * IBSS              0              0
1631  */
1632 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1633 {
1634         wlc_hw->mute_override = 1;
1635
1636         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1637          * override, then there is no change to write
1638          */
1639         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1640                 return;
1641
1642         wlc_mctrl_write(wlc_hw);
1643
1644         return;
1645 }
1646
1647 /* Clear the override on AP and INFRA bits */
1648 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1649 {
1650         if (wlc_hw->mute_override == 0)
1651                 return;
1652
1653         wlc_hw->mute_override = 0;
1654
1655         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1656          * override, then there is no change to write
1657          */
1658         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1659                 return;
1660
1661         wlc_mctrl_write(wlc_hw);
1662 }
1663
1664 /*
1665  * Write a MAC address to the rcmta structure
1666  */
1667 void
1668 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1669                    const u8 *addr)
1670 {
1671         d11regs_t *regs = wlc_hw->regs;
1672         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1673         u32 mac_hm;
1674         u16 mac_l;
1675         struct osl_info *osh;
1676
1677         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1678
1679         ASSERT(wlc_hw->corerev > 4);
1680
1681         mac_hm =
1682             (addr[3] << 24) | (addr[2] << 16) |
1683             (addr[1] << 8) | addr[0];
1684         mac_l = (addr[5] << 8) | addr[4];
1685
1686         osh = wlc_hw->osh;
1687
1688         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1689         (void)R_REG(osh, &regs->objaddr);
1690         W_REG(osh, &regs->objdata, mac_hm);
1691         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1692         (void)R_REG(osh, &regs->objaddr);
1693         W_REG(osh, objdata16, mac_l);
1694 }
1695
1696 /*
1697  * Write a MAC address to the given match reg offset in the RXE match engine.
1698  */
1699 void
1700 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1701                        const u8 *addr)
1702 {
1703         d11regs_t *regs;
1704         u16 mac_l;
1705         u16 mac_m;
1706         u16 mac_h;
1707         struct osl_info *osh;
1708
1709         WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1710
1711         ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1712
1713         regs = wlc_hw->regs;
1714         mac_l = addr[0] | (addr[1] << 8);
1715         mac_m = addr[2] | (addr[3] << 8);
1716         mac_h = addr[4] | (addr[5] << 8);
1717
1718         osh = wlc_hw->osh;
1719
1720         /* enter the MAC addr into the RXE match registers */
1721         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1722         W_REG(osh, &regs->rcm_mat_data, mac_l);
1723         W_REG(osh, &regs->rcm_mat_data, mac_m);
1724         W_REG(osh, &regs->rcm_mat_data, mac_h);
1725
1726 }
1727
1728 void
1729 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1730                             void *buf)
1731 {
1732         d11regs_t *regs;
1733         u32 word;
1734         bool be_bit;
1735 #ifdef IL_BIGENDIAN
1736         volatile u16 *dptr = NULL;
1737 #endif                          /* IL_BIGENDIAN */
1738         struct osl_info *osh;
1739
1740         WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1741
1742         regs = wlc_hw->regs;
1743         osh = wlc_hw->osh;
1744
1745         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1746         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1747         ASSERT((offset & ~0xffff) == 0);
1748
1749         W_REG(osh, &regs->tplatewrptr, offset);
1750
1751         /* if MCTL_BIGEND bit set in mac control register,
1752          * the chip swaps data in fifo, as well as data in
1753          * template ram
1754          */
1755         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1756
1757         while (len > 0) {
1758                 bcopy((u8 *) buf, &word, sizeof(u32));
1759
1760                 if (be_bit)
1761                         word = hton32(word);
1762                 else
1763                         word = htol32(word);
1764
1765                 W_REG(osh, &regs->tplatewrdata, word);
1766
1767                 buf = (u8 *) buf + sizeof(u32);
1768                 len -= sizeof(u32);
1769         }
1770 }
1771
1772 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1773 {
1774         struct osl_info *osh;
1775
1776         osh = wlc_hw->osh;
1777         wlc_hw->band->CWmin = newmin;
1778
1779         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1780         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1781         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1782 }
1783
1784 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1785 {
1786         struct osl_info *osh;
1787
1788         osh = wlc_hw->osh;
1789         wlc_hw->band->CWmax = newmax;
1790
1791         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1792         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1793         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1794 }
1795
1796 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1797 {
1798         bool fastclk;
1799         u32 tmp;
1800
1801         /* request FAST clock if not on */
1802         fastclk = wlc_hw->forcefastclk;
1803         if (!fastclk)
1804                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1805
1806         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1807
1808         ASSERT(wlc_hw->clk);
1809         if (D11REV_LT(wlc_hw->corerev, 17))
1810                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1811
1812         wlc_bmac_phy_reset(wlc_hw);
1813         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1814
1815         /* restore the clk */
1816         if (!fastclk)
1817                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1818 }
1819
1820 static void
1821 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1822 {
1823         d11regs_t *regs = wlc_hw->regs;
1824
1825         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1826                                     bcn);
1827         /* write beacon length to SCR */
1828         ASSERT(len < 65536);
1829         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1830         /* mark beacon0 valid */
1831         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1832 }
1833
1834 static void
1835 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1836 {
1837         d11regs_t *regs = wlc_hw->regs;
1838
1839         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1840                                     bcn);
1841         /* write beacon length to SCR */
1842         ASSERT(len < 65536);
1843         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1844         /* mark beacon1 valid */
1845         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1846 }
1847
1848 /* mac is assumed to be suspended at this point */
1849 void
1850 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1851                                bool both)
1852 {
1853         d11regs_t *regs = wlc_hw->regs;
1854
1855         if (both) {
1856                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1857                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1858         } else {
1859                 /* bcn 0 */
1860                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1861                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1862                 /* bcn 1 */
1863                 else if (!
1864                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1865                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1866                 else            /* one template should always have been available */
1867                         ASSERT(0);
1868         }
1869 }
1870
1871 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1872 {
1873         u16 v;
1874         struct wlc_info *wlc = wlc_hw->wlc;
1875         /* update SYNTHPU_DLY */
1876
1877         if (WLCISLCNPHY(wlc->band)) {
1878                 v = SYNTHPU_DLY_LPPHY_US;
1879         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1880                 v = SYNTHPU_DLY_NPHY_US;
1881         } else {
1882                 v = SYNTHPU_DLY_BPHY_US;
1883         }
1884
1885         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1886 }
1887
1888 /* band-specific init */
1889 static void
1890 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1891 {
1892         struct wlc_hw_info *wlc_hw = wlc->hw;
1893
1894         WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1895                  wlc_hw->unit, wlc_hw->band->bandunit);
1896
1897         /* sanity check */
1898         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1899             PHY_TYPE_LCNXN)
1900                 ASSERT((uint)
1901                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1902                        == wlc_hw->band->phytype);
1903
1904         wlc_ucode_bsinit(wlc_hw);
1905
1906         wlc_phy_init(wlc_hw->band->pi, chanspec);
1907
1908         wlc_ucode_txant_set(wlc_hw);
1909
1910         /* cwmin is band-specific, update hardware with value for current band */
1911         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1912         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1913
1914         wlc_bmac_update_slot_timing(wlc_hw,
1915                                     BAND_5G(wlc_hw->band->
1916                                             bandtype) ? true : wlc_hw->
1917                                     shortslot);
1918
1919         /* write phytype and phyvers */
1920         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1921         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1922
1923         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1924         wlc_upd_ofdm_pctl1_table(wlc_hw);
1925
1926         wlc_bmac_upd_synthpu(wlc_hw);
1927 }
1928
1929 void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1930 {
1931         WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1932
1933         wlc_hw->phyclk = clk;
1934
1935         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1936
1937                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1938                                (SICF_PRST | SICF_FGC));
1939                 udelay(1);
1940                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1941                 udelay(1);
1942
1943         } else {                /* take phy out of reset */
1944
1945                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1946                 udelay(1);
1947                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1948                 udelay(1);
1949
1950         }
1951 }
1952
1953 /* Perform a soft reset of the PHY PLL */
1954 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1955 {
1956         WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1957
1958         si_corereg(wlc_hw->sih, SI_CC_IDX,
1959                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1960         udelay(1);
1961         si_corereg(wlc_hw->sih, SI_CC_IDX,
1962                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1963         udelay(1);
1964         si_corereg(wlc_hw->sih, SI_CC_IDX,
1965                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1966         udelay(1);
1967         si_corereg(wlc_hw->sih, SI_CC_IDX,
1968                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1969         udelay(1);
1970 }
1971
1972 /* light way to turn on phy clock without reset for NPHY only
1973  *  refer to wlc_bmac_core_phy_clk for full version
1974  */
1975 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1976 {
1977         /* support(necessary for NPHY and HYPHY) only */
1978         if (!WLCISNPHY(wlc_hw->band))
1979                 return;
1980
1981         if (ON == clk)
1982                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1983         else
1984                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1985
1986 }
1987
1988 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1989 {
1990         if (ON == clk)
1991                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1992         else
1993                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1994 }
1995
1996 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1997 {
1998         wlc_phy_t *pih = wlc_hw->band->pi;
1999         u32 phy_bw_clkbits;
2000         bool phy_in_reset = false;
2001
2002         WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
2003
2004         if (pih == NULL)
2005                 return;
2006
2007         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2008
2009         /* Specfic reset sequence required for NPHY rev 3 and 4 */
2010         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2011             NREV_LE(wlc_hw->band->phyrev, 4)) {
2012                 /* Set the PHY bandwidth */
2013                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2014
2015                 udelay(1);
2016
2017                 /* Perform a soft reset of the PHY PLL */
2018                 wlc_bmac_core_phypll_reset(wlc_hw);
2019
2020                 /* reset the PHY */
2021                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2022                                (SICF_PRST | SICF_PCLKE));
2023                 phy_in_reset = true;
2024         } else {
2025
2026                 si_core_cflags(wlc_hw->sih,
2027                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2028                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2029         }
2030
2031         udelay(2);
2032         wlc_bmac_core_phy_clk(wlc_hw, ON);
2033
2034         if (pih)
2035                 wlc_phy_anacore(pih, ON);
2036 }
2037
2038 /* switch to and initialize new band */
2039 static void
2040 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
2041                                 chanspec_t chanspec) {
2042         struct wlc_info *wlc = wlc_hw->wlc;
2043         u32 macintmask;
2044
2045         ASSERT(NBANDS_HW(wlc_hw) > 1);
2046         ASSERT(bandunit != wlc_hw->band->bandunit);
2047
2048         /* Enable the d11 core before accessing it */
2049         if (!si_iscoreup(wlc_hw->sih)) {
2050                 si_core_reset(wlc_hw->sih, 0, 0);
2051                 ASSERT(si_iscoreup(wlc_hw->sih));
2052                 wlc_mctrl_reset(wlc_hw);
2053         }
2054
2055         macintmask = wlc_setband_inact(wlc, bandunit);
2056
2057         if (!wlc_hw->up)
2058                 return;
2059
2060         wlc_bmac_core_phy_clk(wlc_hw, ON);
2061
2062         /* band-specific initializations */
2063         wlc_bmac_bsinit(wlc, chanspec);
2064
2065         /*
2066          * If there are any pending software interrupt bits,
2067          * then replace these with a harmless nonzero value
2068          * so wlc_dpc() will re-enable interrupts when done.
2069          */
2070         if (wlc->macintstatus)
2071                 wlc->macintstatus = MI_DMAINT;
2072
2073         /* restore macintmask */
2074         wl_intrsrestore(wlc->wl, macintmask);
2075
2076         /* ucode should still be suspended.. */
2077         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2078                0);
2079 }
2080
2081 /* low-level band switch utility routine */
2082 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
2083 {
2084         WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
2085
2086         wlc_hw->band = wlc_hw->bandstate[bandunit];
2087
2088         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2089         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2090
2091         /* set gmode core flag */
2092         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2093                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2094                                ((bandunit == 0) ? SICF_GMODE : 0));
2095         }
2096 }
2097
2098 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
2099 {
2100
2101         /* reject unsupported corerev */
2102         if (!VALID_COREREV(wlc_hw->corerev)) {
2103                 WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
2104                 return false;
2105         }
2106
2107         return true;
2108 }
2109
2110 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
2111 {
2112         bool goodboard = true;
2113         uint boardrev = wlc_hw->boardrev;
2114
2115         if (boardrev == 0)
2116                 goodboard = false;
2117         else if (boardrev > 0xff) {
2118                 uint brt = (boardrev & 0xf000) >> 12;
2119                 uint b0 = (boardrev & 0xf00) >> 8;
2120                 uint b1 = (boardrev & 0xf0) >> 4;
2121                 uint b2 = boardrev & 0xf;
2122
2123                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2124                     || (b2 > 9))
2125                         goodboard = false;
2126         }
2127
2128         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2129                 return goodboard;
2130
2131         return goodboard;
2132 }
2133
2134 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
2135 {
2136         const char *varname = "macaddr";
2137         char *macaddr;
2138
2139         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2140         macaddr = getvar(wlc_hw->vars, varname);
2141         if (macaddr != NULL)
2142                 return macaddr;
2143
2144         if (NBANDS_HW(wlc_hw) > 1)
2145                 varname = "et1macaddr";
2146         else
2147                 varname = "il0macaddr";
2148
2149         macaddr = getvar(wlc_hw->vars, varname);
2150         if (macaddr == NULL) {
2151                 WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
2152                          wlc_hw->unit, varname);
2153         }
2154
2155         return macaddr;
2156 }
2157
2158 /*
2159  * Return true if radio is disabled, otherwise false.
2160  * hw radio disable signal is an external pin, users activate it asynchronously
2161  * this function could be called when driver is down and w/o clock
2162  * it operates on different registers depending on corerev and boardflag.
2163  */
2164 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2165 {
2166         bool v, clk, xtal;
2167         u32 resetbits = 0, flags = 0;
2168
2169         xtal = wlc_hw->sbclk;
2170         if (!xtal)
2171                 wlc_bmac_xtal(wlc_hw, ON);
2172
2173         /* may need to take core out of reset first */
2174         clk = wlc_hw->clk;
2175         if (!clk) {
2176                 if (D11REV_LE(wlc_hw->corerev, 11))
2177                         resetbits |= SICF_PCLKE;
2178
2179                 /*
2180                  * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2181                  * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2182                  */
2183                 if (D11REV_GE(wlc_hw->corerev, 18))
2184                         flags |= SICF_PCLKE;
2185
2186                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2187                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2188                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2189                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2190                         wlc_hw->regs =
2191                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2192                                                      0);
2193                 si_core_reset(wlc_hw->sih, flags, resetbits);
2194                 wlc_mctrl_reset(wlc_hw);
2195         }
2196
2197         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2198
2199         /* put core back into reset */
2200         if (!clk)
2201                 si_core_disable(wlc_hw->sih, 0);
2202
2203         if (!xtal)
2204                 wlc_bmac_xtal(wlc_hw, OFF);
2205
2206         return v;
2207 }
2208
2209 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2210 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2211 {
2212         if (wlc_hw->wlc->pub->hw_up)
2213                 return;
2214
2215         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2216
2217         /*
2218          * Enable pll and xtal, initialize the power control registers,
2219          * and force fastclock for the remainder of wlc_up().
2220          */
2221         wlc_bmac_xtal(wlc_hw, ON);
2222         si_clkctl_init(wlc_hw->sih);
2223         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2224
2225         if (wlc_hw->sih->bustype == PCI_BUS) {
2226                 si_pci_fixcfg(wlc_hw->sih);
2227
2228                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2229                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2230                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2231                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2232                         wlc_hw->regs =
2233                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2234                                                      0);
2235         }
2236
2237         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2238         wlc_phy_por_inform(wlc_hw->band->pi);
2239
2240         wlc_hw->ucode_loaded = false;
2241         wlc_hw->wlc->pub->hw_up = true;
2242
2243         if ((wlc_hw->boardflags & BFL_FEM)
2244             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2245                 if (!
2246                     (wlc_hw->boardrev >= 0x1250
2247                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2248                         si_epa_4313war(wlc_hw->sih);
2249         }
2250 }
2251
2252 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2253 {
2254         struct hnddma_pub *di = wlc_hw->di[fifo];
2255         struct osl_info *osh;
2256
2257         if (D11REV_LT(wlc_hw->corerev, 12)) {
2258                 bool rxidle = true;
2259                 u16 rcv_frm_cnt = 0;
2260
2261                 osh = wlc_hw->osh;
2262
2263                 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2264                 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2265                          ((rcv_frm_cnt =
2266                            R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2267                          50000);
2268
2269                 if (!rxidle && (rcv_frm_cnt != 0))
2270                         WL_ERROR("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n",
2271                                  wlc_hw->unit, __func__, fifo, rcv_frm_cnt);
2272                 mdelay(2);
2273         }
2274
2275         return dma_rxreset(di);
2276 }
2277
2278 /* d11 core reset
2279  *   ensure fask clock during reset
2280  *   reset dma
2281  *   reset d11(out of reset)
2282  *   reset phy(out of reset)
2283  *   clear software macintstatus for fresh new start
2284  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2285  */
2286 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2287 {
2288         d11regs_t *regs;
2289         uint i;
2290         bool fastclk;
2291         u32 resetbits = 0;
2292
2293         if (flags == WLC_USE_COREFLAGS)
2294                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2295
2296         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2297
2298         regs = wlc_hw->regs;
2299
2300         /* request FAST clock if not on  */
2301         fastclk = wlc_hw->forcefastclk;
2302         if (!fastclk)
2303                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2304
2305         /* reset the dma engines except first time thru */
2306         if (si_iscoreup(wlc_hw->sih)) {
2307                 for (i = 0; i < NFIFO; i++)
2308                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2309                                 WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
2310                                          wlc_hw->unit, __func__, i);
2311                         }
2312
2313                 if ((wlc_hw->di[RX_FIFO])
2314                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2315                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2316                                  wlc_hw->unit, __func__, RX_FIFO);
2317                 }
2318                 if (D11REV_IS(wlc_hw->corerev, 4)
2319                     && wlc_hw->di[RX_TXSTATUS_FIFO]
2320                     && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2321                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2322                                  wlc_hw->unit, __func__, RX_TXSTATUS_FIFO);
2323                 }
2324         }
2325         /* if noreset, just stop the psm and return */
2326         if (wlc_hw->noreset) {
2327                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2328                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2329                 return;
2330         }
2331
2332         if (D11REV_LE(wlc_hw->corerev, 11))
2333                 resetbits |= SICF_PCLKE;
2334
2335         /*
2336          * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2337          * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2338          * need to enable PHY CLK
2339          */
2340         if (D11REV_GE(wlc_hw->corerev, 18))
2341                 flags |= SICF_PCLKE;
2342
2343         /* reset the core
2344          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2345          *  is cleared by the core_reset. have to re-request it.
2346          *  This adds some delay and we can optimize it by also requesting fastclk through
2347          *  chipcommon during this period if necessary. But that has to work coordinate
2348          *  with other driver like mips/arm since they may touch chipcommon as well.
2349          */
2350         wlc_hw->clk = false;
2351         si_core_reset(wlc_hw->sih, flags, resetbits);
2352         wlc_hw->clk = true;
2353         if (wlc_hw->band && wlc_hw->band->pi)
2354                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2355
2356         wlc_mctrl_reset(wlc_hw);
2357
2358         if (PMUCTL_ENAB(wlc_hw->sih))
2359                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2360
2361         wlc_bmac_phy_reset(wlc_hw);
2362
2363         /* turn on PHY_PLL */
2364         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2365
2366         /* clear sw intstatus */
2367         wlc_hw->wlc->macintstatus = 0;
2368
2369         /* restore the clk setting */
2370         if (!fastclk)
2371                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2372 }
2373
2374 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2375  * txfifo sizes needs to be modified(increased) since the newer cores
2376  * have more memory.
2377  */
2378 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2379 {
2380         d11regs_t *regs = wlc_hw->regs;
2381         u16 fifo_nu;
2382         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2383         u16 txfifo_def, txfifo_def1;
2384         u16 txfifo_cmd;
2385         struct osl_info *osh;
2386
2387         if (D11REV_LT(wlc_hw->corerev, 9))
2388                 goto exit;
2389
2390         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2391         txfifo_startblk = TXFIFO_START_BLK;
2392
2393         osh = wlc_hw->osh;
2394
2395         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2396         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2397
2398                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2399                 txfifo_def = (txfifo_startblk & 0xff) |
2400                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2401                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2402                     ((((txfifo_endblk -
2403                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2404                 txfifo_cmd =
2405                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2406
2407                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2408                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2409                 if (D11REV_GE(wlc_hw->corerev, 16))
2410                         W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2411
2412                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2413
2414                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2415         }
2416  exit:
2417         /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2418         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2419                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2420         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2421                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2422         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2423                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2424                             xmtfifo_sz[TX_AC_BK_FIFO]));
2425         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2426                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2427                             xmtfifo_sz[TX_BCMC_FIFO]));
2428 }
2429
2430 /* d11 core init
2431  *   reset PSM
2432  *   download ucode/PCM
2433  *   let ucode run to suspended
2434  *   download ucode inits
2435  *   config other core registers
2436  *   init dma
2437  */
2438 static void wlc_coreinit(struct wlc_info *wlc)
2439 {
2440         struct wlc_hw_info *wlc_hw = wlc->hw;
2441         d11regs_t *regs;
2442         u32 sflags;
2443         uint bcnint_us;
2444         uint i = 0;
2445         bool fifosz_fixup = false;
2446         struct osl_info *osh;
2447         int err = 0;
2448         u16 buf[NFIFO];
2449
2450         regs = wlc_hw->regs;
2451         osh = wlc_hw->osh;
2452
2453         WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2454
2455         /* reset PSM */
2456         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2457
2458         wlc_ucode_download(wlc_hw);
2459         /*
2460          * FIFOSZ fixup
2461          * 1) core5-9 use ucode 5 to save space since the PSM is the same
2462          * 2) newer chips, driver wants to controls the fifo allocation
2463          */
2464         if (D11REV_GE(wlc_hw->corerev, 4))
2465                 fifosz_fixup = true;
2466
2467         /* let the PSM run to the suspended state, set mode to BSS STA */
2468         W_REG(osh, &regs->macintstatus, -1);
2469         wlc_bmac_mctrl(wlc_hw, ~0,
2470                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2471
2472         /* wait for ucode to self-suspend after auto-init */
2473         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2474                  1000 * 1000);
2475         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2476                 WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2477                          wlc_hw->unit);
2478
2479         wlc_gpio_init(wlc);
2480
2481         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2482
2483         if (D11REV_IS(wlc_hw->corerev, 23)) {
2484                 if (WLCISNPHY(wlc_hw->band))
2485                         wlc_write_inits(wlc_hw, d11n0initvals16);
2486                 else
2487                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2488                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2489         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2490                 if (WLCISLCNPHY(wlc_hw->band)) {
2491                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2492                 } else {
2493                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2494                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2495                 }
2496         } else {
2497                 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
2498                          __func__, wlc_hw->unit, wlc_hw->corerev);
2499         }
2500
2501         /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2502         if (fifosz_fixup == true) {
2503                 wlc_corerev_fifofixup(wlc_hw);
2504         }
2505
2506         /* check txfifo allocations match between ucode and driver */
2507         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2508         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2509                 i = TX_AC_BE_FIFO;
2510                 err = -1;
2511         }
2512         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2513         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2514                 i = TX_AC_VI_FIFO;
2515                 err = -1;
2516         }
2517         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2518         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2519         buf[TX_AC_BK_FIFO] &= 0xff;
2520         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2521                 i = TX_AC_BK_FIFO;
2522                 err = -1;
2523         }
2524         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2525                 i = TX_AC_VO_FIFO;
2526                 err = -1;
2527         }
2528         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2529         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2530         buf[TX_BCMC_FIFO] &= 0xff;
2531         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2532                 i = TX_BCMC_FIFO;
2533                 err = -1;
2534         }
2535         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2536                 i = TX_ATIM_FIFO;
2537                 err = -1;
2538         }
2539         if (err != 0) {
2540                 WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
2541                          buf[i], wlc_hw->xmtfifo_sz[i], i);
2542                 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2543                  * shmem, since driver don't overwrite those chip and
2544                  * ucode initialize data will be used.
2545                  */
2546                 if (D11REV_GE(wlc_hw->corerev, 4))
2547                         ASSERT(0);
2548         }
2549
2550         /* make sure we can still talk to the mac */
2551         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2552
2553         /* band-specific inits done by wlc_bsinit() */
2554
2555         /* Set up frame burst size and antenna swap threshold init values */
2556         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2557         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2558
2559         /* enable one rx interrupt per received frame */
2560         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2561         if (D11REV_IS(wlc_hw->corerev, 4))
2562                 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2563
2564         /* set the station mode (BSS STA) */
2565         wlc_bmac_mctrl(wlc_hw,
2566                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2567                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2568
2569         /* set up Beacon interval */
2570         bcnint_us = 0x8000 << 10;
2571         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2572         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2573         W_REG(osh, &regs->macintstatus, MI_GP1);
2574
2575         /* write interrupt mask */
2576         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2577         if (D11REV_IS(wlc_hw->corerev, 4))
2578                 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2579                       DEF_RXINTMASK);
2580
2581         /* allow the MAC to control the PHY clock (dynamic on/off) */
2582         wlc_bmac_macphyclk_set(wlc_hw, ON);
2583
2584         /* program dynamic clock control fast powerup delay register */
2585         if (D11REV_GT(wlc_hw->corerev, 4)) {
2586                 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2587                 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2588         }
2589
2590         /* tell the ucode the corerev */
2591         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2592
2593         /* tell the ucode MAC capabilities */
2594         if (D11REV_GE(wlc_hw->corerev, 13)) {
2595                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2596                                    (u16) (wlc_hw->machwcap & 0xffff));
2597                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2598                                    (u16) ((wlc_hw->
2599                                               machwcap >> 16) & 0xffff));
2600         }
2601
2602         /* write retry limits to SCR, this done after PSM init */
2603         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2604         (void)R_REG(osh, &regs->objaddr);
2605         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2606         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2607         (void)R_REG(osh, &regs->objaddr);
2608         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2609
2610         /* write rate fallback retry limits */
2611         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2612         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2613
2614         if (D11REV_GE(wlc_hw->corerev, 16)) {
2615                 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2616                 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2617         }
2618
2619         /* dma initializations */
2620         wlc->txpend16165war = 0;
2621
2622         /* init the tx dma engines */
2623         for (i = 0; i < NFIFO; i++) {
2624                 if (wlc_hw->di[i])
2625                         dma_txinit(wlc_hw->di[i]);
2626         }
2627
2628         /* init the rx dma engine(s) and post receive buffers */
2629         dma_rxinit(wlc_hw->di[RX_FIFO]);
2630         dma_rxfill(wlc_hw->di[RX_FIFO]);
2631         if (D11REV_IS(wlc_hw->corerev, 4)) {
2632                 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2633                 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2634         }
2635 }
2636
2637 /* This function is used for changing the tsf frac register
2638  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2639  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2640  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2641  * HTPHY Formula is 2^26/freq(MHz) e.g.
2642  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2643  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2644  * For spuron: 123MHz -> 2^26/123    = 545600.5
2645  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2646  * For spur off: 120MHz -> 2^26/120    = 559240.5
2647  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2648  */
2649
2650 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2651 {
2652         d11regs_t *regs;
2653         struct osl_info *osh;
2654         regs = wlc_hw->regs;
2655         osh = wlc_hw->osh;
2656
2657         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2658             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2659                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2660                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2661                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2662                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2663                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2664                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2665                 } else {        /* 120Mhz */
2666                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2667                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2668                 }
2669         } else if (WLCISLCNPHY(wlc_hw->band)) {
2670                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2671                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2672                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2673                 } else {        /* 80Mhz */
2674                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2675                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2676                 }
2677         }
2678 }
2679
2680 /* Initialize GPIOs that are controlled by D11 core */
2681 static void wlc_gpio_init(struct wlc_info *wlc)
2682 {
2683         struct wlc_hw_info *wlc_hw = wlc->hw;
2684         d11regs_t *regs;
2685         u32 gc, gm;
2686         struct osl_info *osh;
2687
2688         regs = wlc_hw->regs;
2689         osh = wlc_hw->osh;
2690
2691         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2692         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2693
2694         /*
2695          * Common GPIO setup:
2696          *      G0 = LED 0 = WLAN Activity
2697          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2698          *      G2 = LED 2 = WLAN 5 GHz Radio State
2699          *      G4 = radio disable input (HI enabled, LO disabled)
2700          */
2701
2702         gc = gm = 0;
2703
2704         /* Allocate GPIOs for mimo antenna diversity feature */
2705         if (WLANTSEL_ENAB(wlc)) {
2706                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2707                         /* Enable antenna diversity, use 2x3 mode */
2708                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2709                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2710                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2711                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2712
2713                         /* init superswitch control */
2714                         wlc_phy_antsel_init(wlc_hw->band->pi, false);
2715
2716                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2717                         ASSERT((gm & BOARD_GPIO_12) == 0);
2718                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2719                         /* The board itself is powered by these GPIOs (when not sending pattern)
2720                          * So set them high
2721                          */
2722                         OR_REG(osh, &regs->psm_gpio_oe,
2723                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2724                         OR_REG(osh, &regs->psm_gpio_out,
2725                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2726
2727                         /* Enable antenna diversity, use 2x4 mode */
2728                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2729                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2730                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2731                                      WLC_BAND_ALL);
2732
2733                         /* Configure the desired clock to be 4Mhz */
2734                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2735                                            ANTSEL_CLKDIV_4MHZ);
2736                 }
2737         }
2738         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2739         if (wlc_hw->boardflags & BFL_PACTRL)
2740                 gm |= gc |= BOARD_GPIO_PACTRL;
2741
2742         /* apply to gpiocontrol register */
2743         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2744 }
2745
2746 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2747 {
2748         struct wlc_info *wlc;
2749         wlc = wlc_hw->wlc;
2750
2751         if (wlc_hw->ucode_loaded)
2752                 return;
2753
2754         if (D11REV_IS(wlc_hw->corerev, 23)) {
2755                 if (WLCISNPHY(wlc_hw->band)) {
2756                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2757                                         bcm43xx_16_mimosz);
2758                         wlc_hw->ucode_loaded = true;
2759                 } else
2760                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2761                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2762         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2763                 if (WLCISLCNPHY(wlc_hw->band)) {
2764                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2765                                         bcm43xx_24_lcnsz);
2766                         wlc_hw->ucode_loaded = true;
2767                 } else {
2768                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2769                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2770                 }
2771         }
2772 }
2773
2774 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2775                               const uint nbytes) {
2776         struct osl_info *osh;
2777         d11regs_t *regs = wlc_hw->regs;
2778         uint i;
2779         uint count;
2780
2781         osh = wlc_hw->osh;
2782
2783         WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2784
2785         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2786
2787         count = (nbytes / sizeof(u32));
2788
2789         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2790         (void)R_REG(osh, &regs->objaddr);
2791         for (i = 0; i < count; i++)
2792                 W_REG(osh, &regs->objdata, ucode[i]);
2793 }
2794
2795 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits)
2796 {
2797         int i;
2798         struct osl_info *osh;
2799         volatile u8 *base;
2800
2801         WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2802
2803         osh = wlc_hw->osh;
2804         base = (volatile u8 *)wlc_hw->regs;
2805
2806         for (i = 0; inits[i].addr != 0xffff; i++) {
2807                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2808
2809                 if (inits[i].size == 2)
2810                         W_REG(osh, (u16 *)(base + inits[i].addr),
2811                               inits[i].value);
2812                 else if (inits[i].size == 4)
2813                         W_REG(osh, (u32 *)(base + inits[i].addr),
2814                               inits[i].value);
2815         }
2816 }
2817
2818 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2819 {
2820         u16 phyctl;
2821         u16 phytxant = wlc_hw->bmac_phytxant;
2822         u16 mask = PHY_TXC_ANT_MASK;
2823
2824         /* set the Probe Response frame phy control word */
2825         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2826         phyctl = (phyctl & ~mask) | phytxant;
2827         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2828
2829         /* set the Response (ACK/CTS) frame phy control word */
2830         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2831         phyctl = (phyctl & ~mask) | phytxant;
2832         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2833 }
2834
2835 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2836 {
2837         /* update sw state */
2838         wlc_hw->bmac_phytxant = phytxant;
2839
2840         /* push to ucode if up */
2841         if (!wlc_hw->up)
2842                 return;
2843         wlc_ucode_txant_set(wlc_hw);
2844
2845 }
2846
2847 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2848 {
2849         return (u16) wlc_hw->wlc->stf->txant;
2850 }
2851
2852 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2853 {
2854         wlc_hw->antsel_type = antsel_type;
2855
2856         /* Update the antsel type for phy module to use */
2857         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2858 }
2859
2860 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2861 {
2862         bool fatal = false;
2863         uint unit;
2864         uint intstatus, idx;
2865         d11regs_t *regs = wlc_hw->regs;
2866
2867         unit = wlc_hw->unit;
2868
2869         for (idx = 0; idx < NFIFO; idx++) {
2870                 /* read intstatus register and ignore any non-error bits */
2871                 intstatus =
2872                     R_REG(wlc_hw->osh,
2873                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2874                 if (!intstatus)
2875                         continue;
2876
2877                 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2878                          unit, idx, intstatus);
2879
2880                 if (intstatus & I_RO) {
2881                         WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
2882                                  unit, idx);
2883                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
2884                         fatal = true;
2885                 }
2886
2887                 if (intstatus & I_PC) {
2888                         WL_ERROR("wl%d: fifo %d: descriptor error\n",
2889                                  unit, idx);
2890                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
2891                         fatal = true;
2892                 }
2893
2894                 if (intstatus & I_PD) {
2895                         WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
2896                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
2897                         fatal = true;
2898                 }
2899
2900                 if (intstatus & I_DE) {
2901                         WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
2902                                  unit, idx);
2903                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
2904                         fatal = true;
2905                 }
2906
2907                 if (intstatus & I_RU) {
2908                         WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
2909                                  idx, unit);
2910                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2911                 }
2912
2913                 if (intstatus & I_XU) {
2914                         WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
2915                                  idx, unit);
2916                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
2917                         fatal = true;
2918                 }
2919
2920                 if (fatal) {
2921                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2922                         break;
2923                 } else
2924                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2925                               intstatus);
2926         }
2927 }
2928
2929 void wlc_intrson(struct wlc_info *wlc)
2930 {
2931         struct wlc_hw_info *wlc_hw = wlc->hw;
2932         ASSERT(wlc->defmacintmask);
2933         wlc->macintmask = wlc->defmacintmask;
2934         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2935 }
2936
2937 /* callback for siutils.c, which has only wlc handler, no wl
2938  * they both check up, not only because there is no need to off/restore d11 interrupt
2939  *  but also because per-port code may require sync with valid interrupt.
2940  */
2941
2942 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2943 {
2944         if (!wlc->hw->up)
2945                 return 0;
2946
2947         return wl_intrsoff(wlc->wl);
2948 }
2949
2950 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2951 {
2952         if (!wlc->hw->up)
2953                 return;
2954
2955         wl_intrsrestore(wlc->wl, macintmask);
2956 }
2957
2958 u32 wlc_intrsoff(struct wlc_info *wlc)
2959 {
2960         struct wlc_hw_info *wlc_hw = wlc->hw;
2961         u32 macintmask;
2962
2963         if (!wlc_hw->clk)
2964                 return 0;
2965
2966         macintmask = wlc->macintmask;   /* isr can still happen */
2967
2968         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
2969         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
2970         udelay(1);              /* ensure int line is no longer driven */
2971         wlc->macintmask = 0;
2972
2973         /* return previous macintmask; resolve race between us and our isr */
2974         return wlc->macintstatus ? 0 : macintmask;
2975 }
2976
2977 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2978 {
2979         struct wlc_hw_info *wlc_hw = wlc->hw;
2980         if (!wlc_hw->clk)
2981                 return;
2982
2983         wlc->macintmask = macintmask;
2984         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2985 }
2986
2987 void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2988 {
2989         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2990
2991         if (on) {
2992                 /* suspend tx fifos */
2993                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2994                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2995                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2996                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2997
2998                 /* zero the address match register so we do not send ACKs */
2999                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3000                                        null_ether_addr);
3001         } else {
3002                 /* resume tx fifos */
3003                 if (!wlc_hw->wlc->tx_suspended) {
3004                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3005                 }
3006                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3007                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3008                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3009
3010                 /* Restore address */
3011                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3012                                        wlc_hw->etheraddr);
3013         }
3014
3015         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3016
3017         if (on)
3018                 wlc_ucode_mute_override_set(wlc_hw);
3019         else
3020                 wlc_ucode_mute_override_clear(wlc_hw);
3021 }
3022
3023 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
3024 {
3025         if (fifo >= NFIFO)
3026                 return BCME_RANGE;
3027
3028         *blocks = wlc_hw->xmtfifo_sz[fifo];
3029
3030         return 0;
3031 }
3032
3033 /* wlc_bmac_tx_fifo_suspended:
3034  * Check the MAC's tx suspend status for a tx fifo.
3035  *
3036  * When the MAC acknowledges a tx suspend, it indicates that no more
3037  * packets will be transmitted out the radio. This is independent of
3038  * DMA channel suspension---the DMA may have finished suspending, or may still
3039  * be pulling data into a tx fifo, by the time the MAC acks the suspend
3040  * request.
3041  */
3042 bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3043 {
3044         /* check that a suspend has been requested and is no longer pending */
3045
3046         /*
3047          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3048          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3049          * chnstatus register.
3050          * The tx fifo suspend completion is independent of the DMA suspend completion and
3051          *   may be acked before or after the DMA is suspended.
3052          */
3053         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3054             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3055              (1 << tx_fifo)) == 0)
3056                 return true;
3057
3058         return false;
3059 }
3060
3061 void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3062 {
3063         u8 fifo = 1 << tx_fifo;
3064
3065         /* Two clients of this code, 11h Quiet period and scanning. */
3066
3067         /* only suspend if not already suspended */
3068         if ((wlc_hw->suspended_fifos & fifo) == fifo)
3069                 return;
3070
3071         /* force the core awake only if not already */
3072         if (wlc_hw->suspended_fifos == 0)
3073                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3074
3075         wlc_hw->suspended_fifos |= fifo;
3076
3077         if (wlc_hw->di[tx_fifo]) {
3078                 /* Suspending AMPDU transmissions in the middle can cause underflow
3079                  * which may result in mismatch between ucode and driver
3080                  * so suspend the mac before suspending the FIFO
3081                  */
3082                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3083                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
3084
3085                 dma_txsuspend(wlc_hw->di[tx_fifo]);
3086
3087                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3088                         wlc_enable_mac(wlc_hw->wlc);
3089         }
3090 }
3091
3092 void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3093 {
3094         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3095          * here for PIO otherwise the watchdog will catch the inconsistency and fire
3096          */
3097         /* Two clients of this code, 11h Quiet period and scanning. */
3098         if (wlc_hw->di[tx_fifo])
3099                 dma_txresume(wlc_hw->di[tx_fifo]);
3100
3101         /* allow core to sleep again */
3102         if (wlc_hw->suspended_fifos == 0)
3103                 return;
3104         else {
3105                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3106                 if (wlc_hw->suspended_fifos == 0)
3107                         wlc_ucode_wake_override_clear(wlc_hw,
3108                                                       WLC_WAKE_OVERRIDE_TXFIFO);
3109         }
3110 }
3111
3112 /*
3113  * Read and clear macintmask and macintstatus and intstatus registers.
3114  * This routine should be called with interrupts off
3115  * Return:
3116  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
3117  *   0 if the interrupt is not for us, or we are in some special cases;
3118  *   device interrupt status bits otherwise.
3119  */
3120 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
3121 {
3122         struct wlc_hw_info *wlc_hw = wlc->hw;
3123         d11regs_t *regs = wlc_hw->regs;
3124         u32 macintstatus;
3125         u32 intstatus_rxfifo, intstatus_txsfifo;
3126         struct osl_info *osh;
3127
3128         osh = wlc_hw->osh;
3129
3130         /* macintstatus includes a DMA interrupt summary bit */
3131         macintstatus = R_REG(osh, &regs->macintstatus);
3132
3133         WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
3134
3135         /* detect cardbus removed, in power down(suspend) and in reset */
3136         if (DEVICEREMOVED(wlc))
3137                 return -1;
3138
3139         /* DEVICEREMOVED succeeds even when the core is still resetting,
3140          * handle that case here.
3141          */
3142         if (macintstatus == 0xffffffff)
3143                 return 0;
3144
3145         /* defer unsolicited interrupts */
3146         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3147
3148         /* if not for us */
3149         if (macintstatus == 0)
3150                 return 0;
3151
3152         /* interrupts are already turned off for CFE build
3153          * Caution: For CFE Turning off the interrupts again has some undesired
3154          * consequences
3155          */
3156         /* turn off the interrupts */
3157         W_REG(osh, &regs->macintmask, 0);
3158         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3159         wlc->macintmask = 0;
3160
3161         /* clear device interrupts */
3162         W_REG(osh, &regs->macintstatus, macintstatus);
3163
3164         /* MI_DMAINT is indication of non-zero intstatus */
3165         if (macintstatus & MI_DMAINT) {
3166                 if (D11REV_IS(wlc_hw->corerev, 4)) {
3167                         intstatus_rxfifo =
3168                             R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3169                         intstatus_txsfifo =
3170                             R_REG(osh,
3171                                   &regs->intctrlregs[RX_TXSTATUS_FIFO].
3172                                   intstatus);
3173                         WL_TRACE("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n",
3174                                  wlc_hw->unit,
3175                                  intstatus_rxfifo, intstatus_txsfifo);
3176
3177                         /* defer unsolicited interrupt hints */
3178                         intstatus_rxfifo &= DEF_RXINTMASK;
3179                         intstatus_txsfifo &= DEF_RXINTMASK;
3180
3181                         /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3182                         /* clear interrupt hints */
3183                         if (intstatus_rxfifo)
3184                                 W_REG(osh,
3185                                       &regs->intctrlregs[RX_FIFO].intstatus,
3186                                       intstatus_rxfifo);
3187                         else
3188                                 macintstatus &= ~MI_DMAINT;
3189
3190                         /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3191                         if (intstatus_txsfifo) {
3192                                 W_REG(osh,
3193                                       &regs->intctrlregs[RX_TXSTATUS_FIFO].
3194                                       intstatus, intstatus_txsfifo);
3195                                 macintstatus |= MI_TFS;
3196                         }
3197                 } else {
3198                         /*
3199                          * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3200                          * If MI_DMAINT is set, assume it is set and clear the interrupt.
3201                          */
3202                         W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3203                               DEF_RXINTMASK);
3204                 }
3205         }
3206
3207         return macintstatus;
3208 }
3209
3210 /* Update wlc->macintstatus and wlc->intstatus[]. */
3211 /* Return true if they are updated successfully. false otherwise */
3212 bool wlc_intrsupd(struct wlc_info *wlc)
3213 {
3214         u32 macintstatus;
3215
3216         ASSERT(wlc->macintstatus != 0);
3217
3218         /* read and clear macintstatus and intstatus registers */
3219         macintstatus = wlc_intstatus(wlc, false);
3220
3221         /* device is removed */
3222         if (macintstatus == 0xffffffff)
3223                 return false;
3224
3225         /* update interrupt status in software */
3226         wlc->macintstatus |= macintstatus;
3227
3228         return true;
3229 }
3230
3231 /*
3232  * First-level interrupt processing.
3233  * Return true if this was our interrupt, false otherwise.
3234  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3235  * false otherwise.
3236  */
3237 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3238 {
3239         struct wlc_hw_info *wlc_hw = wlc->hw;
3240         u32 macintstatus;
3241
3242         *wantdpc = false;
3243
3244         if (!wlc_hw->up || !wlc->macintmask)
3245                 return false;
3246
3247         /* read and clear macintstatus and intstatus registers */
3248         macintstatus = wlc_intstatus(wlc, true);
3249
3250         if (macintstatus == 0xffffffff)
3251                 WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
3252
3253         /* it is not for us */
3254         if (macintstatus == 0)
3255                 return false;
3256
3257         *wantdpc = true;
3258
3259         /* save interrupt status bits */
3260         ASSERT(wlc->macintstatus == 0);
3261         wlc->macintstatus = macintstatus;
3262
3263         return true;
3264
3265 }
3266
3267 /* process tx completion events for corerev < 5 */
3268 static bool wlc_bmac_txstatus_corerev4(struct wlc_hw_info *wlc_hw)
3269 {
3270         struct sk_buff *status_p;
3271         tx_status_t *txs;
3272         struct osl_info *osh;
3273         bool fatal = false;
3274
3275         WL_TRACE("wl%d: wlc_txstatusrecv\n", wlc_hw->unit);
3276
3277         osh = wlc_hw->osh;
3278
3279         while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3280
3281                 txs = (tx_status_t *) status_p->data;
3282                 /* MAC uses little endian only */
3283                 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3284
3285                 /* shift low bits for tx_status_t status compatibility */
3286                 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3287                     | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3288
3289                 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3290
3291                 pkt_buf_free_skb(osh, status_p, false);
3292         }
3293
3294         if (fatal)
3295                 return true;
3296
3297         /* post more rbufs */
3298         dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3299
3300         return false;
3301 }
3302
3303 static bool BCMFASTPATH
3304 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3305 {
3306         /* discard intermediate indications for ucode with one legitimate case:
3307          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3308          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3309          *   transmission count)
3310          */
3311         if (!(txs->status & TX_STATUS_AMPDU)
3312             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3313                 return false;
3314         }
3315
3316         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3317 }
3318
3319 /* process tx completion events in BMAC
3320  * Return true if more tx status need to be processed. false otherwise.
3321  */
3322 static bool BCMFASTPATH
3323 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3324 {
3325         bool morepending = false;
3326         struct wlc_info *wlc = wlc_hw->wlc;
3327
3328         WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3329
3330         if (D11REV_IS(wlc_hw->corerev, 4)) {
3331                 /* to retire soon */
3332                 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3333
3334                 if (*fatal)
3335                         return 0;
3336         } else {
3337                 /* corerev >= 5 */
3338                 d11regs_t *regs;
3339                 struct osl_info *osh;
3340                 tx_status_t txstatus, *txs;
3341                 u32 s1, s2;
3342                 uint n = 0;
3343                 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3344                 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3345
3346                 txs = &txstatus;
3347                 regs = wlc_hw->regs;
3348                 osh = wlc_hw->osh;
3349                 while (!(*fatal)
3350                        && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3351
3352                         if (s1 == 0xffffffff) {
3353                                 WL_ERROR("wl%d: %s: dead chip\n",
3354                                          wlc_hw->unit, __func__);
3355                                 ASSERT(s1 != 0xffffffff);
3356                                 return morepending;
3357                         }
3358
3359                         s2 = R_REG(osh, &regs->frmtxstatus2);
3360
3361                         txs->status = s1 & TXS_STATUS_MASK;
3362                         txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3363                         txs->sequence = s2 & TXS_SEQ_MASK;
3364                         txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3365                         txs->lasttxtime = 0;
3366
3367                         *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3368
3369                         /* !give others some time to run! */
3370                         if (++n >= max_tx_num)
3371                                 break;
3372                 }
3373
3374                 if (*fatal)
3375                         return 0;
3376
3377                 if (n >= max_tx_num)
3378                         morepending = true;
3379         }
3380
3381         if (!pktq_empty(&wlc->active_queue->q))
3382                 wlc_send_q(wlc, wlc->active_queue);
3383
3384         return morepending;
3385 }
3386
3387 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3388 {
3389         struct wlc_hw_info *wlc_hw = wlc->hw;
3390         d11regs_t *regs = wlc_hw->regs;
3391         u32 mc, mi;
3392         struct osl_info *osh;
3393
3394         WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3395                  wlc_hw->unit, wlc_hw->band->bandunit);
3396
3397         /*
3398          * Track overlapping suspend requests
3399          */
3400         wlc_hw->mac_suspend_depth++;
3401         if (wlc_hw->mac_suspend_depth > 1)
3402                 return;
3403
3404         osh = wlc_hw->osh;
3405
3406         /* force the core awake */
3407         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3408
3409         mc = R_REG(osh, &regs->maccontrol);
3410
3411         if (mc == 0xffffffff) {
3412                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3413                 wl_down(wlc->wl);
3414                 return;
3415         }
3416         ASSERT(!(mc & MCTL_PSM_JMP_0));
3417         ASSERT(mc & MCTL_PSM_RUN);
3418         ASSERT(mc & MCTL_EN_MAC);
3419
3420         mi = R_REG(osh, &regs->macintstatus);
3421         if (mi == 0xffffffff) {
3422                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3423                 wl_down(wlc->wl);
3424                 return;
3425         }
3426         ASSERT(!(mi & MI_MACSSPNDD));
3427
3428         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3429
3430         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3431                  WLC_MAX_MAC_SUSPEND);
3432
3433         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3434                 WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
3435                          wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3436                 WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
3437                          wlc_hw->unit,
3438                          R_REG(osh, &regs->psmdebug),
3439                          R_REG(osh, &regs->phydebug),
3440                          R_REG(osh, &regs->psm_brc));
3441         }
3442
3443         mc = R_REG(osh, &regs->maccontrol);
3444         if (mc == 0xffffffff) {
3445                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3446                 wl_down(wlc->wl);
3447                 return;
3448         }
3449         ASSERT(!(mc & MCTL_PSM_JMP_0));
3450         ASSERT(mc & MCTL_PSM_RUN);
3451         ASSERT(!(mc & MCTL_EN_MAC));
3452 }
3453
3454 void wlc_enable_mac(struct wlc_info *wlc)
3455 {
3456         struct wlc_hw_info *wlc_hw = wlc->hw;
3457         d11regs_t *regs = wlc_hw->regs;
3458         u32 mc, mi;
3459         struct osl_info *osh;
3460
3461         WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3462                  wlc_hw->unit, wlc->band->bandunit);
3463
3464         /*
3465          * Track overlapping suspend requests
3466          */
3467         ASSERT(wlc_hw->mac_suspend_depth > 0);
3468         wlc_hw->mac_suspend_depth--;
3469         if (wlc_hw->mac_suspend_depth > 0)
3470                 return;
3471
3472         osh = wlc_hw->osh;
3473
3474         mc = R_REG(osh, &regs->maccontrol);
3475         ASSERT(!(mc & MCTL_PSM_JMP_0));
3476         ASSERT(!(mc & MCTL_EN_MAC));
3477         ASSERT(mc & MCTL_PSM_RUN);
3478
3479         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3480         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3481
3482         mc = R_REG(osh, &regs->maccontrol);
3483         ASSERT(!(mc & MCTL_PSM_JMP_0));
3484         ASSERT(mc & MCTL_EN_MAC);
3485         ASSERT(mc & MCTL_PSM_RUN);
3486
3487         mi = R_REG(osh, &regs->macintstatus);
3488         ASSERT(!(mi & MI_MACSSPNDD));
3489
3490         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3491 }
3492
3493 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3494 {
3495         u8 rate;
3496         u8 rates[8] = {
3497                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3498                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3499         };
3500         u16 entry_ptr;
3501         u16 pctl1;
3502         uint i;
3503
3504         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3505                 return;
3506
3507         /* walk the phy rate table and update the entries */
3508         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3509                 rate = rates[i];
3510
3511                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3512
3513                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3514                 pctl1 =
3515                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3516
3517                 /* modify the value */
3518                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3519                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3520
3521                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3522                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3523                                    pctl1);
3524         }
3525 }
3526
3527 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3528 {
3529         uint i;
3530         u8 plcp_rate = 0;
3531         struct plcp_signal_rate_lookup {
3532                 u8 rate;
3533                 u8 signal_rate;
3534         };
3535         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3536         const struct plcp_signal_rate_lookup rate_lookup[] = {
3537                 {WLC_RATE_6M, 0xB},
3538                 {WLC_RATE_9M, 0xF},
3539                 {WLC_RATE_12M, 0xA},
3540                 {WLC_RATE_18M, 0xE},
3541                 {WLC_RATE_24M, 0x9},
3542                 {WLC_RATE_36M, 0xD},
3543                 {WLC_RATE_48M, 0x8},
3544                 {WLC_RATE_54M, 0xC}
3545         };
3546
3547         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3548                 if (rate == rate_lookup[i].rate) {
3549                         plcp_rate = rate_lookup[i].signal_rate;
3550                         break;
3551                 }
3552         }
3553
3554         /* Find the SHM pointer to the rate table entry by looking in the
3555          * Direct-map Table
3556          */
3557         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3558 }
3559
3560 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3561 {
3562         wlc_hw->hw_stf_ss_opmode = stf_mode;
3563
3564         if (wlc_hw->clk)
3565                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3566 }
3567
3568 void BCMFASTPATH
3569 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3570                   u32 *tsf_h_ptr)
3571 {
3572         d11regs_t *regs = wlc_hw->regs;
3573
3574         /* read the tsf timer low, then high to get an atomic read */
3575         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3576         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3577
3578         return;
3579 }
3580
3581 bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3582 {
3583         d11regs_t *regs;
3584         u32 w, val;
3585         volatile u16 *reg16;
3586         struct osl_info *osh;
3587
3588         WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3589
3590         regs = wlc_hw->regs;
3591         osh = wlc_hw->osh;
3592
3593         /* Validate dchip register access */
3594
3595         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3596         (void)R_REG(osh, &regs->objaddr);
3597         w = R_REG(osh, &regs->objdata);
3598
3599         /* Can we write and read back a 32bit register? */
3600         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3601         (void)R_REG(osh, &regs->objaddr);
3602         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3603
3604         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3605         (void)R_REG(osh, &regs->objaddr);
3606         val = R_REG(osh, &regs->objdata);
3607         if (val != (u32) 0xaa5555aa) {
3608                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
3609                          wlc_hw->unit, val);
3610                 return false;
3611         }
3612
3613         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3614         (void)R_REG(osh, &regs->objaddr);
3615         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3616
3617         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3618         (void)R_REG(osh, &regs->objaddr);
3619         val = R_REG(osh, &regs->objdata);
3620         if (val != (u32) 0x55aaaa55) {
3621                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
3622                          wlc_hw->unit, val);
3623                 return false;
3624         }
3625
3626         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3627         (void)R_REG(osh, &regs->objaddr);
3628         W_REG(osh, &regs->objdata, w);
3629
3630         if (D11REV_LT(wlc_hw->corerev, 11)) {
3631                 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3632                  * for our interface, low to high
3633                  */
3634                 reg16 = (volatile u16 *)&regs->tsf_cfpstart;
3635
3636                 /* write the CFPStart register low half explicitly, starting a buffered write */
3637                 W_REG(osh, reg16, 0xAAAA);
3638
3639                 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3640                  * If the low 16 bits are written first, followed by the high 16 bits then the
3641                  * 32 bit value 0xCCCCBBBB should end up in the register.
3642                  * If the order is reversed, then the write to the high half will trigger a buffered
3643                  * write of 0xCCCCAAAA.
3644                  * If the bus is 32 bits, then this is not much of a test, and the reg should
3645                  * have the correct value 0xCCCCBBBB.
3646                  */
3647                 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3648
3649                 /* verify with the 16 bit registers that have no side effects */
3650                 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3651                 if (val != (uint) 0xBBBB) {
3652                         WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected 0x%x\n",
3653                                  wlc_hw->unit, val, 0xBBBB);
3654                         return false;
3655                 }
3656                 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3657                 if (val != (uint) 0xCCCC) {
3658                         WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected 0x%x\n",
3659                                  wlc_hw->unit, val, 0xCCCC);
3660                         return false;
3661                 }
3662
3663         }
3664
3665         /* clear CFPStart */
3666         W_REG(osh, &regs->tsf_cfpstart, 0);
3667
3668         w = R_REG(osh, &regs->maccontrol);
3669         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3670             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3671                 WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
3672                          wlc_hw->unit, w,
3673                          (MCTL_IHR_EN | MCTL_WAKE),
3674                          (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3675                 return false;
3676         }
3677
3678         return true;
3679 }
3680
3681 #define PHYPLL_WAIT_US  100000
3682
3683 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3684 {
3685         d11regs_t *regs;
3686         struct osl_info *osh;
3687         u32 tmp;
3688
3689         WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3690
3691         tmp = 0;
3692         regs = wlc_hw->regs;
3693         osh = wlc_hw->osh;
3694
3695         if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3696                 return;
3697
3698         if (on) {
3699                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3700                         OR_REG(osh, &regs->clk_ctl_st,
3701                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3702                                 CCS_ERSRC_REQ_PHYPLL));
3703                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3704                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3705                                  PHYPLL_WAIT_US);
3706
3707                         tmp = R_REG(osh, &regs->clk_ctl_st);
3708                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3709                             (CCS_ERSRC_AVAIL_HT)) {
3710                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3711                                          __func__);
3712                                 ASSERT(0);
3713                         }
3714                 } else {
3715                         OR_REG(osh, &regs->clk_ctl_st,
3716                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3717                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3718                                   (CCS_ERSRC_AVAIL_D11PLL |
3719                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3720                                  (CCS_ERSRC_AVAIL_D11PLL |
3721                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3722
3723                         tmp = R_REG(osh, &regs->clk_ctl_st);
3724                         if ((tmp &
3725                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3726                             !=
3727                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3728                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3729                                          __func__);
3730                                 ASSERT(0);
3731                         }
3732                 }
3733         } else {
3734                 /* Since the PLL may be shared, other cores can still be requesting it;
3735                  * so we'll deassert the request but not wait for status to comply.
3736                  */
3737                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3738                 tmp = R_REG(osh, &regs->clk_ctl_st);
3739         }
3740 }
3741
3742 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3743 {
3744         bool dev_gone;
3745
3746         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3747
3748         ASSERT(!wlc_hw->up);
3749
3750         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3751
3752         if (dev_gone)
3753                 return;
3754
3755         if (wlc_hw->noreset)
3756                 return;
3757
3758         /* radio off */
3759         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3760
3761         /* turn off analog core */
3762         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3763
3764         /* turn off PHYPLL to save power */
3765         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3766
3767         /* No need to set wlc->pub->radio_active = OFF
3768          * because this function needs down capability and
3769          * radio_active is designed for BCMNODOWN.
3770          */
3771
3772         /* remove gpio controls */
3773         if (wlc_hw->ucode_dbgsel)
3774                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3775
3776         wlc_hw->clk = false;
3777         si_core_disable(wlc_hw->sih, 0);
3778         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3779 }
3780
3781 /* power both the pll and external oscillator on/off */
3782 void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3783 {
3784         WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3785
3786         /* dont power down if plldown is false or we must poll hw radio disable */
3787         if (!want && wlc_hw->pllreq)
3788                 return;
3789
3790         if (wlc_hw->sih)
3791                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3792
3793         wlc_hw->sbclk = want;
3794         if (!wlc_hw->sbclk) {
3795                 wlc_hw->clk = false;
3796                 if (wlc_hw->band && wlc_hw->band->pi)
3797                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3798         }
3799 }
3800
3801 static void wlc_flushqueues(struct wlc_info *wlc)
3802 {
3803         struct wlc_hw_info *wlc_hw = wlc->hw;
3804         uint i;
3805
3806         wlc->txpend16165war = 0;
3807
3808         /* free any posted tx packets */
3809         for (i = 0; i < NFIFO; i++)
3810                 if (wlc_hw->di[i]) {
3811                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3812                         TXPKTPENDCLR(wlc, i);
3813                         WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3814                                  i);
3815                 }
3816
3817         /* free any posted rx packets */
3818         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3819         if (D11REV_IS(wlc_hw->corerev, 4))
3820                 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3821 }
3822
3823 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3824 {
3825         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3826 }
3827
3828 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3829 {
3830         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3831 }
3832
3833 /* Set a range of shared memory to a value.
3834  * SHM 'offset' needs to be an even address and
3835  * Buffer length 'len' must be an even number of bytes
3836  */
3837 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3838 {
3839         int i;
3840
3841         /* offset and len need to be even */
3842         ASSERT((offset & 1) == 0);
3843         ASSERT((len & 1) == 0);
3844
3845         if (len <= 0)
3846                 return;
3847
3848         for (i = 0; i < len; i += 2) {
3849                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3850         }
3851 }
3852
3853 static u16
3854 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3855 {
3856         d11regs_t *regs = wlc_hw->regs;
3857         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3858         volatile u16 *objdata_hi = objdata_lo + 1;
3859         u16 v;
3860
3861         ASSERT((offset & 1) == 0);
3862
3863         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3864         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3865         if (offset & 2) {
3866                 v = R_REG(wlc_hw->osh, objdata_hi);
3867         } else {
3868                 v = R_REG(wlc_hw->osh, objdata_lo);
3869         }
3870
3871         return v;
3872 }
3873
3874 static void
3875 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3876 {
3877         d11regs_t *regs = wlc_hw->regs;
3878         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3879         volatile u16 *objdata_hi = objdata_lo + 1;
3880
3881         ASSERT((offset & 1) == 0);
3882
3883         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3884         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3885         if (offset & 2) {
3886                 W_REG(wlc_hw->osh, objdata_hi, v);
3887         } else {
3888                 W_REG(wlc_hw->osh, objdata_lo, v);
3889         }
3890 }
3891
3892 /* Copy a buffer to shared memory of specified type .
3893  * SHM 'offset' needs to be an even address and
3894  * Buffer length 'len' must be an even number of bytes
3895  * 'sel' selects the type of memory
3896  */
3897 void
3898 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3899                        int len, u32 sel)
3900 {
3901         u16 v;
3902         const u8 *p = (const u8 *)buf;
3903         int i;
3904
3905         /* offset and len need to be even */
3906         ASSERT((offset & 1) == 0);
3907         ASSERT((len & 1) == 0);
3908
3909         if (len <= 0)
3910                 return;
3911
3912         for (i = 0; i < len; i += 2) {
3913                 v = p[i] | (p[i + 1] << 8);
3914                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3915         }
3916 }
3917
3918 /* Copy a piece of shared memory of specified type to a buffer .
3919  * SHM 'offset' needs to be an even address and
3920  * Buffer length 'len' must be an even number of bytes
3921  * 'sel' selects the type of memory
3922  */
3923 void
3924 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3925                          int len, u32 sel)
3926 {
3927         u16 v;
3928         u8 *p = (u8 *) buf;
3929         int i;
3930
3931         /* offset and len need to be even */
3932         ASSERT((offset & 1) == 0);
3933         ASSERT((len & 1) == 0);
3934
3935         if (len <= 0)
3936                 return;
3937
3938         for (i = 0; i < len; i += 2) {
3939                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3940                 p[i] = v & 0xFF;
3941                 p[i + 1] = (v >> 8) & 0xFF;
3942         }
3943 }
3944
3945 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3946 {
3947         WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3948                  wlc_hw->vars_size);
3949
3950         *buf = wlc_hw->vars;
3951         *len = wlc_hw->vars_size;
3952 }
3953
3954 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3955 {
3956         wlc_hw->SRL = SRL;
3957         wlc_hw->LRL = LRL;
3958
3959         /* write retry limit to SCR, shouldn't need to suspend */
3960         if (wlc_hw->up) {
3961                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3962                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3963                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3964                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
3965                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3966                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3967                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3968                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
3969         }
3970 }
3971
3972 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3973 {
3974         wlc_hw->noreset = noreset_flag;
3975 }
3976
3977 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3978 {
3979         ASSERT(req_bit);
3980
3981         if (set) {
3982                 if (mboolisset(wlc_hw->pllreq, req_bit))
3983                         return;
3984
3985                 mboolset(wlc_hw->pllreq, req_bit);
3986
3987                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3988                         if (!wlc_hw->sbclk) {
3989                                 wlc_bmac_xtal(wlc_hw, ON);
3990                         }
3991                 }
3992         } else {
3993                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3994                         return;
3995
3996                 mboolclr(wlc_hw->pllreq, req_bit);
3997
3998                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3999                         if (wlc_hw->sbclk) {
4000                                 wlc_bmac_xtal(wlc_hw, OFF);
4001                         }
4002                 }
4003         }
4004
4005         return;
4006 }
4007
4008 /* this will be true for all ai chips */
4009 bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
4010 {
4011         return true;
4012 }
4013
4014 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
4015 {
4016         u16 table_ptr;
4017         u8 phy_rate, index;
4018
4019         /* get the phy specific rate encoding for the PLCP SIGNAL field */
4020         /* XXX4321 fixup needed ? */
4021         if (IS_OFDM(rate))
4022                 table_ptr = M_RT_DIRMAP_A;
4023         else
4024                 table_ptr = M_RT_DIRMAP_B;
4025
4026         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4027          * the index into the rate table.
4028          */
4029         phy_rate = rate_info[rate] & RATE_MASK;
4030         index = phy_rate & 0xf;
4031
4032         /* Find the SHM pointer to the rate table entry by looking in the
4033          * Direct-map Table
4034          */
4035         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
4036 }
4037
4038 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
4039 {
4040         wlc_hw->antsel_avail = antsel_avail;
4041 }