drivers/staging/brcm80211/brcmsmac/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <wlc_cfg.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <bcmdefs.h>
  25 #include <osl.h>
  26 #include <proto/802.11.h>
  27 #include <bcmwifi.h>
  28 #include <bcmutils.h>
  29 #include <siutils.h>
  30 #include <bcmendian.h>
  31 #include <wlioctl.h>
  32 #include <sbconfig.h>
  33 #include <sbchipc.h>
  34 #include <pcicfg.h>
  35 #include <sbhndpio.h>
  36 #include <sbhnddma.h>
  37 #include <hnddma.h>
  38 #include <hndpmu.h>
  39 #include <d11.h>
  40 #include <wlc_rate.h>
  41 #include <wlc_pub.h>
  42 #include <wlc_channel.h>
  43 #include <bcmsrom.h>
  44 #include <wlc_key.h>
  45 #include <bcmdevs.h>
  46 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
  47  * dependencies. Need to include these to files to allow a clean include of wlc.h
  48  * with WLC_HIGH defined.
  49  * At some point we may be able to skip the include of wlc.h and instead just
  50  * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
  51  */
  52 #include <wlc_event.h>
  53 #include <wlc_mac80211.h>
  54 #include <wlc_bmac.h>
  55 #include <wlc_phy_shim.h>
  56 #include <wlc_phy_hal.h>
  57 #include <wl_export.h>
  58 #include "wl_ucode.h"
  59 #include "d11ucode_ext.h"
  60 #include <bcmotp.h>
  61
  62 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
  63  * functions defined in the headers below. We should be eliminating those calls and
  64  * will be able to delete these include lines.
  65  */
  66 #include <wlc_antsel.h>
  67
  68 #include <pcie_core.h>
  69
  70 #include <wlc_alloc.h>
  71 #include <wl_dbg.h>
  72
  73 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  74
  75 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  76 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  77 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  78 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  79
  80 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  81
  82 #ifndef BMAC_DUP_TO_REMOVE
  83 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  84
  85 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  86
  87 #endif                          /* BMAC_DUP_TO_REMOVE */
  88
  89 #define DMAREG(wlc_hw, direction, fifonum)      (D11REV_LT(wlc_hw->corerev, 11) ? \
  90         ((direction == DMA_TX) ? \
  91                 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
  92                 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
  93         ((direction == DMA_TX) ? \
  94                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
  95                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
  96
  97 /*
  98  * The following table lists the buffer memory allocated to xmt fifos in HW.
  99  * the size is in units of 256bytes(one block), total size is HW dependent
 100  * ucode has default fifo partition, sw can overwrite if necessary
 101  *
 102  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 103  * the twiki is updated before making changes.
 104  */
 105
 106 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
 107
 108 static u16 xmtfifo_sz[][NFIFO] = {
 109         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 110         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 111         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 112         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 113         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 114 };
 115
 116 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
 117 static void wlc_coreinit(struct wlc_info *wlc);
 118
 119 /* used by wlc_wakeucode_init() */
 120 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits);
 121 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 122                             const uint nbytes);
 123 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 124 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 125
 126 /* used by wlc_dpc() */
 127 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 128                                 u32 s2);
 129 static bool wlc_bmac_txstatus_corerev4(struct wlc_hw_info *wlc);
 130 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 131 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 132
 133 /* used by wlc_down() */
 134 static void wlc_flushqueues(struct wlc_info *wlc);
 135
 136 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 137 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 138 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 139
 140 /* Low Level Prototypes */
 141 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 142                                    u32 sel);
 143 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 144                                   u16 v, u32 sel);
 145 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 146 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 147 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 148 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 149 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 150 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 151 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 152 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 153 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 154 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 155 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 156 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 157 static void wlc_gpio_init(struct wlc_info *wlc);
 158 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 159                                       int len);
 160 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 161                                       int len);
 162 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 163 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 164 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 165                              chanspec_t chanspec);
 166 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 167                                         bool shortslot);
 168 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 169 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 170                                              u8 rate);
 171
 172 /* === Low Level functions === */
 173
 174 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 175 {
 176         wlc_hw->shortslot = shortslot;
 177
 178         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 179                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 180                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 181                 wlc_enable_mac(wlc_hw->wlc);
 182         }
 183 }
 184
 185 /*
 186  * Update the slot timing for standard 11b/g (20us slots)
 187  * or shortslot 11g (9us slots)
 188  * The PSM needs to be suspended for this call.
 189  */
 190 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 191                                         bool shortslot)
 192 {
 193         struct osl_info *osh;
 194         d11regs_t *regs;
 195
 196         osh = wlc_hw->osh;
 197         regs = wlc_hw->regs;
 198
 199         if (shortslot) {
 200                 /* 11g short slot: 11a timing */
 201                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 202                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 203         } else {
 204                 /* 11g long slot: 11b timing */
 205                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 206                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 207         }
 208 }
 209
 210 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 211 {
 212         /* init microcode host flags */
 213         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 214
 215         /* do band-specific ucode IHR, SHM, and SCR inits */
 216         if (D11REV_IS(wlc_hw->corerev, 23)) {
 217                 if (WLCISNPHY(wlc_hw->band)) {
 218                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 219                 } else {
 220                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 221                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 222                 }
 223         } else {
 224                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 225                         if (WLCISLCNPHY(wlc_hw->band)) {
 226                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 227                         } else
 228                                 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 229                                          __func__, wlc_hw->unit,
 230                                          wlc_hw->corerev);
 231                 } else {
 232                         WL_ERROR("%s: wl%d: unsupported corerev %d\n",
 233                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 234                 }
 235         }
 236 }
 237
 238 /* switch to new band but leave it inactive */
 239 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 240 {
 241         struct wlc_hw_info *wlc_hw = wlc->hw;
 242         u32 macintmask;
 243         u32 tmp;
 244
 245         WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
 246
 247         ASSERT(bandunit != wlc_hw->band->bandunit);
 248         ASSERT(si_iscoreup(wlc_hw->sih));
 249         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 250                0);
 251
 252         /* disable interrupts */
 253         macintmask = wl_intrsoff(wlc->wl);
 254
 255         /* radio off */
 256         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 257
 258         ASSERT(wlc_hw->clk);
 259
 260         if (D11REV_LT(wlc_hw->corerev, 17))
 261                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
 262
 263         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 264
 265         wlc_setxband(wlc_hw, bandunit);
 266
 267         return macintmask;
 268 }
 269
 270 /* Process received frames */
 271 /*
 272  * Return true if more frames need to be processed. false otherwise.
 273  * Param 'bound' indicates max. # frames to process before break out.
 274  */
 275 static bool BCMFASTPATH
 276 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 277 {
 278         struct sk_buff *p;
 279         struct sk_buff *head = NULL;
 280         struct sk_buff *tail = NULL;
 281         uint n = 0;
 282         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 283         u32 tsf_h, tsf_l;
 284         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 285
 286         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
 287         /* gather received frames */
 288         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 289
 290                 if (!tail)
 291                         head = tail = p;
 292                 else {
 293                         tail->prev = p;
 294                         tail = p;
 295                 }
 296
 297                 /* !give others some time to run! */
 298                 if (++n >= bound_limit)
 299                         break;
 300         }
 301
 302         /* get the TSF REG reading */
 303         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 304
 305         /* post more rbufs */
 306         dma_rxfill(wlc_hw->di[fifo]);
 307
 308         /* process each frame */
 309         while ((p = head) != NULL) {
 310                 head = head->prev;
 311                 p->prev = NULL;
 312
 313                 /* record the tsf_l in wlc_rxd11hdr */
 314                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 315                 wlc_rxhdr->tsf_l = htol32(tsf_l);
 316
 317                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 318                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 319
 320                 wlc_recv(wlc_hw->wlc, p);
 321         }
 322
 323         return n >= bound_limit;
 324 }
 325
 326 /* second-level interrupt processing
 327  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 328  *   Param 'bounded' indicates if applicable loops should be bounded.
 329  */
 330 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
 331 {
 332         u32 macintstatus;
 333         struct wlc_hw_info *wlc_hw = wlc->hw;
 334         d11regs_t *regs = wlc_hw->regs;
 335         bool fatal = false;
 336
 337         if (DEVICEREMOVED(wlc)) {
 338                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
 339                 wl_down(wlc->wl);
 340                 return false;
 341         }
 342
 343         /* grab and clear the saved software intstatus bits */
 344         macintstatus = wlc->macintstatus;
 345         wlc->macintstatus = 0;
 346
 347         WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
 348                  wlc_hw->unit, macintstatus);
 349
 350         if (macintstatus & MI_PRQ) {
 351                 /* Process probe request FIFO */
 352                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 353         }
 354
 355         /* BCN template is available */
 356         /* ZZZ: Use AP_ACTIVE ? */
 357         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 358             && (macintstatus & MI_BCNTPL)) {
 359                 wlc_update_beacon(wlc);
 360         }
 361
 362         /* PMQ entry addition */
 363         if (macintstatus & MI_PMQ) {
 364         }
 365
 366         /* tx status */
 367         if (macintstatus & MI_TFS) {
 368                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 369                         wlc->macintstatus |= MI_TFS;
 370                 if (fatal) {
 371                         WL_ERROR("MI_TFS: fatal\n");
 372                         goto fatal;
 373                 }
 374         }
 375
 376         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 377                 wlc_tbtt(wlc, regs);
 378
 379         /* ATIM window end */
 380         if (macintstatus & MI_ATIMWINEND) {
 381                 WL_TRACE("wlc_isr: end of ATIM window\n");
 382
 383                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 384                 wlc->qvalid = 0;
 385         }
 386
 387         /* phy tx error */
 388         if (macintstatus & MI_PHYTXERR) {
 389                 WLCNTINCR(wlc->pub->_cnt->txphyerr);
 390         }
 391
 392         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 393         if (macintstatus & MI_DMAINT) {
 394                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 395                         wlc->macintstatus |= MI_DMAINT;
 396                 }
 397         }
 398
 399         /* TX FIFO suspend/flush completion */
 400         if (macintstatus & MI_TXSTOP) {
 401                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 402                         /*      WL_ERROR("dpc: fifo_suspend_comlete\n"); */
 403                 }
 404         }
 405
 406         /* noise sample collected */
 407         if (macintstatus & MI_BG_NOISE) {
 408                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 409         }
 410
 411         if (macintstatus & MI_GP0) {
 412                 WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
 413                          wlc_hw->unit, wlc_hw->now);
 414
 415                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 416                                         __func__, wlc_hw->sih->chip,
 417                                         wlc_hw->sih->chiprev);
 418
 419                 WLCNTINCR(wlc->pub->_cnt->psmwds);
 420
 421                 /* big hammer */
 422                 wl_init(wlc->wl);
 423         }
 424
 425         /* gptimer timeout */
 426         if (macintstatus & MI_TO) {
 427                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 428         }
 429
 430         if (macintstatus & MI_RFDISABLE) {
 431 #if defined(BCMDBG)
 432                 u32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD;
 433 #endif
 434
 435                 WL_ERROR("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n",
 436                          wlc_hw->unit, rfd);
 437
 438                 WLCNTINCR(wlc->pub->_cnt->rfdisable);
 439         }
 440
 441         /* send any enq'd tx packets. Just makes sure to jump start tx */
 442         if (!pktq_empty(&wlc->active_queue->q))
 443                 wlc_send_q(wlc, wlc->active_queue);
 444
 445         ASSERT(wlc_ps_check(wlc));
 446
 447         /* make sure the bound indication and the implementation are in sync */
 448         ASSERT(bounded == true || wlc->macintstatus == 0);
 449
 450         /* it isn't done and needs to be resched if macintstatus is non-zero */
 451         return wlc->macintstatus != 0;
 452
 453  fatal:
 454         wl_init(wlc->wl);
 455         return wlc->macintstatus != 0;
 456 }
 457
 458 /* common low-level watchdog code */
 459 void wlc_bmac_watchdog(void *arg)
 460 {
 461         struct wlc_info *wlc = (struct wlc_info *) arg;
 462         struct wlc_hw_info *wlc_hw = wlc->hw;
 463
 464         WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
 465
 466         if (!wlc_hw->up)
 467                 return;
 468
 469         /* increment second count */
 470         wlc_hw->now++;
 471
 472         /* Check for FIFO error interrupts */
 473         wlc_bmac_fifoerrors(wlc_hw);
 474
 475         /* make sure RX dma has buffers */
 476         dma_rxfill(wlc->hw->di[RX_FIFO]);
 477         if (D11REV_IS(wlc_hw->corerev, 4)) {
 478                 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
 479         }
 480
 481         wlc_phy_watchdog(wlc_hw->band->pi);
 482 }
 483
 484 void
 485 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 486                       bool mute, struct txpwr_limits *txpwr)
 487 {
 488         uint bandunit;
 489
 490         WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
 491                  wlc_hw->unit, chanspec);
 492
 493         wlc_hw->chanspec = chanspec;
 494
 495         /* Switch bands if necessary */
 496         if (NBANDS_HW(wlc_hw) > 1) {
 497                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 498                 if (wlc_hw->band->bandunit != bandunit) {
 499                         /* wlc_bmac_setband disables other bandunit,
 500                          *  use light band switch if not up yet
 501                          */
 502                         if (wlc_hw->up) {
 503                                 wlc_phy_chanspec_radio_set(wlc_hw->
 504                                                            bandstate[bandunit]->
 505                                                            pi, chanspec);
 506                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 507                         } else {
 508                                 wlc_setxband(wlc_hw, bandunit);
 509                         }
 510                 }
 511         }
 512
 513         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 514
 515         if (!wlc_hw->up) {
 516                 if (wlc_hw->clk)
 517                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 518                                                   chanspec);
 519                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 520         } else {
 521                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 522                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 523
 524                 /* Update muting of the channel */
 525                 wlc_bmac_mute(wlc_hw, mute, 0);
 526         }
 527 }
 528
 529 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 530 {
 531         state->machwcap = wlc_hw->machwcap;
 532
 533         return 0;
 534 }
 535
 536 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 537 {
 538         uint i;
 539         char name[8];
 540         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 541         u16 pio_mhf2 = 0;
 542         struct wlc_hw_info *wlc_hw = wlc->hw;
 543         uint unit = wlc_hw->unit;
 544         wlc_tunables_t *tune = wlc->pub->tunables;
 545
 546         /* name and offsets for dma_attach */
 547         snprintf(name, sizeof(name), "wl%d", unit);
 548
 549         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 550                 uint addrwidth;
 551                 int dma_attach_err = 0;
 552                 struct osl_info *osh = wlc_hw->osh;
 553
 554                 /* Find out the DMA addressing capability and let OS know
 555                  * All the channels within one DMA core have 'common-minimum' same
 556                  * capability
 557                  */
 558                 addrwidth =
 559                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 560
 561                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 562                         WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
 563                                  unit);
 564                         return false;
 565                 }
 566
 567                 /*
 568                  * FIFO 0
 569                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 570                  * RX: RX_FIFO (RX data packets)
 571                  */
 572                 ASSERT(TX_AC_BK_FIFO == 0);
 573                 ASSERT(RX_FIFO == 0);
 574                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 575                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 576                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 577                                            (wme ? tune->ntxd : 0), tune->nrxd,
 578                                            tune->rxbufsz, -1, tune->nrxbufpost,
 579                                            WL_HWRXOFF, &wl_msg_level);
 580                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 581
 582                 /*
 583                  * FIFO 1
 584                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 585                  *   (legacy) TX_DATA_FIFO (TX data packets)
 586                  * RX: UNUSED
 587                  */
 588                 ASSERT(TX_AC_BE_FIFO == 1);
 589                 ASSERT(TX_DATA_FIFO == 1);
 590                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 591                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 592                                            tune->ntxd, 0, 0, -1, 0, 0,
 593                                            &wl_msg_level);
 594                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 595
 596                 /*
 597                  * FIFO 2
 598                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 599                  * RX: UNUSED
 600                  */
 601                 ASSERT(TX_AC_VI_FIFO == 2);
 602                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 603                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 604                                            tune->ntxd, 0, 0, -1, 0, 0,
 605                                            &wl_msg_level);
 606                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 607                 /*
 608                  * FIFO 3
 609                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 610                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 611                  * RX: RX_TXSTATUS_FIFO (transmit-status packets)
 612                  *      for corerev < 5 only
 613                  */
 614                 ASSERT(TX_AC_VO_FIFO == 3);
 615                 ASSERT(TX_CTL_FIFO == 3);
 616                 if (D11REV_IS(wlc_hw->corerev, 4)) {
 617                         ASSERT(RX_TXSTATUS_FIFO == 3);
 618                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 619                                                    DMAREG(wlc_hw, DMA_TX, 3),
 620                                                    DMAREG(wlc_hw, DMA_RX, 3),
 621                                                    tune->ntxd, tune->nrxd,
 622                                                    sizeof(tx_status_t), -1,
 623                                                    tune->nrxbufpost, 0,
 624                                                    &wl_msg_level);
 625                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 626                 } else {
 627                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 628                                                    DMAREG(wlc_hw, DMA_TX, 3),
 629                                                    NULL, tune->ntxd, 0, 0, -1,
 630                                                    0, 0, &wl_msg_level);
 631                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 632                 }
 633 /* Cleaner to leave this as if with AP defined */
 634
 635                 if (dma_attach_err) {
 636                         WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
 637                         return false;
 638                 }
 639
 640                 /* get pointer to dma engine tx flow control variable */
 641                 for (i = 0; i < NFIFO; i++)
 642                         if (wlc_hw->di[i])
 643                                 wlc_hw->txavail[i] =
 644                                     (uint *) dma_getvar(wlc_hw->di[i],
 645                                                         "&txavail");
 646         }
 647
 648         /* initial ucode host flags */
 649         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 650
 651         return true;
 652 }
 653
 654 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 655 {
 656         uint j;
 657
 658         for (j = 0; j < NFIFO; j++) {
 659                 if (wlc_hw->di[j]) {
 660                         dma_detach(wlc_hw->di[j]);
 661                         wlc_hw->di[j] = NULL;
 662                 }
 663         }
 664 }
 665
 666 /* low level attach
 667  *    run backplane attach, init nvram
 668  *    run phy attach
 669  *    initialize software state for each core and band
 670  *    put the whole chip in reset(driver down state), no clock
 671  */
 672 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 673                     bool piomode, struct osl_info *osh, void *regsva,
 674                     uint bustype, void *btparam)
 675 {
 676         struct wlc_hw_info *wlc_hw;
 677         d11regs_t *regs;
 678         char *macaddr = NULL;
 679         char *vars;
 680         uint err = 0;
 681         uint j;
 682         bool wme = false;
 683         shared_phy_params_t sha_params;
 684
 685         WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
 686                  unit, vendor, device);
 687
 688         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 689
 690         wme = true;
 691
 692         wlc_hw = wlc->hw;
 693         wlc_hw->wlc = wlc;
 694         wlc_hw->unit = unit;
 695         wlc_hw->osh = osh;
 696         wlc_hw->band = wlc_hw->bandstate[0];
 697         wlc_hw->_piomode = piomode;
 698
 699         /* populate struct wlc_hw_info with default values  */
 700         wlc_bmac_info_init(wlc_hw);
 701
 702         /*
 703          * Do the hardware portion of the attach.
 704          * Also initialize software state that depends on the particular hardware
 705          * we are running.
 706          */
 707         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 708                                 &wlc_hw->vars, &wlc_hw->vars_size);
 709         if (wlc_hw->sih == NULL) {
 710                 WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
 711                 err = 11;
 712                 goto fail;
 713         }
 714         vars = wlc_hw->vars;
 715
 716         /*
 717          * Get vendid/devid nvram overwrites, which could be different
 718          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 719          * SDIO_BUS, and SROMless devices on PCI_BUS.
 720          */
 721 #ifdef BCMBUSTYPE
 722         bustype = BCMBUSTYPE;
 723 #endif
 724         if (bustype != SI_BUS) {
 725                 char *var;
 726
 727                 var = getvar(vars, "vendid");
 728                 if (var) {
 729                         vendor = (u16) simple_strtoul(var, NULL, 0);
 730                         WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
 731                 }
 732                 var = getvar(vars, "devid");
 733                 if (var) {
 734                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 735                         if (devid != 0xffff) {
 736                                 device = devid;
 737                                 WL_ERROR("Overriding device id = 0x%x\n",
 738                                          device);
 739                         }
 740                 }
 741
 742                 /* verify again the device is supported */
 743                 if (!wlc_chipmatch(vendor, device)) {
 744                         WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
 745                                  unit, vendor, device);
 746                         err = 12;
 747                         goto fail;
 748                 }
 749         }
 750
 751         wlc_hw->vendorid = vendor;
 752         wlc_hw->deviceid = device;
 753
 754         /* set bar0 window to point at D11 core */
 755         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 756         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 757
 758         regs = wlc_hw->regs;
 759
 760         wlc->regs = wlc_hw->regs;
 761
 762         /* validate chip, chiprev and corerev */
 763         if (!wlc_isgoodchip(wlc_hw)) {
 764                 err = 13;
 765                 goto fail;
 766         }
 767
 768         /* initialize power control registers */
 769         si_clkctl_init(wlc_hw->sih);
 770
 771         /* request fastclock and force fastclock for the rest of attach
 772          * bring the d11 core out of reset.
 773          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 774          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 775          */
 776         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 777         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 778
 779         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 780                 WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
 781                          unit);
 782                 err = 14;
 783                 goto fail;
 784         }
 785
 786         /* get the board rev, used just below */
 787         j = getintvar(vars, "boardrev");
 788         /* promote srom boardrev of 0xFF to 1 */
 789         if (j == BOARDREV_PROMOTABLE)
 790                 j = BOARDREV_PROMOTED;
 791         wlc_hw->boardrev = (u16) j;
 792         if (!wlc_validboardtype(wlc_hw)) {
 793                 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
 794                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 795                 err = 15;
 796                 goto fail;
 797         }
 798         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 799         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 800         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 801
 802         if (D11REV_LE(wlc_hw->corerev, 4)
 803             || (wlc_hw->boardflags & BFL_NOPLLDOWN))
 804                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 805
 806         if ((wlc_hw->sih->bustype == PCI_BUS)
 807             && (si_pci_war16165(wlc_hw->sih)))
 808                 wlc->war16165 = true;
 809
 810         /* check device id(srom, nvram etc.) to set bands */
 811         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 812                 /* Dualband boards */
 813                 wlc_hw->_nbands = 2;
 814         } else
 815                 wlc_hw->_nbands = 1;
 816
 817         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 818                 wlc_hw->_nbands = 1;
 819
 820         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 821          * init of these values
 822          */
 823         wlc->vendorid = wlc_hw->vendorid;
 824         wlc->deviceid = wlc_hw->deviceid;
 825         wlc->pub->sih = wlc_hw->sih;
 826         wlc->pub->corerev = wlc_hw->corerev;
 827         wlc->pub->sromrev = wlc_hw->sromrev;
 828         wlc->pub->boardrev = wlc_hw->boardrev;
 829         wlc->pub->boardflags = wlc_hw->boardflags;
 830         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 831         wlc->pub->_nbands = wlc_hw->_nbands;
 832
 833         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 834
 835         if (wlc_hw->physhim == NULL) {
 836                 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 837                          unit);
 838                 err = 25;
 839                 goto fail;
 840         }
 841
 842         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 843         sha_params.osh = osh;
 844         sha_params.sih = wlc_hw->sih;
 845         sha_params.physhim = wlc_hw->physhim;
 846         sha_params.unit = unit;
 847         sha_params.corerev = wlc_hw->corerev;
 848         sha_params.vars = vars;
 849         sha_params.vid = wlc_hw->vendorid;
 850         sha_params.did = wlc_hw->deviceid;
 851         sha_params.chip = wlc_hw->sih->chip;
 852         sha_params.chiprev = wlc_hw->sih->chiprev;
 853         sha_params.chippkg = wlc_hw->sih->chippkg;
 854         sha_params.sromrev = wlc_hw->sromrev;
 855         sha_params.boardtype = wlc_hw->sih->boardtype;
 856         sha_params.boardrev = wlc_hw->boardrev;
 857         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 858         sha_params.boardflags = wlc_hw->boardflags;
 859         sha_params.boardflags2 = wlc_hw->boardflags2;
 860         sha_params.bustype = wlc_hw->sih->bustype;
 861         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 862
 863         /* alloc and save pointer to shared phy state area */
 864         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 865         if (!wlc_hw->phy_sh) {
 866                 err = 16;
 867                 goto fail;
 868         }
 869
 870         /* initialize software state for each core and band */
 871         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 872                 /*
 873                  * band0 is always 2.4Ghz
 874                  * band1, if present, is 5Ghz
 875                  */
 876
 877                 /* So if this is a single band 11a card, use band 1 */
 878                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 879                         j = BAND_5G_INDEX;
 880
 881                 wlc_setxband(wlc_hw, j);
 882
 883                 wlc_hw->band->bandunit = j;
 884                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 885                 wlc->band->bandunit = j;
 886                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 887                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 888
 889                 if (D11REV_GE(wlc_hw->corerev, 13)) {
 890                         wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 891                         wlc_hw->machwcap_backup = wlc_hw->machwcap;
 892                 }
 893
 894                 /* init tx fifo size */
 895                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 896                        ARRAY_SIZE(xmtfifo_sz));
 897                 wlc_hw->xmtfifo_sz =
 898                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 899
 900                 /* Get a phy for this band */
 901                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 902                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
 903                 if (wlc_hw->band->pi == NULL) {
 904                         WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
 905                                  unit);
 906                         err = 17;
 907                         goto fail;
 908                 }
 909
 910                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 911
 912                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 913                                        &wlc_hw->band->phyrev,
 914                                        &wlc_hw->band->radioid,
 915                                        &wlc_hw->band->radiorev);
 916                 wlc_hw->band->abgphy_encore =
 917                     wlc_phy_get_encore(wlc_hw->band->pi);
 918                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 919                 wlc_hw->band->core_flags =
 920                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 921
 922                 /* verify good phy_type & supported phy revision */
 923                 if (WLCISNPHY(wlc_hw->band)) {
 924                         if (NCONF_HAS(wlc_hw->band->phyrev))
 925                                 goto good_phy;
 926                         else
 927                                 goto bad_phy;
 928                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 929                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 930                                 goto good_phy;
 931                         else
 932                                 goto bad_phy;
 933                 } else {
 934  bad_phy:
 935                         WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
 936                                  unit,
 937                                  wlc_hw->band->phytype, wlc_hw->band->phyrev);
 938                         err = 18;
 939                         goto fail;
 940                 }
 941
 942  good_phy:
 943                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 944                  * high level attach. However we can not make that change until all low level access
 945                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 946                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 947                  * low only init when all fns updated.
 948                  */
 949                 wlc->band->pi = wlc_hw->band->pi;
 950                 wlc->band->phytype = wlc_hw->band->phytype;
 951                 wlc->band->phyrev = wlc_hw->band->phyrev;
 952                 wlc->band->radioid = wlc_hw->band->radioid;
 953                 wlc->band->radiorev = wlc_hw->band->radiorev;
 954
 955                 /* default contention windows size limits */
 956                 wlc_hw->band->CWmin = APHY_CWMIN;
 957                 wlc_hw->band->CWmax = PHY_CWMAX;
 958
 959                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 960                         err = 19;
 961                         goto fail;
 962                 }
 963         }
 964
 965         /* disable core to match driver "down" state */
 966         wlc_coredisable(wlc_hw);
 967
 968         /* Match driver "down" state */
 969         if (wlc_hw->sih->bustype == PCI_BUS)
 970                 si_pci_down(wlc_hw->sih);
 971
 972         /* register sb interrupt callback functions */
 973         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 974                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 975
 976         /* turn off pll and xtal to match driver "down" state */
 977         wlc_bmac_xtal(wlc_hw, OFF);
 978
 979         /* *********************************************************************
 980          * The hardware is in the DOWN state at this point. D11 core
 981          * or cores are in reset with clocks off, and the board PLLs
 982          * are off if possible.
 983          *
 984          * Beyond this point, wlc->sbclk == false and chip registers
 985          * should not be touched.
 986          *********************************************************************
 987          */
 988
 989         /* init etheraddr state variables */
 990         macaddr = wlc_get_macaddr(wlc_hw);
 991         if (macaddr == NULL) {
 992                 WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
 993                 err = 21;
 994                 goto fail;
 995         }
 996         bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
 997         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 998             is_zero_ether_addr(wlc_hw->etheraddr)) {
 999                 WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
1000                          unit, macaddr);
1001                 err = 22;
1002                 goto fail;
1003         }
1004
1005         WL_ERROR("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1006                  __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1007                  wlc_hw->sih->boardtype, macaddr);
1008
1009         return err;
1010
1011  fail:
1012         WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
1013         return err;
1014 }
1015
1016 /*
1017  * Initialize wlc_info default values ...
1018  * may get overrides later in this function
1019  *  BMAC_NOTES, move low out and resolve the dangling ones
1020  */
1021 void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
1022 {
1023         struct wlc_info *wlc = wlc_hw->wlc;
1024
1025         /* set default sw macintmask value */
1026         wlc->defmacintmask = DEF_MACINTMASK;
1027
1028         /* various 802.11g modes */
1029         wlc_hw->shortslot = false;
1030
1031         wlc_hw->SFBL = RETRY_SHORT_FB;
1032         wlc_hw->LFBL = RETRY_LONG_FB;
1033
1034         /* default mac retry limits */
1035         wlc_hw->SRL = RETRY_SHORT_DEF;
1036         wlc_hw->LRL = RETRY_LONG_DEF;
1037         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1038 }
1039
1040 /*
1041  * low level detach
1042  */
1043 int wlc_bmac_detach(struct wlc_info *wlc)
1044 {
1045         uint i;
1046         wlc_hwband_t *band;
1047         struct wlc_hw_info *wlc_hw = wlc->hw;
1048         int callbacks;
1049
1050         callbacks = 0;
1051
1052         if (wlc_hw->sih) {
1053                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1054                  * interrupt object may has been freed. this must be done before sb core switch
1055                  */
1056                 si_deregister_intr_callback(wlc_hw->sih);
1057
1058                 if (wlc_hw->sih->bustype == PCI_BUS)
1059                         si_pci_sleep(wlc_hw->sih);
1060         }
1061
1062         wlc_bmac_detach_dmapio(wlc_hw);
1063
1064         band = wlc_hw->band;
1065         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1066                 if (band->pi) {
1067                         /* Detach this band's phy */
1068                         wlc_phy_detach(band->pi);
1069                         band->pi = NULL;
1070                 }
1071                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1072         }
1073
1074         /* Free shared phy state */
1075         wlc_phy_shared_detach(wlc_hw->phy_sh);
1076
1077         wlc_phy_shim_detach(wlc_hw->physhim);
1078
1079         /* free vars */
1080         if (wlc_hw->vars) {
1081                 kfree(wlc_hw->vars);
1082                 wlc_hw->vars = NULL;
1083         }
1084
1085         if (wlc_hw->sih) {
1086                 si_detach(wlc_hw->sih);
1087                 wlc_hw->sih = NULL;
1088         }
1089
1090         return callbacks;
1091
1092 }
1093
1094 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1095 {
1096         WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1097
1098         WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1099
1100         /* reset the core */
1101         if (!DEVICEREMOVED(wlc_hw->wlc))
1102                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1103
1104         /* purge the dma rings */
1105         wlc_flushqueues(wlc_hw->wlc);
1106
1107         wlc_reset_bmac_done(wlc_hw->wlc);
1108 }
1109
1110 void
1111 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1112                           bool mute) {
1113         u32 macintmask;
1114         bool fastclk;
1115         struct wlc_info *wlc = wlc_hw->wlc;
1116
1117         WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1118
1119         /* request FAST clock if not on */
1120         fastclk = wlc_hw->forcefastclk;
1121         if (!fastclk)
1122                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1123
1124         /* disable interrupts */
1125         macintmask = wl_intrsoff(wlc->wl);
1126
1127         /* set up the specified band and chanspec */
1128         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1129         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1130
1131         /* do one-time phy inits and calibration */
1132         wlc_phy_cal_init(wlc_hw->band->pi);
1133
1134         /* core-specific initialization */
1135         wlc_coreinit(wlc);
1136
1137         /* suspend the tx fifos and mute the phy for preism cac time */
1138         if (mute)
1139                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1140
1141         /* band-specific inits */
1142         wlc_bmac_bsinit(wlc, chanspec);
1143
1144         /* restore macintmask */
1145         wl_intrsrestore(wlc->wl, macintmask);
1146
1147         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1148          * and wlc_enable_mac() will clear this override bit.
1149          */
1150         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1151
1152         /*
1153          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1154          */
1155         wlc_hw->mac_suspend_depth = 1;
1156
1157         /* restore the clk */
1158         if (!fastclk)
1159                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1160 }
1161
1162 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1163 {
1164         uint coremask;
1165
1166         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1167
1168         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1169
1170         /*
1171          * Enable pll and xtal, initialize the power control registers,
1172          * and force fastclock for the remainder of wlc_up().
1173          */
1174         wlc_bmac_xtal(wlc_hw, ON);
1175         si_clkctl_init(wlc_hw->sih);
1176         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1177
1178         /*
1179          * Configure pci/pcmcia here instead of in wlc_attach()
1180          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1181          */
1182         coremask = (1 << wlc_hw->wlc->core->coreidx);
1183
1184         if (wlc_hw->sih->bustype == PCI_BUS)
1185                 si_pci_setup(wlc_hw->sih, coremask);
1186
1187         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1188
1189         /*
1190          * Need to read the hwradio status here to cover the case where the system
1191          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1192          */
1193         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1194                 /* put SB PCI in down state again */
1195                 if (wlc_hw->sih->bustype == PCI_BUS)
1196                         si_pci_down(wlc_hw->sih);
1197                 wlc_bmac_xtal(wlc_hw, OFF);
1198                 return BCME_RADIOOFF;
1199         }
1200
1201         if (wlc_hw->sih->bustype == PCI_BUS)
1202                 si_pci_up(wlc_hw->sih);
1203
1204         /* reset the d11 core */
1205         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1206
1207         return 0;
1208 }
1209
1210 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1211 {
1212         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1213
1214         wlc_hw->up = true;
1215         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1216
1217         /* FULLY enable dynamic power control and d11 core interrupt */
1218         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1219         ASSERT(wlc_hw->wlc->macintmask == 0);
1220         wl_intrson(wlc_hw->wlc->wl);
1221         return 0;
1222 }
1223
1224 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1225 {
1226         bool dev_gone;
1227         uint callbacks = 0;
1228
1229         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1230
1231         if (!wlc_hw->up)
1232                 return callbacks;
1233
1234         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1235
1236         /* disable interrupts */
1237         if (dev_gone)
1238                 wlc_hw->wlc->macintmask = 0;
1239         else {
1240                 /* now disable interrupts */
1241                 wl_intrsoff(wlc_hw->wlc->wl);
1242
1243                 /* ensure we're running on the pll clock again */
1244                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1245         }
1246         /* down phy at the last of this stage */
1247         callbacks += wlc_phy_down(wlc_hw->band->pi);
1248
1249         return callbacks;
1250 }
1251
1252 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1253 {
1254         uint callbacks = 0;
1255         bool dev_gone;
1256
1257         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1258
1259         if (!wlc_hw->up)
1260                 return callbacks;
1261
1262         wlc_hw->up = false;
1263         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1264
1265         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1266
1267         if (dev_gone) {
1268                 wlc_hw->sbclk = false;
1269                 wlc_hw->clk = false;
1270                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1271
1272                 /* reclaim any posted packets */
1273                 wlc_flushqueues(wlc_hw->wlc);
1274         } else {
1275
1276                 /* Reset and disable the core */
1277                 if (si_iscoreup(wlc_hw->sih)) {
1278                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1279                             MCTL_EN_MAC)
1280                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1281                         callbacks += wl_reset(wlc_hw->wlc->wl);
1282                         wlc_coredisable(wlc_hw);
1283                 }
1284
1285                 /* turn off primary xtal and pll */
1286                 if (!wlc_hw->noreset) {
1287                         if (wlc_hw->sih->bustype == PCI_BUS)
1288                                 si_pci_down(wlc_hw->sih);
1289                         wlc_bmac_xtal(wlc_hw, OFF);
1290                 }
1291         }
1292
1293         return callbacks;
1294 }
1295
1296 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1297 {
1298         if (D11REV_IS(wlc_hw->corerev, 4))      /* no slowclock */
1299                 udelay(5);
1300         else {
1301                 /* delay before first read of ucode state */
1302                 udelay(40);
1303
1304                 /* wait until ucode is no longer asleep */
1305                 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1306                           DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1307         }
1308
1309         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1310 }
1311
1312 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1313 {
1314         bcopy(wlc_hw->etheraddr, ea, ETH_ALEN);
1315 }
1316
1317 int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1318 {
1319         return wlc_hw->band->bandtype;
1320 }
1321
1322 /* control chip clock to save power, enable dynamic clock or force fast clock */
1323 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1324 {
1325         if (PMUCTL_ENAB(wlc_hw->sih)) {
1326                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1327                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1328                  *      which means the FCA bit may not be set.
1329                  *      should wakeup mac if driver wants it to run on HT.
1330                  */
1331
1332                 if (wlc_hw->clk) {
1333                         if (mode == CLK_FAST) {
1334                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1335                                        CCS_FORCEHT);
1336
1337                                 udelay(64);
1338
1339                                 SPINWAIT(((R_REG
1340                                            (wlc_hw->osh,
1341                                             &wlc_hw->regs->
1342                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1343                                          PMU_MAX_TRANSITION_DLY);
1344                                 ASSERT(R_REG
1345                                        (wlc_hw->osh,
1346                                         &wlc_hw->regs->
1347                                         clk_ctl_st) & CCS_HTAVAIL);
1348                         } else {
1349                                 if ((wlc_hw->sih->pmurev == 0) &&
1350                                     (R_REG
1351                                      (wlc_hw->osh,
1352                                       &wlc_hw->regs->
1353                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1354                                         SPINWAIT(((R_REG
1355                                                    (wlc_hw->osh,
1356                                                     &wlc_hw->regs->
1357                                                     clk_ctl_st) & CCS_HTAVAIL)
1358                                                   == 0),
1359                                                  PMU_MAX_TRANSITION_DLY);
1360                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1361                                         ~CCS_FORCEHT);
1362                         }
1363                 }
1364                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1365         } else {
1366                 bool wakeup_ucode;
1367
1368                 /* old chips w/o PMU, force HT through cc,
1369                  * then use FCA to verify mac is running fast clock
1370                  */
1371
1372                 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1373
1374                 if (wlc_hw->up && wakeup_ucode)
1375                         wlc_ucode_wake_override_set(wlc_hw,
1376                                                     WLC_WAKE_OVERRIDE_CLKCTL);
1377
1378                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1379
1380                 if (D11REV_LT(wlc_hw->corerev, 11)) {
1381                         /* ucode WAR for old chips */
1382                         if (wlc_hw->forcefastclk)
1383                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1384                                              MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1385                         else
1386                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1387                                              WLC_BAND_ALL);
1388                 }
1389
1390                 /* check fast clock is available (if core is not in reset) */
1391                 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1392                     && wlc_hw->clk)
1393                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1394
1395                 /* keep the ucode wake bit on if forcefastclk is on
1396                  * since we do not want ucode to put us back to slow clock
1397                  * when it dozes for PM mode.
1398                  * Code below matches the wake override bit with current forcefastclk state
1399                  * Only setting bit in wake_override instead of waking ucode immediately
1400                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1401                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1402                  * (protected by an up check) was executed just below.
1403                  */
1404                 if (wlc_hw->forcefastclk)
1405                         mboolset(wlc_hw->wake_override,
1406                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1407                 else
1408                         mboolclr(wlc_hw->wake_override,
1409                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1410
1411                 /* ok to clear the wakeup now */
1412                 if (wlc_hw->up && wakeup_ucode)
1413                         wlc_ucode_wake_override_clear(wlc_hw,
1414                                                       WLC_WAKE_OVERRIDE_CLKCTL);
1415         }
1416 }
1417
1418 /* set initial host flags value */
1419 static void
1420 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1421 {
1422         struct wlc_hw_info *wlc_hw = wlc->hw;
1423
1424         memset(mhfs, 0, MHFMAX * sizeof(u16));
1425
1426         mhfs[MHF2] |= mhf2_init;
1427
1428         /* prohibit use of slowclock on multifunction boards */
1429         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1430                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1431
1432         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1433                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1434                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1435         }
1436 }
1437
1438 /* set or clear ucode host flag bits
1439  * it has an optimization for no-change write
1440  * it only writes through shared memory when the core has clock;
1441  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1442  *
1443  *
1444  * bands values are: WLC_BAND_AUTO <--- Current band only
1445  *                   WLC_BAND_5G   <--- 5G band only
1446  *                   WLC_BAND_2G   <--- 2G band only
1447  *                   WLC_BAND_ALL  <--- All bands
1448  */
1449 void
1450 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1451              int bands)
1452 {
1453         u16 save;
1454         u16 addr[MHFMAX] = {
1455                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1456                 M_HOST_FLAGS5
1457         };
1458         wlc_hwband_t *band;
1459
1460         ASSERT((val & ~mask) == 0);
1461         ASSERT(idx < MHFMAX);
1462         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1463
1464         switch (bands) {
1465                 /* Current band only or all bands,
1466                  * then set the band to current band
1467                  */
1468         case WLC_BAND_AUTO:
1469         case WLC_BAND_ALL:
1470                 band = wlc_hw->band;
1471                 break;
1472         case WLC_BAND_5G:
1473                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1474                 break;
1475         case WLC_BAND_2G:
1476                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1477                 break;
1478         default:
1479                 ASSERT(0);
1480                 band = NULL;
1481         }
1482
1483         if (band) {
1484                 save = band->mhfs[idx];
1485                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1486
1487                 /* optimization: only write through if changed, and
1488                  * changed band is the current band
1489                  */
1490                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1491                     && (band == wlc_hw->band))
1492                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1493                                            (u16) band->mhfs[idx]);
1494         }
1495
1496         if (bands == WLC_BAND_ALL) {
1497                 wlc_hw->bandstate[0]->mhfs[idx] =
1498                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1499                 wlc_hw->bandstate[1]->mhfs[idx] =
1500                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1501         }
1502 }
1503
1504 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1505 {
1506         wlc_hwband_t *band;
1507         ASSERT(idx < MHFMAX);
1508
1509         switch (bands) {
1510         case WLC_BAND_AUTO:
1511                 band = wlc_hw->band;
1512                 break;
1513         case WLC_BAND_5G:
1514                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1515                 break;
1516         case WLC_BAND_2G:
1517                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1518                 break;
1519         default:
1520                 ASSERT(0);
1521                 band = NULL;
1522         }
1523
1524         if (!band)
1525                 return 0;
1526
1527         return band->mhfs[idx];
1528 }
1529
1530 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1531 {
1532         u8 idx;
1533         u16 addr[] = {
1534                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1535                 M_HOST_FLAGS5
1536         };
1537
1538         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1539
1540         for (idx = 0; idx < MHFMAX; idx++) {
1541                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1542         }
1543 }
1544
1545 /* set the maccontrol register to desired reset state and
1546  * initialize the sw cache of the register
1547  */
1548 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1549 {
1550         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1551         wlc_hw->maccontrol = 0;
1552         wlc_hw->suspended_fifos = 0;
1553         wlc_hw->wake_override = 0;
1554         wlc_hw->mute_override = 0;
1555         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1556 }
1557
1558 /* set or clear maccontrol bits */
1559 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1560 {
1561         u32 maccontrol;
1562         u32 new_maccontrol;
1563
1564         ASSERT((val & ~mask) == 0);
1565
1566         maccontrol = wlc_hw->maccontrol;
1567         new_maccontrol = (maccontrol & ~mask) | val;
1568
1569         /* if the new maccontrol value is the same as the old, nothing to do */
1570         if (new_maccontrol == maccontrol)
1571                 return;
1572
1573         /* something changed, cache the new value */
1574         wlc_hw->maccontrol = new_maccontrol;
1575
1576         /* write the new values with overrides applied */
1577         wlc_mctrl_write(wlc_hw);
1578 }
1579
1580 /* write the software state of maccontrol and overrides to the maccontrol register */
1581 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1582 {
1583         u32 maccontrol = wlc_hw->maccontrol;
1584
1585         /* OR in the wake bit if overridden */
1586         if (wlc_hw->wake_override)
1587                 maccontrol |= MCTL_WAKE;
1588
1589         /* set AP and INFRA bits for mute if needed */
1590         if (wlc_hw->mute_override) {
1591                 maccontrol &= ~(MCTL_AP);
1592                 maccontrol |= MCTL_INFRA;
1593         }
1594
1595         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1596 }
1597
1598 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1599 {
1600         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1601
1602         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1603                 mboolset(wlc_hw->wake_override, override_bit);
1604                 return;
1605         }
1606
1607         mboolset(wlc_hw->wake_override, override_bit);
1608
1609         wlc_mctrl_write(wlc_hw);
1610         wlc_bmac_wait_for_wake(wlc_hw);
1611
1612         return;
1613 }
1614
1615 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1616 {
1617         ASSERT(wlc_hw->wake_override & override_bit);
1618
1619         mboolclr(wlc_hw->wake_override, override_bit);
1620
1621         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1622                 return;
1623
1624         wlc_mctrl_write(wlc_hw);
1625
1626         return;
1627 }
1628
1629 /* When driver needs ucode to stop beaconing, it has to make sure that
1630  * MCTL_AP is clear and MCTL_INFRA is set
1631  * Mode           MCTL_AP        MCTL_INFRA
1632  * AP                1              1
1633  * STA               0              1 <--- This will ensure no beacons
1634  * IBSS              0              0
1635  */
1636 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1637 {
1638         wlc_hw->mute_override = 1;
1639
1640         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1641          * override, then there is no change to write
1642          */
1643         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1644                 return;
1645
1646         wlc_mctrl_write(wlc_hw);
1647
1648         return;
1649 }
1650
1651 /* Clear the override on AP and INFRA bits */
1652 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1653 {
1654         if (wlc_hw->mute_override == 0)
1655                 return;
1656
1657         wlc_hw->mute_override = 0;
1658
1659         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1660          * override, then there is no change to write
1661          */
1662         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1663                 return;
1664
1665         wlc_mctrl_write(wlc_hw);
1666 }
1667
1668 /*
1669  * Write a MAC address to the rcmta structure
1670  */
1671 void
1672 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1673                    const u8 *addr)
1674 {
1675         d11regs_t *regs = wlc_hw->regs;
1676         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1677         u32 mac_hm;
1678         u16 mac_l;
1679         struct osl_info *osh;
1680
1681         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1682
1683         ASSERT(wlc_hw->corerev > 4);
1684
1685         mac_hm =
1686             (addr[3] << 24) | (addr[2] << 16) |
1687             (addr[1] << 8) | addr[0];
1688         mac_l = (addr[5] << 8) | addr[4];
1689
1690         osh = wlc_hw->osh;
1691
1692         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1693         (void)R_REG(osh, &regs->objaddr);
1694         W_REG(osh, &regs->objdata, mac_hm);
1695         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1696         (void)R_REG(osh, &regs->objaddr);
1697         W_REG(osh, objdata16, mac_l);
1698 }
1699
1700 /*
1701  * Write a MAC address to the given match reg offset in the RXE match engine.
1702  */
1703 void
1704 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1705                        const u8 *addr)
1706 {
1707         d11regs_t *regs;
1708         u16 mac_l;
1709         u16 mac_m;
1710         u16 mac_h;
1711         struct osl_info *osh;
1712
1713         WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1714
1715         ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1716
1717         regs = wlc_hw->regs;
1718         mac_l = addr[0] | (addr[1] << 8);
1719         mac_m = addr[2] | (addr[3] << 8);
1720         mac_h = addr[4] | (addr[5] << 8);
1721
1722         osh = wlc_hw->osh;
1723
1724         /* enter the MAC addr into the RXE match registers */
1725         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1726         W_REG(osh, &regs->rcm_mat_data, mac_l);
1727         W_REG(osh, &regs->rcm_mat_data, mac_m);
1728         W_REG(osh, &regs->rcm_mat_data, mac_h);
1729
1730 }
1731
1732 void
1733 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1734                             void *buf)
1735 {
1736         d11regs_t *regs;
1737         u32 word;
1738         bool be_bit;
1739 #ifdef IL_BIGENDIAN
1740         volatile u16 *dptr = NULL;
1741 #endif                          /* IL_BIGENDIAN */
1742         struct osl_info *osh;
1743
1744         WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1745
1746         regs = wlc_hw->regs;
1747         osh = wlc_hw->osh;
1748
1749         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1750         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1751         ASSERT((offset & ~0xffff) == 0);
1752
1753         W_REG(osh, &regs->tplatewrptr, offset);
1754
1755         /* if MCTL_BIGEND bit set in mac control register,
1756          * the chip swaps data in fifo, as well as data in
1757          * template ram
1758          */
1759         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1760
1761         while (len > 0) {
1762                 bcopy((u8 *) buf, &word, sizeof(u32));
1763
1764                 if (be_bit)
1765                         word = hton32(word);
1766                 else
1767                         word = htol32(word);
1768
1769                 W_REG(osh, &regs->tplatewrdata, word);
1770
1771                 buf = (u8 *) buf + sizeof(u32);
1772                 len -= sizeof(u32);
1773         }
1774 }
1775
1776 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1777 {
1778         struct osl_info *osh;
1779
1780         osh = wlc_hw->osh;
1781         wlc_hw->band->CWmin = newmin;
1782
1783         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1784         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1785         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1786 }
1787
1788 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1789 {
1790         struct osl_info *osh;
1791
1792         osh = wlc_hw->osh;
1793         wlc_hw->band->CWmax = newmax;
1794
1795         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1796         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1797         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1798 }
1799
1800 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1801 {
1802         bool fastclk;
1803         u32 tmp;
1804
1805         /* request FAST clock if not on */
1806         fastclk = wlc_hw->forcefastclk;
1807         if (!fastclk)
1808                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1809
1810         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1811
1812         ASSERT(wlc_hw->clk);
1813         if (D11REV_LT(wlc_hw->corerev, 17))
1814                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1815
1816         wlc_bmac_phy_reset(wlc_hw);
1817         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1818
1819         /* restore the clk */
1820         if (!fastclk)
1821                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1822 }
1823
1824 static void
1825 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1826 {
1827         d11regs_t *regs = wlc_hw->regs;
1828
1829         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1830                                     bcn);
1831         /* write beacon length to SCR */
1832         ASSERT(len < 65536);
1833         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1834         /* mark beacon0 valid */
1835         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1836 }
1837
1838 static void
1839 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1840 {
1841         d11regs_t *regs = wlc_hw->regs;
1842
1843         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1844                                     bcn);
1845         /* write beacon length to SCR */
1846         ASSERT(len < 65536);
1847         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1848         /* mark beacon1 valid */
1849         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1850 }
1851
1852 /* mac is assumed to be suspended at this point */
1853 void
1854 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1855                                bool both)
1856 {
1857         d11regs_t *regs = wlc_hw->regs;
1858
1859         if (both) {
1860                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1861                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1862         } else {
1863                 /* bcn 0 */
1864                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1865                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1866                 /* bcn 1 */
1867                 else if (!
1868                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1869                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1870                 else            /* one template should always have been available */
1871                         ASSERT(0);
1872         }
1873 }
1874
1875 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1876 {
1877         u16 v;
1878         struct wlc_info *wlc = wlc_hw->wlc;
1879         /* update SYNTHPU_DLY */
1880
1881         if (WLCISLCNPHY(wlc->band)) {
1882                 v = SYNTHPU_DLY_LPPHY_US;
1883         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1884                 v = SYNTHPU_DLY_NPHY_US;
1885         } else {
1886                 v = SYNTHPU_DLY_BPHY_US;
1887         }
1888
1889         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1890 }
1891
1892 /* band-specific init */
1893 static void
1894 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1895 {
1896         struct wlc_hw_info *wlc_hw = wlc->hw;
1897
1898         WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1899                  wlc_hw->unit, wlc_hw->band->bandunit);
1900
1901         /* sanity check */
1902         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1903             PHY_TYPE_LCNXN)
1904                 ASSERT((uint)
1905                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1906                        == wlc_hw->band->phytype);
1907
1908         wlc_ucode_bsinit(wlc_hw);
1909
1910         wlc_phy_init(wlc_hw->band->pi, chanspec);
1911
1912         wlc_ucode_txant_set(wlc_hw);
1913
1914         /* cwmin is band-specific, update hardware with value for current band */
1915         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1916         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1917
1918         wlc_bmac_update_slot_timing(wlc_hw,
1919                                     BAND_5G(wlc_hw->band->
1920                                             bandtype) ? true : wlc_hw->
1921                                     shortslot);
1922
1923         /* write phytype and phyvers */
1924         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1925         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1926
1927         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1928         wlc_upd_ofdm_pctl1_table(wlc_hw);
1929
1930         wlc_bmac_upd_synthpu(wlc_hw);
1931 }
1932
1933 void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1934 {
1935         WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1936
1937         wlc_hw->phyclk = clk;
1938
1939         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1940
1941                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1942                                (SICF_PRST | SICF_FGC));
1943                 udelay(1);
1944                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1945                 udelay(1);
1946
1947         } else {                /* take phy out of reset */
1948
1949                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1950                 udelay(1);
1951                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1952                 udelay(1);
1953
1954         }
1955 }
1956
1957 /* Perform a soft reset of the PHY PLL */
1958 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1959 {
1960         WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1961
1962         si_corereg(wlc_hw->sih, SI_CC_IDX,
1963                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1964         udelay(1);
1965         si_corereg(wlc_hw->sih, SI_CC_IDX,
1966                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1967         udelay(1);
1968         si_corereg(wlc_hw->sih, SI_CC_IDX,
1969                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1970         udelay(1);
1971         si_corereg(wlc_hw->sih, SI_CC_IDX,
1972                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1973         udelay(1);
1974 }
1975
1976 /* light way to turn on phy clock without reset for NPHY only
1977  *  refer to wlc_bmac_core_phy_clk for full version
1978  */
1979 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1980 {
1981         /* support(necessary for NPHY and HYPHY) only */
1982         if (!WLCISNPHY(wlc_hw->band))
1983                 return;
1984
1985         if (ON == clk)
1986                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1987         else
1988                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1989
1990 }
1991
1992 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1993 {
1994         if (ON == clk)
1995                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1996         else
1997                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1998 }
1999
2000 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
2001 {
2002         wlc_phy_t *pih = wlc_hw->band->pi;
2003         u32 phy_bw_clkbits;
2004         bool phy_in_reset = false;
2005
2006         WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
2007
2008         if (pih == NULL)
2009                 return;
2010
2011         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2012
2013         /* Specfic reset sequence required for NPHY rev 3 and 4 */
2014         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2015             NREV_LE(wlc_hw->band->phyrev, 4)) {
2016                 /* Set the PHY bandwidth */
2017                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2018
2019                 udelay(1);
2020
2021                 /* Perform a soft reset of the PHY PLL */
2022                 wlc_bmac_core_phypll_reset(wlc_hw);
2023
2024                 /* reset the PHY */
2025                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2026                                (SICF_PRST | SICF_PCLKE));
2027                 phy_in_reset = true;
2028         } else {
2029
2030                 si_core_cflags(wlc_hw->sih,
2031                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2032                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2033         }
2034
2035         udelay(2);
2036         wlc_bmac_core_phy_clk(wlc_hw, ON);
2037
2038         if (pih)
2039                 wlc_phy_anacore(pih, ON);
2040 }
2041
2042 /* switch to and initialize new band */
2043 static void
2044 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
2045                                 chanspec_t chanspec) {
2046         struct wlc_info *wlc = wlc_hw->wlc;
2047         u32 macintmask;
2048
2049         ASSERT(NBANDS_HW(wlc_hw) > 1);
2050         ASSERT(bandunit != wlc_hw->band->bandunit);
2051
2052         /* Enable the d11 core before accessing it */
2053         if (!si_iscoreup(wlc_hw->sih)) {
2054                 si_core_reset(wlc_hw->sih, 0, 0);
2055                 ASSERT(si_iscoreup(wlc_hw->sih));
2056                 wlc_mctrl_reset(wlc_hw);
2057         }
2058
2059         macintmask = wlc_setband_inact(wlc, bandunit);
2060
2061         if (!wlc_hw->up)
2062                 return;
2063
2064         wlc_bmac_core_phy_clk(wlc_hw, ON);
2065
2066         /* band-specific initializations */
2067         wlc_bmac_bsinit(wlc, chanspec);
2068
2069         /*
2070          * If there are any pending software interrupt bits,
2071          * then replace these with a harmless nonzero value
2072          * so wlc_dpc() will re-enable interrupts when done.
2073          */
2074         if (wlc->macintstatus)
2075                 wlc->macintstatus = MI_DMAINT;
2076
2077         /* restore macintmask */
2078         wl_intrsrestore(wlc->wl, macintmask);
2079
2080         /* ucode should still be suspended.. */
2081         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2082                0);
2083 }
2084
2085 /* low-level band switch utility routine */
2086 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
2087 {
2088         WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
2089
2090         wlc_hw->band = wlc_hw->bandstate[bandunit];
2091
2092         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2093         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2094
2095         /* set gmode core flag */
2096         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2097                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2098                                ((bandunit == 0) ? SICF_GMODE : 0));
2099         }
2100 }
2101
2102 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
2103 {
2104
2105         /* reject unsupported corerev */
2106         if (!VALID_COREREV(wlc_hw->corerev)) {
2107                 WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
2108                 return false;
2109         }
2110
2111         return true;
2112 }
2113
2114 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
2115 {
2116         bool goodboard = true;
2117         uint boardrev = wlc_hw->boardrev;
2118
2119         if (boardrev == 0)
2120                 goodboard = false;
2121         else if (boardrev > 0xff) {
2122                 uint brt = (boardrev & 0xf000) >> 12;
2123                 uint b0 = (boardrev & 0xf00) >> 8;
2124                 uint b1 = (boardrev & 0xf0) >> 4;
2125                 uint b2 = boardrev & 0xf;
2126
2127                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2128                     || (b2 > 9))
2129                         goodboard = false;
2130         }
2131
2132         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2133                 return goodboard;
2134
2135         return goodboard;
2136 }
2137
2138 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
2139 {
2140         const char *varname = "macaddr";
2141         char *macaddr;
2142
2143         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2144         macaddr = getvar(wlc_hw->vars, varname);
2145         if (macaddr != NULL)
2146                 return macaddr;
2147
2148         if (NBANDS_HW(wlc_hw) > 1)
2149                 varname = "et1macaddr";
2150         else
2151                 varname = "il0macaddr";
2152
2153         macaddr = getvar(wlc_hw->vars, varname);
2154         if (macaddr == NULL) {
2155                 WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
2156                          wlc_hw->unit, varname);
2157         }
2158
2159         return macaddr;
2160 }
2161
2162 /*
2163  * Return true if radio is disabled, otherwise false.
2164  * hw radio disable signal is an external pin, users activate it asynchronously
2165  * this function could be called when driver is down and w/o clock
2166  * it operates on different registers depending on corerev and boardflag.
2167  */
2168 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2169 {
2170         bool v, clk, xtal;
2171         u32 resetbits = 0, flags = 0;
2172
2173         xtal = wlc_hw->sbclk;
2174         if (!xtal)
2175                 wlc_bmac_xtal(wlc_hw, ON);
2176
2177         /* may need to take core out of reset first */
2178         clk = wlc_hw->clk;
2179         if (!clk) {
2180                 if (D11REV_LE(wlc_hw->corerev, 11))
2181                         resetbits |= SICF_PCLKE;
2182
2183                 /*
2184                  * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2185                  * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2186                  */
2187                 if (D11REV_GE(wlc_hw->corerev, 18))
2188                         flags |= SICF_PCLKE;
2189
2190                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2191                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2192                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2193                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2194                         wlc_hw->regs =
2195                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2196                                                      0);
2197                 si_core_reset(wlc_hw->sih, flags, resetbits);
2198                 wlc_mctrl_reset(wlc_hw);
2199         }
2200
2201         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2202
2203         /* put core back into reset */
2204         if (!clk)
2205                 si_core_disable(wlc_hw->sih, 0);
2206
2207         if (!xtal)
2208                 wlc_bmac_xtal(wlc_hw, OFF);
2209
2210         return v;
2211 }
2212
2213 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2214 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2215 {
2216         if (wlc_hw->wlc->pub->hw_up)
2217                 return;
2218
2219         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2220
2221         /*
2222          * Enable pll and xtal, initialize the power control registers,
2223          * and force fastclock for the remainder of wlc_up().
2224          */
2225         wlc_bmac_xtal(wlc_hw, ON);
2226         si_clkctl_init(wlc_hw->sih);
2227         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2228
2229         if (wlc_hw->sih->bustype == PCI_BUS) {
2230                 si_pci_fixcfg(wlc_hw->sih);
2231
2232                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2233                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2234                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2235                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2236                         wlc_hw->regs =
2237                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2238                                                      0);
2239         }
2240
2241         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2242         wlc_phy_por_inform(wlc_hw->band->pi);
2243
2244         wlc_hw->ucode_loaded = false;
2245         wlc_hw->wlc->pub->hw_up = true;
2246
2247         if ((wlc_hw->boardflags & BFL_FEM)
2248             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2249                 if (!
2250                     (wlc_hw->boardrev >= 0x1250
2251                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2252                         si_epa_4313war(wlc_hw->sih);
2253         }
2254 }
2255
2256 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2257 {
2258         struct hnddma_pub *di = wlc_hw->di[fifo];
2259         struct osl_info *osh;
2260
2261         if (D11REV_LT(wlc_hw->corerev, 12)) {
2262                 bool rxidle = true;
2263                 u16 rcv_frm_cnt = 0;
2264
2265                 osh = wlc_hw->osh;
2266
2267                 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2268                 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2269                          ((rcv_frm_cnt =
2270                            R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2271                          50000);
2272
2273                 if (!rxidle && (rcv_frm_cnt != 0))
2274                         WL_ERROR("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n",
2275                                  wlc_hw->unit, __func__, fifo, rcv_frm_cnt);
2276                 mdelay(2);
2277         }
2278
2279         return dma_rxreset(di);
2280 }
2281
2282 /* d11 core reset
2283  *   ensure fask clock during reset
2284  *   reset dma
2285  *   reset d11(out of reset)
2286  *   reset phy(out of reset)
2287  *   clear software macintstatus for fresh new start
2288  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2289  */
2290 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2291 {
2292         d11regs_t *regs;
2293         uint i;
2294         bool fastclk;
2295         u32 resetbits = 0;
2296
2297         if (flags == WLC_USE_COREFLAGS)
2298                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2299
2300         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2301
2302         regs = wlc_hw->regs;
2303
2304         /* request FAST clock if not on  */
2305         fastclk = wlc_hw->forcefastclk;
2306         if (!fastclk)
2307                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2308
2309         /* reset the dma engines except first time thru */
2310         if (si_iscoreup(wlc_hw->sih)) {
2311                 for (i = 0; i < NFIFO; i++)
2312                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2313                                 WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
2314                                          wlc_hw->unit, __func__, i);
2315                         }
2316
2317                 if ((wlc_hw->di[RX_FIFO])
2318                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2319                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2320                                  wlc_hw->unit, __func__, RX_FIFO);
2321                 }
2322                 if (D11REV_IS(wlc_hw->corerev, 4)
2323                     && wlc_hw->di[RX_TXSTATUS_FIFO]
2324                     && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2325                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2326                                  wlc_hw->unit, __func__, RX_TXSTATUS_FIFO);
2327                 }
2328         }
2329         /* if noreset, just stop the psm and return */
2330         if (wlc_hw->noreset) {
2331                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2332                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2333                 return;
2334         }
2335
2336         if (D11REV_LE(wlc_hw->corerev, 11))
2337                 resetbits |= SICF_PCLKE;
2338
2339         /*
2340          * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2341          * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2342          * need to enable PHY CLK
2343          */
2344         if (D11REV_GE(wlc_hw->corerev, 18))
2345                 flags |= SICF_PCLKE;
2346
2347         /* reset the core
2348          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2349          *  is cleared by the core_reset. have to re-request it.
2350          *  This adds some delay and we can optimize it by also requesting fastclk through
2351          *  chipcommon during this period if necessary. But that has to work coordinate
2352          *  with other driver like mips/arm since they may touch chipcommon as well.
2353          */
2354         wlc_hw->clk = false;
2355         si_core_reset(wlc_hw->sih, flags, resetbits);
2356         wlc_hw->clk = true;
2357         if (wlc_hw->band && wlc_hw->band->pi)
2358                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2359
2360         wlc_mctrl_reset(wlc_hw);
2361
2362         if (PMUCTL_ENAB(wlc_hw->sih))
2363                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2364
2365         wlc_bmac_phy_reset(wlc_hw);
2366
2367         /* turn on PHY_PLL */
2368         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2369
2370         /* clear sw intstatus */
2371         wlc_hw->wlc->macintstatus = 0;
2372
2373         /* restore the clk setting */
2374         if (!fastclk)
2375                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2376 }
2377
2378 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2379  * txfifo sizes needs to be modified(increased) since the newer cores
2380  * have more memory.
2381  */
2382 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2383 {
2384         d11regs_t *regs = wlc_hw->regs;
2385         u16 fifo_nu;
2386         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2387         u16 txfifo_def, txfifo_def1;
2388         u16 txfifo_cmd;
2389         struct osl_info *osh;
2390
2391         if (D11REV_LT(wlc_hw->corerev, 9))
2392                 goto exit;
2393
2394         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2395         txfifo_startblk = TXFIFO_START_BLK;
2396
2397         osh = wlc_hw->osh;
2398
2399         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2400         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2401
2402                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2403                 txfifo_def = (txfifo_startblk & 0xff) |
2404                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2405                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2406                     ((((txfifo_endblk -
2407                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2408                 txfifo_cmd =
2409                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2410
2411                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2412                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2413                 if (D11REV_GE(wlc_hw->corerev, 16))
2414                         W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2415
2416                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2417
2418                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2419         }
2420  exit:
2421         /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2422         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2423                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2424         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2425                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2426         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2427                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2428                             xmtfifo_sz[TX_AC_BK_FIFO]));
2429         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2430                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2431                             xmtfifo_sz[TX_BCMC_FIFO]));
2432 }
2433
2434 /* d11 core init
2435  *   reset PSM
2436  *   download ucode/PCM
2437  *   let ucode run to suspended
2438  *   download ucode inits
2439  *   config other core registers
2440  *   init dma
2441  */
2442 static void wlc_coreinit(struct wlc_info *wlc)
2443 {
2444         struct wlc_hw_info *wlc_hw = wlc->hw;
2445         d11regs_t *regs;
2446         u32 sflags;
2447         uint bcnint_us;
2448         uint i = 0;
2449         bool fifosz_fixup = false;
2450         struct osl_info *osh;
2451         int err = 0;
2452         u16 buf[NFIFO];
2453
2454         regs = wlc_hw->regs;
2455         osh = wlc_hw->osh;
2456
2457         WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2458
2459         /* reset PSM */
2460         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2461
2462         wlc_ucode_download(wlc_hw);
2463         /*
2464          * FIFOSZ fixup
2465          * 1) core5-9 use ucode 5 to save space since the PSM is the same
2466          * 2) newer chips, driver wants to controls the fifo allocation
2467          */
2468         if (D11REV_GE(wlc_hw->corerev, 4))
2469                 fifosz_fixup = true;
2470
2471         /* let the PSM run to the suspended state, set mode to BSS STA */
2472         W_REG(osh, &regs->macintstatus, -1);
2473         wlc_bmac_mctrl(wlc_hw, ~0,
2474                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2475
2476         /* wait for ucode to self-suspend after auto-init */
2477         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2478                  1000 * 1000);
2479         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2480                 WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2481                          wlc_hw->unit);
2482
2483         wlc_gpio_init(wlc);
2484
2485         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2486
2487         if (D11REV_IS(wlc_hw->corerev, 23)) {
2488                 if (WLCISNPHY(wlc_hw->band))
2489                         wlc_write_inits(wlc_hw, d11n0initvals16);
2490                 else
2491                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2492                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2493         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2494                 if (WLCISLCNPHY(wlc_hw->band)) {
2495                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2496                 } else {
2497                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2498                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2499                 }
2500         } else {
2501                 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
2502                          __func__, wlc_hw->unit, wlc_hw->corerev);
2503         }
2504
2505         /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2506         if (fifosz_fixup == true) {
2507                 wlc_corerev_fifofixup(wlc_hw);
2508         }
2509
2510         /* check txfifo allocations match between ucode and driver */
2511         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2512         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2513                 i = TX_AC_BE_FIFO;
2514                 err = -1;
2515         }
2516         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2517         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2518                 i = TX_AC_VI_FIFO;
2519                 err = -1;
2520         }
2521         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2522         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2523         buf[TX_AC_BK_FIFO] &= 0xff;
2524         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2525                 i = TX_AC_BK_FIFO;
2526                 err = -1;
2527         }
2528         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2529                 i = TX_AC_VO_FIFO;
2530                 err = -1;
2531         }
2532         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2533         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2534         buf[TX_BCMC_FIFO] &= 0xff;
2535         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2536                 i = TX_BCMC_FIFO;
2537                 err = -1;
2538         }
2539         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2540                 i = TX_ATIM_FIFO;
2541                 err = -1;
2542         }
2543         if (err != 0) {
2544                 WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
2545                          buf[i], wlc_hw->xmtfifo_sz[i], i);
2546                 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2547                  * shmem, since driver don't overwrite those chip and
2548                  * ucode initialize data will be used.
2549                  */
2550                 if (D11REV_GE(wlc_hw->corerev, 4))
2551                         ASSERT(0);
2552         }
2553
2554         /* make sure we can still talk to the mac */
2555         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2556
2557         /* band-specific inits done by wlc_bsinit() */
2558
2559         /* Set up frame burst size and antenna swap threshold init values */
2560         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2561         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2562
2563         /* enable one rx interrupt per received frame */
2564         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2565         if (D11REV_IS(wlc_hw->corerev, 4))
2566                 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2567
2568         /* set the station mode (BSS STA) */
2569         wlc_bmac_mctrl(wlc_hw,
2570                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2571                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2572
2573         /* set up Beacon interval */
2574         bcnint_us = 0x8000 << 10;
2575         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2576         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2577         W_REG(osh, &regs->macintstatus, MI_GP1);
2578
2579         /* write interrupt mask */
2580         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2581         if (D11REV_IS(wlc_hw->corerev, 4))
2582                 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2583                       DEF_RXINTMASK);
2584
2585         /* allow the MAC to control the PHY clock (dynamic on/off) */
2586         wlc_bmac_macphyclk_set(wlc_hw, ON);
2587
2588         /* program dynamic clock control fast powerup delay register */
2589         if (D11REV_GT(wlc_hw->corerev, 4)) {
2590                 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2591                 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2592         }
2593
2594         /* tell the ucode the corerev */
2595         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2596
2597         /* tell the ucode MAC capabilities */
2598         if (D11REV_GE(wlc_hw->corerev, 13)) {
2599                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2600                                    (u16) (wlc_hw->machwcap & 0xffff));
2601                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2602                                    (u16) ((wlc_hw->
2603                                               machwcap >> 16) & 0xffff));
2604         }
2605
2606         /* write retry limits to SCR, this done after PSM init */
2607         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2608         (void)R_REG(osh, &regs->objaddr);
2609         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2610         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2611         (void)R_REG(osh, &regs->objaddr);
2612         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2613
2614         /* write rate fallback retry limits */
2615         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2616         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2617
2618         if (D11REV_GE(wlc_hw->corerev, 16)) {
2619                 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2620                 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2621         }
2622
2623         /* dma initializations */
2624         wlc->txpend16165war = 0;
2625
2626         /* init the tx dma engines */
2627         for (i = 0; i < NFIFO; i++) {
2628                 if (wlc_hw->di[i])
2629                         dma_txinit(wlc_hw->di[i]);
2630         }
2631
2632         /* init the rx dma engine(s) and post receive buffers */
2633         dma_rxinit(wlc_hw->di[RX_FIFO]);
2634         dma_rxfill(wlc_hw->di[RX_FIFO]);
2635         if (D11REV_IS(wlc_hw->corerev, 4)) {
2636                 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2637                 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2638         }
2639 }
2640
2641 /* This function is used for changing the tsf frac register
2642  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2643  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2644  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2645  * HTPHY Formula is 2^26/freq(MHz) e.g.
2646  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2647  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2648  * For spuron: 123MHz -> 2^26/123    = 545600.5
2649  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2650  * For spur off: 120MHz -> 2^26/120    = 559240.5
2651  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2652  */
2653
2654 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2655 {
2656         d11regs_t *regs;
2657         struct osl_info *osh;
2658         regs = wlc_hw->regs;
2659         osh = wlc_hw->osh;
2660
2661         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2662             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2663                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2664                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2665                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2666                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2667                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2668                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2669                 } else {        /* 120Mhz */
2670                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2671                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2672                 }
2673         } else if (WLCISLCNPHY(wlc_hw->band)) {
2674                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2675                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2676                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2677                 } else {        /* 80Mhz */
2678                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2679                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2680                 }
2681         }
2682 }
2683
2684 /* Initialize GPIOs that are controlled by D11 core */
2685 static void wlc_gpio_init(struct wlc_info *wlc)
2686 {
2687         struct wlc_hw_info *wlc_hw = wlc->hw;
2688         d11regs_t *regs;
2689         u32 gc, gm;
2690         struct osl_info *osh;
2691
2692         regs = wlc_hw->regs;
2693         osh = wlc_hw->osh;
2694
2695         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2696         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2697
2698         /*
2699          * Common GPIO setup:
2700          *      G0 = LED 0 = WLAN Activity
2701          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2702          *      G2 = LED 2 = WLAN 5 GHz Radio State
2703          *      G4 = radio disable input (HI enabled, LO disabled)
2704          */
2705
2706         gc = gm = 0;
2707
2708         /* Allocate GPIOs for mimo antenna diversity feature */
2709         if (WLANTSEL_ENAB(wlc)) {
2710                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2711                         /* Enable antenna diversity, use 2x3 mode */
2712                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2713                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2714                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2715                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2716
2717                         /* init superswitch control */
2718                         wlc_phy_antsel_init(wlc_hw->band->pi, false);
2719
2720                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2721                         ASSERT((gm & BOARD_GPIO_12) == 0);
2722                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2723                         /* The board itself is powered by these GPIOs (when not sending pattern)
2724                          * So set them high
2725                          */
2726                         OR_REG(osh, &regs->psm_gpio_oe,
2727                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2728                         OR_REG(osh, &regs->psm_gpio_out,
2729                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2730
2731                         /* Enable antenna diversity, use 2x4 mode */
2732                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2733                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2734                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2735                                      WLC_BAND_ALL);
2736
2737                         /* Configure the desired clock to be 4Mhz */
2738                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2739                                            ANTSEL_CLKDIV_4MHZ);
2740                 }
2741         }
2742         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2743         if (wlc_hw->boardflags & BFL_PACTRL)
2744                 gm |= gc |= BOARD_GPIO_PACTRL;
2745
2746         /* apply to gpiocontrol register */
2747         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2748 }
2749
2750 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2751 {
2752         struct wlc_info *wlc;
2753         wlc = wlc_hw->wlc;
2754
2755         if (wlc_hw->ucode_loaded)
2756                 return;
2757
2758         if (D11REV_IS(wlc_hw->corerev, 23)) {
2759                 if (WLCISNPHY(wlc_hw->band)) {
2760                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2761                                         bcm43xx_16_mimosz);
2762                         wlc_hw->ucode_loaded = true;
2763                 } else
2764                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2765                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2766         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2767                 if (WLCISLCNPHY(wlc_hw->band)) {
2768                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2769                                         bcm43xx_24_lcnsz);
2770                         wlc_hw->ucode_loaded = true;
2771                 } else {
2772                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2773                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2774                 }
2775         }
2776 }
2777
2778 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2779                               const uint nbytes) {
2780         struct osl_info *osh;
2781         d11regs_t *regs = wlc_hw->regs;
2782         uint i;
2783         uint count;
2784
2785         osh = wlc_hw->osh;
2786
2787         WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2788
2789         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2790
2791         count = (nbytes / sizeof(u32));
2792
2793         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2794         (void)R_REG(osh, &regs->objaddr);
2795         for (i = 0; i < count; i++)
2796                 W_REG(osh, &regs->objdata, ucode[i]);
2797 }
2798
2799 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits)
2800 {
2801         int i;
2802         struct osl_info *osh;
2803         volatile u8 *base;
2804
2805         WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2806
2807         osh = wlc_hw->osh;
2808         base = (volatile u8 *)wlc_hw->regs;
2809
2810         for (i = 0; inits[i].addr != 0xffff; i++) {
2811                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2812
2813                 if (inits[i].size == 2)
2814                         W_REG(osh, (u16 *)(base + inits[i].addr),
2815                               inits[i].value);
2816                 else if (inits[i].size == 4)
2817                         W_REG(osh, (u32 *)(base + inits[i].addr),
2818                               inits[i].value);
2819         }
2820 }
2821
2822 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2823 {
2824         u16 phyctl;
2825         u16 phytxant = wlc_hw->bmac_phytxant;
2826         u16 mask = PHY_TXC_ANT_MASK;
2827
2828         /* set the Probe Response frame phy control word */
2829         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2830         phyctl = (phyctl & ~mask) | phytxant;
2831         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2832
2833         /* set the Response (ACK/CTS) frame phy control word */
2834         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2835         phyctl = (phyctl & ~mask) | phytxant;
2836         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2837 }
2838
2839 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2840 {
2841         /* update sw state */
2842         wlc_hw->bmac_phytxant = phytxant;
2843
2844         /* push to ucode if up */
2845         if (!wlc_hw->up)
2846                 return;
2847         wlc_ucode_txant_set(wlc_hw);
2848
2849 }
2850
2851 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2852 {
2853         return (u16) wlc_hw->wlc->stf->txant;
2854 }
2855
2856 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2857 {
2858         wlc_hw->antsel_type = antsel_type;
2859
2860         /* Update the antsel type for phy module to use */
2861         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2862 }
2863
2864 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2865 {
2866         bool fatal = false;
2867         uint unit;
2868         uint intstatus, idx;
2869         d11regs_t *regs = wlc_hw->regs;
2870
2871         unit = wlc_hw->unit;
2872
2873         for (idx = 0; idx < NFIFO; idx++) {
2874                 /* read intstatus register and ignore any non-error bits */
2875                 intstatus =
2876                     R_REG(wlc_hw->osh,
2877                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2878                 if (!intstatus)
2879                         continue;
2880
2881                 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2882                          unit, idx, intstatus);
2883
2884                 if (intstatus & I_RO) {
2885                         WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
2886                                  unit, idx);
2887                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
2888                         fatal = true;
2889                 }
2890
2891                 if (intstatus & I_PC) {
2892                         WL_ERROR("wl%d: fifo %d: descriptor error\n",
2893                                  unit, idx);
2894                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
2895                         fatal = true;
2896                 }
2897
2898                 if (intstatus & I_PD) {
2899                         WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
2900                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
2901                         fatal = true;
2902                 }
2903
2904                 if (intstatus & I_DE) {
2905                         WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
2906                                  unit, idx);
2907                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
2908                         fatal = true;
2909                 }
2910
2911                 if (intstatus & I_RU) {
2912                         WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
2913                                  idx, unit);
2914                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2915                 }
2916
2917                 if (intstatus & I_XU) {
2918                         WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
2919                                  idx, unit);
2920                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
2921                         fatal = true;
2922                 }
2923
2924                 if (fatal) {
2925                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2926                         break;
2927                 } else
2928                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2929                               intstatus);
2930         }
2931 }
2932
2933 void wlc_intrson(struct wlc_info *wlc)
2934 {
2935         struct wlc_hw_info *wlc_hw = wlc->hw;
2936         ASSERT(wlc->defmacintmask);
2937         wlc->macintmask = wlc->defmacintmask;
2938         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2939 }
2940
2941 /* callback for siutils.c, which has only wlc handler, no wl
2942  * they both check up, not only because there is no need to off/restore d11 interrupt
2943  *  but also because per-port code may require sync with valid interrupt.
2944  */
2945
2946 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2947 {
2948         if (!wlc->hw->up)
2949                 return 0;
2950
2951         return wl_intrsoff(wlc->wl);
2952 }
2953
2954 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2955 {
2956         if (!wlc->hw->up)
2957                 return;
2958
2959         wl_intrsrestore(wlc->wl, macintmask);
2960 }
2961
2962 u32 wlc_intrsoff(struct wlc_info *wlc)
2963 {
2964         struct wlc_hw_info *wlc_hw = wlc->hw;
2965         u32 macintmask;
2966
2967         if (!wlc_hw->clk)
2968                 return 0;
2969
2970         macintmask = wlc->macintmask;   /* isr can still happen */
2971
2972         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
2973         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
2974         udelay(1);              /* ensure int line is no longer driven */
2975         wlc->macintmask = 0;
2976
2977         /* return previous macintmask; resolve race between us and our isr */
2978         return wlc->macintstatus ? 0 : macintmask;
2979 }
2980
2981 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2982 {
2983         struct wlc_hw_info *wlc_hw = wlc->hw;
2984         if (!wlc_hw->clk)
2985                 return;
2986
2987         wlc->macintmask = macintmask;
2988         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2989 }
2990
2991 void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2992 {
2993         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2994
2995         if (on) {
2996                 /* suspend tx fifos */
2997                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2998                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2999                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
3000                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
3001
3002                 /* zero the address match register so we do not send ACKs */
3003                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3004                                        null_ether_addr);
3005         } else {
3006                 /* resume tx fifos */
3007                 if (!wlc_hw->wlc->tx_suspended) {
3008                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3009                 }
3010                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3011                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3012                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3013
3014                 /* Restore address */
3015                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3016                                        wlc_hw->etheraddr);
3017         }
3018
3019         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3020
3021         if (on)
3022                 wlc_ucode_mute_override_set(wlc_hw);
3023         else
3024                 wlc_ucode_mute_override_clear(wlc_hw);
3025 }
3026
3027 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
3028 {
3029         if (fifo >= NFIFO)
3030                 return BCME_RANGE;
3031
3032         *blocks = wlc_hw->xmtfifo_sz[fifo];
3033
3034         return 0;
3035 }
3036
3037 /* wlc_bmac_tx_fifo_suspended:
3038  * Check the MAC's tx suspend status for a tx fifo.
3039  *
3040  * When the MAC acknowledges a tx suspend, it indicates that no more
3041  * packets will be transmitted out the radio. This is independent of
3042  * DMA channel suspension---the DMA may have finished suspending, or may still
3043  * be pulling data into a tx fifo, by the time the MAC acks the suspend
3044  * request.
3045  */
3046 bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3047 {
3048         /* check that a suspend has been requested and is no longer pending */
3049
3050         /*
3051          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3052          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3053          * chnstatus register.
3054          * The tx fifo suspend completion is independent of the DMA suspend completion and
3055          *   may be acked before or after the DMA is suspended.
3056          */
3057         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3058             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3059              (1 << tx_fifo)) == 0)
3060                 return true;
3061
3062         return false;
3063 }
3064
3065 void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3066 {
3067         u8 fifo = 1 << tx_fifo;
3068
3069         /* Two clients of this code, 11h Quiet period and scanning. */
3070
3071         /* only suspend if not already suspended */
3072         if ((wlc_hw->suspended_fifos & fifo) == fifo)
3073                 return;
3074
3075         /* force the core awake only if not already */
3076         if (wlc_hw->suspended_fifos == 0)
3077                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3078
3079         wlc_hw->suspended_fifos |= fifo;
3080
3081         if (wlc_hw->di[tx_fifo]) {
3082                 /* Suspending AMPDU transmissions in the middle can cause underflow
3083                  * which may result in mismatch between ucode and driver
3084                  * so suspend the mac before suspending the FIFO
3085                  */
3086                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3087                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
3088
3089                 dma_txsuspend(wlc_hw->di[tx_fifo]);
3090
3091                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3092                         wlc_enable_mac(wlc_hw->wlc);
3093         }
3094 }
3095
3096 void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3097 {
3098         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3099          * here for PIO otherwise the watchdog will catch the inconsistency and fire
3100          */
3101         /* Two clients of this code, 11h Quiet period and scanning. */
3102         if (wlc_hw->di[tx_fifo])
3103                 dma_txresume(wlc_hw->di[tx_fifo]);
3104
3105         /* allow core to sleep again */
3106         if (wlc_hw->suspended_fifos == 0)
3107                 return;
3108         else {
3109                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3110                 if (wlc_hw->suspended_fifos == 0)
3111                         wlc_ucode_wake_override_clear(wlc_hw,
3112                                                       WLC_WAKE_OVERRIDE_TXFIFO);
3113         }
3114 }
3115
3116 /*
3117  * Read and clear macintmask and macintstatus and intstatus registers.
3118  * This routine should be called with interrupts off
3119  * Return:
3120  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
3121  *   0 if the interrupt is not for us, or we are in some special cases;
3122  *   device interrupt status bits otherwise.
3123  */
3124 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
3125 {
3126         struct wlc_hw_info *wlc_hw = wlc->hw;
3127         d11regs_t *regs = wlc_hw->regs;
3128         u32 macintstatus;
3129         u32 intstatus_rxfifo, intstatus_txsfifo;
3130         struct osl_info *osh;
3131
3132         osh = wlc_hw->osh;
3133
3134         /* macintstatus includes a DMA interrupt summary bit */
3135         macintstatus = R_REG(osh, &regs->macintstatus);
3136
3137         WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
3138
3139         /* detect cardbus removed, in power down(suspend) and in reset */
3140         if (DEVICEREMOVED(wlc))
3141                 return -1;
3142
3143         /* DEVICEREMOVED succeeds even when the core is still resetting,
3144          * handle that case here.
3145          */
3146         if (macintstatus == 0xffffffff)
3147                 return 0;
3148
3149         /* defer unsolicited interrupts */
3150         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3151
3152         /* if not for us */
3153         if (macintstatus == 0)
3154                 return 0;
3155
3156         /* interrupts are already turned off for CFE build
3157          * Caution: For CFE Turning off the interrupts again has some undesired
3158          * consequences
3159          */
3160         /* turn off the interrupts */
3161         W_REG(osh, &regs->macintmask, 0);
3162         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3163         wlc->macintmask = 0;
3164
3165         /* clear device interrupts */
3166         W_REG(osh, &regs->macintstatus, macintstatus);
3167
3168         /* MI_DMAINT is indication of non-zero intstatus */
3169         if (macintstatus & MI_DMAINT) {
3170                 if (D11REV_IS(wlc_hw->corerev, 4)) {
3171                         intstatus_rxfifo =
3172                             R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3173                         intstatus_txsfifo =
3174                             R_REG(osh,
3175                                   &regs->intctrlregs[RX_TXSTATUS_FIFO].
3176                                   intstatus);
3177                         WL_TRACE("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n",
3178                                  wlc_hw->unit,
3179                                  intstatus_rxfifo, intstatus_txsfifo);
3180
3181                         /* defer unsolicited interrupt hints */
3182                         intstatus_rxfifo &= DEF_RXINTMASK;
3183                         intstatus_txsfifo &= DEF_RXINTMASK;
3184
3185                         /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3186                         /* clear interrupt hints */
3187                         if (intstatus_rxfifo)
3188                                 W_REG(osh,
3189                                       &regs->intctrlregs[RX_FIFO].intstatus,
3190                                       intstatus_rxfifo);
3191                         else
3192                                 macintstatus &= ~MI_DMAINT;
3193
3194                         /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3195                         if (intstatus_txsfifo) {
3196                                 W_REG(osh,
3197                                       &regs->intctrlregs[RX_TXSTATUS_FIFO].
3198                                       intstatus, intstatus_txsfifo);
3199                                 macintstatus |= MI_TFS;
3200                         }
3201                 } else {
3202                         /*
3203                          * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3204                          * If MI_DMAINT is set, assume it is set and clear the interrupt.
3205                          */
3206                         W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3207                               DEF_RXINTMASK);
3208                 }
3209         }
3210
3211         return macintstatus;
3212 }
3213
3214 /* Update wlc->macintstatus and wlc->intstatus[]. */
3215 /* Return true if they are updated successfully. false otherwise */
3216 bool wlc_intrsupd(struct wlc_info *wlc)
3217 {
3218         u32 macintstatus;
3219
3220         ASSERT(wlc->macintstatus != 0);
3221
3222         /* read and clear macintstatus and intstatus registers */
3223         macintstatus = wlc_intstatus(wlc, false);
3224
3225         /* device is removed */
3226         if (macintstatus == 0xffffffff)
3227                 return false;
3228
3229         /* update interrupt status in software */
3230         wlc->macintstatus |= macintstatus;
3231
3232         return true;
3233 }
3234
3235 /*
3236  * First-level interrupt processing.
3237  * Return true if this was our interrupt, false otherwise.
3238  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3239  * false otherwise.
3240  */
3241 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3242 {
3243         struct wlc_hw_info *wlc_hw = wlc->hw;
3244         u32 macintstatus;
3245
3246         *wantdpc = false;
3247
3248         if (!wlc_hw->up || !wlc->macintmask)
3249                 return false;
3250
3251         /* read and clear macintstatus and intstatus registers */
3252         macintstatus = wlc_intstatus(wlc, true);
3253
3254         if (macintstatus == 0xffffffff)
3255                 WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
3256
3257         /* it is not for us */
3258         if (macintstatus == 0)
3259                 return false;
3260
3261         *wantdpc = true;
3262
3263         /* save interrupt status bits */
3264         ASSERT(wlc->macintstatus == 0);
3265         wlc->macintstatus = macintstatus;
3266
3267         return true;
3268
3269 }
3270
3271 /* process tx completion events for corerev < 5 */
3272 static bool wlc_bmac_txstatus_corerev4(struct wlc_hw_info *wlc_hw)
3273 {
3274         struct sk_buff *status_p;
3275         tx_status_t *txs;
3276         struct osl_info *osh;
3277         bool fatal = false;
3278
3279         WL_TRACE("wl%d: wlc_txstatusrecv\n", wlc_hw->unit);
3280
3281         osh = wlc_hw->osh;
3282
3283         while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3284
3285                 txs = (tx_status_t *) status_p->data;
3286                 /* MAC uses little endian only */
3287                 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3288
3289                 /* shift low bits for tx_status_t status compatibility */
3290                 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3291                     | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3292
3293                 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3294
3295                 pkt_buf_free_skb(osh, status_p, false);
3296         }
3297
3298         if (fatal)
3299                 return true;
3300
3301         /* post more rbufs */
3302         dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3303
3304         return false;
3305 }
3306
3307 static bool BCMFASTPATH
3308 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3309 {
3310         /* discard intermediate indications for ucode with one legitimate case:
3311          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3312          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3313          *   transmission count)
3314          */
3315         if (!(txs->status & TX_STATUS_AMPDU)
3316             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3317                 return false;
3318         }
3319
3320         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3321 }
3322
3323 /* process tx completion events in BMAC
3324  * Return true if more tx status need to be processed. false otherwise.
3325  */
3326 static bool BCMFASTPATH
3327 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3328 {
3329         bool morepending = false;
3330         struct wlc_info *wlc = wlc_hw->wlc;
3331
3332         WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3333
3334         if (D11REV_IS(wlc_hw->corerev, 4)) {
3335                 /* to retire soon */
3336                 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3337
3338                 if (*fatal)
3339                         return 0;
3340         } else {
3341                 /* corerev >= 5 */
3342                 d11regs_t *regs;
3343                 struct osl_info *osh;
3344                 tx_status_t txstatus, *txs;
3345                 u32 s1, s2;
3346                 uint n = 0;
3347                 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3348                 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3349
3350                 txs = &txstatus;
3351                 regs = wlc_hw->regs;
3352                 osh = wlc_hw->osh;
3353                 while (!(*fatal)
3354                        && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3355
3356                         if (s1 == 0xffffffff) {
3357                                 WL_ERROR("wl%d: %s: dead chip\n",
3358                                          wlc_hw->unit, __func__);
3359                                 ASSERT(s1 != 0xffffffff);
3360                                 return morepending;
3361                         }
3362
3363                         s2 = R_REG(osh, &regs->frmtxstatus2);
3364
3365                         txs->status = s1 & TXS_STATUS_MASK;
3366                         txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3367                         txs->sequence = s2 & TXS_SEQ_MASK;
3368                         txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3369                         txs->lasttxtime = 0;
3370
3371                         *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3372
3373                         /* !give others some time to run! */
3374                         if (++n >= max_tx_num)
3375                                 break;
3376                 }
3377
3378                 if (*fatal)
3379                         return 0;
3380
3381                 if (n >= max_tx_num)
3382                         morepending = true;
3383         }
3384
3385         if (!pktq_empty(&wlc->active_queue->q))
3386                 wlc_send_q(wlc, wlc->active_queue);
3387
3388         return morepending;
3389 }
3390
3391 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3392 {
3393         struct wlc_hw_info *wlc_hw = wlc->hw;
3394         d11regs_t *regs = wlc_hw->regs;
3395         u32 mc, mi;
3396         struct osl_info *osh;
3397
3398         WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3399                  wlc_hw->unit, wlc_hw->band->bandunit);
3400
3401         /*
3402          * Track overlapping suspend requests
3403          */
3404         wlc_hw->mac_suspend_depth++;
3405         if (wlc_hw->mac_suspend_depth > 1)
3406                 return;
3407
3408         osh = wlc_hw->osh;
3409
3410         /* force the core awake */
3411         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3412
3413         mc = R_REG(osh, &regs->maccontrol);
3414
3415         if (mc == 0xffffffff) {
3416                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3417                 wl_down(wlc->wl);
3418                 return;
3419         }
3420         ASSERT(!(mc & MCTL_PSM_JMP_0));
3421         ASSERT(mc & MCTL_PSM_RUN);
3422         ASSERT(mc & MCTL_EN_MAC);
3423
3424         mi = R_REG(osh, &regs->macintstatus);
3425         if (mi == 0xffffffff) {
3426                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3427                 wl_down(wlc->wl);
3428                 return;
3429         }
3430         ASSERT(!(mi & MI_MACSSPNDD));
3431
3432         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3433
3434         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3435                  WLC_MAX_MAC_SUSPEND);
3436
3437         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3438                 WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
3439                          wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3440                 WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
3441                          wlc_hw->unit,
3442                          R_REG(osh, &regs->psmdebug),
3443                          R_REG(osh, &regs->phydebug),
3444                          R_REG(osh, &regs->psm_brc));
3445         }
3446
3447         mc = R_REG(osh, &regs->maccontrol);
3448         if (mc == 0xffffffff) {
3449                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3450                 wl_down(wlc->wl);
3451                 return;
3452         }
3453         ASSERT(!(mc & MCTL_PSM_JMP_0));
3454         ASSERT(mc & MCTL_PSM_RUN);
3455         ASSERT(!(mc & MCTL_EN_MAC));
3456 }
3457
3458 void wlc_enable_mac(struct wlc_info *wlc)
3459 {
3460         struct wlc_hw_info *wlc_hw = wlc->hw;
3461         d11regs_t *regs = wlc_hw->regs;
3462         u32 mc, mi;
3463         struct osl_info *osh;
3464
3465         WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3466                  wlc_hw->unit, wlc->band->bandunit);
3467
3468         /*
3469          * Track overlapping suspend requests
3470          */
3471         ASSERT(wlc_hw->mac_suspend_depth > 0);
3472         wlc_hw->mac_suspend_depth--;
3473         if (wlc_hw->mac_suspend_depth > 0)
3474                 return;
3475
3476         osh = wlc_hw->osh;
3477
3478         mc = R_REG(osh, &regs->maccontrol);
3479         ASSERT(!(mc & MCTL_PSM_JMP_0));
3480         ASSERT(!(mc & MCTL_EN_MAC));
3481         ASSERT(mc & MCTL_PSM_RUN);
3482
3483         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3484         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3485
3486         mc = R_REG(osh, &regs->maccontrol);
3487         ASSERT(!(mc & MCTL_PSM_JMP_0));
3488         ASSERT(mc & MCTL_EN_MAC);
3489         ASSERT(mc & MCTL_PSM_RUN);
3490
3491         mi = R_REG(osh, &regs->macintstatus);
3492         ASSERT(!(mi & MI_MACSSPNDD));
3493
3494         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3495 }
3496
3497 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3498 {
3499         u8 rate;
3500         u8 rates[8] = {
3501                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3502                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3503         };
3504         u16 entry_ptr;
3505         u16 pctl1;
3506         uint i;
3507
3508         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3509                 return;
3510
3511         /* walk the phy rate table and update the entries */
3512         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3513                 rate = rates[i];
3514
3515                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3516
3517                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3518                 pctl1 =
3519                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3520
3521                 /* modify the value */
3522                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3523                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3524
3525                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3526                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3527                                    pctl1);
3528         }
3529 }
3530
3531 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3532 {
3533         uint i;
3534         u8 plcp_rate = 0;
3535         struct plcp_signal_rate_lookup {
3536                 u8 rate;
3537                 u8 signal_rate;
3538         };
3539         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3540         const struct plcp_signal_rate_lookup rate_lookup[] = {
3541                 {WLC_RATE_6M, 0xB},
3542                 {WLC_RATE_9M, 0xF},
3543                 {WLC_RATE_12M, 0xA},
3544                 {WLC_RATE_18M, 0xE},
3545                 {WLC_RATE_24M, 0x9},
3546                 {WLC_RATE_36M, 0xD},
3547                 {WLC_RATE_48M, 0x8},
3548                 {WLC_RATE_54M, 0xC}
3549         };
3550
3551         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3552                 if (rate == rate_lookup[i].rate) {
3553                         plcp_rate = rate_lookup[i].signal_rate;
3554                         break;
3555                 }
3556         }
3557
3558         /* Find the SHM pointer to the rate table entry by looking in the
3559          * Direct-map Table
3560          */
3561         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3562 }
3563
3564 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3565 {
3566         wlc_hw->hw_stf_ss_opmode = stf_mode;
3567
3568         if (wlc_hw->clk)
3569                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3570 }
3571
3572 void BCMFASTPATH
3573 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3574                   u32 *tsf_h_ptr)
3575 {
3576         d11regs_t *regs = wlc_hw->regs;
3577
3578         /* read the tsf timer low, then high to get an atomic read */
3579         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3580         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3581
3582         return;
3583 }
3584
3585 bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3586 {
3587         d11regs_t *regs;
3588         u32 w, val;
3589         volatile u16 *reg16;
3590         struct osl_info *osh;
3591
3592         WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3593
3594         regs = wlc_hw->regs;
3595         osh = wlc_hw->osh;
3596
3597         /* Validate dchip register access */
3598
3599         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3600         (void)R_REG(osh, &regs->objaddr);
3601         w = R_REG(osh, &regs->objdata);
3602
3603         /* Can we write and read back a 32bit register? */
3604         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3605         (void)R_REG(osh, &regs->objaddr);
3606         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3607
3608         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3609         (void)R_REG(osh, &regs->objaddr);
3610         val = R_REG(osh, &regs->objdata);
3611         if (val != (u32) 0xaa5555aa) {
3612                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
3613                          wlc_hw->unit, val);
3614                 return false;
3615         }
3616
3617         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3618         (void)R_REG(osh, &regs->objaddr);
3619         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3620
3621         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3622         (void)R_REG(osh, &regs->objaddr);
3623         val = R_REG(osh, &regs->objdata);
3624         if (val != (u32) 0x55aaaa55) {
3625                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
3626                          wlc_hw->unit, val);
3627                 return false;
3628         }
3629
3630         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3631         (void)R_REG(osh, &regs->objaddr);
3632         W_REG(osh, &regs->objdata, w);
3633
3634         if (D11REV_LT(wlc_hw->corerev, 11)) {
3635                 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3636                  * for our interface, low to high
3637                  */
3638                 reg16 = (volatile u16 *)&regs->tsf_cfpstart;
3639
3640                 /* write the CFPStart register low half explicitly, starting a buffered write */
3641                 W_REG(osh, reg16, 0xAAAA);
3642
3643                 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3644                  * If the low 16 bits are written first, followed by the high 16 bits then the
3645                  * 32 bit value 0xCCCCBBBB should end up in the register.
3646                  * If the order is reversed, then the write to the high half will trigger a buffered
3647                  * write of 0xCCCCAAAA.
3648                  * If the bus is 32 bits, then this is not much of a test, and the reg should
3649                  * have the correct value 0xCCCCBBBB.
3650                  */
3651                 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3652
3653                 /* verify with the 16 bit registers that have no side effects */
3654                 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3655                 if (val != (uint) 0xBBBB) {
3656                         WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected 0x%x\n",
3657                                  wlc_hw->unit, val, 0xBBBB);
3658                         return false;
3659                 }
3660                 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3661                 if (val != (uint) 0xCCCC) {
3662                         WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected 0x%x\n",
3663                                  wlc_hw->unit, val, 0xCCCC);
3664                         return false;
3665                 }
3666
3667         }
3668
3669         /* clear CFPStart */
3670         W_REG(osh, &regs->tsf_cfpstart, 0);
3671
3672         w = R_REG(osh, &regs->maccontrol);
3673         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3674             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3675                 WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
3676                          wlc_hw->unit, w,
3677                          (MCTL_IHR_EN | MCTL_WAKE),
3678                          (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3679                 return false;
3680         }
3681
3682         return true;
3683 }
3684
3685 #define PHYPLL_WAIT_US  100000
3686
3687 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3688 {
3689         d11regs_t *regs;
3690         struct osl_info *osh;
3691         u32 tmp;
3692
3693         WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3694
3695         tmp = 0;
3696         regs = wlc_hw->regs;
3697         osh = wlc_hw->osh;
3698
3699         if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3700                 return;
3701
3702         if (on) {
3703                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3704                         OR_REG(osh, &regs->clk_ctl_st,
3705                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3706                                 CCS_ERSRC_REQ_PHYPLL));
3707                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3708                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3709                                  PHYPLL_WAIT_US);
3710
3711                         tmp = R_REG(osh, &regs->clk_ctl_st);
3712                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3713                             (CCS_ERSRC_AVAIL_HT)) {
3714                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3715                                          __func__);
3716                                 ASSERT(0);
3717                         }
3718                 } else {
3719                         OR_REG(osh, &regs->clk_ctl_st,
3720                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3721                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3722                                   (CCS_ERSRC_AVAIL_D11PLL |
3723                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3724                                  (CCS_ERSRC_AVAIL_D11PLL |
3725                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3726
3727                         tmp = R_REG(osh, &regs->clk_ctl_st);
3728                         if ((tmp &
3729                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3730                             !=
3731                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3732                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3733                                          __func__);
3734                                 ASSERT(0);
3735                         }
3736                 }
3737         } else {
3738                 /* Since the PLL may be shared, other cores can still be requesting it;
3739                  * so we'll deassert the request but not wait for status to comply.
3740                  */
3741                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3742                 tmp = R_REG(osh, &regs->clk_ctl_st);
3743         }
3744 }
3745
3746 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3747 {
3748         bool dev_gone;
3749
3750         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3751
3752         ASSERT(!wlc_hw->up);
3753
3754         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3755
3756         if (dev_gone)
3757                 return;
3758
3759         if (wlc_hw->noreset)
3760                 return;
3761
3762         /* radio off */
3763         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3764
3765         /* turn off analog core */
3766         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3767
3768         /* turn off PHYPLL to save power */
3769         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3770
3771         /* No need to set wlc->pub->radio_active = OFF
3772          * because this function needs down capability and
3773          * radio_active is designed for BCMNODOWN.
3774          */
3775
3776         /* remove gpio controls */
3777         if (wlc_hw->ucode_dbgsel)
3778                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3779
3780         wlc_hw->clk = false;
3781         si_core_disable(wlc_hw->sih, 0);
3782         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3783 }
3784
3785 /* power both the pll and external oscillator on/off */
3786 void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3787 {
3788         WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3789
3790         /* dont power down if plldown is false or we must poll hw radio disable */
3791         if (!want && wlc_hw->pllreq)
3792                 return;
3793
3794         if (wlc_hw->sih)
3795                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3796
3797         wlc_hw->sbclk = want;
3798         if (!wlc_hw->sbclk) {
3799                 wlc_hw->clk = false;
3800                 if (wlc_hw->band && wlc_hw->band->pi)
3801                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3802         }
3803 }
3804
3805 static void wlc_flushqueues(struct wlc_info *wlc)
3806 {
3807         struct wlc_hw_info *wlc_hw = wlc->hw;
3808         uint i;
3809
3810         wlc->txpend16165war = 0;
3811
3812         /* free any posted tx packets */
3813         for (i = 0; i < NFIFO; i++)
3814                 if (wlc_hw->di[i]) {
3815                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3816                         TXPKTPENDCLR(wlc, i);
3817                         WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3818                                  i);
3819                 }
3820
3821         /* free any posted rx packets */
3822         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3823         if (D11REV_IS(wlc_hw->corerev, 4))
3824                 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3825 }
3826
3827 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3828 {
3829         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3830 }
3831
3832 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3833 {
3834         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3835 }
3836
3837 /* Set a range of shared memory to a value.
3838  * SHM 'offset' needs to be an even address and
3839  * Buffer length 'len' must be an even number of bytes
3840  */
3841 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3842 {
3843         int i;
3844
3845         /* offset and len need to be even */
3846         ASSERT((offset & 1) == 0);
3847         ASSERT((len & 1) == 0);
3848
3849         if (len <= 0)
3850                 return;
3851
3852         for (i = 0; i < len; i += 2) {
3853                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3854         }
3855 }
3856
3857 static u16
3858 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3859 {
3860         d11regs_t *regs = wlc_hw->regs;
3861         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3862         volatile u16 *objdata_hi = objdata_lo + 1;
3863         u16 v;
3864
3865         ASSERT((offset & 1) == 0);
3866
3867         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3868         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3869         if (offset & 2) {
3870                 v = R_REG(wlc_hw->osh, objdata_hi);
3871         } else {
3872                 v = R_REG(wlc_hw->osh, objdata_lo);
3873         }
3874
3875         return v;
3876 }
3877
3878 static void
3879 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3880 {
3881         d11regs_t *regs = wlc_hw->regs;
3882         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3883         volatile u16 *objdata_hi = objdata_lo + 1;
3884
3885         ASSERT((offset & 1) == 0);
3886
3887         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3888         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3889         if (offset & 2) {
3890                 W_REG(wlc_hw->osh, objdata_hi, v);
3891         } else {
3892                 W_REG(wlc_hw->osh, objdata_lo, v);
3893         }
3894 }
3895
3896 /* Copy a buffer to shared memory of specified type .
3897  * SHM 'offset' needs to be an even address and
3898  * Buffer length 'len' must be an even number of bytes
3899  * 'sel' selects the type of memory
3900  */
3901 void
3902 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3903                        int len, u32 sel)
3904 {
3905         u16 v;
3906         const u8 *p = (const u8 *)buf;
3907         int i;
3908
3909         /* offset and len need to be even */
3910         ASSERT((offset & 1) == 0);
3911         ASSERT((len & 1) == 0);
3912
3913         if (len <= 0)
3914                 return;
3915
3916         for (i = 0; i < len; i += 2) {
3917                 v = p[i] | (p[i + 1] << 8);
3918                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3919         }
3920 }
3921
3922 /* Copy a piece of shared memory of specified type to a buffer .
3923  * SHM 'offset' needs to be an even address and
3924  * Buffer length 'len' must be an even number of bytes
3925  * 'sel' selects the type of memory
3926  */
3927 void
3928 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3929                          int len, u32 sel)
3930 {
3931         u16 v;
3932         u8 *p = (u8 *) buf;
3933         int i;
3934
3935         /* offset and len need to be even */
3936         ASSERT((offset & 1) == 0);
3937         ASSERT((len & 1) == 0);
3938
3939         if (len <= 0)
3940                 return;
3941
3942         for (i = 0; i < len; i += 2) {
3943                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3944                 p[i] = v & 0xFF;
3945                 p[i + 1] = (v >> 8) & 0xFF;
3946         }
3947 }
3948
3949 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3950 {
3951         WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3952                  wlc_hw->vars_size);
3953
3954         *buf = wlc_hw->vars;
3955         *len = wlc_hw->vars_size;
3956 }
3957
3958 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3959 {
3960         wlc_hw->SRL = SRL;
3961         wlc_hw->LRL = LRL;
3962
3963         /* write retry limit to SCR, shouldn't need to suspend */
3964         if (wlc_hw->up) {
3965                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3966                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3967                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3968                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
3969                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3970                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3971                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3972                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
3973         }
3974 }
3975
3976 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3977 {
3978         wlc_hw->noreset = noreset_flag;
3979 }
3980
3981 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3982 {
3983         ASSERT(req_bit);
3984
3985         if (set) {
3986                 if (mboolisset(wlc_hw->pllreq, req_bit))
3987                         return;
3988
3989                 mboolset(wlc_hw->pllreq, req_bit);
3990
3991                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3992                         if (!wlc_hw->sbclk) {
3993                                 wlc_bmac_xtal(wlc_hw, ON);
3994                         }
3995                 }
3996         } else {
3997                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3998                         return;
3999
4000                 mboolclr(wlc_hw->pllreq, req_bit);
4001
4002                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4003                         if (wlc_hw->sbclk) {
4004                                 wlc_bmac_xtal(wlc_hw, OFF);
4005                         }
4006                 }
4007         }
4008
4009         return;
4010 }
4011
4012 /* this will be true for all ai chips */
4013 bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
4014 {
4015         return true;
4016 }
4017
4018 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
4019 {
4020         u16 table_ptr;
4021         u8 phy_rate, index;
4022
4023         /* get the phy specific rate encoding for the PLCP SIGNAL field */
4024         /* XXX4321 fixup needed ? */
4025         if (IS_OFDM(rate))
4026                 table_ptr = M_RT_DIRMAP_A;
4027         else
4028                 table_ptr = M_RT_DIRMAP_B;
4029
4030         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4031          * the index into the rate table.
4032          */
4033         phy_rate = rate_info[rate] & RATE_MASK;
4034         index = phy_rate & 0xf;
4035
4036         /* Find the SHM pointer to the rate table entry by looking in the
4037          * Direct-map Table
4038          */
4039         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
4040 }
4041
4042 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
4043 {
4044         wlc_hw->antsel_avail = antsel_avail;
4045 }